VLSI Design

MODULE 4
 Sequential Circuits
 Sequential circuits in which the output depends on
previous as well as current inputs; such circuits are said to
have state.
 Finite state machines and pipelines are two important
examples of sequential circuits.
 Sequential circuits are usually designed with flip-flops or
latches, which are sometimes called memory elements,
that hold data called tokens.
 These circuits are also called as sequencing elements.

 They add some delay to tokens that are already critical,

decreasing the performance of the system. This extra
delay is called sequencing overhead.
 Static and Dynamic Circuits
 Static circuits refer to gates that have no clock input, such as
complementary CMOS, pseudo-nMOS, or pass transistor
logic.
 Dynamic circuits refer to gates that have a clock input,
especially domino logic.
 Sequencing elements themselves can be either static or
dynamic.
 A sequencing element with static storage employs some sort
of feedback to retain its output value indefinitely.
 An element with dynamic storage generally maintains its
value as charge on a capacitor that will leak away if not
refreshed for a long period of time.
 Circuit Design of Latches and Flip-Flops

 Conventional CMOS latches are built using pass

transistors or tristate buffers
 to pass the data while the latch is transparent
 to hold the data while the latch is opaque- feedback.

 The True Single Phase Clocking (TSPC) technique

 Uses a single clock with no inversions to simplify clock
distribution.

 The Klass Semidynamic Flip-Flop (SDFF) is a fast flip-flop

using a domino-style input stage.
 Differential flip-flops are good for certain applications.
Conventional CMOS Latches
 Figure shows a very simple transparent latch
built from a single transistor.
 It is compact and fast but suffers four
limitations.
4 Limitations
 The output does not swing from rail-to-rail (i.e., from
GND to VDD); it never rises above VDD – Vt.
 The output is also dynamic; in other words, the output
floats when the latch is opaque. If it floats long
enough, it can lead to leakage.
 D drives the input of a pass transistor directly.
 Leading to potential noise issues and making the delay
harder to model.
 The state node is exposed.
 Noise on the output can corrupt the state.
Conventional CMOS Latches


 Conventional CMOS Latches
 To get the Q_Bar output

 This Circuit adds an output inverter so that the

state node X is isolated from noise on the output.

 This design creates an inverting latch.

Conventional CMOS Latches
 Nodes retain their values for only a short time
 To prevent the output form floating a feedback
network can be employed.
 When the clock is 1, the input transmission gate
is ON, the feedback tristate is OFF, and the latch
is transparent.
 When the clock is 0, the input transmission gate
turns OFF.

 However, the feedback tristate turns ON, holding X at

the correct level.
 Both the combinations will introduce noise in the
output level.
Conventional CMOS Latches
Conventional CMOS Latches

 Output noise sensitivity:

 A large noise spike on the
output can propagate
backward through the
feedback gates
 Corrupting the state node X.
Conventional CMOS Latches
 The next combination is a robust transparent
latch.

 The following deficiencies(discussed earlier) are

addressed in the following combinations of
Latches:
 The latch is static
 All nodes swing rail-to-rail
 The state noise is isolated from output noise
 The input drives transistor gates rather than
diffusion
Conventional CMOS Latches
Conventional CMOS Latches
Conventional CMOS Latches
 Jamb latch
 Reduces the clock load
 Saves two transistors by using a weak
feedback inverter in place of the tristate.
 C2MOS Latch
 The dynamic latch can be redrawn as clocked tri- state.
 It is also called as Clocked CMOS(C2MOS)
 The conventional form using the inverter and transmission
gate is slightly faster because the output is driven through
the nMOS and pMOS working in parallel.
Conventional CMOS Flip- Flops
 A dynamic inverting flip-flop built from a pair
of back-to-back dynamic latches.

 The first or the last inverter can be removed

to reduce delay at the expense of greater
noise sensitivity on the unbuffered input or
output.
Conventional CMOS Flip- Flops
 This combination adds a feedback and
another inverter to produce a non-inverting
static flip-flop.
Conventional CMOS Flip- Flops
 This combination adds a feedback and
another inverter to produce a non-inverting
static flip-flop.
Conventional CMOS Flip- Flops
 This design uses a two-phase non- overlapping
clocks
 By making the non- overlap large enough, the circuit
will work despite large skews.
Resettable Latches and Flip-Flops
 Any sequencing elements require a reset
signal to enter a known initial state on startup
and ensure deterministic behavior.
Resettable Latches and Flip-Flops
 There are two types of reset: synchronous and asynchronous.

 Asynchronous reset
 Asynchronous reset forces Q low immediately.
 Asynchronous reset is characterized by a propagation delay
from reset to output.
 Asynchronous reset requires gating both the data and the
feedback to force the reset independent of the clock.

 Synchronous reset
 Synchronous reset waits for the clock to force Q to Low.
 Synchronous reset signals must be stable for a setup and hold
time around the clock edge.
 Synchronous reset simply requires ANDing the input D with
negation of reset.
Resettable Latches and Flip-Flops
 Synchronous reset latch
Resettable Latches and Flip-Flops
 Asynchronous reset latch
Resettable Latches and Flip-Flops
 Synchronous reset flip-flop
Resettable Latches and Flip-Flops
 Asynchronous reset flip-flop
Dynamic Logic Circuits
 Introduction
 Basic Principles of Pass Transistor Circuits.
 Synchronous Dynamic Circuit Techniques.
 Dynamic CMOS Circuit Techniques.
Dynamic Logic Circuits:
Introduction
 What are the disadvantages of Static logic
circuits?
 A typical static logic gate generates its output
corresponding to the applied input voltages
after a certain time delay, and it can preserve
its output level (or state) as long as the power
supply is provided.
 It require a large number of transistors to
implement a function, and may cause a
considerable time delay.
Dynamic Logic Circuits:
Introduction
 The major objectives of any high- performance, high-
density logic circuit implementation are,
 Reduction of circuit delay
 Reduction of silicon area

 The capability of temporarily storing a state, i.e., a voltage

level, at a capacitive node allows us to implement very
simple sequential circuits with memory functions.
 Also, the use of common clock signals throughout the
system enables us to synchronize the operations of various
circuit blocks.

 As a result, dynamic circuit techniques lend themselves

well to synchronous logic design.
Dynamic Logic Circuits:
Introduction
 Dynamic logic implementation of complex
functions generally requires a smaller silicon area
than does the static logic implementation.

 The power consumption which increases with the

parasitic capacitances, the dynamic circuit
implementation in a smaller area will, in many
cases, consume less power than the static
counterpart, despite its use of clock signals.
 Dynamic D-latch circuit
 Consists of two inverters connected in cascade.

 One nMOS pass transistor driving the input of

the primary inverter stage
Dynamic D-latch circuit
 The parasitic input capacitance Cx of the primary
inverter stage plays an important role in the dynamic
operation of this circuit.

 The input pass transistor is being driven by the

external periodic clock signal
 When the clock is high (CK = 1), the pass transistor turns on. The
capacitor Cx, is either charged up, or charged down through the
pass transistor MP, depending on the input (D) voltage level. The
output (Q) assumes the same logic level as the input.

 When the clock is low (CK = 0), the pass transistor MP turns off,
and the capacitor Cx is isolated from the input D. Since there is no
current path from the intermediate node X to either VDD or ground,
the amount of charge stored in Cx. during the previous cycle
determines the output voltage level Q.
Dynamic D-latch circuit
 The transistor count can be reduced by removing the
last inverter stage if the latch output can be inverted.

 The "hold" operation during the inactive clock cycle is

accomplished by temporarily storing charge in the
parasitic capacitance Cx.

 Correct operation of the circuit critically depends on

how long a sufficient amount of charge can be
retained at node X, before the output state changes
due to charge leakage.

 the capacitive intermediate node X is also called a

soft node.
Let us examine the charge-up and charge-
down events for the soft-node capacitance
C, in greater detail.
Basic Principles of Pass Transistor Circuits

 The fundamental building block of nMOS dynamic

logic circuits, consisting of an nMOS pass transistor
driving the gate of another nMOS transistor is shown
in the figure.
Basic Principles of Pass Transistor Circuits

 Logic 1 transfer : Assume that the soft node voltage is equal to 0 initially,
i.e., Vx(t = 0) = 0 V. A logic " 1" level is applied to the input terminal, which
corresponds to Vin = VOH = VDD. Now, the clock signal at the gate of the
pass transistor goes from 0 to VDD at t = 0. It can be seen that the pass
transistor MP starts to conduct as soon as the clock signal becomes active and
that MP will operate in saturation throughout this cycle,
 Since, VDS = VGS.
 Consequently, VD > VGS – VT

Equivalent circuit for the logic " 1 " transfer event

Basic Principles of Pass Transistor Circuits
Variation of V as a function of time during logic “1" transfer
Basic Principles of Pass Transistor Circuits

Node voltages during the logic " 1 " transfer, in a Pass Transistor Chain.
Basic Principles of Pass Transistor Circuits

Node voltages during the logic " 1 " transfer, when each pass transistor is driving
another pass transistor.
Basic Principles of Pass Transistor Circuits
Logic 0 transfer:
 Assume that the soft-node voltage Vx is equal to a logic " 1 " level initially, i.e.,
Vx(t = 0) = Vm = (VDD- VTn). A logic “0" level is applied to the input
terminal, which corresponds to Vin = 0 V. Now, the clock signal at the gate of
the pass transistor goes from 0 to VDD at t = 0.
 The pass transistor MP starts to conduct as soon as the clock signal becomes
active, and the direction of drain current flow through MP will be opposite to
that during the charge-up (logic " 1 " transfer) event. The intermediate node X
will now correspond to the drain terminal of MP and that the input node will
correspond to its source terminal. With VGS = VDD and VDS = Vmax, it can be
seen that
 the pass transistor operates in the linear region throughout this cycle, since VDS
< VGS - VTn.

Equivalent circuit for the logic "0" transfer event.

Basic Principles of Pass Transistor Circuits

Variation of V as a function of time during logic “0" transfer

 Charge Storage and Charge Leakage
 The preservation of a correct logic level at the soft node Vx during the in-active
clock phase depends on preserving a sufficient amount of charge in. Cx

 Dynamic Logic Circuits during the in-active clock phase, both the input voltage Vin
and the clock are equal to 0 V.

 The charge stored in Cx will gradually leak away, primarily due to the leakage
currents associated with the pass transistor.
Synchronous Dynamic Circuit Techniques

Let us investigate different examples of

synchronous dynamic circuits implemented using
depletion-load nMOS, and CMOS building blocks.
Dynamic Pass Transistor Circuits
 Multi-stage pass transistor logic driven by two
non-overlapping clocks
Nonoverlapping clock signals used for
two-phase synchronous operation.
Three stages of a depletion-load nMOS dynamic shift
register circuit driven with two-phase clocking.
A depletion- load dynamic shift register circuit, in which the input data are inverted
once and transferred, or shifted into the next stage during each clock phase.
Operation of the shift register circuit
 CMOS Transmission Gate Logic
 The operation of CMOS dynamic logic relies on
charge storage in the parasitic input
capacitances during the inactive clock cycles.

Basic building block of a CMOS transmission gate dynamic shift register.

Basic building block of a CMOS
transmission gate dynamic shift register.
 It consists of a CMOS inverter, which is driven by a
CMOS transmission gate. During the active clock
phase (CK =1), the input voltage Vin is transferred
onto the parasitic input capacitance Cx, via the
transmission

 When the clock signal becomes inactive, the CMOS

transmission gate turns off and the voltage level
across Cx, can be preserved until the next cycle.
Dynamic CMOS Logic
(Precharge-Evaluate Logic)
 A dynamic CMOS circuit technique which allows us
to significantly reduce the number of transistors used
to implement any logic function.

 The circuit operation is based on first pre-charging

the output node capacitance and subsequently,
evaluating the output level according to the applied
inputs.

 Both of these operations are scheduled by a single

clock signal, which drives one nMOS and one pMOS
transistor in each dynamic stage.
Dynamic CMOS Logic
(Precharge-Evaluate Logic)
F = (A1. A2. A3 + B1. B2)
Dynamic CMOS Logic
(Precharge-Evaluate Logic)
 When the clock signal is low (precharge phase), the
pMOS precharge transistor Mp is conducting, while
the complementary nMOS transistor Me is off.
 The parasitic output capacitance of the circuit is
charged up through the conducting pMOS transistor
to a logic-high level of Vout = VDD.
 The input voltages are also applied during this phase,
but they have no influence yet upon the output level
since Me is turned off.
Dynamic CMOS Logic
(Precharge-Evaluate Logic)
 When the clock signal becomes high (evaluate
phase), the precharge transistor Mp turns off and Me
turns on.
 The output node voltage may now remain at the
logic- high level or drop to a logic low, depending on
the input voltage levels.
 If the input signals create a conducting path between
the output node and the ground, the output
capacitance will discharge toward Vout = 0 V.
 The final discharged output level depends on the time
span of the evaluation phase. Otherwise, Vout
remains at VDD.
Domino CMOS Logic
 The generalized circuit diagram of a domino
CMOS logic gate shown
Domino CMOS Logic
 During the precharge phase (when CK = 0), the
output node of the dynamic CMOS stage is
precharged to a high logic level, and the output of the
CMOS inverter (buffer) becomes low.

 When the clock signal rises at the beginning of the

evaluation phase, there are two possibilities:
 The output node of the dynamic CMOS stage is either
discharged to a low level through the nMOS circuitry (1 to 0
transition).
 it remains high.

 The inverter output voltage can also make at most

one transition during the evaluation phase,
from 0 to 1.