05-12-2023

Unit -III
• Dynamic Logic Circuits
• Testing and Verification

Reference Book
Sung Mo Kang, Yosuf Leblebici, “CMOS Digital Integrated Circuits:
Analysis and Design”, Third Edition, Tata McGraw-Hill, 2003.

Dynamic Logic Circuits: Introduction

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Dynamic Logic Circuits: Introduction

• A static logic gate generates its output corresponding to the applied
input voltages after a certain time delay, and it can preserve its
output level (or state) as long as the power supply is provided.
• The operation of all dynamic logic gates depends on temporary
storage of charge in parasitic node capacitances, instead of relying
on steady-state circuit behaviour.
• This operational property necessitates periodic updating of internal
node voltage levels, since stored charge in a capacitor
cannot be retained indefinitely. Consequently, dynamic logic circuits
require periodic clock signals in order to control charge refreshing.
• The use of common clock signals throughout the system enable us to
synchronize the operations of various circuit blocks. As a result,
dynamic circuit techniques lend themselves well to synchronous logic
design.

Dynamic Logic Circuits Versus Static Circuits

• Static logic gate implementation require a large number of
transistors to implement a function, and may cause a
considerable time delay. The dynamic logic implementation of
complex functions generally requires a smaller silicon area than
does the static logic implementation.
• As for the power consumption which increases with the
parasitic capacitances, the dynamic circuit implementation in a
smaller area will, in many cases, consume less power than the
static counterpart, despite its use of clock signals.
• In high-density, high-performance digital implementations
where silicon area and reduction of circuit delay is a major
objective, dynamic logic circuits offer several significant
advantages over static logic circuits.
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Dynamic D-latch
• Dynamic D-latch circuit shown , consists of
two cascaded inverters and one nMOS pass
transistor driving the input of the primary
inverter stage.
• The parasitic input capacitance Cx of the
primary inverter stage plays an important
role in the dynamic operation of this
circuit.
• The input pass transistor is being driven by
the external periodic clock signal.

Dynamic D-latch operation

• Load : When the clock is high (CK = 1), the
pass transistor turns on. The capacitor Cx
is either charged up, or charged down
through the pass transistor MP, depending
on the input (D) voltage level. The output
(Q)assumes the same logic level as the
input.
• Hold: When the clock is low (CK = 0), the
pass transistor MP turns off, and the
capacitor Cx is isolated from the input D.
The amount of charge stored in Cx
during the previous cycle determines the
output voltage level Q.

The "hold" operation during the inactive clock cycle is accomplished by temporary storage
of charge in the parasitic capacitance CX. Correct operation of the circuit critically depends
on how long a sufficient amount of charge can be retained at node X, before the output
state changes due to charge leakage. The capacitive intermediate node X is also called a
soft node.

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Dynamic CMOS Circuit Techniques: CMOS Transmission gate logic

Dynamic CMOS transmission gate logic.

Typical example of dynamic CMOS transmission gate logic.

Static CMOS gates are used for implementing the logic blocks, and CMOS
transmission gates are used for transferring the output levels of one stage to the
inputs of the next stage.

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CMOS transmission gate dynamic shift register.

• The operation of CMOS dynamic logic
relies on charge storage in the parasitic
input capacitances during the inactive
clock cycles.
• Basic building block consists of a CMOS
inverter, which is driven by a CMOS
transmission gate.
• During the active clock phase (CK =1), the
input voltage Vin is transferred onto the
parasitic input capacitance Cx via the
transmission gate.
• When the clock signal becomes inactive,
the CMOS transmission gate turns off and
the voltage level across CX, can be
preserved until the next cycle.
Basic building block of a CMOS transmission
gate dynamic shift register.
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Single-phase CMOS transmission gate dynamic shift register.

Single-phase CMOS transmission gate dynamic shift register

Figure shows a single-phase CMOS shift register, which is built by cascading identical
units and by driving each stage alternately with the clock signal and its complement.

The transmission gates of the odd-numbered stages would conduct during the active
clock phase (when CK = 1), while the transmission gates of the even-numbered stages
are off, so that the cascaded inverter stages in the chain are alternately isolated.

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Single-phase CMOS transmission gate dynamic shift register.

• In practice, however, the clock signal and its complement do not

constitute a truly non-overlapping signal pair, since the clock voltage
waveform has finite rise and fall times.
• Also, the clock skew between CK and 𝐶𝐾 may be unavoidable
because one of the signals is generated by inverting the other.
• Therefore, true two-phase clocking with two non-overlapping clock
signals (ɸ1 and ɸ2) and their complements is usually preferred over
single-phase clocking in dynamic CMOS transmission gate logic.

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Dynamic CMOS Logic (Precharge-Evaluate Logic)

• Dynamic CMOS circuit technique significantly reduce the number of

transistors used to implement any logic function.
• The circuit operation is based on first pre-charging the output node
capacitance and subsequently, evaluating the output level according
to the applied inputs.
• Both of these operations are scheduled by a single clock signal, which
drives one nMOS and one pMOS
transistor in each dynamic stage.

For clk ɸ = 0, Mp-ON, Me-OFF => Vout = VDD

For clk ɸ = 1, Mp-OFF, Me-ON => Vout depends on input
A1,A2,A3,B1,B2 Hence Vout = 0 V or VDD
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Cascading Problem in Dynamic CMOS gates

Illustration of the cascading problem in dynamic CMOS logic.

Cascading Problem in Dynamic CMOS gates

(contd.)

• During the pre-charge phase, both output voltages

Vout1 and Vout2 are pulled up by the respective pMOS
precharge devices.
• The input variables of the first stage are assumed to be
such that the output Vout will drop to logic "0" during
the evaluation phase.
• On the other hand, the external input of the second-
stage NAND2 gate is assumed to be a logic "1”.

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Cascading Problem in Dynamic CMOS gates (contd.)

• When the evaluation phase begins, both output voltages Vout1 and
Vout2 are at logic-high.
• The output of the first stage (Vout1) eventually drops to its correct logic
level after a certain time delay. However, since the evaluation in the
second stage is done concurrently, starting with the high value of Vout1
at the beginning of the evaluation phase, the output voltage Vout2 at
the end of the evaluation phase will be erroneously low. Although the
first stage output subsequently assumes its correct output value once
the stored charge is drained, the correction of the second-stage output
is not possible.
• Hence dynamic CMOS logic stages driven by the same clock signal
cannot be cascaded directly. Alternative clocking schemes and circuit
structures must be developed to overcome this problem.

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Domino CMOS Logic

• Domino stage is a dynamic CMOS
logic stage cascaded with a static
CMOS inverter stage.

• During the precharge phase (when

Clock ɸ = 0), the output node X of
the dynamic CMOS stage is pre-
charged to a high logic level, and
the output of the CMOS inverter
(buffer) becomes low.

Domino CMOS Logic operation contd.

• Clock ɸ = 1 i.e evaluation phase,
there are two possibilities:

• The output node X, of the dynamic

CMOS stage is either discharged to a
low level through the nMOS circuitry
(1 to 0 transition), or it remains high.

• Consequently, the inverter (buffer)

output voltage can also make at most
one transition during the evaluation
phase, from 0 to 1

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Cascaded Domino CMOS Gates

• All input transistors (NMOSFET
which receives previous stage
inverter output as the input) in
subsequent NMOS logic blocks
will be turned off during the
precharge phase, since all
inverter outputs are equal to 0.

• During the evaluation phase,

each buffer(inverter) output
can make at most one
transition (from 0 to 1), and
thus each input of all
subsequent logic stages can
also make at most one (0 to 1)
transition.
In a cascade structure consisting of several such stages, the evaluation of each stage
“triggers” (ripples through) the next stage evaluation, similar to a chain of dominos
falling one after the other. The structure is hence called domino CMOS logic.
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4-input Domino CMOS AND Gate

4-input Domino CMOS AND Gate

Design a Domino CMOS circuit for a gate defined by, y= AB+CD

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Issues with Domino CMOS Logic

• Only non-inverting structures can be implemented

using domino CMOS.
• If necessary, inversion must be carried out using conventional
CMOS logic.
• Charge sharing between the dynamic stage output
node capacitance and the intermediate nodes of the
NMOS logic block during the evaluation phase may
cause erroneous outputs.

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Charge sharing phenomenon (Problem)

Pre-charge phase : Vx=VC1 = V DD
Evaluation phase:
Assume only top most NMOS
input =1 as shown.

Charge in C2 is now share with

C1, hence the name charge
sharing phenomenon.

VC1 after charge sharing

= VDD .C1/C1+C2
VC1 = VDD/1+ (C2/C1)

If C1 >> C2, then VC1 = VDD and

hence Vout will be correct value.
Otherwise, VC1 may fall below
Charge sharing between the output capacitance threshold voltage of the
C1 and an intermediate node capacitance C2 following inverter causing
during the evaluation cycle may reduce the erroneous switching of Vout to
output voltage level. HIGH 7

Solutions to charge sharing problem

• Use a weak (with a small (WIL) ratio) pMOS pull-up device at the dynamic CMOS
stage output.

A weak pMOS pull-up device in a feedback loop

can be used to prevent the loss of output
voltage level due to charge sharing

The weak pMOS transistor will be turned

ON only when the pre-charge node voltage is
kept high. Otherwise, it will be turned off as
Vout becomes high.

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UNIT III
• Dynamic Logic Circuts
• Testing and Verification

IC Testing and Verification : Introduction

• In real estate, key word is “Location! Location! Location!”…In IC
context it is…. “Testing! Testing! Testing!”.

• For many chips, testing accounts for more effort than does design!!

• Tests fall into three main categories :

• Functionality tests or logic Verification, before tape-out
• Silicon (Chip) Debug on a fabricated chip
• Manufacturing Tests on fabricated chip

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Categories of Testing
• Functionality tests or logic verification: These tests verifies that the chip performs its intended
function. These tests are run before tape-out to verify the functionality of the circuit.
• Silicon (Chip)Debug: These tests are run in a lab environment on the first batch of chips that
return from fabrication. These tests confirm that the chip operates as it was intended and help
debug any discrepancies. They can be much more extensive than the logic verification tests
because the chip can be tested at full speed in a system.
• For example, a new microprocessor can be placed in a prototype motherboard to try to boot the operating
system.
• This silicon debug requires creative detective work to locate the cause of failures because the
designer has much less visibility into the fabricated chip compared to during design verification.
• Manufacturing Tests: Whereas functionality tests or logic verification seek to confirm the
function of a chip as a whole, manufacturing tests are used to verify that every gate operates as
expected. The need to do this arises from a number of manufacturing defects that might occur
during either chip fabrication or accelerated life testing (where the chip is stressed by over-
voltage and over-temperature operation).

Levels of testing a die (i.e. a Chip / Integrated Circuit )

Testing a die (chip) can occur at the following levels:

• Wafer level
• Packaged chip level
• Board level
• System level
• Field level

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Importance of early detection of faults by testing

• By detecting a malfunctioning chip early, the manufacturing cost can be kept
low.
• For instance, the approximate cost to a company of detecting a fault at the
various levels is at least :

• Obviously, if faults can be detected at the wafer level, the cost of

manufacturing is lower.
• In 1994, Intel suffered a loss of $ 450 million with the Pentium which had a flaw in its
floating point divider circuit.

Importance of testing
• Defects are unavoidable
• Murphy's law:- “whatever can go wrong, will go wrong”.
• Testing is required to guarantee fault-free chips.
• Product quality depends on:
• Test cost
• Test quality
• Test time

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Manufacturing Test Principles

Wafer yield
• The Wafer yield is defined as the ratio of number of good
ICs (die) divided by the total number of ICs per wafer. not all die on a
wafer function correctly.
• Because of the complexity of the manufacturing process and
manufacturing defects, Integrated circuits have a yield of less than
100%.
• Dust particles and small imperfections in starting material or photo-masking
can result in unintended connections or missing features, termed as faults.
• Typical commercial products target a defect rate of 350–1000 Defects Per
Million (DPM) chips shipped.

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Fault Types: Typical manufacturing defects

Typical defects include the following:
• Layer-to-layer shorts (e.g., metal-to-metal)
• Discontinuous wires (e.g., metal thins when crossing vertical topology jumps)
• Missing or damaged vias
• Shorts through the thin gate oxide to the substrate or well

These in turn lead to particular circuit maladies, including the following:

• Nodes shorted to power or ground
• Nodes shorted to each other
• Inputs floating/outputs disconnected

Images of Manufacturing defects in ICs

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Fault Models
• Fault model: It is a model to mimic manufacturing defects (faults) in
an IC and it can be used to predict the consequences of the defect
on the output. The most popular model is called the “Stuck-At
fault” model.
• “Stuck-At faults” occur when a line is permanently stuck to Vdd or
ground giving a faulty output, independent of the inputs to the
circuit. This line may be an input or output to any gate.
• When a signal, or gate output, is stuck at a 0 or 1 value, the signal is
said to be “Stuck- at-0 fault” or “Stuck- at-1 fault” and the fault model
used to describe this type of error is called a “stuck- at- fault model”.

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Stuck-At faults
• Stuck-At-1 (SA1) fault
• Stuck-At-0 (SA0) Fault

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Stuck-at 0 Example

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Design for Testability (DFT)

A critical factor in all VLSI design is the need to incorporate

methods of testing circuits. This task should proceed
concurrently with architectural considerations and not be left until
fabricated parts are available .

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Design for Testability (DFT)

• According to Moore’s law, feature size is decreasing.
Test generation complexity increases exponentially with the size of the
circuit.
• Design for Testability (DFT) is a design technique that makes testing
a chip possible and cost-effective by adding additional circuitry to
the chip.
• Design-for-testability techniques improve the controllability and
observability of internal nodes
• Controllability : The ability to set node to a specific value is to
1or 0) .
• Observability is the ability to observe, either directly or
indirectly, the state of any node in the circuit.

• DFT makes testing possible after manufacturing-“The game

changer”

Why DFT?
• To increase Productivity:
• Shorter time-to-market
• Reduced cost of manufacturing test

• To improve Quality:
• Reduced Defects per Million (DPM)

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DFT Metrics
• Observability
• Controllability
• Repeatability
• Survivability

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Observability
• The observability of a particular circuit node is the degree to which
test engineer can observe that node at the outputs of an integrated
circuit (i.e., the pins).
• This metric is relevant when one want to measure the output of a
gate within a larger circuit to check that it operates correctly.
• Given the limited number of nodes that can be directly observed, it is
the aim of good chip designers to have easily observed gate outputs.
• Adoption of some basic design for test techniques can aid
tremendously in this respect. Ideally, one should be able to observe
directly or with moderate indirection (i.e., you may have to wait a few
cycles) every gate output within an integrated circuit.

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Controllability
• The controllability of an internal circuit node within a chip is a
measure of the ease of setting the node to a 1 or 0 state.
• This metric is of importance when assessing the degree of
difficulty of testing a particular signal within a circuit.
• An easily controllable node would be directly settable via an
input pad.
• Often, it is impossible to generate a test sequence to set a
number of poorly controllable nodes into the right state.
• It should be the aim of good chip designers to make all nodes
easily controllable.
• The adoption of some simple design for test techniques can aid
the controllability
• Making all flip-flops resettable via a global reset signal

Repeatability
• The repeatability of system is the ability to produce the same
outputs given the same inputs.
• Combinational logic and synchronous sequential logic is
always repeatable when it is functioning correctly.
• However, certain asynchronous sequential circuits are
nondeterministic.
• E.g. An arbiter may select either input when both arrive at
nearly the same time.
• Testing is much easier when the system is repeatable.

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Survivability
• The survivability of a system is the ability to continue
function after a fault.
• E.g. Error-correcting codes provide survivability in the event
of soft errors (error caused by external source ,not due to
manufacturing defects/circuit bugs).
• Redundant rows and columns in memories and spare cores
provide survivability in the event of manufacturing defects.
• Adaptive techniques provide survivability in the event of
process variation.

DFT Techniques: Provides good controllability and observability

• Ad-hoc Testing
• Built-in Self Test (BIST)
• Scan-based approaches

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Ad-hoc Testing
• As the name implies Ad-hoc Technique is a temporary
Technique.
• It is a strategy to enhance the design testability without
making much change to design style.
• In Ad-hoc testing, good design practices learnt through
experience over the years are used as guidelines avoiding the
overhead of a systematic approach to testing.
• The following are common techniques for Ad hoc testing:
• Partitioning large sequential circuits
• Adding test points
• Adding multiplexers
• Providing for easy state reset
• Ad-hoc approach is still quite valid, but process densities and
chip complexities necessitate a structured approach to testing.

Built-in Self -Test (BIST)

• BIST is a Structured Design-for-Testability technique for logic
circuits to improve access to internal signals from primary
inputs/outputs
• In BIST technique, the Integrated Circuit has self-testable facility
in it.
• The basic BIST architecture requires the addition of three
hardware blocks to a digital circuit:
• A test pattern generator : The test pattern generator generates the test
patterns for the Circuit Under Test (CUT).
• A Output Response Analyser (ORA)
• A test controller.
• These techniques add area to the chip for the test logic, but
reduce the test time required and thus can lower the overall
system cost.

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BIST Architecture

BIST Procedure
BIST procedure:
• Generate a test pattern
• Most BIST technique use Pseudo-Random Sequence
Generator (PRSG)
• Apply the pattern to “Circuit Under Test” (CUT)
• Check the response
• Repeat for each test pattern
• Most BIST technique compress responses into a
single “signature”
• Output Response Analyser (ORA) gives the test
result as Pass/Fail

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Pseudo-Random Sequence Generator (PRSG)

• A PRSG of length n is constructed

from a linear feedback shift
register (LFSR), which in turn is
made of n flip-flops connected in
a serial fashion.

• Using feedback from the various

stages of an n-bit shift register,
connected to the first stage by
means of XOR gates, it is possible
to generate a sequence of 2n-1
Pseudo-random sequence generator
patterns that have the
characteristics of randomly
generated numbers.

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