Experiment no 5

01/04/2024

Experiment No. ( 5 )

1 AIM
To design and simulate T flip flop , D flip flop , SR flip flop and JK
flipflop

1-1-1 SOFTWARE USED

AMD Vivado 2023.2
2 Theory
• T flip flop
T stands for ("toggle") flip-flop to avoid an intermediate state in SR flip-flop. We
should provide only one input to the flip-flop called Trigger input Toggle input to
avoid an intermediate state occurrence.
• D flip flop
A D flip-flop stores a single bit of data. On each clock edge, it copies the input (D) to
its output (Q). It is widely used for synchronous digital systems, such as in memory
storage, register transfer, and data synchronization applications.
Clock (Clk) | Data Input (D) | Output (Q)
-------------------------------------------
0 | X | Q (unchanged)
-------------------------------------------
1 | 0 | 0
-------------------------------------------
1 | 1 | 1
• SR flip flop
• A Set-Reset (SR) flip-flop is a digital circuit with two inputs, S (Set) and R (Reset),
and two outputs, Q and Q_bar. It can store one bit of data. The outputs change in
response to the inputs according to the following truth table:
• S | R || Q | Q_bar
• -------------------------------
 Experiment no 5
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• 0 | 0 || Q | Q_bar
• 0 | 1 || 0 | 1
• 1 | 0 || 1 | 0
• 1 | 1 || X | X (Invalid state, both outputs undefined)
• JK flip flip
• A JK flip-flop is a sequential logic device with two inputs, J (set) and K (reset), and
two outputs, Q and Q_bar. Its behavior is described by the following truth table
• J | K || Q | Q_bar
• -------------------------------
• 0 | 0 || Q | Q_bar
• 0 | 1 || 0 | 1
• 1 | 0 || 1 | 0
• 1 | 1 || ~Q | ~Q_bar

3 VERILOG CODE
• T flip flop

module t_flip_flop (
input wire clk, // Clock input
input wire t, // Toggle input
output reg q // Output
);
// Toggle flip-flop behavior
always @(posedge clk) begin
if (t == 1'b1)
q <= ~q; // Toggle Q output
end
endmodule
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• D flip flop
module d_flip_flop (
input wire clk, // Clock input
input wire d, // Data input
output reg q // Output
);
// D flip-flop behavior
always @(posedge clk) begin
q <= d; // Update Q with D on clock edge
end
endmodule
• SR flip flop
module sr_flip_flop (
input wire clk, // Clock input
input wire s, // Set input
input wire r, // Reset input
output reg q, // Output Q
output reg q_bar // Output Q'
);
// SR flip-flop behavior
always @(posedge clk) begin
if (s && ~r) begin
q <= 1'b1; // Set Q
q_bar <= 1'b0; // Reset Q'
end else if (~s && r) begin
q <= 1'b0; // Reset Q
q_bar <= 1'b1; // Set Q'
end
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end
Endmodule
• JK flip flop
module jk_flip_flop (
input wire clk, // Clock input
input wire j, // J input
input wire k, // K input
output reg q, // Output Q
output reg q_bar // Output Q'
);
// JK flip-flop behavior
always @(posedge clk) begin
if (j && ~k) begin
q <= 1'b1; // Set Q
q_bar <= 1'b0; // Reset Q'
end else if (~j && k) begin
q <= 1'b0; // Reset Q
q_bar <= 1'b1; // Set Q'
end else if (j && k) begin
q <= ~q; // Toggle Q
q_bar <= ~q_bar; // Toggle Q'
end
end

endmodule

4 TESTBENCH
•
SR flip flop
module testbench_half_subtractor;
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// Inputs
reg a, b;
// Outputs
wire diff, borrow;

// Instantiate the half subtractor

half_subtractor uut (
.a(a),
.b(b),
.diff(diff),
.borrow(borrow)
);

initial begin
$monitor("At time %t: a = %b, b = %b, diff = %b, borrow = %b", $time, a,
b, diff, borrow);

a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
$finish;
end
endmodule

• D flip flop
`timescale 1ns / 1p
module d_flip_flop_tb;

// Parameters
parameter CLK_PERIOD = 10; // Clock period in nanoseconds
// Signals
reg clk = 0; // Clock signal
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reg d = 0; // Data input

wire q; // Output
// Instantiate D flip-flop
d_flip_flop d_ff (
.clk(clk),
.d(d),
.q(q)
);
// Clock generation
always #(CLK_PERIOD/2) clk = ~clk;
// Stimulus
initial begin
$display("Time\tD\tQ");
$monitor("%d\t%d\t%d", $time, d, q);
// Test case 1: D=0
#10 d = 0;
// Test case 2: D=1
#10 d = 1;
// Test case 3: D=0
#10 d = 0;
// Test case 4: D=1
#10 d = 1;
// Test case 5: D=0
#10 d = 0;

// Add more test cases as needed

$finish;
end
initial begin
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$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule
• SR flip flop
`timescale 1ns / 1ps
module sr_flip_flop_tb;

// Parameters
parameter CLK_PERIOD = 10; // Clock period in nanoseconds
// Signals
reg clk = 0; // Clock signal
reg s = 0; // Set input
reg r = 0; // Reset input
wire q; // Output Q
wire q_bar; // Output Q'
// Instantiate SR flip-flop
sr_flip_flop sr_ff (
.clk(clk),
.s(s),
.r(r),
.q(q),
.q_bar(q_bar)
);
// Clock generation
always #(CLK_PERIOD/2) clk = ~clk;
// Stimulus
initial begin
 Experiment no 5
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$display("Time\tS\tR\tQ\tQ_bar");
$monitor("%d\t%d\t%d\t%d\t%d", $time, s, r, q, q_bar);
// Test case 1: S=0, R=0
#10 s = 0; r = 0;
// Test case 2: S=1, R=0
#10 s = 1; r = 0;
// Test case 3: S=0, R=1
#10 s = 0; r = 1;
// Test case 4: S=1, R=1
#10 s = 1; r = 1;
// Test case 5: S=0, R=0
#10 s = 0; r = 0;
// Add more test cases as needed
$finish;
end
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule
• JK flip flop
`timescale 1ns / 1ps

module jk_flip_flop_tb;

// Parameters
parameter CLK_PERIOD = 10; // Clock period in nanoseconds
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// Signals
reg clk = 0; // Clock signal
reg j = 0; // J input
reg k = 0; // K input
wire q; // Output Q
wire q_bar; // Output Q'

// Instantiate JK flip-flop
jk_flip_flop jk_ff (
.clk(clk),
.j(j),
.k(k),
.q(q),
.q_bar(q_bar)
);

// Clock generation
always #(CLK_PERIOD/2) clk = ~clk;

// Stimulus
initial begin
$display("Time\tJ\tK\tQ\tQ_bar");
$monitor("%d\t%d\t%d\t%d\t%d", $time, j, k, q, q_bar);

// Test case 1: J=0, K=0

#10 j = 0; k = 0;
// Test case 2: J=1, K=0
#10 j = 1; k = 0;
// Test case 3: J=0, K=1
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#10 j = 0; k = 1;
// Test case 4: J=1, K=1
#10 j = 1; k = 1;
// Test case 5: J=0, K=0
#10 j = 0; k = 0;

// Add more test cases as needed

$finish;
end
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end

endmodule

5 OUTPUT WAVEFORM
• T flip flop
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• D flip flop

• SR flip flop
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• JK flip flop
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6 RESULT
1 T , D, SR, JK flip flop have been implement using Gate Level Modelling, and the corresponding wave
form and RTL Schematic Diagram have been observed.