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CA Lab5 - RS and JK Flip Flop

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Souvik Gon
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25 views4 pages

CA Lab5 - RS and JK Flip Flop

Uploaded by

Souvik Gon
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Design SR Flip Flop Circuit

The SR flip flop has two inputs SET ‘S’ and RESET ‘R’. As the name suggests, when S = 1,
output Q becomes 1, and when R = 1, output Q becomes 0. The output Q’ is the
complement of Q.

Block Diagram Truth Table

For S = 1 and R = 1, output Q = x i.e. 1 or 0. Hence, S=1 and R=1 input combination
is invalid and must be avoided in the SR flip flop.

SR Flip Flop Verilog Code


module SR_flipflop (
input clk, rst_n,
input s,r,
output reg q,
output q_bar
);
// always@(posedge clk or negedge rst_n) // for asynchronous reset
always@(posedge clk) begin // for synchronous reset
if(!rst_n) q <= 0;
else begin
case({s,r})
2'b00: q <= q; // No change
2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
2'b11: q <= 1'bx; // Invalid inputs
endcase
end
end
assign q_bar = ~q;
endmodule

module tb;
reg clk, rst_n;
reg s, r;
wire q, q_bar;
SR_flipflop dff(clk, rst_n, s, r, q, q_bar);
always #2 clk = ~clk;
initial begin
clk = 0; rst_n = 0;
$display("Reset=%b --> q=%b, q_bar=%b", rst_n, q, q_bar);
#3 rst_n = 1;
$display("Reset=%b --> q=%b, q_bar=%b", rst_n, q, q_bar);
drive(2'b00);
drive(2'b01);
drive(2'b10);
drive(2'b11);
#5;
$finish;
end
task drive;
input [1:0] ip;
begin
#2; {s, r} = ip; #2;
$display("s=%b, r=%b --> q=%b, q_bar=%b", s, r, q, q_bar);
end
endtask
endmodule
Output:
Reset=0 --> q=x, q_bar=x
Reset=1 --> q=0, q_bar=1
s=0, r=0 --> q=0, q_bar=1
s=0, r=1 --> q=0, q_bar=1
s=1, r=0 --> q=1, q_bar=0
s=1, r=1 --> q=x, q_bar=x
Design JK Flip Flop Circuit
The JK flip flop has two inputs ‘J’ and ‘K’. It behaves the same as SR flip flop except that it
eliminates undefined output state (Q = x for S=1, R=1).
For J=1, K=1, output Q toggles from its previous output state.

Block Diagram Truth Table

JK Flip Flop Verilog Code


module JK_flipflop (
input clk, rst_n,
input j,k,
output reg q,
output q_bar
);
// always@(posedge clk or negedge rst_n) // for asynchronous reset
always@(posedge clk) begin // for synchronous reset
if(!rst_n) q <= 0;
else begin
case({j,k})
2'b00: q <= q; // No change
2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
2'b11: q <= ~q; // Toggle
endcase
end
end
assign q_bar = ~q;
endmodule

module tb;
reg clk, rst_n;
reg j, k;
wire q, q_bar;
JK_flipflop dff(clk, rst_n, j, k, q, q_bar);
always #2 clk = ~clk;
initial begin
clk = 0; rst_n = 0;
$display("Reset=%b --> q=%b, q_bar=%b", rst_n, q, q_bar);
#3 rst_n = 1;
$display("Reset=%b --> q=%b, q_bar=%b", rst_n, q, q_bar);
drive(2'b00);
drive(2'b01);
drive(2'b10);
drive(2'b11); // Toggles previous output
drive(2'b11); // Toggles previous output
#5;
$finish;
end
task drive;
input [1:0] ip;
begin
#2; {j,k} = ip; #2;
$display("j=%b, k=%b --> q=%b, q_bar=%b",j, k, q, q_bar);
end
endtask
endmodule
Output:
Reset=0 --> q=x, q_bar=x
Reset=1 --> q=0, q_bar=1
j=0, k=0 --> q=0, q_bar=1
j=0, k=1 --> q=0, q_bar=1
j=1, k=0 --> q=1, q_bar=0
j=1, k=1 --> q=0, q_bar=1
j=1, k=1 --> q=1, q_bar=0

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