VLSI Design and Testing 1 Introduction to MOS Transistor

Department of Electronics and Communication Engg.

VLSI Design and Testing(BEC602)

MOS Transistor Theory

1 Introduction to MOS Transistor

A MOS transistor is a majority carrier device, in which the current in the channel between
the source and drain is modulated by a voltage applied to the gate.

1.1 nMOS Transistor

Majority carriers are electrons.

A positive gate voltage relative to the substrate increases electron concentration in the
channel, enhancing conductivity.

For gate voltages below the threshold voltage Vt, the channel is cut off, leading to a very
low drain-to-source current.

1.2 pMOS Transistor

Majority carriers are holes.

A negative gate voltage enhances conduction.

The operation is analogous to nMOS but with opposite voltage polarities.

1.3 Threshold Voltage (Vt)

The threshold voltage Vt is the voltage at which a MOSFET begins to conduct.

The source-to-drain current Ids depends on the gate-to-source voltage Vgs.

1.4 Enhancement vs. Depletion Mode

There are two types of MOS transistors based on conduction behavior at zero gate bias:

1. Enhancement Mode: The transistor is normally OFF (requires a gate voltage to conduct).

2. Depletion Mode: The transistor is normally ON (conducts even at zero gate voltage).

1.5 nMOS vs. pMOS Transistors

nMOS and pMOS transistors are duals of each other, meaning they function similarly but
with opposite voltage polarities.

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VLSI Design and Testing 1 Introduction to MOS Transistor

The threshold voltages are denoted as:

Vtn : (n-channel MOSFET)
Vtp : (p-channel MOSFET)

Figure 1: Conduction characteristics for enhancement and depletion mode transistors (assuming fixed
Vds)

1.6 CMOS Technology

Both nMOS and pMOS transistors are used together in CMOS (Complementary MOS)
circuits.

Most modern CMOS integrated circuits use enhancement-mode transistors.

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VLSI Design and Testing 2 n-MOS Enhancement Transistor

2 n-MOS Enhancement Transistor

An nMOS enhancement-mode transistor is a voltage-controlled device widely used in digital
and analog circuits.

It operates based on an electric field-induced conduction channel between its source and drain
terminals.

Unlike bipolar junction transistors (BJTs), where charge carriers are introduced by doping, an
nMOS transistor forms a conductive channel through an applied gate voltage.

2.1 Structure of nMOS Enhancement-Mode Transistor

The basic structure of an nMOS enhancement-mode transistor is shown in figure below. It
consists of:

– A moderately doped p-type silicon substrate.

– Two heavily doped n-type regions called the source and drain, diffused into the
substrate.
– A thin insulating layer of silicon dioxide (SiO2) covering the channel region, known as
the gate oxide.
– A polycrystalline silicon (polysilicon) gate electrode over the oxide layer.

Since SiO2 is an excellent insulator, the gate does not allow direct current flow to the channel.

Figure 2: Physical structure of an nMOS transistor

The transistor is symmetrical, meaning the source and drain can be interchanged physically.

However, in circuit design, the source is usually defined as the terminal at a lower potential.

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VLSI Design and Testing 2 n-MOS Enhancement Transistor

2.2 Principle of Operation

The operation of the nMOS transistor depends on the applied gate-source voltage (VGS) and
drain-source voltage (VDS).

2.2.1 With Zero Gate Bias (VGS = 0)

The p-type substrate prevents current flow between the source and drain because the two p-n
junctions (between the n+ regions and the p-substrate) are reverse biased.

The source and drain act as two isolated n-regions, with only leakage current flowing.

2.2.2 Applying a Positive Gate Voltage (VGS > 0)

The positive voltage on the gate creates an electric field (E) that repels holes and attracts
electrons toward the oxide-silicon interface.

When VGS exceeds a threshold voltage (Vt), sufficient electrons accumulate to form an
inversion layer, effectively turning the p-type region beneath the gate into an n-type channel.

This allows current to flow between source and drain if a voltage VDS is applied.

2.2.3 Field-Induced vs. Metallurgical Junction

Unlike BJTs, where n-type conductivity is introduced via doping, the MOSFET channel is
induced by an electric field.

This field-induced junction enables voltage-controlled operation.

2.3 Operating Regions of nMOS Transistor

The nMOS transistor operates in three regions based on the applied voltages:
1. Cutoff Region (VGS < Vt):

The gate voltage is below the threshold voltage.

No conduction occurs except for a small leakage current.
The transistor acts as an open switch.
2. Linear (Triode) Region (VGS > Vt and VDS < VGS − Vt):
The inversion layer forms a conductive channel between the source and drain.
The transistor behaves like a voltage-controlled resistor.
Drain current IDS is approximately proportional to VDS.
The drain current in this region is given by:
W V2
DS
(VGS − Vt)VDS − (1)
IDS = µnCox 2
L
where:

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VLSI Design and Testing 2 n-MOS Enhancement Transistor

µn is the electron mobility.

Cox is the gate oxide capacitance per unit area.
W is the channel width.
L is the channel length.

Figure 3: nMOS in Linear region

3. Saturation Region (VGS > Vt and VDS > VGS − Vt):

The channel becomes pinched off at the drain end.
The drain current is primarily controlled by VGS and is almost independent of VDS.
The drain current in this region is given by:
1 W
IDS — Vt)2 (2)
= Cox
µn2 L
(VGS

Figure 4: nMOS in Saturation region

Pinch-Off and Channel Behavior

– At the source end, the full gate voltage is effective.
– At the drain end, only (VGS − VDS) is effective.
– When VDS > VGS − Vt, the channel is pinched off.

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VLSI Design and Testing 2 n-MOS Enhancement Transistor

– Electrons drift toward the drain due to the electric field.

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 VLSI Design and Testing 2 n-MOS Enhancement Transistor

2.3.1 Factors Affecting Drain Current

The drain current IDS is influenced by:

The distance between source and drain, i.e., channel length (L).

The channel width (W ).

The threshold voltage (Vt).

The thickness of the gate-insulating oxide layer.

The dielectric constant of the gate insulator.

Carrier mobility (µn).

2.3.2 Breakdown and Abnormal Conditions

1. Avalanche Breakdown
If a very high voltage is applied to the drain, impact ionization occurs.

This leads to excessive current flow, causing possible device failure.

2. Punch-Through Effect
If VDS is too high, the depletion region extends from the source to drain, allowing direct
current flow.

This results in loss of gate control over the drain current.

2.3.3 Summary
Region Gate Voltage (VGS) Drain Voltage (V
Current
DS) Flow (IDS)
Cutoff VGS < Vt Any conduction (only leakage
current)
Linear VGS > Vt VDS < VGS − Vt Increases linearly with VDS
Saturation VGS > Vt VDS > VGS − Vt Controlled by VGS, nearly
independent of VDS

2.4 Conclusion
The nMOS enhancement-mode transistor is an essential component in digital and analog
circuits.

It operates as a voltage-controlled switch, allowing conduction only when VGS > Vt.

By varying the gate and drain voltages, the device transitions between different operating
regions, making it ideal for digital logic and analog applications.

Understanding its different operating regions and the impact of design parameters is crucial
for efficient circuit design.

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VLSI Design and Testing 3 pMOS Transistor

3 pMOS Transistor
While most discussions on MOS transistors focus on nMOS devices, a complementary type
called the pMOS transistor exists.
A pMOS transistor is structurally similar to an nMOS transistor but with reversed doping
polarities.
This means the substrate is n-type, and the source and drain are p-type.
The pMOS transistor operates in a manner similar to an nMOS transistor but with opposite
voltage polarities and charge carrier movement.

3.1 Structure of a pMOS Enhancement-Mode Transistor

A pMOS enhancement-mode transistor consists of:
An n-type silicon substrate.
Two heavily doped p-type regions, called the source and drain, diffused into the substrate.
A thin insulating layer of silicon dioxide (SiO2) covering the channel region, known as the
gate oxide.
A polycrystalline silicon (polysilicon) gate electrode over the oxide layer.
Figure below illustrates the structure of a pMOS transistor.

Figure 5: Physical structure of PMOS transistor

3.2 Operation of a pMOS Transistor

Similar to the nMOS transistor, a pMOS transistor operates based on the creation of a conductive
channel between the source and drain when a proper gate voltage is applied.

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VLSI Design and Testing 3 pMOS Transistor

3.2.1 With Zero Gate Bias (VGS = 0)

No conduction occurs because the source and drain are separated by two reverse-biased p-n
junctions.

The source and drain act as two isolated p-regions in an n-type substrate.

3.2.2 Applying a Negative Gate Voltage (VGS < 0)

A negative voltage on the gate repels electrons and attracts holes toward the SiO2-silicon
interface.

When VGS is sufficiently negative (i.e., less than a threshold voltage Vt), an inversion layer
forms, converting the n-type region under the gate into a p-type conductive channel.

This allows holes to flow from the source to the drain if a negative drain-to-source voltage
(VDS) is applied.

3.2.3 Charge Carrier Movement

In an nMOS transistor, conduction occurs due to electron movement.

In a pMOS transistor, conduction occurs due to hole movement.

A negative drain voltage causes holes to move from the source through the channel to the
drain.

3.3 Comparison Between pMOS and nMOS Transistors

Parameter nMOS pMOS
Substrate Type p-type n-type
Source/Drain Doping n+ regions p+ regions
Charge Carriers Electrons Holes
Gate Control Positive voltage creates n-channel Negative voltage creates p-channel
Drain Voltage Positive for conduction Negative for conduction
Carrier Mobility High Lower than electrons

3.4 Conclusion
The pMOS transistor operates in a manner similar to an nMOS transistor but with reversed
voltage polarities and charge carrier movement.

While nMOS transistors dominate modern digital circuits due to higher electron mobility,
pMOS transistors are still used in complementary MOS (CMOS) technology to achieve low
power consumption and enhanced performance.

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VLSI Design and Testing 4 Threshold Voltage (Vt)

4 Threshold Voltage (Vt)

The threshold voltage, Vt, of an MOS transistor is the minimum gate-to-source voltage
(VGS) required to create a conductive inversion layer (channel) between the source and drain
terminals.

Below this voltage, the drain-to-source current (IDS) is negligible, meaning the transistor is in
the cut-off region.

4.1 Factors Affecting Threshold Voltage

The threshold voltage is influenced by several factors, including:

Gate material: Different materials have different work functions, which affect the required
voltage for inversion.

Gate insulation material: The dielectric constant of the insulator affects the threshold
voltage.

Gate insulator thickness: Thinner oxide layers result in stronger electric fields and lower
threshold voltages.

Channel doping: Heavily doped substrates increase the threshold voltage.

Impurities at the silicon-insulator interface: Trapped charges and interface states can
shift the threshold voltage.

Voltage between source and substrate (VSB): Also known as the body effect, an
increase in VSB raises the threshold voltage.

4.2 Temperature Dependence of Threshold Voltage

The absolute value of the threshold voltage decreases with increasing temperature. This variation is
approximately:
−4 mV/ C for high substrate doping levels.
−2 mV/ C for low substrate doping levels.
As temperature rises, increased carrier generation reduces the depletion region width, leading to a
lower threshold voltage.

4.3 Conclusion
The threshold voltage is a key parameter in MOS transistor operation, determining when the
device transitions from the off-state to conduction.

It depends on material properties, doping levels, and external bias conditions, and exhibits
temperature sensitivity that must be considered in circuit design.

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VLSI Design and Testing 5 Threshold Voltage Adjustment

5 Threshold Voltage Adjustment

The native (original) threshold voltage (Vt) of an MOS transistor may not always be suitable
for a given application.

Therefore, it is often necessary to adjust Vt to achieve desired device characteristics.

Two common techniques used for threshold voltage adjustment are:
1. Varying the doping concentration at the silicon-insulator interface through
ion implantation.
2. Using different insulating materials for the gate dielectric.

5.1 Ion Implantation for Threshold Voltage Control

One effective method to modify the threshold voltage is through ion implantation, which
alters the doping concentration at the silicon-insulator interface.
This technique allows precise control over Vt by introducing dopant atoms into the channel
region.

5.2 Using Different Gate Insulating Materials

Another approach to adjusting the threshold voltage is by modifying the gate dielectric
material.
Instead of using only silicon dioxide (SiO2), a combination of silicon nitride (Si3N4) and silicon
dioxide can be used.

– Silicon nitride (Si3N4) has a relative permittivity of 7.5.

– Silicon dioxide (SiO2) has a relative permittivity of 3.9.
– When a layer of silicon nitride is combined with a layer of silicon dioxide, the resulting
effective permittivity is about 6.
Since the effective permittivity of the dual-dielectric structure is higher than that of SiO 2
alone, the dual-layer dielectric is electrically equivalent to a thinner SiO2 layer of the same
physical thickness.
This reduces the required gate voltage to achieve inversion, effectively lowering Vt.

5.3 Preventing Unwanted Inversion

To ensure that the silicon surface does not invert in regions between transistors, the threshold
voltage in these field regions is increased by:
Heavily doped diffusions.

Ion implantation into the silicon surface.

Increasing the oxide layer thickness in these regions.

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VLSI Design and Testing 6 Body Effect

5.4 Self-Isolation of MOS Transistors

MOS transistors are inherently self-isolating as long as:

The silicon surface inverts under the gate.

The surface does not invert in the regions between transistors under normal circuit voltage
conditions.

5.5 Conclusion
Threshold voltage adjustment is an essential technique in MOS transistor design, allowing
fine-tuning of device performance.

Ion implantation and high-permittivity gate dielectrics provide effective means to control Vt,
ensuring proper operation and isolation between transistors in integrated circuits.

6 Body Effect
In MOSFETs, the body effect (also known as the substrate bias effect) occurs when the
voltage difference between the source and substrate (Vsb) affects the threshold voltage
(Vt).

This effect becomes significant in circuits where multiple transistors are connected in series,
such as in CMOS logic gates, because the substrate voltage is usually common for all
transistors.

6.1 Common Substrate and its Impact

d2
g2

s2 Vsb2 ̸= 0
Vt2 > Vt1
d1
Vt2 g1

Vt1 s1 Vsb1 = 0

Figure 6: The effect of body effect on series connected transistors

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VLSI Design and Testing 6 Body Effect

In most MOS circuits, all transistors share a common substrate.

Under normal conditions, the substrate voltage remains the same for all transistors.

However, in certain configurations — especially when multiple MOSFETs are connected in

series — this assumption no longer holds.

Consider a chain of MOSFETs connected in series, as shown in figure above.

The first transistor in the series may have its source directly connected to ground, leading to a
source-to-substrate voltage of zero (Vsb1 = 0).

However, for the second transistor in the series, its source is connected to the drain of the first
transistor, which is at a higher potential.
This results in a nonzero source-to-substrate voltage (Vsb2 ̸= 0).
As we move along the series chain, Vsb continues to increase.

6.2 How the Body Effect Alters the Threshold Voltage

The threshold voltage of a MOSFET is the minimum gate-to-source voltage (Vgs) required
to form a conductive channel between the source and drain.

Under normal conditions, when Vgs > Vt, a channel is formed, and charge carriers (electrons
in nMOS or holes in pMOS) flow from the source to the drain.

When Vsb increases, it affects the depletion region at the substrate-channel junction:

– The depletion layer width increases.

– More charge carriers get trapped in the depletion layer.
– To maintain charge neutrality, the available channel charge decreases.

Since the channel charge is reduced, the gate must apply more voltage to invert the channel.

This means that the threshold voltage (Vt) increases, making it harder to turn the transistor
ON.

This phenomenon is called the body effect.

6.3 Mathematical Expression for the Body Effect

The modified threshold voltage in the presence of a nonzero Vsb can be approximated using the
following equation:
√
where: Vt = Vt(0) ± γ Vsb (3)

Vt(0) is the threshold voltage when Vsb = 0 (i.e., when the source and substrate are at the
same potential).

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VLSI Design and Testing 7 MOS Device Design Equations

γ is the body-effect coefficient, which depends on substrate doping. Typical values range
from 0.4 to 1.2.
Vsb is the source-to-substrate voltage.
The negative sign is used for pMOS transistors because their substrate is typically at a
higher potential than the source.
This equation shows that as Vsb increases, the threshold voltage Vt also increases, making the
MOSFET less conductive.

6.4 Impact of the Body Effect on Circuit Performance

The increase in Vt due to the body effect has several consequences on circuit behavior:
Reduced Drain Current (ID)
Slower Switching Speeds
Design Considerations for CMOS Technology

6.5 Conclusion
The body effect plays a crucial role in MOSFET operation, particularly in
series-connected transistors where Vsb is nonzero.
It leads to an increase in the threshold voltage, which in turn reduces the drain current
and slows down circuit operation.
Understanding and managing this effect is essential in CMOS circuit design, especially in
high-speed and low-power applications.

7 MOS Device Design Equations

MOS transistors operate in three distinct regions, each governed by specific design equations:
1. Cut-off Region
2. Linear (Triode) Region
3. Saturation (Active) Region
Before going into the equations, let us establish few important concepts.

7.1 Important Concepts

7.1.1 Geometric terms:
Consider the diagram given below.
The channel length is represented by L.
The channel width is represented by W.

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VLSI Design and Testing 7 MOS Device Design Equations

Figure 7: Geometric terms in the MOS device equations

7.1.2 MOS Gain Factor (β)

The MOS gain factor is defined as:
µCoxW (4)
β= L
where:

µ = Effective carrier mobility

εox
Cox = = Gate oxide capacitance per unit area
tox
tox = Gate oxide thickness

W = Channel width

L = Channel length

A typical calculation for an nMOS device:

500 × (4 × 8.85 × 10 )W
−14
2
β= ≈ 35µA/V
5 × 10−5L
7.1.3 Process Gain Factor (Kp)
µϵox
Kp = is known as the process gain factor.
tox
It is a key SPICE model parameter.
Typical values: 10 to 30 µA/V 2, with a variation of 10 − 20%.

7.1.4 The carrier mobility (µ)

The mobility, µ, describes the ease with which carriers drift in the substrate material.

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VLSI Design and Testing 7 MOS Device Design Equations

It is defined by:
average carrier drift velocity(v)
µ= (5)
Electric Field (E)
If the velocity (v) is given in cm/sec. and the electric field (E) in V/cm, the mobility has
dimensions of cm2/V − sec.

7.1.5 Threshold Voltage and Body Effect

A more accurate expression for the threshold voltage is:
√ √
Vt = Vt0 + γ VSB + 2ϕF − 2ϕF (6)

where:
Vt0 = Threshold voltage at VSB = 0
γ = Body-effect coefficient
VSB = Source-to-body voltage
ϕF = Fermi potential
The body-effect coefficient is given by:
tox √
γ= 2qϵ N (7)
Si
ϵox
where:
q = Charge of an electron
N = Concentration density of the substrate
Cox = Gate oxide capacitance
εsi = Dielectric constant of silicon substrate

7.1.6 Short-Channel Effects and Channel Length Modulation

The effective channel length is:
Leff = L − ∆L (8)
where ∆L accounts for channel reduction at high VDS.
This reduces output resistance and increases drain conductance.

7.2 Regions of MOS Transistor Operation

7.2.1 Cut-off Region (VGS < Vt)
The MOS transistor is off, and there is no conduction between drain and source (IDS ≈ 0).
A small leakage current exists.

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VLSI Design and Testing 8 V-I Characteristics

7.2.2 Linear Region (0 < VDS < VGS − Vt)

The MOSFET behaves like a voltage-controlled resistor.
The drain current is given by:

IDS = β (VGS 1
— Vt) VDS − βV 2 (9)
2 DS
7.2.3 Saturation Region (VDS > VGS − Vt)
The MOSFET is fully on and behaves like a constant current source.
The drain current is:
IDS = 1β (V — Vt)2 (10)
GS
2
The above equation assumes that the current in the channel saturates (i.e., is constant) and is
independent of the applied drain voltage.
In practice, the drain current in saturation increases slightly with increasing drain voltage.
This phenomenon is called the channel length modulation
A more accurate model accounting for channel length modulation is:
I = 1β (V — V )2 (1 + ) (11)
λV
DS GS t DS
2
7.3 Application to PMOS Devices
The same equations apply to PMOS transistors.
The only difference is the signs of voltages and currents:
– For nMOS: VGS, VDS, IDS are positive.
– For pMOS: VGS, VDS, IDS are negative.

7.4 Summary
MOS transistors operate in cut-off, linear, and saturation regions.
The MOS gain factor depends on mobility, oxide capacitance, and device geometry.
Body effect influences Vt, which must be considered in design.
Channel length modulation affects IDS in saturation.
PMOS equations are the same as nMOS but with reversed signs.

8 V-I Characteristics
The voltage-current (V -I) characteristics of n-channel and p-channel MOSFETs in both

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VLSI Design and Testing 8 V-I Characteristics

the linear and saturation regions describe how the drain current IDS varies with the
applied drain-to-source voltage VDS and gate-to-source voltage VGS.

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VLSI Design and Testing 8 V-I Characteristics

In figure below, the characteristics are plotted using the absolute values of the voltages so
that both n-type and p-type transistors can be represented on the same axes.

Figure 8: V-1 characterlstics for n- and p-transistors

The boundary between the linear and saturation regions is determined by the condition:
VDS = VGS − Vt (12)
where Vt is the threshold voltage.
This boundary appears as a dashed line in the characteristic curves.

8.1 Output Resistance in the Linear Region

In the linear region, the MOSFET behaves as a voltage-controlled resistor.
The output resistance (also known as channel resistance Rc) can be derived by
differentiating the drain current equation with respect to VDS.
The resulting output conductance is given by:
lim dIDS
dVDS = β(VGS — Vt) (13)

Rearranging the above equation, the channel resistance Rc is approximated as:

1
Rc = (14)
β(VGS — Vt)
This equation shows that the resistance of the MOSFET channel is controlled by the
gate-to-source voltage VGS.

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 VLSI Design and Testing 8 V-I Characteristics

Note: The above relation is valid as long as carrier mobility remains constant in the
channel.

8.2 MOSFET Behavior in the Saturation Region

In the saturation region (VDS ≥ VGS − Vt), the MOSFET behaves like a constant current
source rather than a variable resistor.

From the MOSFET current equation in saturation:

1
IDS = β(VGS — Vt)2 (15)
2
it can be seen that drain current IDS is nearly independent of VDS.

This can be verified by differentiating IDS with respect to VDS:

dIDS
≈0 (16)
dVDS

Since the derivative is nearly zero, the drain current remains constant despite changes in VDS.

This is a key property of MOSFETs used as current sources in analog circuits.

8.3 Transconductance (gm)

Transconductance (gm) is a key parameter that defines the gain of a MOSFET.

It expresses the relationship between the output current (IDS) and the input voltage (VGS):

dIDS
g
m = dVGS (17)
VD =constant
S

This parameter determines how efficiently the MOSFET converts a voltage signal at the gate
into a current signal at the drain.

8.3.1 Transconductance in the Linear and Saturation Regions

1. Linear Region:
gm = βVDS (18)
This equation shows that in the linear region, transconductance is directly proportional to
VDS.

2. Saturation Region:
gm = β(VGS − Vt) (19)
In the saturation region, transconductance depends only on (VGS − Vt), meaning the
MOSFET behaves like an amplifier with a gain controlled by VGS.

For a p-type transistor, absolute values are used for voltages to ensure that transconductance
remains positive.

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VLSI Design and Testing 9 The CMOS inverter DC Characteristics

8.4 Key Takeaways

MOSFETs have distinct operating regions: Linear (resistive) and Saturation (current
source).
The boundary between these regions is at VDS = VGS − Vt.
Channel resistance Rc is controlled by VGS and is inversely proportional to (VGS − Vt).
In saturation, IDS is almost independent of VDS, making the MOSFET suitable for
amplification.

Transconductance gm determines MOSFET gain, with different expressions in linear

and saturation regions.

9 The CMOS inverter DC Characteristics

A CMOS inverter is shown below:

VDD
S p-Device
G

D
D
Vin G Vo

S n-Device

Figure 9: A CMOS inverter (with substrate connections)

The threshold voltage of n - channel device is Vtn.

The threshold voltage of p - channel device is Vtp. Vtp is negative.

As the source of the nMOS transistor is grounded,

Vgsn = Vin and Vdsn = Vout

As the source of the pMOS transistor is tied to VDD,

Vgsp = Vin − VDD and Vdsp = Vout − VDD

The various regions of operations for the n - and p - transistors are shown in table below.

For simplicity, assume Vtp = −Vtn

and also assume that the pMOS transistor is 2–3 times as wide as the nMOS transistor, so
βn = βp

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VLSI Design and Testing 9 The CMOS inverter DC Characteristics

Table 1: Relationships between voltages for the three regions of operation of a CMOS inverter

Cutoff Linear Saturation

Vgsn > Vtn Vgsn > Vtn
Vgsn < Vtn Vin > Vtn Vin > Vtn
nMOS
Vin < Vtn Vdsn < Vgsn − Vtn Vdsn > Vgsn − Vtn
Vout < Vin − Vtn Vout > Vin − Vtn
Vgsp < Vtp Vgsp < Vtp
Vgsp > Vtp Vin < Vtp + VDD Vin < Vtp + VDD
pMOS
Vin > Vtp + VDD Vdsp > Vgsp − Vtp Vdsp < Vgsp − Vtp
Vout > Vin − Vtp Vout < Vin − Vtp

The characteristics of Idsn and Idsp in terms of Vdsn and Vdsp for various values of Vgsn and Vgsp
can be drawn as:

Figure 10: I - V characteristics of CMOS inverter

Figure below shows the same plot of Idsn and |Idsp| now in terms of Vout for various values of
Vin.

Figure 11: Idsn and |Idsp| in terms of Vout for various values of Vin

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VLSI Design and Testing 9 The CMOS inverter DC Characteristics

The possible operating points of the inverter are the values of Vout where Idsn = |Idsp| for a
given value of Vin.
These operating points are plotted on Vout vs. Vin axes to show the inverter DC transfer
characteristics.

Figure 12: DC transfer characteristics of CMOS inverter

The operation of the CMOS inverter can be divided into five regions A, B, C, D and E. The
state of each transistor in each region is shown in table below.

Table 2: Summary of CMOS inverter operation

Region Condition p-device n-device Output

A 0 ≤ Vin < Vtn Linear Cutoff Vout = VDD
B Vtn ≤ Vin < VDD/2 Linear Saturated Vout > VDD/2
Vout
C Vin = VDD/2 Saturated Saturated
drops sharply
VDD/2 < Vin ≤
D Saturated Linear Vout < VDD/2
VDD − |Vtp|
E Vin > VDD − |Vtp| Cutoff Linear Vout = 0

Regions of Operation
Region A: Vin < Vtn
NMOS: Cut-off (Idsn = 0)
PMOS: Linear region
Output: Vo = VDD The PMOS is fully on, pulling the output to VDD, while the NMOS is off.

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 VLSI Design and Testing 9 The CMOS inverter DC Characteristics

Region B: Vtn < Vin < VDD

2

NMOS: Saturation

PMOS: Linear region

Output: Vo decreases as Vin increases. The NMOS starts to conduct, and the PMOS is still in
the linear region, causing the output voltage to drop gradually.
The saturation current for the NMOS is given by:

I = 1β (V
— V )2
dsn n in tn
2
The output voltage in this region can be expressed as:
βn
Vo = VDD — βp (Vin — Vtn)2

VDD
Region C: Vin ≈ 2

NMOS: Saturation

PMOS: Saturation

Output: High gain region. Both transistors are in saturation, leading to a steep transition
where a small change in Vin results in a large change in Vo. This region is critical for the
inverter’s switching behavior.
The saturation currents for the NMOS and PMOS are given by:

I = 1β (V
— V )2
dsn n in tn
2
I = 1β (V − V — V )2
dsp p in DD tp
2
VDD
At the switching point (Vin = ), the output voltage is:
2
VDD
V =
o 2
VDD < Vin < VDD − |Vtp|
Region D: 2

NMOS: Linear region

PMOS: Saturation

Output: Vo continues to decrease as Vin increases. The NMOS is now in the linear region,
and the PMOS is in saturation, pulling the output closer to GND.
The output voltage in this region is given by:
βp VDD
V = (V —
o
βn in
24
VLSI Design and Testing 9 The CMOS inverter DC Characteristics

— Vtp)2

25
 VLSI Design and Testing 10 Influence of βn/βp ratio on transfer characteristics

Region E: Vin > VDD − |Vtp|

NMOS: Linear region

PMOS: Cut-off (Idsp = 0)

Output: Vo = 0 The NMOS is fully on, pulling the output to GND, while the PMOS is off.

Key Points
Switching Point: The switching point of the CMOS inverter is typically designed to be at
VDD
. This ensures a balanced transition between high and low states, maximizing noise
2
margins.
Current Spike: During the transition region (Region C), both transistors are momentarily
on, leading to a short current spike from the power supply. This is known as short-circuit
current and is a consideration in power dissipation.

Steep Transition: The CMOS inverter exhibits a very steep transition between high and low
states. This is desirable for digital circuits as it provides good noise immunity and a clear
distinction between logic levels.

Noise Margins: The steep transition also contributes to high noise margins, making CMOS
inverters robust against noise and variations in supply voltage.

10 Influence of βn/βp ratio on transfer characteristics

Figure 13: Influence of βn/βp on inverter DC transfer characteristic

. 26
VLSI Design and Testing 10 Influence of βn/βp ratio on transfer characteristics

The voltage transfer characteristic (VTC) of a CMOS inverter depends on the ratio of the
electron to hole mobility factors, βn/βp.

The gate threshold voltage Vinv is defined by the condition:

Vin = Vout (20)

This threshold voltage varies with βn/βp.

The transfer characteristic shifts as this ratio changes.

Specifically, as βn/βp decreases, the transition region moves from left to right.

However, the output voltage transition remains sharp, ensuring that the switching
performance is not affected.

This behavior contrasts with an nMOS inverter, where the transition gain strongly depends on
the ratio of the pull-up (load) and pull-down (driver) transistors.

10.1 Adjusting βn/βp Through Channel Dimensions

For a given semiconductor fabrication process, βn/βp can be modified by adjusting the channel
dimensions—specifically, the channel length L and width W of the MOS transistors.

A balanced design, where:

βn
= 1 (21)
βp
is often desirable.

This ensures that a capacitive load charges and discharges in equal time intervals, providing
equal current source and sink capabilities.

10.2 Temperature Dependence of Transfer Characteristics

Temperature variations influence the effective carrier mobility in MOS transistors, which in
turn affects β.

As temperature increases, carrier mobility decreases, leading to a reduction in β.

The dependence of β on temperature T can be expressed as:

β ∝ T−3/2 (22)
Therefore
Ids ∝ T−3/2 (23)

Since both electron and hole mobilities are affected similarly by temperature, the ratio βn/βp
remains approximately constant.

However, the threshold voltages (Vtn and Vtp) decrease with temperature.

. 27
VLSI Design and Testing 11 Noise Margin

This causes the extent of region A in the transfer characteristic to reduce, while region E
expands.

Consequently, the overall transfer curve shifts to the left as temperature increases.

For instance, if the temperature rises by 50 C, the threshold voltages decrease by

approximately 200 mV each, leading to a 0.4 V shift in the input threshold.

10.3 Conclusion
The βn/βp ratio influences the position of the transition region in the transfer characteristic of
a CMOS inverter but does not degrade switching performance.

Temperature variations cause a leftward shift in the VTC due to the reduction in threshold
voltages, though the βn/βp ratio itself remains relatively stable.

11 Noise Margin
Noise margin allows us to determine the allowable noise voltage on the input of a gate so that
the output will not be corrupted.

Figure 14: Noise margin definitions

The LOW noise margin, NML, is defined as the difference in maximum LOW input voltage
recognized by the receiving gate and the maximum LOW output voltage produced by the
driving gate.
NML = VIL − VOL (24)
The high noise margin, NM H , is the difference between the minimum HIGH output voltage of
the driving gate and the minimum HIGH input voltage recognized by the receiving gate.
NMH = VOH − VIH (25)
Where-

28
VLSI Design and Testing 12 Alternate CMOS Inverters

VIH = minimum HIGH input voltage

VIL = maximum LOW input voltage
VOH = minimum HIGH output voltage
VOL = maximum LOW output voltage

For an ideal inverter:

VOH = VDD
VIH VDD
= 2
VOL = GND
VIL VDD
= 2

Hence for an ideal inverter:

V
NML = NMH ≡ 2DD (26)

12 Alternate CMOS Inverters

12.1 Pseudo-nMOS Inverter

VDD

V
out
Vin

Figure 15: Pseudo-nMOS Inverter

A pseudo-nMOS inverter is a variation of the standard CMOS inverter, where the pMOS
pull-up transistor has its gate permanently grounded.

This design is similar to using a depletion-mode transistor as a load in nMOS logic.

12.1.1 Characteristics
Unlike a complementary CMOS inverter, this circuit dissipates DC power whenever the
nMOS pull-down transistor is turned on.

The transfer characteristic of the inverter depends on the ratio βn/βp, affecting both the
output low voltage (VOL) and the switching threshold.

29
VLSI Design and Testing 12 Alternate CMOS Inverters

Figure 16: DC transfer characteristics of Pseudo-nMOS Inverter

12.2 Cascaded Pseudo-nMOS Inverters

To analyze signal integrity in pseudo-nMOS inverters, consider two such inverters
connected in series.

Cascading inverters without signal degradation requires that the output of one inverter
should be a valid input level for the next inverter.

This leads to the condition:

VO = Vin = Vinv
where Vinv is the inverter threshold voltage.

VDD

Vo

Figure 17: Cascaded Pseudo-nMOS Inverter

30
VLSI Design and Testing 12 Alternate CMOS Inverters

12.2.1 Inverter Threshold Voltage (Vinv)

For equal noise margins, the threshold voltage should be set at approximately:

Vinv ≈ 0.5VDD
At this operating point:
The nMOS transistor (pull-down) operates in saturation
0 < Vinv − Vtn < Vdsn

The pMOS transistor (pull-up) operates in linear mode

0 < Vdsp < −Vtp

12.2.2 β-Ratio Calculation

From the MOSFET current equations:
For the nMOS transistor in saturation mode:
I = 1β (V — V )2
dsn n inv tn
2
For the pMOS transistor in linear mode:
Idsp = βp(VDD − Vinv)Vinv

Equating the currents:

1β (V — V )2 = β —V )V
(V
n inv tn p DD inv inv
2
Solving for the β-ratio:
βn 2Vinv(VDD − Vinv)
β = (Vinv − Vtn)2
p

For VDD = 5V and typical values Vinv = 0.5VDD, Vtn = 0.2VDD, we obtain:

βn
≈3
βp
A 4 : 1 ratio can be used for slightly lower noise immunity, following a common nMOS design
rule.

12.2.3 Effect of Cascading

If the βn/βp ratio is too small, signal levels degrade, causing unreliable logic transitions.
A higher ratio ensures faster switching and better signal integrity across multiple stages.
Proper β-ratio selection allows cascaded inverters to maintain sharp logic transitions
without excessive power dissipation.

31
VLSI Design and Testing 12 Alternate CMOS Inverters

12.2.4 Applications
Cascaded pseudo-nMOS inverters are used in:

Precharge logic circuits

Memory cell designs (e.g., ROMs, PLAs)

High-density nMOS-dominated logic circuits

12.3 CMOS Tri-State Inverter

VDD

CL

A Z

CL

Figure 18: CMOS Tri - State Inverter

A tri-state inverter introduces a control mechanism, allowing the output to be either active
(logic high/low) or in a high-impedance (Z) state.

12.3.1 Functionality
When CL = 0, the output is in a high-impedance (Z) state (not driven by the input A).

When CL = 1, the output follows the input A (acting as a regular inverter).

12.3.2 Performance Considerations

For equal-sized nMOS and pMOS transistors, the tri-state inverter is approximately half
the speed of a standard CMOS inverter.

12.3.3 Applications
The tri-state inverter is widely used in:

Clocked logic circuits

32
VLSI Design and Testing 13 Transmission gate DC characteristics

Latches and multiplexers

I/O structures

12.4 Summary

Inverter Type Advantages Disadvantages Common Applica-

tions
Pseudo-nMOS In- High transistor den- Dissipates static Static ROMs, PLAs
verter sity, simple design power
Cascaded Pseudo- Improved logic transi- Requires careful β- Precharge logic, Mem-
nMOS Inverters tions, compact design ratio selection ory cells
CMOS Tri-State In- Enables bus sharing, Slower than standard Latches, Multiplexers,
verter supports clocked logic CMOS inverter I/O structures

These inverters are essential in low-power, high-density digital circuits, where trade-offs
between power consumption, speed, and circuit complexity must be carefully considered.

13 Transmission gate DC characteristics

A transmission gate is a complementary switch that consists of an n-channel MOS (nMOS)
transistor and a p-channel MOS (pMOS) transistor connected in parallel.

Each transistor has separate gate connections but shares common source and drain terminals.
The control signal ϕ is applied to the gate of the nMOS transistor, while its complement
ϕ¯ is applied to the gate of the pMOS transistor.

Vin Vo

Figure 19: Transistor connection for CMOS transmission gate

13.1 nMOS Pass Transistor Characteristics

The behavior of an nMOS transistor as a pass transistor can be analyzed in two cases:

33
VLSI Design and Testing 13 Transmission gate DC characteristics

Vo
Vin
Vgs
CL

Figure 20: nMOS Transistor in transmission gate

Case I: Transmission of Logic ‘1’ (Vin = VDD)

Initially, the load capacitor CL is discharged (VO = 0).

When Vin = 1 and ϕ = 1, the nMOS transistor turns on and starts charging the capacitor.
Current flows until VO approaches VDD − Vt, where Vt is the threshold voltage.
Since VO is limited to VDD − Vt, the transmission of logic ‘1’ is degraded.

Case II: Transmission of Logic ‘0’ (Vin = 0)

When Vin = 0 and ϕ = 1, the nMOS transistor discharges the capacitor.

As VO approaches 0V, the current diminishes.

Logic ‘0’ is transmitted accurately.

13.2 pMOS Pass Transistor Characteristics

Vo
Vin
Vgs
CL

Figure 21: pMOS Transistor in transmission gate

Similarly, for a pMOS transistor, the behavior of a pMOS transistor as a pass transistor can be
analyzed in two cases:

Case I: Transmission of Logic ‘1’ (Vin = VDD)

Initially, the load capacitor CL is discharged (VO = 0).

34
VLSI Design and Testing 13 Transmission gate DC characteristics

When Vin = 1 and ϕ¯ = 0, the pMOS transistor turns on and starts charging the capacitor.

Current flows until VO approaches VDD, meaning the transmission of logic ‘1’ is strong and
accurate.

Case II: Transmission of Logic ‘0’ (Vin = 0)

When Vin = 0 and ϕ¯ = 0, the pMOS transistor turns on, allowing the capacitor to discharge.

As VO approaches Vt, where Vt is the threshold voltage, the transistor ceases conduction.

Since VO is limited to Vt, the transmission of logic ‘0’ is degraded.

Table 3: Transmission characteristics of n-channel and p-channel pass transistors

Device Transmission of ‘1’ Transmission of ‘0’

n poor good
p good poor

13.3 Combining nMOS and pMOS — The Transmission Gate

The transmission gate is a CMOS switch that combines an nMOS transistor and a pMOS
transistor in parallel to capitalize on their complementary strengths.

When these two transistors are combined:

– They ensure that both logic levels are transmitted without degradation.
– Both devices are controlled by complementary gate signals derived from a single control
signal ϕ.
– When ϕ = 1, both transistors turn ON, allowing the input Vin to be accurately
transferred to the output Vout.
– When ϕ = 0, both transistors are OFF, isolating the input from the output and
presenting a high impedance state.

The overall operation is shown in table below:

Table 4: Operation of a Transmission Gate

Control Signal nMOS pMOS Vin Vo

ϕ = 0, ϕ = 1 OFF OFF 0 Z (High Impedance)
ϕ = 0, ϕ = 1 OFF OFF 1 Z (High Impedance)
ϕ = 1, ϕ = 0 ON ON 0 0 (Strong)
ϕ = 1, ϕ = 0 ON ON 1 1 (Strong)

35
VLSI Design and Testing 14 Latch-up in CMOS

The corresponding output characteristic is shown in figure below.

Figure 22: Transmission gate output characteristic

14 Latch-up in CMOS
Latch-up is a parasitic circuit effect that causes a low-resistance path between power supply
rails (VDD and VSS) in CMOS circuits.

This results in excessive current flow, leading to circuit failure or permanent damage.

Early CMOS processes were highly susceptible to latch-up, but modern fabrication techniques
and circuit design strategies have significantly mitigated this issue.

14.1 Mechanism of Latch-up

Latch-up occurs due to the presence of parasitic bipolar junction transistors (BJTs)
within the CMOS structure.

These unintended transistors can form a positive feedback loop, causing a short circuit
between VDD and VSS.

14.1.1 Parasitic Bipolar Transistor Formation

A CMOS structure consists of nMOS transistors in a p-well and pMOS transistors in an n-substrate.
Two parasitic bipolar transistors—npn and pnp—are inadvertently formed:

The npn transistor consists of:

– Emitter: n+ source/drain of nMOS

– Base: p-well
– Collector: n-substrate

36
 VLSI Design and Testing 14 Latch-up in CMOS

The pnp transistor consists of:

– Emitter: p+ source/drain of pMOS

– Base: n-substrate
– Collector: p-well

Figure 23: Source of latch-up In CMOS

14.1.2 Latch-up Condition

Latch-up occurs when:

1. Excess carrier injection: Voltage spikes or transient currents inject minority carriers into
the substrate or well.

2. Voltage drop across Rs and Rw: If sufficient voltage develops, it can forward bias the
base-emitter junctions of the parasitic transistors.

3. Positive feedback activation: The feedback loop between the npn and pnp transistors
sustains the low-resistance state.

14.2 Preventive Measures

To prevent latch-up, the following design strategies are implemented:

37
VLSI Design and Testing 14 Latch-up in CMOS

14.2.1 Substrate and Well Contacting

Every well should have a substrate contact.

Substrate contacts should be directly connected to supply pads using metal.

Contacts should be placed close to transistor source connections to reduce resistance.

14.2.2 Transistor Placement Guidelines

Maintain separation between nMOS and pMOS devices.

Group nMOS transistors closer to VSS and pMOS transistors closer to VDD.

Avoid checkerboard-style layouts.

14.2.3 I/O Structure Design

Use guard rings (p+ around nMOS, n+ around pMOS).

Employ minimum-area p-wells to reduce photocurrent injection.

Hard-wire the p-well to ground (via p+ contact).

Reduce spacing between p-well and nMOS source contact.

14.3 Conclusion
Modern CMOS processes incorporate design strategies such as proper substrate contacting,
optimized transistor placement, and structured I/O design to ensure latch-up immunity.

By following these best practices, latch-up failures can be minimized.

38