, . .

, commodore MPS

~ aamicanduct:or group 6522

VERSATILE

~UYAJ@@ INTERFACE
ADAPTER

6522 VERSATILE INTERFACE ADAPTER

DESCRIPTION

The 6522 Versatile Interface Adapter (VIA) provides all of the capability of the 6520.1 n addition, this
device contains a pair of very powerful interval timers, a serial-to-parallellparallel-to-serial shift
register and input data latching on the peripheral ports. Expanded handshaking capability allows
control of bi-directional data transfers between VIA's in multiple processor systems.

Control of peripheral devices is handled primarily through two 8-bit bi-directional ports. Each of
these lines can be programmed toactaseitheran inputoran output.Also, several peripheralI/O lines
can be controlled directly from the interval timers for generating programmable-frequency square
waves and for counting externally generated pulses. To facilitate control of the many powerful
features of this chip, the internal registers have been organized into an interrupt flag register, an
interrupt enable register and a pair of function control registers.

FEATURES
• Very powerful expansion of basic 6520 capability. 6522
• N channel, depletion load technology, single +5V supply.
• Completely static and TIL compatible. vSS CA1
• CMOS compatible peripheral control lines. PAO CA2
• Expanded "handshake" capability allows very positive PA1 RSO
control of data transfers betvoJeen processor PA2 RS1
and peripheral devices. PA3 RS2
PA4 RS3
PA5 RES
PA6 DO
6522 Interface Diagram PA7 01
PBO 02
PB1 03
PB2 04
8 Bit
Data Bus
--.. Control PB3 05
PB4 06
R/W 8 Bi: PB5 07
To Clock Port To PB6
6522 Peripheral
¢2
650X PB7 CS1
Register 8 Bit Devices
& Chip Port
CB1 CS2
Selects CB2 R/W
Control VCC IRQ
IRQ

2-50
 MPS
6522
INTERRUPT
CONTROL
INPUT
FlAB!
IIFRI
_ ~1!H_
DATA OUTPUT PORT
IUS ENABLE loRAI A
IIERI DATA OIR.
100RA
PORT A
REGISTERS

CAl
PORT A
CA2
R/W FUNCTION PORT B
CONTROL
CLK HANDSHAKE
CONTROL
CSI
CBI

I
ffi
CBl
RSO
RII PORT B REGISTERS

RSZ INPUT LATCH

RI3 OUTPUT 1/"'"---....1 BUFFERS PORT

IOABI IPBI B
DATA OIR.
100RBI

Figure 1. 6522 Block Diagram

PROCESSOR INTERFACE 4. Read/Write Line (R/W)

This section contains a description of the buses and control The direction of data transfers ,between the 6522 and the
lines which are used to interface the 6522 to the system system processor is controlled by the R/W line. If R/W is low,
processor. AC and DC parameters associated with this inter- data will be transferred out of the processor into the selected
face are specified on pages 21 through 24 of this document. 6522 register (write operation). If R/W is high and the chip is
1. Phase Two Clock «(J'2) selected, data will be transferred out of the 6522 (read operation).
Data transfers between the 6522 and the system processor 5. Data Bus (OBo-OB7)
take place only while the Phase Two Clock is high. In addition, The 8 bi-directional data bus lines are used to transfer data
;j2 acts as the time base for the various timers, shift registers, between the 6522 and the system processor. The internal
etc. on the chip. drivers will remain in the high-impedance state except when the
2. Chip Select Lines (CS1 , CS2) crip is selected (CS1 = 1 ,CS2 = 0), Read/Write is high and the
The two chip select inputs are normally connected to Phase Two Clock is high. At this time, the contents of the
processor address lines either directly or through decoding. selected register are placed on the data bus. When the chip is
The selected 6522 register will be accessed when CS1 is high selected, with Read/Write low and,02 = 1, the data on the data
and CS2 is' low. bus will be transferred into the selected 6522 register.

3. Register Select Lines (RSO, RS1, RS2, RS3) 6. Reset (RES)

The four Register select lines are normally connected to the The Reset input clears all internal registers to logic 0 (except
processor address bus lines to allow the processor to select the T1, T2 and SR). This places all peripheral interface lines in the
internal 6522 register which is to be accessed. The sixteen input state, disables the timers, shift register, etc. and disables
possible combinations access the registers as follows: interrupting from the chip.

RS3 RS2 RS1 RSO Register Remarks RS3 RS2 RS1 RSO Register Remarks
L L L L ORB H L L L T2L-L Write Latch
L L L H ORA T2C-L Read Counter
Controls
Handshake H L L H T2C-H Triggers T2L-LJ
L L H L DDRB T2C-L Transfer

L L H H DDRA H L H L SR

L H L T1L-L H L H H ACR
L Write Latch
T1C-L Read Counter H H K K PCR
L H H L T1C-H H H L H IFR
Trigger T1 L-LJ
H H H IER
T1 Col Trans!.
L H H L T1L-L H H H H ORA No Effect
on Handshake
L H H H T1L-H
Note. L - D.4V DC, H - 2.4V DC.

2-51
 MPS
6522
7. Interrupt Request (IRQ)
The Interrupt Request output goes low whenever an internal Register. These lines represent one standard TI~ load in the
interrupt flag is setand the corresponding interrupt enable bit is input mode and will drive one standard TIL load In the output
a logic 1. This output is "open-drain" to allow the interrupt mode. In addition, they are capable of sourcing 1.0 ma at 1.5
request signal to be "wire-or'ed" with other equivalent signals in VDC in the output mode to allow the outputs to directly drive
the system. Darlington transistor switches.
PERIPHERAL INTERFACE
6522 OPERATION
This section contains a brief description of the buses and
This section contains a discussion of the various blocks of
control lines which are used to drive peripheral devices under
logic shown in Figure 1.ln addition, the internal operation of the
control of the internal 6522 registers.
6522 is described in detail.
1. Peripheral A Port (PAo-PA7)
A. Data Bus Buffers (DB), Peripheral A Buffers (PA),
The Peripheral A port consists of a lines which can be
Peripheral B Buffers (PB)
individually programmed to act as an input or an output under
The characteristics of the buffers which provide the required
control of a Data Direction Register. The polarity of output pins
voltage and current drive capability were discussed in the
is controlled by an Output Register and input data can be
previous section. AC and DC parameters fOl these buffers are
latched into an internal register under control of the CA 1 line. All specified on pages 21 through 24 of this document.
of these modes of operation are controlled by the system
processor through the internal control registers. These lines B. Chip Access Control
represent one standard TIL load in the input mode and will The Chip Access Control contains the necessary logic to
drive one standard TIL load in the output mode. detect the chip select condition and to decode the Register
Select inputs to allow acceSSing the desired internal register. In
2. Peripheral A Control Lines (CA1 , CA2) addition, the R/W and ~2 signals are utilized to control the
The two peripheral A control lines act as interrupt inputs or as direction and timing of data transfers. When writing into the
handshake outputs. Each line controls an internal interrupt flag
6522, data is first latched into a data input register during ~2.
with a corresponding interrupt enable bit. In addition, CA 1 Data is then transferred into the desired internal register dunng
controls the latching of data on Peripheral A Port input lines. 02 . Chip Select. This allows the peripheral I/O line to change
The various modes of operation are controlled by the system without "glitching." When the processor reads the 6522, data is
processor through the internal control registers. CA 1 is a high-
transferred from the desired internal register directly onto the
impedance input only while CA2 represents one standard TIL
Data Bus during 0'2.
load in the input mode. CA2 will drive one standard TIL load in
the output mode. C. Port A Registers, Port B Registers
Three registers are used in accessing each of the a-bit
3. Peripheral B Port (PBo-PB7)
peripheral ports. Each port has a Data Direction .Register
The Peripheral B port consists of a bi-directionallines which (DORA, DDRB) for specifying whether the peripheral pins are to
are controlled by an output register and a data direction reg ister
act as inputs or outputs. A 0 in a bit of the Data Direction
in much the same manner as the PA port. In addition, the Register causes the corresponding peripheral pin to act as an
polarity of the PB 7 output signa I can be controlled by one of the
input. A 1 causes the pin to act as an output.
interval timers while the second timer can be programmed to
Each peripheral pin is also controlled by a bit in the Output
count pulses on the PB6 pin. These lines represent one
Register (ORA, ORB) and an Input Register (IRA, IRB). When
standard TIL load in the input mode and will drive one standard
the pin is programmed to act as an output, the voltage on the pin
TIL load in the output mode. In addition, they are capable of
is controlled by the corresponding bit of the Output Register. A
sourcing 30 ma at 1.5 VDC in the output mode to allow the
1 in the Output Register causes the pin to go high, and a 0
outputs to directly drive Darlington transistor switches.
causes the pin to go low. Data can be written into Output
4. Peripheral B Control Lines (CB1, CB2) Register bits corresponding to pins which are programmed to
The Peripheral B control lines act as interrupt inputs or as act as inputs; however, the pin will be unaffected.
handshake outputs. As with CA 1 and CA2, each line controls Reading a peripheral port causes the contents of the Input
an interrupt flag with a corresponding interrupt enable bit. In Register (IRA, IRB) to be transferred onto the Data Bus. With
addition, these lines act as a serial port under control of the Shift input latching disabled, IRA will always reflect the data on the

+5 V +5 v

InpuVOutput~
Control :

'--_-+-........_ PAO-PA 7, PBO-PB7,

CA2 CB1, CB2

Output Data I

Input Data .......- - - - - - - - ' Input Data _ - - - - - - - - - - -

Figure 2. Peripheral Output Buffers

2-52
 MPS
6522
PA pins. With input latching enabled, IRA will reflect the generation of a "Data Taken" signal. The peripheral device
contents of the Port A prior to setting the CA 1 Interrupt Flag responds by making new data available. This process con-
(IFR1) by an active transition on CA1. tinues until the data transfer is complete.
The IRB register operates in a similar manner. However, for In the 6522, automatic "Read" handshaking is possible on
output pins, the corresponding I RB bit will reflect the contents the Perij2)heral A port only. The CA 1 interrupt input pin accepts
of the Output Register bit instead of the actual pin. This 'allows the "Data Ready" signal and CA2 generates the "Data Taken"
proper data to be read into the processor if the output pin is not signal. The Data Heady signal will set an internal flag which may
allowed to go to full voltage. With input latching enabled on Port interruptthe processor or which can be polled under software
B, setting CB 1 interrupt flag will cause I RB to latch this control. The Data Taken signal can be either a pulse or a DC
combination of input data and ORB data until the interrupt flag level which is set low by the system processor and is cleared by
is cleared. the Data Ready signal. These options are shown in Figure 3
O. Handshake Control which illustrates the normal Read Handshaking sequence.
The 6522 allows very positive control of data transfers
Write Handshake
between the system processor and peripheral devices through
The sequence of operations which allows handshaking data
the operation of "handshake" lines. Port A lines (CA1, CA2)
from the system processor to a peripheral device is very similar
handshake data on both a read and a write operation while the
to that described in Section A for Read Handshaking. However,
Port B lines (CB1, CB2) handshake on a write operation only.
for "Write" handshaking, the processor must generate the "Data
Read Handshake Ready" signal (through the 6522) and the peripheral device
Positive control of data transfers from peripheral devices into must respond with the "Data Taken" signal. This can be accom-
the system processor can be accomplished very effectively plished on both the PA port and the PB port on the 6522. CA2 or
using "Read" handshaking. In this case, the peripheral device CB2 acts as a Data Ready output in either the DC level or pulse
must generate "Data Ready" to signal the processor that valid mode and CA 1 or CB 1 accepts the "Data Taken" Signal from
data is present on the peripheral port. This signal normally the peripheral device, setting the interrupt flag and clearing the
interrupts the processor, which then reads the data, causing "Data Ready" output. This sequence is shown in Figure 4.

Data Available
(CAl)

IRQOutput l
~ ________________ ~r-

Read ORA _______________________ ~r__l~ _____________________

Operation 2
Data Taken-
Handshake M o d e - - - - - - - - - - - - - - - - - - ,
(CA2) '------------1
r---
Data Taken-
Pulse Mode L-1
(CA2) Notes:
1. Signals "data available" 10 the system processor.
2. R/W- l.~-O.CSl - l.RS3-0. RS2 -0. RSl -O.RSO- 1.

Figure 3. Read Handshake Timing Sequence

Phase Two Clock ~~~

Write ORA
Operation l ~~----------------------~~
Data Availabl&-
Handshake Mode
(CA2.CB2)
~ __________ ~r----

Data Available-
Pulse Mode
(CA2.CB2)
Data Taken
(CA1,CB1)

iFiQ Output2
~---- __________ ~r----
Notes:
1. R/W-O,CS2-0,CSl -l,RS3-0,RS2-0,RSl -0.RSO-1
2. Signals "data taken" to the system processor.

Figura 4. Write Handshake Timing Sequence

2-53
 MPS
6522
TIMER 1 TImer 1 Operating Modes
Introduction Two bits are provided in the Auxiliary Control Register to
Interval Timer T1 consists of two 8-bit latches and a 16-bit allow selection of the T1 operating modes. These bits and the
counter. The latches are used to store data which is to be four possible modes are as follows:
loaded into the counter. After loading, the counter decrements
ACR7 ACR6
at system clock rate, i.e., under control of the clock applied to Output "Free-Run"
the Phase Two input pin. Upon reaching zero, an interrupt flag Enable Enable Mode
will be set, and iTiQ will go low. The timer will then disable any 0 0 Generate a single time-out interrupt each time Tl is
further interrupts, or will automatically transfer the contents of loaded. PB7 disabled.
the latches into the counter and will continue to decrement. In 0 1 Generate continuous interrupts. PB7 disabled.
addition, the timer can be instructed to invert the output signal 1 0 Generate a single interrupt and an output pulse on PB7
on a peripheral pin each time it "times-out." Each of these for each Tl load operation.
modes is discussed separately below. 1 1 Generate continuous interrupts and a square wave
output on PB7.
Writing the Timer 1 Registers
The operations which take place when writing to each of the Timer 1 One-Shot Mode
four T1 addresses are as follows: The interval timer one-shot mode allows generation of a
single interrupt for each timer load operation. As with any
Transfer low order latch into low order interval timer, the delay between the "write T1 C-H" operation
and generation of the processor interrupt is a direct function of
RS3 RS2 RS1 RSO Operation (R/W = L) the data loaded into the timing counter. In addition to gener-
L H L L Write into low order latch. ating a single interrupt, Timer 1 can be programmed to produce
L H L H Write into high order latch. a single negative pulse on the PB7 peripheral pin. With the
Write into high order counter. output enabled (ACR&=1) a "write T1 C-H" operation will cause
Transfer low order latch into low order counter.
Reset Tl interrupt flag.
PB7 to go low. PB7 will return high when Timer 1 times out. The
H
result is a single programmable width pulse.
L H L Write low order latch.
L H H H Write high order latch. NOTE
Reset Tl interrupt flag. PB7 will act as an output if DDRB7 = 1 or if ACR7 = 1. However, if
Note that the processor does not write directly Into the low both DDRB7 and ACR7 are logic 1, PB7 will be controlled from Timer 1
order counter (T1 Col). I nstead, this half of the counter is loaded and ORB7 will have no effect on the pin.
automatically from the low order latch when the processor In the one-shot mode, writing into the high order latch has no
writes into the high order counter. In fact, it may not be effect on the operation of Timer 1. However, it will be necessary
necessary to write to the low order counter in some appl ications to assure that the low order latch contains the proper data
since the timing operation is triggered by writing to the high before initiating the count-down with a "write T1 C-H" operation.
order counter. When the processor writes into the high order counter, the T1
The second set of addresses allows the processor to write interrupt flag will be cleared, the contents of the low order latch
into the latch register without affecting the count-down in will be transferred into the low order counter, and the timer will
progress. This is discussed in detail below. begin to decrement at system clock rate. If the PB7 output is
enabled, this signal will go low on the phase two following the
Reading the Timer 1 Registers
write operation. When the counter reaches zero; the T1 interrupt
For reading the Timer 1 registers, the four addresses relate
flag will be set, the IRQ pin will go low (interrupt enabled), and
directly to the four registers as follows:
the signal on PB7 will go high. At this time the counter will
RS3 RS2 RS1 RSO Operation (R/W = HI continue to decrement at system clock rate. This allows the
L H L L Read Tl low order counter. system processor to' read the contents of the counter to
Reset Tl interrupt flag. determine the time since interrupt. However, the T1 interrupt
L H L H Read Tl high order counter. flag cannot be set again unless it has been cleared as
L H H L Read Tl low order latch. described on page 13 of this specification.
L H H H Read Tl high order latch.
Timing for the 6522 interval timer one-shot modes is shown
in Figure 5.

Phase Two Clock

Write TtC-Hl
Operation
~L----------Ilf---------------­

IRQ Output - - - - - - - - - - - - - - - - I f - - - - - - - - - , L -_ _ _ _ _ _ __

PB7 Output _ _ _ _.....,

o I I I
FF FE I FD I FC I
·1
Notes:
1. RtW-L,CS2-L,CS1-H,RS3-LRS2-H,RS1-RSO-H.

Figure 5. Interval Timer "One-shot" Mode Timing Sequence.

2-54
 MPS
6522
Timer 1 Free-Running Mode
The most important advantage associated with the latches in peripheral pin. A single control bit is provided in the Auxiliary
T1 is the ability to produce a continuous series of evenly Control Register to select between these two modes. This timer
spaced interrupts and the ability to produce a square wave on is comprised of a "write-only" low-order latch (T2L-L), a "read-
PB7 whose frequency is not affected by variations in the only" low-order counter and a read/write high-order counter.
processor interrupt response time. This is accomplished in the The counter registers act as a 16-bitcounterwhich decrements
"free-running" mode. at 02 rate.
In the free-running mode (ACR6 = 1), the interrupt flag is set Timer 2 addressing can be summarized as follows:
and the signal on PB7 is inverted each time the counter
reaches zero. However, instead of continuing to decrement RS3 RS2 RS1 RSO R/W=O R/W=1
from zero after a time-out, the timer automatically transfers the H L L L Write T2L-L Read T2C-L
Clear Interrupt flag
contents of the latch into the counter (16 bits) and continues to
H L L H WriteT2C-H Read T2C-H
decrement from there. The interrupt flag can be cleared by Transfer T2L-L to T2C-L
writing T1 C-H, by reading T1 C-L, or by writing directly into the Clear Interrupt flag
flag as described below. However, it is not necessary to rewrite
the timer to enable setting the interrupt flag on the next time-out. Timer 2 Interval Timer Mode

I
All interval timers in the 6500 family devices are "re- As an interval timer, T2 operates in the "one-shot" mode
triggerable." Rewriting the counter will always re··initialize the similarto Timer 1.ln this mode, T2 provides a single interruptfor
time-out period. In fact, the time-out can be prevented com- each "write T2C-H" operation. After timing out, the counter will
pletely if the processor continues to rewrite the timer before it continue to decrement. However, setting of the interrupt flag will
reaches zero. Timer 1 will operate in this manner if the be disabled after initial time-out so that it will not be set by the
processor writes into the high order counter (T1 C-H). However, counter continuing to decrement through zero. The processor
by loading the latches only, the processor can access the timer must rewrite T2C-H to enable setting of the interrupt flag. The
during each down-counting operation without affecting the interrupt flag is cleared by reading T2C-L or by writing T2C-H.
time-out in process. Instead, the data loaded into the latches Timing for this operation is shown in Figure 5.
will determine the length of the next time-out period. This
capability is particyl§lrly valuable in the free-running mode with
Timer 2 Pulse Counting Mode
In the pulse counting mode, T2 serves primarily to count a
the output enabled. In this mode, the signal on PB7 is inverted
and the interrupt flag is set with each time-out. By responding to predetermined number of negative-going pulses on PB6. This
the interrupts with new data for the latches, the processor can is accomplished by first loading a number into T2. Writing into
determine the period of the next half cycle during each half T2C-H clears the interrupt flag and allows the counter to
cycle of the output signal on PB7.ln this manner, very complex decrement each time a pulse is applied to PB6. The interrupt
flag will be set when T2 reaches zero. At this time the counter will
waveforms can be generated. Timing for the free-running mode
is shown in Figure 6. continue to decrement with each pulse on PB6. However, it is
necessary to rewrite T2C-H to allow the interrupt flag to set on
TIMER 2 subquent down-counting operations. Timing for this mode is
Timer 2 operates as an interval timer (in the "one-shot" mode shown in Figure 7. The pulse must be Iowan the leading edge
only), or as a counter for counting negative pulses on the PB6 02.

systemClock~~~~
Write T1 C-H .-----, .
Operation ----J L----Jlt-----------·----------------
'iRa Output ------------~fI~--------~
'-----------1)/
t
(!
PB70utput ~~. _ _ _ _~
"
f---- N+1.5 Cycles
+ N+2 Cycles

Figure 6. Timer 1 "Free-Running" Mode

WriteT2C-H
Operation ~--------------------------------------
PB61nput
u u.-----·-II
u u
iRQ Output

N N-1 N-2 fJ 2 o

Figure 7. Timer 2 Pulse Coulntlng Mode

2-55
 MPS
6522
SHIFT REGISTER
The Shift Register (SR) performs serial data transfers into and Mode 001 - Shift In under Control ot Timer 2
out of the CB2 pin under control of an internal modulo-8 In this mode the shifting rate is controlled by the low order 8
counter. Shift pulses can be applied to the CB1 pin from an bits of T2. Shift 'pulses are generated on the CB 1 pin to control
external source or, with the proper mode selection,shift pulses shifting in external devices. The time between transitions of this
generated intemally will appear on the CB 1 pin for controlling output clock is a function of the system clock period and the
shifting in external devices. contents of the low order T2 latch.
The control bits which allow control of the various shift The shifting operation is triggered by writing or reading the
register operating modes are located in the Auxiliary Control shift register. Data is shifted first into the low order bit of SR and
Register. These bits can be set and cleared by the system is then shifted into the next higher order bit of the shaft register
processor to select one of the operating modes diSCUSSed in on the trailing edge of each clock pulse.As shown in Figure 8,
the following paragraphs. the input data should change before the leading edge of the
clock pulse. This data is loaded into the shift register during the
Shift Register Input Modes
system clock cycle following the trailing edge of the clock
Bit 4 of the Auxiliary Control Register selects the input or
pulse. After 8 clock pulses, the shift register interrupt flag will be
output modes. There are three input modes and four output
set and IRQ will go low.
modes, differing primarily in the source of the pulses which
control the shifting operation. With ACR4 = 0 the input modes Mode 010 - Shift In at System Clock Rate
are selected by ACR3 and ACR2 as follows: In this mode the shift rate is a direct function of the system
clock frequency. CB1 becomes an output which generates
ACR4 ACR3 ACR2 Mode shift pulses for controlling external devices. Timer 2 operates as
0 0 0 Shift Register Disabled an independent interval timer and has no effect on SR. The
0 0 1 Shift in under control of Timer 2 shifting operation is triggered by reading or writing the Shift
0 1 0 Shift in at System Clock Rate. Register. Data is shifted first into bit 0 and is then shifted into the
0 1 1 Shift in under control of external next higher order bit of the shift register on the trailing edge of
input pulses each clock pulse. After 8 clock pulses, the shift register interrupt
flag will be set, and the output clock pulses on CB1 will stop.
Mode 000 - Shift Register Disabled
The 000 mode is used to disable the Shift Register. In this Mode 011 - Shift In under Control of External Clock
mode the microprocessor can write or read the SR, but the In this mode CB 1 becomes an input. This allows an external
shifting operation is disabled and operation ofCB1 and CB2 is device to load the shift register at its own pace. The shift register
controlled by the appropriate bits in the Peripheral Control counter will interrupt the processor each time 8 bits have been
Register (PCR). In this mode the SR Interrupt Flag is disabled shifted in. However, the shift register counter does not stop the
(held to a logic 0). shifting operation; it acts simply as a pulse counter. Reading or

Write or Read ----.lI

Shift Reg. ~-----

CS2
Input Data
y//llll
CS1
Shift Clock

IRQ

Figure 8. Shifting In Under Control of T2

System Clock
(02)

WriteSR ~'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Operation

Output Clock - - - - - - - - - - - -{~­

(CS1)

Input Data
(CB2) \\\\\\\\\\\\\\\\illlli\"S%\\"VX K\\\\\~~ K\\\\\\\\\\\
IRQ

Figure 9. Timing Sequence tor Shifting In at System Clock Rate

2-56
 MPS
6522
writing the Shift Register resets the Interrupt flag and initializes Mode 101 - Shift out under Control of T2
the SR counter to count another 8 pulses. In this mode the shift rate is controlled by T2 (as in the
Note that data is shifted during the first system clock cycle previous mode). However, with each read or write of the shift
following the leading edge of the CB1 shift pulse. For this register the SR Counter is reset and 8 bits are shifted onto CB2.
reason, data must be held stable during the first full cycle At the same time, 8 shift pulses are generated on CB 1 to control
foliowingCB1 going high.Timing forthis operation is illustrated shifting in external devices. After the 8 shift pulses, the shifting is
in Figure 10. disabled, the SR Interrupt flag is set and CB2 goes to a state
Shift Register Output Modes determined by the CB2 Control bit (PCS) in the Peripheral
The four Shift Register Output Modes are selected by setting Control F~egister.
the InpuVOutput Control Bit (ACR4) to a logic 1 and then If the shift register is reloaded before the last time-out, the
selecting the specific output mode with ACR3 and ACR2. In shifting will continue. This sequence is illustrated in Figure 11.
each of these modes the Shift Register shifts data out of bit 7 to
the CB2 pin. At the same time the contents of bit 7 are shifted
Mode 1 '10 - Shifting out at System Clock Rate
back into bit O. As in the input modes, CB 1 is used either as an
In this mode the shift register operation is similar to that
output to provide shifting pulses out or as an input to allow
shown in Figure 11. However, the shifting rate is a function of the
shifting from an external pulse. The four modes are as follows:

I
system clock on the chip enable pin (02) and is independent of
ACR4 ACR3 ACR2 Mode T2. Timer 2 resumes its normal function as an independent
1 0 0 Shift out - Free-running mode. interval timer. Figure 12 illustrates the timing sequence for
Shift rate controlled by T2. mode 110.
1 0 1 Shiftout-ShiftratecontroliedbyT2.
Shift pulses generated on CB1.
1 1 0 Shift out at system clock rate. Mode 111 - Shift out under Control of an External Pulse
1 1 1 Shift out under control of an external
In this mode, shifting is controlled by pulses applied to the
pulse. CB1 pin by an external device. The SR counter sets the SR
Interru pt flag each ti me it counts 8 pulses but it does not disable
Mode 100 Free-Running Output the shifting function. Each time the microprocessor writes or
This mode is very simiJar to mode 101 in which the shifting reads the shift register, the SR Interrupt flag is reset and the SR
rate is set byT2. However, in mode 100 the SR Counter does not Counter is initialized to begin counting the next 8 sh ift pulses on
stop the shifting operation. Since the Shift Register bit 7 (SR7) is pin CB 1. After 8 shift pulses, the interrupt flag is set. The micro-
recirculated back into bit 0, the 8 bits loaded into the shift processor can tren load the shift register with the next byte of
register will be clocked onto 9B2 repetitively. In this mode the data. .
shift register counter is disabled.

CB1
L-----ffr-- - - - ' L
CB.2
________________ ~x__~ _________________
IRQ

NOTE: Data is shifted at pOint A

Figure 10. Timing sequence for shifting In under control of external clock

Phase Two
Clock

WRITE SR ~L-________~_______________________________
Operation

Output Data
(CB2) --------~x~-----------~f~,---_________ ~
~---------~~~~-------------
Output Clock
(CB1)

IRQ
Notes:
1. Data out determined by CB2 control in PCR.

Figure 11. Shifting out under Control of T2.

2-57
 MPS
6522
INTERRUPT CONTROL
Controlling interrupts within the 6522 involves three prin- Bits sixthrough zero are latches which are set and cleared as
cipal operations. These are flagging the interrupts, enabling follows:
interrupts and signalling to the processor that an active
interrupt exists within the chip. Interrupt flags are set by Blt# Selby Cleared by
interrupting conditions which exist within the chip or on inputs 0 Active transition of the Reading or writing the A Port Output
signal on the CA2 pin. Register (ORA) using address 0001.
to the chip. These flags normally remain set until the interrupt
1 Active transition of the Reading or writing the A Port Output
has been serviced. To determine the source of an interrupt, the signal on the CA 1 pin. Register (ORA) using address 0001 .
microprocessor must examine these flags in order from highest Reading or writing the Shift Register.
2 Completion of eight shifts
to lowest priority. This is accomplished by reading the flag
3 Active transition of the Reading or writing the B Port Output
register into the processor accumulator, shifting this register signal on the CB2 pin. Register.
either right or left and then using conditional branch instruc- 4 Active transition of the Reading or writing the B Port Output
tions to detect an active interrupt. signal on the CB1 pin. Register.

Associated with each interrupt flag is an interrupt enable bit. S Time-<>ut of Timer 2. Reading T2 low order counter.
Writing T2 high order counter.
This bit can be set or cleared by the processor to enable
6 Time-<>ut of Timer 1. Reading T1 lower order counter.
interrupting the processor from the corresponding interrupt Writing T1 high order latch.
flag. If an interrupt flag is set to a logic 1 by an interrupting
condition, and the corresponding.interrupt enable biti§...§.et to a The IFR bit 7 is not a flag. Therefore, this bit is not directly
1, the Interrupt Request Output (IRO) will go low. IRO is an cleared by writing a logic 1 into it. It can only be cleared by
"open-collector" output which can be "wire or'ed" with other clearing all the flags in the register or by disabiling all the active
devices in the system to interrupt the processor. interrupts as discussed in the next section.
In the 6522, all the interrupt flags are contained in one Interrupt Enable Register (lER)
register. In addition, bit 7 of this register will be read as a logic 1 For each interrupt flag in I FR, there is a corresponding bit in
when an interrupt exists within the chip. This allows very the I nterrupt Enable Register. The system processor can set or
convenient polling of several devices within a system to locate clear selected bits in this register to facilitate controlling
the source of an interrupt. individual interrupts without affecting others. This is accom-
plished by writing to address 1110 (IER address). If bit 7 of the
7 6 5 4 3 2 1 0 data placed on the system data bus during this write operation
Interrupt IRQ T1 T2 CB1 CB2 SR CA1 CA2 is a 0, each 1 in bits 6 through 0 clears the corresponding bit in
Flag
Register the Interrupt Enable Register. For each zero in bits 6 through 0,
Interrupt SeV T1 T2 CB1 CB2 SR CA1 CA2 the corresponding bit is unaffected.
Enable clear Setting selected bits in the Interrupt Enable Register is
Register control accomplished by writing to the same address with bit 7 in the
data word set to a logic 1.In this case, each 1 in bits 6 through 0
Interrupt Flag Register will set the corresponding bit. For each zero, the corresponding
The IFR is a read/bit-clear register. When the proper chip bit will be unaffected. This individual control of the setting and
select and register signals are applied to the chip, the contents clearing operations allows very convenient control of interrupts
of this register are placed on the data bus. Bit 7 indicates the during system operation.
status of the I RO output. This bit corresponds to the logic In addition to setting and clearing IER bits, the processor
function: IRO = IFR6 X IER6 + IFR5 X IER5 + IFR4 X IER4 + can read the contents of this register by placing the proper
IFR3 X IER3 + IFR2 X IER2 + IFR1 X IER1 + IFRO X IERO. address on the register select and chip select inputs with the
Note: X = logic AN D, + = Logic OR. RNI line high. Bit 7 will be read as a logic O.

Phase Two
Clock

~--------------------------------------
Write SA
Operation

Clock Out
(CB1) ~

----~~~--~--~~
Data Out
(CB2)

IAQ

Figure 12. Shifting out under Control of System Clock

Write SA
Operation
---II' - - - - - - - - - - - - - - - - - - - - - - - - - - -
InputCLK ~
(CB1)

Output Data
(CB2) ________Jx,~__________~x~____~i~-------
IAQ

Figure 13. Shifting out under Control of External Clock

2-58
 MPS

6522
FUNCTION CONTROL
Control of the various functions and operating modes within In the independent input mode, writing or reading the ORA
the 6522 is accomplished primarily through two registers, the register has no effect on the CA2 interruptflag. This flag must be
Peripheral Control Register (PCR), and the Auxiliary Control cleared by writing a logic 1 into the appropriate IFR bit. This
Register (ACR). The PCR is used primarily to select the mode allows the processor to handle interrupts which are
operating mode for the four peripheral control pins. The independent of any operations taking place on the peripheral
Auxiliary Control Register selects the operating mode for the I/O ports.
interval timers (T1, T2), and the serial port (SR). The handshake and pulse output modes have been de-
scribed previously. Note that the timing of the output signal
Peripheral Control Register
varies slightly depending on whether the operation is initiated
The Peripheral Control Register is organized as follows:
by a read or a write.
3. CB1 Control
Control of the active transition of the CB1 input signal
operates in exactly the same manner as that described above
forCA1.lf PCR4 isa logicOtheCB1 interrupt flag (lFR4) will be

I
Each of these functions is discussed in detail below. set by a negative transition of the CB1 input signal and cleared
bya read or write of the ORB register. If PCR4 is a logic 1, IFR4
1. CA 1 Control
will be set by a positive transition of CB1.
Bit 0 of the Peripheral Control Register selects the active
If the Shift Register function has been enabled, CB 1 will act
transitiol) of the input signal applied to the CA 1 interrupt input
as an input or output for the shift register clock signals. In this
pin. If this bit is a logic 0, the CA 1 interrupt flag will be set by a
mode the CB1 interrupt flag will still respond to the selected
negative transition (high to low) of the signal on the CA 1 pin. If
transition of the signal on the CB 1 pin.
PCRO is a logic 1, the CA 1 interrupt flag will be set by a positive
transition (low to high) of this signal. 4. CB2 Control
With the serial port disabled, operation of the CB2 pin is a
2. CA2 Control
function of the three high order bits of the PCR. The CB2 modes
The CA2 pin can be programmed to act asn an interrupt
are very similar to those described previously for CA2. These
input or as a peripheral control output. As an input, CA2
modes are selected as follows:
operates in two modes, differing primarily in the methods
available for resetting the interrupt flag. Each of these two input PCR7 FCR6 PCR5 Mode
modes can operate with either a positive or a negative active 0 0 0 Interrupt input mode - Set CB2 interrupt flag
transition as described above for CA 1. (IFR3) on a negative transition of the CB2 input
In the output mode, the CA2 pin combines the operations signal. Clear IFR3 on a read or write of the
Peripheral B Output Register.
performed on the CA2 and CB2 pins of the 6520. This added
0 0 1 Independent interrupt input mode - Set IFR3 on
flexibility allows processor to perform a normal "write" hand- a negative transition of the CB2 input signal.
shaking in a system which uses CB1 and CB2 for the serial Reading or writing ORB does not cear the
operations described above. The CA2 operating modes are interrupt flag.
selected as follows: 0 1 0 Input mode- SetCB2 interrupt flag on a pOSitive
transition of the CB2 input signal. Clear the CB2
interrupt flag on a read or write of ORB.
PCR3 PCR2 PCR1 Mode
0 1 1 Independent input mode - Set IFR3 on a posi-
0 0 0 Input mode - Set CA2 interrupt flag (I FRO) on a tive transition of the CB2 input Signal. Reading or
negative transition of the input signal. Clear I FRO writing ORB does notcieartheCB2 interrupt flag.
on a read or write of the Peripheral A Output
Register. 1 0 0 Handshake output mode - Set CB2 Iowan a
write ORB operation. Reset CB2 high with an
0 0 1 I ndependent interrupt input mode - Set IFRO on active transition of the CBl input signal.
a negative transition of the CA2 input signal.
Reading or writing ORA does not clear the CA2 1 0 1 Pulse output mode - Set CB2 low for one cycle
interrupt flag. following a write ORB operation.
0 1 0 Input mode - Set CA2 interrupt flag on a positive 1 1 0 Manual output mode - The CB2 output is held
transition of the CA2 input signal. Clear IFRO with low in this mode.
a read or write of the Peripheral A Output Register. I 1 1 Manual output mode - The CB2 output is held
0 1 1 Independent interrupt input mode -Set IFRO on high in this mode.
a positive transition of the CA2 input Signal.
Reading or writing ORA does not clear the CA2
interrupt flag.
1 0 0 Handshake output mode - Set CA2 output low Auxiliary Control Register
on a read or write of the Peripheral A Output Many of the functions in the Auxiliary Control Register have
Register. Reset CA2 high with an active transition been discussed previously. However, a summary of this register
on CAl.
is presented here as a convenient reference for the 6522 user.
1 0 1 Pulse Output mode - CA2 goes low for one cycle
following a read or write of the Peripheral A The Auxiliary Control Register is organized as follows:
Output Register.
1 1 0 Manual output mode - The CA2 output is held
low in this mode.
Bit#:-
Function-
1 I 6 5
T2
4 I 3 I 2 1
PB PA
0

Tl Control Control Shift Register Control Latch Latch

1 1 1 Manual output mode - The CA2 output is held
Enable Enable
high in this mode.

2-59
 MPS

6522
APPLICATION OF THE 6522
1. PA Latch Enable The 6522 represents a significant advance in general-
The 6522 provides input latching on both the PA and PB purpose microprocessor I/O. Unfortunately, its many powerful
ports. In this mode, the data present on the peripheral A input features, coupled with a set of very flexible operating modes,
pins will be latched within the chip when the CA 1 interrupt flag cause this device to appear to be very complex at first glance.
is set. Reading the PA port will result in these latches being wever, a detailed analysis will show that theVIA is organized to
transferred into the processor. As long as the CA 1 interrupt flag allow convenient control of these powerful features. This
is set, the data on the peripheral pins can change without section seeks to assist the system designer in his under-
standing of the 6522 by illustrating how the device can be used
affecting the data in the latches. This input latching can be used in microprocessor-based systems.
with any of the CA2 input or output modes.
It is important to note that on the PA port, the proCessor A. Control of 6522 Interrupts
always reads the data on the peripheral pins (as reflected in the Organization of the 6522 interrupt flags into a single register
latches). For output pins, the processor still reads the latches. greatly facilitates the servicing of interrupts from this device.
Since there is only one I RQ output for the seven possible
This mayor may not reflect the data currently in the ORA. Proper sources of interrupt within the chip, the processor must exam-
system operation requires careful planning on the part of the ine these flags to determine the cause of an interrupt. This is
system designer if input latching is combined with output pins best accomplished by first transferring the contents of the flag
on the peripheral ports. register into the accumulator. At this time it may be necessary to
Input latching is enabled by setting bit a in the Auxiliary mask off those flags which have been disabled in the Interrupt
Control Register to a logic 1.As long as this bit isaO, the latches Enable Register. This is particularly important for the edge
will directly reflect the data on the pins. detecting inputs where the flags may be set whether or not the
interrupting function has been enabled. Masking off those flags
2. PB Latch Enable can be accomplished by performing an AND operation be-
Input latching on the PB port is controlled in the same tween the IE R and the accumulator or by performing an "AN D
manner as that described for the PA port. However, with the IMMEDIATE." The second byte of this AND # instruction
peripheral B port the input latch will store either the voltage on should specify those flags which correspond to interrupt
the pin or the contents ofthe Output Register (ORB) depending functions which are to be serviced.
on whether the pin is programmed to act as an input or an If the N flag is set after these operations, an active interrupt
output. As with the PA port, the processor always reads the input exists within the chips. This interrupt can be detected with a
latches. series of shift and branch instructions.
Clearing interrupt flags is accomplished very conveniently
3. Shift Register Control by writing a logic 1 directly into the appropriate bit of the
The Shift Register operating mode is selected as follows: Interrupt Flag Register. This can be combined with an interrupt
enable or disable operation as follows:
LDA #@1 001 0000 initialize accumulator
ACR4 ACR3 ACR2 Mode STA IFR clear interrupt flag
0 0 0 Shift Register Disabled. STA IER set interrupt enable flag
0 0 1 Shift in under control of Timer 2. or:
0 1 0 Shift in under control of system clock.
LDA #@00001 000 initialize accumulator
0 1 1 Shift in under control of extemal clock pulses. STA IFR clear interrupt flag
1 0 0 Free-running output at rate determined by Timer 2. STA IFR disable interrupt
1 0 1 Shift out under control of Timer 2. Another very useful technique for clearing interrupt flags is to
1 1 0 Shift out under control of the system clock. simply transfer the contents of the flag register back into this
register as follows:
1 1 1 Shift out under control of external clock pulses.
LDAIFR transfer I FR to accumulator
STA IFR clear flags corresponding to active
4. T2 Control interrupts
Timer 2 operates in two modes. If ACR5 = a, T2 acts as an After completion of this operation the accumulator will still
interval timer in the one-shot mode. If ACR5 = 1, Timer 2 acts to contain the interrupt flag information. Most important, writing
count a predetermined number of pulses on pin PB6. into the flag register clears only those flags which are already
5. T1 Control set. This eliminates the possibility of inadvertently clearing a
flag while it is being set.
Timer 1 operates in the one-shot or free-running mode with
the PB7 output control enabled or disabled. These modes are B. Use of Timer 1
selected as follows: Timer 1 represents one of the most powerful features of the
6522. The ability to generate very evenly spaced interrupts and
the ability to control the voltage on PB7 makes this timer
ACR7 ACR8 Mode particularly valuable in various timing,data detection and wave-
0 0 One-shot mode - Output to PB7 disabled. form generation applications.
0 1 Free-running mode -Output to PB7 disabled.
Tlme-of-Day Clock Applications
1 0 One-shot mode - Output to PB7 enabled. An important feature of many 'systems is the time-of-day
1 1 Free-running mode. Output to PB7 enabled. clock. In microprocessor-based systems the time of day is
usually maintained in memory and is updated in an interrupt
service routine. A regular processor interrupt will then assure
that this time of day will always be available when it is needed in
the main program.

2-60
 MPS
6522
Generating very regular interrupts using previously available (output mode). In this mode a single negative pulse can be
timers presented difficulties because of the need to re-Ioad the generated on PB7 (one-shot mode), or in the free-running
timer for each interrupt. Unfortunately, the time between the mode, a continuous waveform can be generated. In this latter
interrupts will fluctuate due to variations in the interrupt response mode the voltage on PB7 will be inverted each time T1 times
time. This program is eliminated in the Timer 1 "free-running"
out.
mode. The accuracy of these "free-running" interrupts is only a
function of the system clock and is not affected by interrupt A single solenoid can be triggered very conveniently in the
response time. one-shot mode if the PB 7 signal is used to control the solenoid
directly. With this configuration the solenoid can be triggered
Asynchronous Data Detection by simply writing to T1 C-H.
The extraction of clock and data information from serial Generating very complex waveforms can be a simple prob-
asynchronous ASCII signals or from any single channel data lem ifT1 is used to control PB7 in the free-running mode. During
recording device relies on the ability to establish accurate any count-down process the latches can be loaded to deter-
strobes. As discussed previously, the period of these strobes mine the length of the next count-down period. Figure 15 shows
can be seriously affected by the interrupt response time using this timing sequence for generating ASCII serial data.
conventional timers. However, T1 again allows generation of
very accurate interrupts. The processor responds to these An application where this mode of operation is also very
interrupts by strobing the input data. The ability to reload the T1 powerful is in the generation of bi-phase encoded data for tape

I
latches without affecting the count-down in progress is very
useful in this application. This allows the strobe time to be or disk storage. This encoding technique and the sequence of
doubled or halved during data detection. See Figure 14 for operations which would take place are illustrated in Figure 16.
sequence of operations. These applications represent only a tiny portion of the
potentia1 T1 applications. Some other possibilities are pulse
Waveform Generation with Timer 1 width modulation waveforms, sound generation for video
In addition to generating processor interrupts, Timer 1 can games, AID techniques requiring very accurate pulse widths,
be used to control the output voltage on peripheral pin PB7 and waveform synthesis in electronic games.

Start Bit Data Bit Data Bit

u U L.J

4 T III « 2T

Load T into T1 counter and 2T into

T1 latch at beginning of start bit.
-I •

Figure 14. Detecting Asynchronous Data Using Timer 1

2T 2T -----00/

Output
I Start Bit Data Bit I I
Data (PB7) I ~ L -_ _ ----JI
IRO
~ L~
I I I I

1. Load T into T1 counter and latch. Load T into T2 to trigger T1 latch reload
2. Load 2T into T1 latch dUrIng this bit time. Load 2T ,nto T2.
3. Load T into T1 latch anytime during this period. Load NT into T2. N = number of
1's or O'S which follow.
4. A series of 1's and O's will be generated until the T1 latch IS again changed.
Note that the use of T2 to control reloading the T1 latch eliminates the need to
interrupt on each transition.

Figure 15. ASCII Serial Data Generation Using T1

Output I I 1 I
Data fPB7) IL.___---J ~'--_--'I
I L,-'
1. Load T1 counter and latch.
2. Shift T1 latch one bit to the right during this period.
3. Shift T1 latch left during this period.
4. Shift T1 latch right during this period.

Note that T1 must be accessed only when the output data changes. A string of 1's
and O's can be generated without processor intervention.

Figure 16. Generating SI-phase Encoded Data

2-61
 MPS

6522
Using the 6522 Shift Register
The Shift Register in the 6522 is designed primarily as a CB2 Data
CBI Ctock
synchronous serial communications port for distributed sys- PBO Setect I
tems. These systems can be either single-processor with 650X 6522
PBI Setect 2
distributed peripheral controllers or distributed processor sys-
tems. The most important characteristic of the Shift Register in
~H-j...j.........-..I PB2
PB3
Setect3
il To Display
lamp Drivers

these applications is its ability to transfer information at rela-

tively slow data rates to allow the use of R-C noise suppression
techniques. This transfer can be accomplished while the
processor is servicing other aspects of the system. An example
of a simple 2-processor distributed system is shown in Figure Tone'"
display
17. Use of the 6522 Shift Register allows effective communica- To Display
Lamp Drivers
tion between the two systems without the use of relatively
complex asynchronous communications techniques.

System I System 2
CB2 Data CB2

CBI Clock CBI

6522 PBO "Busy" Control PBO

Figure 18. USing the Shift Register for Servicing Remote

Status Displays
TO Lamp Drivers. elc
Figure 17. Using Shift Register for Inter-System
Communication
In a system with distributed peripherals, the Shift Register
CB2
can be used to transfer data to the peripheral interface devices.
This is illustrated in Figure 18 for a system with a number of CS'
PBO
distributed status displays. These displays. are serviced by
stand-alone controllers which actuate the lamps in the status 6522 rP-"'S'-' +--+_+_-----+-+------+....,
displays through simple drivers. The data and clock lines are
wired in parallel to each unit. In addition, a single 6522
peripheral port output allows selection of the display to be
loaded. These select lines can be eliminated if all displays are
to contain the same information. With the system shown, the
status display can be updated at any time by simply selecting To lnp~t SWItches
the desired display and then writing to the Shift Register. Figure 19. expanding System I/O Using Shift Register
Remote input devices can be serviced in much the same
manner by shifting data into the Shift Register under control of a Clock Generation Using the Shift Register
peripheral port output as shown in Figure 18. Each set of input In all output modes the data shifted out of bit 7 will also be
switches can be polled by first selecting the set to be polled and shifted into bit O. For this reason the Shift Register need not be
then triggering the shifting operation with a Shift Register read re-Ioaded if the same data is to be shifted out each time. A Shift
operation. A shift register interrupt can be used to cause the Register read operation can be used to trigger the shifting
processor to read the resulting input information after shifting is operation.
complete. This capability is very useful for generating peripheral clocks
The techniques described above can be utilized to expand in the continuous output mode. This mode allows an 8-bit
I/O capability in a microprocessor based system. In a system pattern to be shifted out continuously. This is illustrated in
with many status lamps or many input switches, simple TTL shift Figure 20. Note that in this mode the shifting operation is
registers will provide the necessary I/O in a very cost effective controlled by Timer 2. A single bit time can therefore be up to
manner. This is illustrated in Figure 19. 256 clock cycles in length.

CB1
-IT I--
CB2
~~------~L-____________~
L....-_ _ _ _ _---I r
Notes:
1. Shift Register loaded with 1110 00002 initially.
2. T determined by Timer 2.

Figure 20. Clock Generation Using SR Free-Running Mode

2-62
 MPS
6522
MAXIMUM RATINGS COMME.NT
Supply Voltage, Vcc -0.3V to + 7.0V Stresses above those listed under "Absolute Maximum
Input/Output Voltage, VIN -0.3V to + 7.0V Ratings" may cause permanent damage to the device.
Operating Temperature, TOp OCto 70 C These are stress ratings only. Functional operation of this
Storage Temperature, TSTG -55 C to 150 C device at these or any other conditions above those indi-
All inputs contain protection circuitry to prevent damage due cated in the operational sections of this specification is not
to high static discharges. Care should be exercised to implied and exposure to absolute maximum rating condi-
prevent unnecessary application of voltages in excess of the tions for extended periods may affect device reliability.
allowable limits.

STATIC D.C. CHARACTERISTICS 01cc = 5.0 V ± 5%, Vss = 0, TA = 0 to +70 0C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit

Input high voltage (normal operation) VIH +2.4 - Vcc Vdc

Input low voltage (normal operation) VIL -0.3 - +0.4 Vdc

Input leakage current- Vin = 0 to 5 Vdc .IIN - ±1.0 ±2.5 /JAdc

RAN, RES, RSO, RS1, RS2, RS3,CS1,
CS2, CA1,,02

Off-state input current- Vin = .4 to 2.4 V ITSI - ±2.0 ±10 /JAde

Vcc= Max, DO to 07

Input high current- VIH = 2.4 V IIH -100 -250 - /JAdc

PAO-·PA7, CA2, PBO-PB7, CB1, CB2

Input low current- VIL = 0.4 Vdc IlL - -1.0 -1.6 mAdc
PAO-.pA 7, CA2, PBO-PB 7, CB 1, CB2

Output high voltage VCH 2.4 - - Vdc

Vcc = min, Iload = -1 00 ~Adc
PAO .. PA7, CA2, PBO-PB7, CB1, CB2

Output low voltage VOL - - +0.4 Vdc

Vcc = min, Iload = 1.6 mAdc
Output high current (sourcing) IOH
VOH = 2.4 V -100 -1000 - /JAdc
VOH = 1.5 V, PBO-PB7, CB1, CB2 -3.0 -5.0 - mAdc
Output low current (sinking) IOL 1.6 - - mAdc
VOL = 0.4 Vdc.
OU!£l:!t leakage current (off state) IOFF - 1.0 10 /JAde
IRQ

Input Capacitance- TA = 25 cc, f = 1 MHz CIN

RAN, RES, RSO, RS1, RS2, RS3,CS1,CS2 - - 7.0 pF
00-07, PAO-PA7, CA2, PBO-PB7, - - 10 pF
CB1, CB2
02 input - - 20 pF
Output capacitance- TA = 25 cc, f = 1 MHz COUT - - 10 pF
Power dissipation Po - 1000 MW

2-63
 MPS
6522
Phase Two
Clock

--2.4V
Phase Two Address
Clock _ _ _ _+-.JJ
0.4 V

r..---- 2.4 V
Address
ReadJWrite
______ 0.4V

Peripheral
Data Data Bus
1\---+-'1- - - - - - - - - 0.4 V
TCP~W
------.Vcc
. ' --2.4V
Data Bus Peripheral
Data
-------------------------
Figure 21. Read Timing Characteristics Figure 22. Write Timing Characteristics
A.C. CHARACTERISTICS
Read Timing Characteristics (loading 130 pF and one TIL load)

Characteristic Symbol Min Typ Max Unit

Delay time, address valid to clock positive transition TACR 180 - - nS
Delay time, clock positive transition to data valid on bus TCDR - - 395 nS
Peripheral data setup time TPCR 300 - - nS
Data bus hold time THR 10 - - nS
Rise and fall time for clock input TRC - - 25 nS
TRF

Write Timing Characteristics

Characteristic Symbol Min Typ Max Unit

Enable pulse width TC 0.47 - 25 IJS
Delay time, address valid to clock positive transition TACW 180 - - nS
Delay time, data valid to clock negative transition TDCW 300 - - nS
Delay time, read/write negative transition to clock TWCW 180 - - nS
positive transition
Data bus hold time THW 10 - - nS
Delay time, Enable negative transition to peripheral data valid TCPIN - - 1.0 }JS
Delay time, clock negative transition to peripheral data valid TCMOS - .- 2.0 IJS
CMOS Nee - 300AlI

2.4V

\r. ------- k
CB2Seriai
Data In
-----------------------. 0.4 V

f
SR3
TICW - - - - - 1 2.4 V

--_.~=1------------:::
CBI Clock

-A~-------------
CB2Seriai
DaIaOuI
0.4 V
Figure 23. 1/0 Timing Characteristics

2-64
 MPS

6522

Peripheral Interface Characteristics

Characteristics Symbol Min Typ Max Unit

Rise and fall time for CA 1, CB 1, CA2 and CB2 input signals. TRF 1.0 I-lS

Delay time, clock negative transition to CA2 negative TCA2 1.0 IJS
transition (read handshake or pulse mode).

Delay time, clock negative transition to CA2 positive TRS1 1.0 IJS
transition (pulse mode).

Delay time, CA 1 active transition to CA2 positive TRS2 2.0 fJS

transition (handshake mode).

I
Delay time,clock positive transition to CA2 or CB2 TWHS 1.0 IJS
negative transition (write handshake).

Delay time, peripheral data valid to CB2 negative TDC 0 1.5 I-lS
transition.

Delay time, clock positive transition to CA2 or CB2 TRS3 1.0 fJS
positive transition (pulse mode).

Delay time, CB 1 active transition to CA2 or CB2 positive TRS4 2.0 I-lS
transition (handshake mode).

Delay time, peripheral data valid to CA 1 or CB 1 active TIL 300 nS

transition (input latching).

Delay time, CB1 negative transition to CB2 data valid TSR1 300 nS
(internal SR clock, shift out).

Delay time, negative transition of CB 1 input clock to TSR2 300 nS

CB2 data valid (external clock. shift out).

Delay time. CB2 data valid to positive transition of TSR3 300 nS

CB 1 clock (shift in. internal or external clock)

Pulse Width - PB6 Input Pulse TIPW I-lS

Pulse Width,---- CB1 Input Clock TICW 2 IJS

Pulse Spacing - PB6 Input Pulse liPS JJS

Pulse Spacing - CB1 Input Pulse IICS JJS

COMMODORE SEMICONDUCTOR GROUP reserves the right to make changes to any products herein to
improve reliability, function or design. COMMODORE SEMICONDUCTOR GROUP does not assume any
liability arising out of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others.

2-65