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Vcs Usage

The document provides a step-by-step guide for setting up and using Synopsys Tools Suite for Verilog design and simulation. It includes instructions for creating directories, compiling designs, and verifying simulations, along with additional options for debugging and coverage metrics. Users are also directed to access help resources for further assistance.

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Aditya Kumar Dhanraj
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16 views5 pages

Vcs Usage

The document provides a step-by-step guide for setting up and using Synopsys Tools Suite for Verilog design and simulation. It includes instructions for creating directories, compiling designs, and verifying simulations, along with additional options for debugging and coverage metrics. Users are also directed to access help resources for further assistance.

Uploaded by

Aditya Kumar Dhanraj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Usage:

1) Ensure that your PC has an active internet connection for licensing purposes.
2) Create a directory then use a text editor to write your Verilog designs and test
bench in separate files, and save them in the created folder.
3) Open a terminal within the created folder.
4) In the terminal, execute the following commands:
a) csh
b) source /home/synopsys/cshrc

5) Upon completing the above steps, you should see a welcome message
displaying "Welcome to Synopsys Tools Suite" on the screen.
6) Compile your design using the following command:
a) vcs -R -gui <verilog_files> <test_bench>
Replace <verilog_files> and <test_bench> with the appropriate file names.

7) Upon successful compilation, a message indicating 'simv up to date' should be


visible and the Design and Verification Environment (DVE) application would also
open up.
8) Else if errors are there, the same would be displayed and operation terminates
9) Inside DVE, in the hierarchy pane, expand the hierarchy and locate your module
of interest. Select the signals you want to view from the variables pane,
right-click, and choose "Add to Wave" & “New Wave View”.

10) Once the wave window is open, navigate to the “simulator” option, select
"Start/Continue".

11) Verify the waveform and also check the console prints if any to ensure the
simulation is running as expected.

Other options

1) +lint=all -> Turns on all verilog warnings


2) -sverilog -> For system verilog designs
3) -l <filename> -> redirecting log to file
4) In DVE -> scope -> show schematic -> View schematic display of design
5) -debug_access+all -> To enable step-by-step execution
6) -cm <options> -> Enable coverage metrics
a) Coverage: Measures how much code is being exercised when tests are
run
b) Helps find areas of code not accessed by test cases
c) Indirect measure of quality of test bench
d) Higher coverage -> lower chance for bugs
e) Inorder to get code coverage:
i) VCS -lca -cm <options> <verilog_files>
ii) ./simv -cm <options>
iii) urg -lca -dir simv.vdb
iv) Now open dashboard.html in urgReport folder to analyze coverage

Options can be:


1) Line (line)
2) Toggle (tgl)
3) FSM (fsm)
4) Branch (branch)
5) Condition (cond)
7) For more options:
a) In terminal: VCS -help
b) In DVE: Help -> Tutorial

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