S.I.E.

S College of Arts, Science and Commerce(EAutonomous)

Sion(W), Mumbai – 400 022.

CERTIFICATE

This is to certify that Miss./Mr Harsh Pitkekar

Roll No. FCS2425078 has successfully completed the necessary course of
experiments in the subject of Digital Electronics during the academic
year 2024 – 2025 complying with the requirements of University of
Mumbai, for the course of FYBSc Computer Science [Semester-II].

Prof. In-Charge
Mr.Rajesh Yadav Examiner’s Signature & Date

Head of the College Seal

Department Dr. Manoj
Singh

1
2
 PRACTICAL 1
ROLL NO: FCS2425078
SUBJECT: DIGITAL ELECTRONICS
AIM: WORKING WITH NUMBER SYSTEMS
NUMBER SYSTEM: A set of values which is used to represent different quantities is known
as Number System. It defines how the number are represented using different symbols
TYPES OF NUMBER SYSTEM:
1) BINARY NUMBER SYSTEM
2) OCTAL NUMBER SYSTEM
3) DECIMAL NUMBER SYSTEM
4) HEXADECIMAL NUMBER SYSTEM

BINARY NUMBER SYSTEM (BASE 2):

 Uses 2 digits: 0 and 1.
 The fundamental number system used by computers.
 Each digit's position represents a power of 2.

OCTAL NUMBER SYSTEM:

 Uses 8 digits: 0, 1, 2, 3, 4, 5, 6, 7,10,11,12,13,14,15,16.
 Often used as a shorthand for representing binary numbers.
 Each digit's position represents a power of 8.

DECIMAL NUMBER SYSTEM:

 Uses 10 digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15.
 The most commonly used number system in everyday life.
 Each digit's position represents a power of 10.

HEXADECIMAL NUMBER SYSTEM:

 Uses 16 digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F.
 Commonly used in computer programming and hardware addressing.
 Each digit's position represents a power of 16.

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 A diagrammatic representation of the values in each number system:

Decimal Number Binary Number Octal Number Hexadecimal number

system (base 10) system (base 2) system (base 8) system (16)
0 0000 0 0
1 0001 1 1
2 0010 2 2
3 0011 3 3
4 0100 4 4
5 0101 5 5
6 0110 6 6
7 0111 7 7
8 1000 10 8
9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F

Q1. CONVERT THE DECIMAL NUMBER INTO BINARY EQUIVALENT

1. (25)10
Ans.
INTEGER PART QUOTIENT REMAINDER
25/2 12 1
12/2 6 0
6/2 3 0
3/2 1 1
1/2 0 1
FINAL ANSWER:(128)10 = (11001)2
2. (128)10
Ans.
INTEGER PART QUOTIENT REMAINDER
128/2 64 0
64/2 32 0
32/2 16 0
16/2 8 0
8/2 4 0
4/2 2 0
4
 2/2 1 0
1/2 0 1
FINAL ANSWER: (128)10 = (10000000)2

5
3. (225)10
Ans.
INTEGER PART QUOTIENT REMAINDER
225/2 127 1
127/2 63 1
63/2 31 1
31/2 7 1
7/2 3 1
3/2 2 1
2/2 1 1
1/2 0 1
FINAL ANSWER: (225)10= (11111111)2
4.(19)10
Ans.
INTEGER PART QUOTIENT REMAINDER
19/2 9 1
9/2 4 1
4/2 2 0
2/2 1 0
1/2 0 1
FINAL ANSWER: (19)10=(10011)2

5. (89)10
Ans.
INTEGER PART QUOTIENT REMAINDER
89/2 44 1
44/2 22 0
22/2 11 0
11/2 5 1
5/2 2 1
2/2 1 0
1/2 0 1
FINAL ANSWER: (89)10=(1011001)2
Q2. CONVERT THE FOLLOWING BINARY INTO DECIMAL EQUIVALENT.

6
1. (1011)2
Ans.

7
=1+0+1+1
=1 x 23
+ 0 x 22 + 1 x 21 + 1 x 20
=8+0+2+1
=11
Final answer: (1011)2= (11)10
2. (111001)2
Ans.
=1+1+1+0+0+1
=1 x 25 + 1 x 24 + 1 x 23 + 0 x 22 + 0 x 21 + 1 x 20

=32+16+8+0+0+1
=57
Final answer: (111001)2= (57)10
3. (1000001)2
Ans.
=1+0+0+0+0+0+1
=1 x 26 + 0 x 25 + 0 x 24 + 0 x 23 + 0 x 22 + 0 x 21 + 1 x 20

=64+0+0+0+0+0+1
=65
Final answer: (1000001)2=(65)10
4. (1001)2
Ans.
=1+0+0+1
=
1 x 23 + 0 x 22 + 0 x 21 + 1 x 20
=8+0+0+1
=9
Final answer: (1001)2= (9)10
5.(1111)2
8
Ans.

9
=1+1+1+1

10
=
1 x 23 + 1 x 22 + 1 x 21 + 1 x 20
=8+4+2+1
=15
Final answer: (1111)2= (15)10
6. (1101.011)10
= (1×23) + (1×22) + (0×21) + (1×20) + (0×2-1) + (1×2-2) + (1×2-3)
= 8 + 4 + 0 + 1 + 0 + 1/4 + 1/8
= 8 + 4 + 0 + 1 + 0 + 0.25 + 0.125
=13.375
Final answer:(1101.011) 2 = (13.375)10

7. (100.1011)2
Ans.
= (1×22) + (0×21) + (0 × 20) + (1×2-1) + (0×2-2) + (1×2-3) + (1 x 2-4 )
= 4+0+0+1/2 +0 +1/8+1/16
=4+0+0+0.5+0+0.125+0.0625
=4.6875
Final answer: (100.1011) 2 = (4.6875)10
8. (1110.0011)2
Ans.
=(1×23) + (1×22) + (1×21) + (0×20) + (0×2-1) + (0×2-2) + (1×2-3) + (1 x 2-4 )
=8+4+2+0+0+0+1/8+1/16
=8+4+2+0+0+0+0.125+0.0625

11
=14.1875

12
Final answer: (1110.0011) 2 = (14.1875)10

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9. (101.1101)2
Ans.
= (1×22) + (0×21) + (1×20) + (1×2-1) + (1×2-2) + (0×2-3) + (1 x 2-4 )
=4+0+1+1 /2+1 /4+0+1/16
=4+0+1+0.5+0.25+0+0.0625
=5.8125
Final answer: (101.1101) 2 = (5.8125)10

10. (0.101)2
Ans.
= (0×20) + (1×2-1) + (0×2-2) + (1×2-3)
=0+1 /2+0+1 /8
=0+0.5+0+0.125
=0.625
Final answer: (0.101) 2 = (0.625)10
Q2. CONVERT THE FOLLOWING DECIMAL INTO OCTAL AND HEXADECIMAL
EQUIVALENT
1.(17)10
OCTAL:
INTEGER PART QUOTIENT REMAINDER
17/8 2 1
2/8 0 2
Final answer: (17)10= (21)8
HEXADECIMAL:
INTEGER PART QUOTIENT REMAINDER
17/16 1 1
2/16 0 1

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Final answer: (17)10= (11)16
2.(75)10
OCTAL:
INTEGER PART QUOTIENT REMAINDER
75/8 9 3
9/8 1 1
1/8 0 1
Final answer: (17)10= (113)8
HEXADECIMAL:
INTEGER PART QUOTIENT REMAINDER
75/16 4 11(B)
4/16 0 4
Final answer: (17)10= (4B)16 3.
(199)10
OCTAL:
INTEGER PART QUOTIENT REMAINDER
199/8 24 7
24/8 3 1
3/8 0 3
Final answer: (199)10= (307)8
HEXADECIMAL:
INTEGER PART QUOTIENT REMAINDER
199/16 12 7
12/16 0 12(C)
Final answer: (199)10= (C7)16 4.
(256)10
OCTAL:
INTEGER PART QUOTIENT REMAINDER
256/8 32 0
32/8 4 0
4/8 0 4
Final answer: (256)10= (400)8
HEXADECIMAL:
INTEGER PART QUOTIENT REMAINDER
256/16 16 0

15
 16/16 1 0
1/16 0 1
Final answer: (256)10= (100)16

16
5.(100)10
OCTAL:
INTEGER PART QUOTIENT REMAINDER
100/8 12 4
12/8 1 4
1/8 0 1
Final answer: (100)10= (144)8

HEXADECIMAL:
INTEGER PART QUOTIENT REMAINDER
100/16 6 4
6/16 0 6
Final answer: (100)10= (64)16
Q3. Convert Binary into Decimal, Octal and Hexadecimal
a) (1011)2
=
1 x 23 + 0 x 22 + 1 x 21 + 1 x 20
= 8+0+2+1
=11
(1011)2 = (11)10
OCTAL
INTEGER PART QUOTIENT REMAINDER
11/8 1 3
1/8 0 1
(11)10= (13)8
HEXADECIMAL
INTEGER PART QUOTIENT REMAINDER
11/16 0 11(B)
(11)10=(B)16
b) (101001)2
=1 x 25 + 0 x 24 + 1 x 23 + 0 x 22 + 0 x 21 +1 x 20

=32+0+8+0+0+0+1
=41

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(101001)2= (41)10

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OCTAL
INTEGER PART QUOTIENT REMAINDER
41/8 5 1
5/8 0 5

(41)10 = (51)8
HEXADECIMAL
INTEGER PART QUOTIENT REMAINDER
41/16 2 9
2/16 0 2
(41)10 = (29)16
c) (11100011)2
=1 x 27 +1 x 26 + 1 x 25 + 0 x 24 + 0 x 23 + 0 x 22 + 1 x 21 + 1 x 20

=128+64+32+0+0+0+2+1
=227
(11100011)2= (227)10
OCTAL
INTEGER PART QUOTIENT REMAINDER
227/8 28 3
28/8 3 4
3/8 0 3
(227)10= (343)8
HEXADECIMAL
INTEGER PART QUOTIENT REMAINDER
227/16 14 3
14/16 1 14(E)
(227)10= (E3)16
d) (110001110)2
=1 x 28 +1 x 27 +0 x 26 + 0 x 25 + 0 x 24 + 1 x 23 + 1 x 22 + 1 x 21 + 0 x 20

=256+128+0+0+0+8+4+2+0
=398
(110001110)2=(398)10

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INTEGER PART QUOTIENT REMAINDER
398/8 49 6
49/8 6 1

20
(398)10= (616)8
HEXADECIMAL
INTEGER PART QUOTIENT REMAINDER
398/16 24 14(E)
24/16 1 8
1/16 0 1
(398)10= (18E)16
e) (10000010001)2
=1 x 210 + 0 x 29+0 x 28 +0 x 27 +0 x 26 + 0 x 25 + 1 x 24 + 0 x 23 + 0 x 22 + 0 x 21 + 1 x 20

=1020+0+0+0+0+0+16+0+0+0+1
=1041
(10000010001)2= (1041)10
OCTAL:
INTEGER PART QUOTIENT REMAINDER
1041/8 130 1
130/8 16 2
16/8 2 0
2/8 0 2
(1041)10= (2021)8
HEXADECIMAL
INTEGER PART QUOTIENT REMAINDER
1041/16 65 1
65/16 4 1
4/16 0 4
(1041)10= (411)16
Q4) Convert Octal into Decimal Numbers
a) (57)8
=5 x 81
+ 7 x 80
=40+7
=47
(57)8=(47)10

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b) (101)8

22
 =1 x 82 +0 x 81 +1 x 80

=64+0+1
=65
(101)8=(65)10
c) (77)8
=7 x 81
+ 7 x 80
=56+7
=63
(77)8=(63)10
d) (245)8
=2 x 82 +4 x 81 + 5 x 80

=128+32+5
=165
(245)8=(165)10
e) (1205)8
=1 x 83 + 2 x 82 +0 x 81 + 5 x 80

=645+128+0+5
=778
(1205)8=(778)10
Q5) Convert Hexadecimal to Decimal
a) (2D)16
Here D=13,
=2 x 161
+ 13 x 160
=32+13
=45 (2D)16=(45)10
b) (101)16
=1 x 162 + 0 x 161 + 1 x 16 =256+0+1
23
=257
(101)16=(257)10
c) (AB)16
Here A=10, B=11
=10 x 161
+ 11 x 160
=160+11
=171
(AB)16=(171)10
d) (1F8)16
Here F=15
=1 x 162
+ 15 x 161 + 8 x 160
=256+240+8
=504
(1F8)16= (504)10
e) (ABC16)16
Here A=10, B=11, C=12
=10 x 163
+ 11 x 162 + 12 x 161 + 16 x 160
=40960+2816+192+16
=43984
(ABC)16= (43984)10

Q6. Convert Octal to Binary and Hexadecimal

a) (67)8
=6 x 81
+ 7 x 80
=48 + 7
24
=55 (67)8= (55)10

25
BINARY:
INTEGER PART QUOTIENT REMAINDER
55/2 27 1
27/2 13 1
13/2 6 1
6/2 3 0
3/2 1 1
1/2 0 1
(55)10= (110111)2
HEXADECIMAL:
INTEGER PART QUOTIENT REMAINDER
55/16 3 7
3/16 0 3
(55)10= (37)16
b) (123)8
=1 x 82
+ 2 x 81 + 3 x 80
=64+16+3
=83
(123)8= (83)10
BINARY:
INTEGER PART QUOTIENT REMAINDER
83/2 41 1
41/2 20 1
20/2 10 0
10/2 5 0
5/2 2 1
2/2 1 0
1/2 0 1
(83)10= (1010011)2
HEXADECIMAL:
INTEGER PART QUOTIENT REMAINDER
83/16 5 3
5/16 0 5
(83)10= (53)16
c) (167)8

26
=1 x 82
+ 6 x 81 + 7 x 80

27
=64+48+7

28
=119
(167)8= (119)10
BINARY:
INTEGER PART QUOTIENT REMAINDER
119/2 59 1
59/2 29 1
29/2 14 1
14/2 7 0
7/2 3 1
3/2 1 1
1/2 0 1
(119)10= (1110111)2
HEXADECIMAL:
INTEGER PART QUOTIENT REMAINDER
119/16 7 7
7/16 0 7
(119)10= (77)16
d) 123.35
=1 x 82 + 2 x 81 + 3 x 80 + 3 x 8-1 + 5 x 8-2

=64+16+3+0.375+0.046875
=83.421875
(123.35)8= (83.421875)10
BINARY:
INTEGER PART QUOTIENT REMAINDER
83/2 41 1
41/2 20 1
20/2 10 0
10/2 5 0
5/2 2 1
2/2 1 0
1/2 0 1
(83)10= (1010011)2
HEXADECIMAL:
INTEGER PART QUOTIENT REMAINDER
83/16 5 3
5/16 0 5
29
(83)10= (53)16
e) (745)8

30
=7 x 82
+ 4 x 81+ 5 x 80
= 448+32+5
=485
(745)8= (485)10
BINARY:
INTEGER PART QUOTIENT REMAINDER
485/2 242 1
242/2 121 0
121/2 60 1
60/2 30 0
30/2 15 0
15/2 7 1
7/2 3 1
3/2 1 1
1/2 0 1
(485)10= (111100101)2
HEXADECIMAL:
INTEGER PART QUOTIENT REMAINDER
485/16 30 5
30/16 1 14(E)
1/16 0 1
(485)10= (1E5)16
f) (1054)8
=1 x 83 + 0 x 82 + 5 x 81 + 4 x 80

=512+0+40+4
=556
(1054)8= (556)10
BINARY:
INTEGER PART QUOTIENT REMAINDER
556/2 278 0
278/2 139 0
139/2 69 1
69/2 34 1
34/2 17 0
17/2 8 1
8/2 4 0
31
4/2 2 0
2/2 1 0
1/2 0 1

32
(556)10= (1000101100)2
HEXADECIMAL:
INTEGER PART QUOTIENT REMAINDER
556/16 34 12(C)
34/16 2 2
2/16 0 2
(556)10= (22C)16
Q7. Convert Hexadecimal into Binary and Octal
1) (7F)16
Here F=15
=7 x 161
+ 15 x 160
=112+15
=127
(7F)16= (127)10
BINARY:
INTEGER PART QUOTIENT REMAINDER
127/2 63 1
63/2 31 1
31/2 15 1
15/2 7 1
7/2 3 1
3/2 1 1
1/2 0 1
(127)10= (1111111)2
OCTAL:
INTEGER PART QUOTIENT REMAINDER
127/8 15 7
15/8 1 7
1/8 0 1
(127)10= (177)8
2) (207)16
=2 x 162
+ 0 x 161 + 7 x 160
=512+0+7

33
=519

34
(207)16= (519)10 BINARY:

35
 INTEGER PART QUOTIENT REMAINDER
519/2 259 1
259/2 129 1
129/2 64 1
64/2 32 0
32/2 16 0
16/2 8 0
8/2 4 0
4/2 2 0
2/2 1 0
1/2 0 1
(519)10= (1000000111)2
OCTAL:
INTEGER PART QUOTIENT REMAINDER
519/8 64 7
64/8 8 0
8/8 1 0
1/8 0 1
(519)10= (1007)8

3) (AB)16
=10 x 161
+ 11 x 160
=160+11
=171
(AB)16= (171)10
BINARY:
INTEGER PART QUOTIENT REMAINDER
171/2 85 1
85/2 42 1
42/2 21 0
21/2 10 1
10/2 5 0
5/2 2 1
2/2 1 0
1/2 0 1
(171)10= (10101011)2
OCTAL:

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 INTEGER PART QUOTIENT REMAINDER
171/8 21 3
21/8 2 5
2/8 0 2
(171)10= (253)8
4) (ABC)16
Here A=10, B=11, C=13
=10 x 162
+ 11 x 161 + 13 x 160
=2560+176+13
=2749
(ABC)16= (2749)10
BINARY:
INTEGER PART QUOTIENT REMAINDER
2749/2 1374 1
1374/2 687 0
687/2 343 1
343/2 171 1
171/2 85 1
85/2 42 1
42/2 21 0
21/2 10 1
10/2 5 0
5/2 2 1
2/2 1 0
1/2 0 1
(2749)10= (101010111101)2
OCTAL:
INTEGER PART QUOTIENT REMAINDER
2749/8 343 5
343/8 42 7
42/8 5 2
5/8 0 5
(2749)10= (5275)8
5) (9F8)16
Here F=15
=9 x 162
+ 15 x 161 + 8 x 160
37
=2304+240+8
=2552
(9F8)16= (2552)10
BINARY:

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 INTEGER PART QUOTIENT REMAINDER
2552/2 1276 0
1276/2 638 0
638/2 319 0
319/2 159 1
159/2 79 1
79/2 39 1
39/2 19 1
19/2 9 1
9/2 4 1
4/2 2 0
2/2 1 0
1/2 0 1
(2552)10= (100111111000)2
OCTAL:
INTEGER PART QUOTIENT REMAINDER
2552/8 319 0
319/8 39 7
39/8 4 7
4/8 0 4
(2552)10= (4770)8

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 PRACTICAL-2
ROLL NO:
FCS2425078 AIM:
LOGIC GATE
NOT: A NOT gate, also known as an inverter, is a fundamental building block in digital electronics. It is a
logic gate that has only one input and one output, and its function is to invert the input signal

CIRCUIT DIAGRAM:

TRUTH TABLE:
INPUT OUTPUT
0 1
1 0

LOGISIM:
CASE 1: WHEN A=0 THEN THE OUTPUT IS A=1

CASE 2: WHEN A=1 THEN THE OUTPUT IS A=0

40
AND: An AND gate is a logic gate having two or more inputs and a single output. An AND gate operates
on logical multiplication rules.
CIRCUIT DIAGRAM:

TRUTH TABLE:
INPUT 1 (A) INPUT 2 (B) OUTPUT
0 0 0
0 1 0
1 0 0
1 1 1

LOGISIM:
CASE 1: WHEN A=0 AND B=0 THEN THE OUTPUT IS Y= 0

CASE 2: WHEN A=0 AND B=1 THEN THE OUTPUT IS Y=0

CASE 3: WHEN A=1 AND B=0 THEN THE OUTPUT IS Y=0

41
CASE 4 : WHEN A=1 AND B=1 THEN THE OUTPUT IS Y=1

OR: OR GATE is most widely used digital logic circuit and is known as a primitive digital
electronics building block in digital logic. The output state of OR gate will be high i.e.,(1) if
any of the input state is high or 1, else output state will be low i.e., 0
CIRCUIT DIAGRAM:

TRUTH TABLE:
INPUT 1 (A) INPUT 2 (B) OUTPUT (Y)
0 0 0
0 1 1
1 0 1
1 1 1

LOGISIM:

CASE 1: WHEN A=0 AND B=0 THEN THE OUTPUT IS Y= 0

42
CASE 2: WHEN A=0 AND B=1 THEN THE OUTPUT IS Y=1

CASE 3: WHEN A=1 AND B=0 THEN THE OUTPUT IS Y=1

CASE 4: WHEN A=1 AND B=1 THEN THE OUTPUT IS Y=1

XOR (UNIVERSAL GATE): XOR gate (sometimes EOR, or EXOR and pronounced as
Exclusive OR) is a digital logic gate that gives a true (1 or HIGH) output when the number of
true inputs is odd

CIRCUIT DIAGRAM:

TRUTH TABLE:
INPUT 1 (A) INPUT 2 (B) OUTPUT (Y)
0 0 0
0 1 1
1 0 1
1 1 0
43
CASE 1: WHEN A=0 AND B=0 THEN THE OUTPUT IS Y=0

CASE 2: WHEN A=0 AND B=1 THEN THE OUTPUT IS Y=1

CASE 3: WHEN A=1 AND B=0 THEN THE OUTPUT IS Y=1

CASE 4: WHEN A=1 AND B=1 THEN THE OUTPUT IS Y=0

XNOR (UNIVERSAL GATE): The XNOR gate is a type of logic gate used to
perform an exclusive NOR gate. It is a special type of logic gate used in digital
circuits. An XNOR gate, also known as an equivalence gate or an EX-NOR gate, is a
digital logic gate that outputs true (1) when an even number of true inputs are present.
It produces a true output if both of its inputs are the same (either both true or both
false). It is also known as the material biconditional

44
CIRCUIT DIAGRAM:

TRUTH TABLE:
INPUT 1 (A) INPUT 2 (B) OUTPUT (Y)
0 0 1
0 1 0
1 0 0
1 1 1

LOGISIM:
CASE 1: WHEN A=0 AND B=0 THEN THE OUTPUT IS Y=1

CASE 2: WHEN A=0 AND B=1 THEN THE OUTPUT IS Y=0

CASE 3: WHEN A=1 AND B=0 THEN THE OUTPUT IS Y=0

45
CASE 4: WHEN A=1 AND B=1 THEN THE OUTPUT IS Y=1

NAND (UNIVERSAL GATE): NAND gate (NOT-AND) is a logic gate which produces an
output which is false only if all its inputs are true; thus its output is complement to that of an
AND gate. A LOW (0) output results only if all the inputs to the gate are HIGH (1); if any input
is LOW (0), a HIGH (1) output results.
CIRCUIT DIAGRAM:

TRUTH TABLE:
INPUT 1 (A) INPUT 2 (B) OUTPUT (Y)
0 0 1
0 1 1
1 0 1
1 1 0

LOGISIM:
CASE 1: WHEN A=0 AND B=0 THEN THE OUTPUT IS Y=1

46
CASE 2: WHEN A=0 AND B=1 THEN THE OUTPUT IS Y=1

CASE 3: WHEN A=1 AND B=0 THEN THE OUTPUT IS Y=1

CASE 4: WHEN A=1 AND B=1 THEN THE OUTPUT IS Y=0

NOR GATE (UNIVERSAL GATE): NOR gate performs NOR(NOT OR) operation between
two or more binary inputs and gives output binary signal. This is a combination of OR gate and
NOT gate. It gives the output high(1) only when all of its inputs are low(0). In simple words we
can say that NOR gate is the opposite (inverted) of OR Gate
CIRCUIT DIAGRAM:

47
TRUTH TABLE:
INPUT 1 (A) INPUT 2 (B) OUTPUT (Y)
0 0 1
0 1 0
1 0 0
1 1 0

LOGISIM:
CASE 1: WHEN A=0 AND B=0 THEN THE OUTPUT IS Y=1

CASE 2: WHEN A=0 AND B=1 THEN THE OUTPUT IS Y=0

CASE 3: WHEN A=1 AND B=0 THEN THE OUTPUT IS Y=0

CASE 4: WHEN A=1 AND B=1 THEN THE OUTPUT IS Y=0

48
49
 PRACTICAL-3
ROLL NO: FCS2425078
AIM: Design and verify a half/full Subtractor
A) HALF SUBTRACTOR:
1. A Half Subtractor subtracts 2 binary bits at a time
2. Given below is the circuit diagram

Logic Diagram

1. It is constructed by using EX-OR Gate, NOT Gate, AND gate.

2. The output of EX-OR gives Difference and output of AND gate gives Borrow
3. The input of A is applied EX-OR while it is the compliment of A is applied to AND gate
4. The input of B is applied to both EX-OR and

AND Difference :Y=A ⊕ B= A.B’ + A’.B

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Borrow: Y=A’. B

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TRUTH TABLE:
I/p A I/p B DIFFERENCE BORROW
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
LOGISIM:
CASE 1: When A=0 , B=0 then Difference=0 and Borrow=0

CASE 2: When A=0 , B=1 then Difference=1 and Borrow=0

CASE 3: When A=1 , B=0 then Difference=1 and Borrow=0

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CASE 4: When A=1 , B=1 then Difference=0 and Borrow=0

B) FULL SUBTRACTOR:
1. Full Subtractor subtracts 3 binary bits at a time.
2. Given below is circuit diagram

Logic Diagram:

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1. It is constructed by using 2 EX-OR Gate, 2 NOT Gate, 2 AND gate, 1 NOT gate
2. The output of EX-OR gives Difference and output of OR gate gives Borrow
3. The input of A & B is applied First EX-OR while the output is given as input to second
EX- OR Gate with input C
4. The compliment of EX-OR gate’s output & input C is applied to first AND
Gate. Difference Equation: Y=A’. B’.C + A’. B .C’ + A. B’. C’
Borrow Equation: Y=C(A ⊕ B)+A’B
TRUTH TABLE:
I/p A I/p B I/p C Difference Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

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Logisim:

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CASE 1: When A=0 , B=0, C=0 then Difference=0 and Borrow=0

CASE 2: When A=0 , B=0, C=1 then Difference=1 and Borrow=1

CASE 3: When A=0 , B=1, C=0 then Difference=1 and Borrow=1

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CASE 4: When A=0 , B=1, C=1 then Difference=0 and Borrow=1

CASE 5: When A=1 , B=0, C=0 then Difference=1 and Borrow=0

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CASE 6: When A=1 , B=0, C=1 then Difference=0 and Borrow=0

CASE 7: When A=1 , B=1, C=0 then Difference=0 and Borrow=0

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CASE 8: When A=1 , B=1, C=1 then Difference=1 and Borrow=1

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 PRACTICAL-4
ROLL NO: FCS2425078
AIM: Design and verify a half/full Adder
A) Half Adder:
1. Half Adder adds 2 binary bits at a time.
2. Given below is the circuit diagram

LOGIC DIAGRAM:

1. It is constructed by using EX-OR Gate, AND gate.

2. The output of EX-OR gives Sum and output of AND gate gives Carry
3. The input of A is applied EX-OR & AND Gate
4. The input of B is applied to both EX-OR & AND

Gate Sum: Y=A ⊕ B= A.B’ + A’.B

Carry: Y=A. B

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TRUTH TABLE:

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 I/p A I/p B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 1 1

Logisim:
CASE 1: When A=0 , B=0 then Sum=0 and Carry=0

CASE 2: When A=0 , B=1 then Sum=1 and Carry=0

CASE 3: When A=1 , B=0 then Sum=1 and Carry=0

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CASE 4: When A=1 , B=1 then Sum=1 and Carry=1

B) Full Adder:
1. Full Adder adds 3 binary bits at a time
2. Given below is the circuit diagram.

LOGIC DIAGRAM:

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1. It is constructed by using 2 EX-OR Gate, 2 AND gate, 1 OR gate
2. The output of EX-OR gives Sum and output of OR gate gives Carry
3. The input of A & B is applied First EX-OR while the output is given as input to second
EX- OR Gate with input C
4. The EX-OR gate’s output & input C is applied to first AND
Gate. Sum Equation: Y=A’. B’.C + A’. B .C’ + A. B’. C’
Carry Equation: Y=A.B + B.C+ A.C
TRUTH TABLE:
I/p A I/p B I/p C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1

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 1 1 1 1 1
LOGISIM:
CASE 1: When A=0 , B=0, C=0 then SUM=0 and CARRY=0

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CASE 2: When A=0 , B=0, C=1 then SUM=1 and CARRY=0

CASE 3: When A=0 , B=1, C=0 then SUM=1 and CARRY=0

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CASE 4: When A=0 , B=1, C=1 then SUM=0 and CARRY=1

CASE 5: When A=1 , B=0, C=0 then SUM=1 and CARRY=0

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CASE 6: When A=1, B=0, C=1 then SUM=0 and CARRY=1

CASE 7: When A=1 , B=1, C=0 then SUM=0 and CARRY=1

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CASE 8: When A=1 , B=1, C=1 then SUM=1 and CARRY=1

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 PRACTICAL –5
ROLL NO : FCS2425078
AIM: MINIMIZING BOOLEAN EXPRESSIONS
1) X= ABC + ~AB + AB~C

INPUT:

OUTPUT:

TABLE:

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EXPRESSION:

CIRCUIT 1:

MINIMIZED:

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TABLE:

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CIRCUIT 2:

2) X= ~AB~C + A~B~C + ~A~B~C + ~AB + AC

INPUT:

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OUTPUT:

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TABLE:

EXPRESSION:

CIRCUIT 1:

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MINIMIZED:

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TABLE:

CIRCUIT 2:

3) X= A~B~C + ~A~B~C + ~AB~C + ~A~BC

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INPUT:

OUTPUT:

TABLE:

EXPRESSION:

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CIRCUIT 1:

MINIMIZED:

TABLE:

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CIRCUIT 2:

4) X= ABC + ~AC +BC

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INPUT:

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OUTPUT:

TABLE:

EXPRESSION:

CIRCUIT 1:

MINIMIZED:

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TABLE:

CIRCUIT 2:

5) X= AB + A(~B + C) +AB~C

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INPUT:

OUTPUT:

TABLE:

EXPRESSION:

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CIRCUIT 1:

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MINIMIZED:

TABLE:

CIRCUIT 2:

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6) X= ABC +~AC

INPUT:

OUTPUT:

TABLE:

EXPRESSION:

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CIRCUIT 1:

MINIMIZED:

TABLE:

CIRCUIT 2:

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7) X= ABC + A~BC +~A

INPUT:

OUTPUT:

TABLE:

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EXPRESSION:

CIRCUIT 1:

MINIMIZED:

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TABLE:

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CIRCUIT 2:

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 PRACTICAL – 6
ROLL NO:
FCS2425078 AIM:
S-R FLIPFLOP: SR flip flop, also known as SR latch is the basic and
simplest type of flip flop. It is a single bit storage element. It has only
two logic gates. The output of each gate is connected to the input of
another gate.

TRUTH TABLE:
INPUT: S INPUT: R OUTPUT:Q OUTPUT:Q’ STATUS
0 0 1 0 PREVIOUS
0 1 0 1 RESET
1 0 1 0 SET
1 1 0 0 FORBIDDEN
LOGISIM:
CASE 1: WHEN S=0, R=0, CLK= OFF, Q=NO CHANGE, STATE= PREVIOUS.

CASE 2: WHEN S=0, R=1, CLK= ON, Q=0, Q’=1 , STATE= RESET

CASE 3: WHEN S=1, R=0, CLK= ON, Q=1, Q’=0 , STATE= SET

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CASE 4: WHEN S=1, R=1, CLK= ON, Q=0, Q’=0, STATE= FORBIDDEN

D FLIPFLOP:
D flip flop is an electronic devices that is known as “delay flip flop” or “data flip
flop” which is used to store single bit of data.D flip flops are synchronous or
asynchronous. The clock single required for the synchronous version of D flip
flops but not for the asynchronous one.The D flip flop has two inputs, data and
clock input which controls the flip flop. when clock input is high, the data is
transferred to the output of the flip flop and when the clock input is low, the output
of the flip flop is held in its previous
TRUTH TABLE:
INPUT: D OUTPUT: Q’
0 0
1 1

LOGISIM:
CASE 1: WHEN D = 0, Q’ = 0

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CASE 2: WHEN D = 1, Q’ = 1

T FLIPFLOP:
T flip flop or to be precise is known as Toggle Flip Flop because it can able to
toggle its output depending upon on the input.
T here stands for Toggle.
Toggle basically indicates that the bit will be flipped i.e., either from 1 to 0 or
from 0 to 1.
Here, a clock pulse is supplied to operate this flop, hence it is a clocked flip-flop.

TRUTH TABLE:
INPUT :T CLOCK OUTPUT: Q OUTPUT: Q’
0 ON Q Q’
1 ON Q’ Q
X OFF Q Q’

LOGISIM:

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CASE 1: WHEN T=0, CLOCK= ON THEN Q= 0, Q’= 1

CASE 2: WHEN T=1, CLOCK= ON THEN Q= 1, Q’= 0

CASE 3: WHEN T=X, CLOCK= OFF THEN Q= 0, Q’= 1

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 PRACTICAL-7
ROLL NO: FCS2425078
AIM: LOGISIM ON MULTIPLEXER
MULTIPLEXER: A multiplexer (MUX), also known as a data selector, is a combinational
logic circuit that selects one of several input signals and forwards it to a single output line.
The selection of the input is controlled by a set of select lines. Think of it like a switch
that can connect one of many inputs to a single output.
TYPES OF MULTIPLEXERS:
1) 2:1 MULTIPLEXER
2) 4:1 MULTIPLEXER
1) 2:1 MULTIPLEXER: The 2×1 is a fundamental circuit which is also known 2-to-1
multiplexer that are used to choose one signal from two inputs and transmits it to the
output. The 2×1 mux has two input lines, one output line, and a single selection line. It has
various applications in digital systems such as in microprocessor it is used to select
between two different data sources or between two different instructions.
CIRCUIT DIAGRAM:

TRUTH TABLE:
Select input: s Data input : D0 Data input: D1 Output: Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

LOGISIM:
CASE 1: When D0=0, D1= 0, select input=0 then output=0

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CASE 2: When D0=0, D1= 1, select input=0 then output=0

CASE 3: When D0=1, D1= 0, select input=0 then output=1

CASE 4: When D0=1, D1= 1, select input=0 then output=1

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CASE 5: When D0=0, D1= 0, select input=1 then output=0

CASE 6: When D0=0, D1= 1, select input=1 then output=1

CASE 7: When D0=1, D1= 0, select input=1 then output=0

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CASE 8: When D0=1, D1= 1, select input=1 then output=1

10
0
2) 4:1 MULTIPLEXER: The 4×1 Multiplexer which is also known as the 4-to-1
multiplexer. It is a multiplexer that has 4 inputs and a single output. The Output is selected
as one of the 4 inputs which is based on the selection inputs. The number of the Selection
lines will depend on the number of the input which is determined by the equation log2nlog2
n ,In 4×1 Mux the selection lines can be determined as log4=2log4 =2 ,slo two selections
TRUTH TABLE :
Select input: S1 Select input: S0 Input Output
0 0 D0 D0
0 1 D1 D1
1 0 D2 D2
1 1 D3 D3

LOGISIM:
CASE 1: When S0=0, S1=0, input=D0, output= D0

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CASE 2: When S0=1, S1=0, input=D1, output= D1

CASE 3: When S0=0, S1=1, input=D2, output= D2

CASE 4: When S0=1, S1=1, input=D3, output= D3

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