Bluetooth Headset IC - WS9625ABSCF

Datasheet

Version: V1.1, May 2014

110/F 530 Tower, QingYuan Road, TaiHu International Technology Park,

WuXi New District, 214135, China
Tel: 86-510-81816000
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Web: www.vimicro.com
WS9625ABSCF

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Datasheet (V1.1) Copyright © Vimicro_wx, Inc. 1999-2014

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WS9625ABSCF

TABLE OF CONTENTS
OVERVIEW ............................................................................................................... 4
FEATURES ............................................................................................................... 4
TYPICAL APPLICATION .......................................................................................... 5
PIN CONFIGURATIONS ........................................................................................... 6
PIN DESCRIPTION ................................................................................................... 7
FUNCTIONAL BLOCK DESCRIPTION ................................................................... 9
Radio Transceiver .................................................................................... 9
Transmitter Path ....................................................................................... 9
Receiver Path ........................................................................................... 9
Audio codec .............................................................................................. 9
Power Management ................................................................................. 9
SRAM ......................................................................................................... 9
ROM ........................................................................................................... 9
DEVICE TERMINAL DESCRIPTIONS ................................................................... 10
Power Supply ......................................................................................... 10
Crystal Oscillator ................................................................................... 10
RF Interface ............................................................................................ 11
Audio Interface ....................................................................................... 11
UART Interface ....................................................................................... 11
Function Description .......................................................................... 11
Serial Operation .................................................................................. 11
UART External Connection for Bluetooth .......................................... 11
2
I C Interface ............................................................................................ 12
2
Interface Timing Signal with I C bus .................................................. 13
System Configuration .......................................................................... 13
I2C Protocol ......................................................................................... 13
START Signal...................................................................................... 13
Slave Address Transfer ....................................................................... 13
Data Transfer ...................................................................................... 13
STOP Signal ....................................................................................... 14
Arbitration Procedure .......................................................................... 14
GPIO interface ........................................................................................ 14
ELECTRICAL CHARACTERISTICS ...................................................................... 16
RF Specifications ................................................................................... 16
Power Consumption .............................................................................. 17
Power Meter ............................................................................................ 17
PACKAGE INFORMATION .................................................................................... 18
CONTACT INFORMATION ..................................................................................... 19

Datasheet (V1.1) Copyright © Vimicro_wx, Inc. 1999-2014

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WS9625ABSCF

OVERVIEW
WS9625ABSCF is a stereo single chip headset solution based on Bluetooth protocol. It consists of 128 MHz high
performance CPU processor, SRAM, via ROM Bluetooth baseband controller, MODEM, RF, Audio CODEC, PMU,
etc. The protocol stack is stored in the on-chip ROM. It is fully compliant with all the mandatory features of
Bluetooth version 4.1 + EDR specification.

FEATURES
 128 MHz high performance CPU processor.  Working temperature range -40 to +80 ℃.
 Internal 512KB via ROM.  Dual Mic Acoustic Noise Cancellation. Used
 Internal 4M bit SPI flash. to eliminate the stationary and
non-stationary noise on Tx.
 -92dBm RX sensitivity and +9dBm TX output
power capability  Single-microphone echo Cancellation. Used
to cancel acoustic echo.
 Logic for forward error correction, header
error control, access code correlation, CRC,  Single-microphone noise suppression. Used
demodulation, encryption bit stream to reduce stationary noise on Tx and Rx
generation, and whitening and transmit pulse  Packet Loss Concealment. Used to restore
shaping. audio quality in difficult RF environment on
 Fully qualified Bluetooth v4.1 + EDR feature Rx.
including eSCO and AFH.  Equalizer. Supports six arbitrarily frequency
 Internal 128KB SRAM. Allows full-speed bands and the bandwidth can be adjusted.
data transfer with full piconet support, mixed  Automatic Gain Control. Performs automatic
voice and data, including all EDR packet volume adjustment of the signal on Tx and
types. Rx.
 Audio transcoders for A-law, μ-law and linear  Speech Tone. Encoded with SBC (Sub-Band
voice from host and A-law, μ-law and CVSD Codec) format and stored in EEPROM, to
voice over air. indicate general event from headset by
 UART interface with programmable baud specified tone directly.
rate up to 3Mbps for HCI communication.  Speech recognition support. Speaker

2
Multiple I C interface for external EEPROM. dependent speech recognition to handle
answering/rejecting incoming call or other
 Boot loader with external memory interface speech instructions.
for software debugging.
 Voice Name Prompt support. Record voice
 Internal 32 KHz oscillator for low power tags for each phone numbers. After that,
operation. when the phone with the dedicate phone
 QFN48 package. number incoming call, headset will play out
 SPI flash support. Operation voltage is 3.3V. corresponding voice tag.
 Battery power display support. Allows user to  Advanced multi-point support. Allows
use buttons to trigger a tone/speech tone or connecting 2 devices (either phones or pads)
a led, to prompt the current battery. and handling multiple calls or music at the
same time.
 SPP support. Increased SPP protocol, which
is used to transmit commands and data,  Bluetooth Air path parameter configuration.
realize interaction control with other  24 bit Audio codec, -98dB SNR.
equipment that supports SPP.  Low radio power realizes 10+meter
 AT Command support. Communicates with communication (class2).
MCU through the UART，controlled by the  Fast charger: 30 minutes charging time.
MCU，or converted the command to
 No Balun filter required for connection.
bluetooth command，sent to the mobile
phone to realize the control of the phone by  Battery monitor designed for smart phones.
MCU.  Watch dog for link loss alarm.

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WS9625ABSCF
TYPICAL APPLICATION
CRYSTAL 26M+-10PPM

GPIO7/EEPROM_SCK

GPIO8/EEPROM_SDA
Y1 2

C1 C2 C3 4

XTAL_OUT
NC NC 0.22µF

XTAL_IN
3
RFOUT C4
20pF

U1

38
RF_RTXP 35

AVDD_RF 36

PROM_SDA 26

PROM_SCL 24

39

XTAL_IN
XTAL_OUT
MBIAS C5 10µF VREF 9 VREF 33
GPIO1/TX GPIO1
31
GPIO3/RX GPIO3
C6 2.2µF MBIAS 10 32
MBIAS GPIO2/RTS GPIO2
30
MBIAS C7 1µF VCOM 15 RF GPIO4/CTS GPIO4
VCOM PROM Crystal

C8 0.22µF MICLP 11 28
MICLP GPIO5/SWCLK GPIO5/SWCLK
AUDIO

27
R1 MBIAS C9 0.22µF MICLN 12 GPIO6/SWDIO GPIO6/SWDIO
MICLN
MICL 2.2k
C10 0.22µF MICRP 13

GPIO INTERFACE
MICRP
R2 MBIAS C11 0.22µF MICRN 14 23
GPIO9/SPI_CSN GPIO9/SPI_CSN
MICRN 22
MICR 2.2k GPIO10/SPI_SI GPIO10/SPI_SI
CDC_HPOUT-R 4 GPIO11/SPI_SO 21 GPIO11/SPI_SO
CDC_HPOUT-R HPOUT_R 20
5 NC WS9625ABSCF GPIO12/SPI_SCLK

CDC_HPOUT_L 6
CDC_HPOUT_L HPOUT_L
7 18
NC GPIO13/LED1 GPIO13/LED1/UART1_TX

C12 VBAT 44 VBAT GPIO14/LED2 17 GPIO14/LED2/UART1_RX

10µF QFN48
SWS 43 GPIO15/LED3 16 GPIO15/LED3/SEL0
SWS
10µH/绕线/500mA
47 GPIO_B/LED4 42 GPIOB/LED4/SEL1
DCDC15
FBS
VCHGER 46
D1 VCHG 41
GPIO_A/GPIO20 GPIO_A
C13 C14 PWR 2
PWR
NC POWER
10µF
4.7µF ceramic DVDD33 45
VOL1
VDD33/SPI_VDD

C15 DVDD12 48
VOL2
VDD_ADDA

1µF ceramic
VDD_PAM

VDD_REG
VDD12_2

VDD12_1

C16 49
GROUND
VOL5

1µF ceramic
RST

VSS

34

37

40
1

29

25
19

VDD_ADDA
VDD_PAM

DCDC15
DVDD12

DVDD12

DVDD33

RST
AVDD

RST

R3
0
C17 C18 C19 C20 C21 C22 C23
1µF ceramic 0.22µF 1µF 1µF 1µF 0.22µF 4.7µF ceramic

Figure 1 WS9625ABSC Typical Application

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WS9625ABSCF
PIN CONFIGURATIONS

TOP VIEW

VDD_ADDA
XTAL_OUT
VDD_REG

XTAL_IN
GPIO_B

GPIO_A
VCHG

VBAT
VOL2

VOL1

SWS
FBS
48 47 46 45 44 43 42 41 40 39 38 37
36 AVDD_RF
RST 1
35 RF_RTXP
PWR 2
34 VDDA_PAMID
VOL5 3
33 GPIO[1]
HPOUT_R 4
32 GPIO[2]
NC 5
31 GPIO[3]
HPOUT_L

NC
6

7
WS9625ABSCF 30 GPIO[4]

VSS 8 29 VDD12_2

VREF 9 28 GPIO[5]
VCOM 10 27 GPIO[6]
MBIAS 11 26 GPIO[7]

MICLP 12 25 VDD33
13 14 15 16 17 18 19 20 21 22 23 24
MICRN
MICRP

GPIO[13]

VDD12_1
MICLN

GPIO[8]
GPIO[9]
GPIO[15]

GPIO[14]

GPIO[12]

GPIO[11]

GPIO[10]

QFN48

Figure 2 WS9625ABSCF Pin Assignment (Not to scale)

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WS9625ABSCF
PIN DESCRIPTION
[Table 1] PIN Descriptions by Order
ORDER PIN NAME DIR POWER DESCRIPTION

1 RST AI AVDDBAT Set charging current.

2 PWR AI AVDDBAT High level (BAT voltage) means button is turned on.
LDO5 (3.3V) output. Power Supply for Audio an HP (AVDD33 power
3 VOL5 AIO AVDDBAT
domain).
4 HPOUT_R A, O AVDD33 Headphone right channel output.

5 NC - - Not connected.

6 HPOUT_L A, O AVDD33 Headphone left channel output.

7 NC - - Not connected.

8 VSS P AVDD33 Ground for Audio.

9 VREF AIO AVDD33 Internal reference voltage output,

10 MBIAS AIO AVDD33 Common mode reference voltage.

11 MICLP A, O AVDD33 Microphone bias voltage output, tied 2.2μF capacitor to AVSS.

12 MICLN A, I AVDD33 Microphone left channel input, positive end.

13 MICRP A, I AVDD33 Microphone left channel input, negative end.

14 MICRN A, I AVDD33 Microphone right channel input, positive end.

15 VCOM A, I AVDD33 Microphone right channel input, negative end.

16 GPIO[15] B VDD33 General purpose IO.

17 GPIO[14] B VDD33 General purpose IO.

18 GPIO[13] B VDD33 General purpose IO.

19 VDD12_1 P DVDD12 Digital core power.

20 GPIO[12] B VDD33 General purpose IO.

21 GPIO[11] B VDD33 General purpose IO.

22 GPIO[10] B VDD33 General purpose IO.

23 GPIO[9] B VDD33 General purpose IO.

24 GPIO[8] B VDD33 General purpose IO.

25 VDD33 P DVDD33 Digital I/O power.

26 GPIO[7] B VDD33 General purpose IO.

27 GPIO[6] B VDD33 General purpose IO.

28 GPIO[5] B VDD33 General purpose IO.

29 VDD12_2 P DVDD12 Digital core power.

30 GPIO[4] B VDD33 General purpose IO.

31 GPIO[3] B VDD33 General purpose IO.

32 GPIO[2] B VDD33 General purpose IO.

33 GPIO[1] B VDD33 General purpose IO.

34 VDDA_PAMID P,O AVDD125 PA supply. LDO output, connect to decoupling cap.

35 RF_RTXP AIO AVDD125 RF input/output, drive SAW filter. Require on board matching network.

36 AVDD_RF P AVDD125 RF front end supply.LDO output, connect to decoupling cap.

37 VDD_ADDA P AVDD125 analog vdd, LDO output, connect to decoupling cap.

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WS9625ABSCF
ORDER PIN NAME DIR POWER DESCRIPTION
38 XTAL_IN AIO AVDD125 XTAL input, connect to crystal.

39 XTAL_OUT AIO AVDD125 XTAL output, connect to crystal

VDD_REG XTAL/analog/RF LDO power (1.5V) input, external power supply from
40 P, I AVDD15
FBS .need 3.3uF and 4.7pF on board caps.
41 GPIO_A B VDD33 General purpose IO.

42 GPIO_B B VDD33 General purpose IO.

43 SWS AIO AVDDBAT Connect the inductor of switching Buck DC-DC.

44 VBAT P, IO AVDDBAT Battery positive terminal.

LDO1 (3.3V) output and input for POR. Power Supply of digital I/O
45 VOL1 AIO AVDDBAT
(DVDD33 power domain).
46 VCHG P, I AVDDBAT Charger input terminal.
The feedback pin of switching Buck DC-DC. Source of AVDD 15 power
47 FBS AIO AVDDBAT
domain.
48 VOL2 AIO AVDDBAT LDO2 (1.2V) output. Power Supply of core of digital logic.

[Table 2] PIN Numbers by Interface

INTERFACE PIN NUMBER

GPIO Interface 16~18, 20~24, 26~28, 30~33, 41~42

PMU Interface 1~3, 8~10, 19, 25, 29, 34, 36~37, 40, 43~48

Audio Interface 6~7, 11~15,

Radio Interface 35

Crystal Interface 38~39

Note 1:
P Power/Ground
A Analog
I Input
O Output
B Bi-direction
PP Internal programmable pull up/down
Sch Schmitt Input

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WS9625ABSCF
FUNCTIONAL BLOCK DESCRIPTION
that the controller can participate in a Bluetooth
power-controlled link.
Radio Transceiver
The WS9625ABSCF features an integrated radio
transceiver that has been optimized for Bluetooth 2.4
Audio codec
GHz wireless systems. It has been designed to Audio Codec includes two channel voice band 24bit
provide low power, low cost, and robust ADC, which can support stereo microphone recording,
communications for applications operating in the with one microphone bias output. The codec also has
globally available 2.4 GHz unlicensed ISM band. It is two channel CD quality 24bit Audio DACs, which
fully compliant with the Bluetooth Radio Specification support two 16Ω headphone / speakers with 40*2mW
4.1 and EDR specification, and meets or exceeds the output, or two 32Ω headphone / speakers with
requirements to provide the highest communication 40*2mW output.
link quality of service.
Power Management
Transmitter Path PMU is an integrated power solution for applications
The WS9625ABSCF features a fully integrated zero-IF powered by one small Li-Ion battery. It provides total
transmitter. The baseband transmits GFSK, DQPSK, power solution for WS9625ABSCF. It provides one
8DPSK data is digitally modulated in the modem block, highly efficient, low output ripple step-down converter
and then up-converts the data to the 2.4 GHz ISM to the core voltage. Step-down converter enters PFM
band in the transmitter path. The transmitter path mode at light load for maximum efficiency over the
consists of signal filters, I/Q up-converters, output widest possible range of load currents. The PMU also
Power Amplifiers (PAs), and RF filters. The digital integrates three LDO regulators (with Charger bypass
modulator performs the data modulation and filtering mode), POR, Start-up controller and a battery charger.
required for the GFSK, DQPSK, and 8-DPSK signals. The charger block will provide smart battery charging
The fully digital modulator minimizes any frequency management, while LDO will provide a low-noise
drift or anomalies in the modulation characteristics of power supply for WS9625, and POR will provide reset
the transmitted signal. signal for digital core.

Receiver Path SRAM

The receiver path uses an innovative The SRAM of 128kB is used in WS9625ABSCF Chip.
Adaptive-Adjustable-IF architecture (patent pending) This memory stores the data generated or required by
for improved anti-interference performance and low running the high performance CPU.
power consumption. The front-end topology with
built-in out-of-band attenuation enables the
WS9625ABSCF to be used in most applications with ROM
no off-chip filtering. The digital demodulator and bit
The VIA ROM of 512KB is employed in
synchronizer take the down-converted received signal
WS9625ABSCF Chip. This memory is used to store
and perform an optimal frequency tracking and bit
the firmware.
synchronization algorithm. The radio portion of the
WS9625ABSCF also provides a Received Signal
Strength Indication (RSSI) signal to the baseband so

Datasheet (V1.1) Copyright © Vimicro_wx, Inc. 1999-2014

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WS9625ABSCF
DEVICE TERMINAL DESCRIPTIONS
Power Supply
WS9625ABSCF is powered by one small Li-Ion battery via the pins VBAT and GNDS1. The voltage value range of
battery is from 3.0V to 5.5V.
It can be connected to charger via the pin VCHG; the charger block will provide smart battery charging
management and power supply through LDO for chip simultaneously. The Input voltage value range of charger is
from 3.0V to 6.5V (From Adapter or USB).

COL5
VOL5
1µF

VOL5
COL2
VDC(Adj) 1µF VOL2 (3.3V)
SWS VOL2
LS
COS 22µH VOL1 (1.2V)
GNDS VOL1
4.7µF

WS9625ABSCF COL1
FBS VCHG VCHG 1µF

PWR PWR VBAT VBAT

BAT

RS CBAT
4.7µF

RSET
2.5kΩ

Figure 3 WS9625ABSCF Typical Power Application

Crystal Oscillator
Port XTAL_IN and XTAL_OUT need to be bonded out and connect to the on-board crystal circuit. The load cap for
both pins is 4-12pF. The on-board crystal circuit needs to be placed close to the chip. The on-chip DCXO circuit
can work with crystal frequency from 13 to 52MHz.
The initialization time for the DCXO circuit to settle to 20ppm accuracy is 2mS. The reference clock generated by
the DCXO goes to RFPLL and DPLL. However, the reference clock generated by DCXO can be directly feed to the
digital baseband in that case.
The on-chip DCXO circuit has a cap tuning array that can be used to trim reference clock frequency.

XTAL_OUT XTAL_IN

CL=4-12pF

Figure 4Typical Applications of XTAL_IN and XTAL_OUT

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WS9625ABSCF
RF Interface
Port RFXP and AVDD_RF are the RF I/O ports and need to be bonded out. The two RF pins are connected to
on-board matching network which should be placed close to the chip. The associated on–board transmission line
routing should have 50Ω impedance matching.

Audio Interface
WS9625ABSCF supports Dual Microphone Audio inputs. The MICLP port is microphone left channel inputs, the
MICLN port is differential inputs, the MICRP port is microphone right channel inputs and the MICRN port is
differential inputs.
The stereo Audio output ports are HPOUTL and HPOUTR, while HPOUTL is headphone left channel output and
HPOUTR is headphone right channel output.

UART Interface
The UART ports are shared with GIPO [3:0]. Those ports are used as UART by configuring related register by SW.

Function Description
Serial Operation

The UART module has one operation mode --- non-return to zero (NRZ).
The NRZ mode is primarily associated with RS-232. Each character is transmitted as a frame delimited by a start
bit at the beginning and a stop bit at the end. Data bits are transmitted least significant bit first, each bit occupies a
period of time equal to 1 full bit. If parity is used, then the parity bit is transmitted after the most significant bit.
Following is the waveform in NRZ mode.
Start Bit
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Parity Bit
Stop Bit

NRZ mode transmits an ASCII “A” Character with Odd

parity Figure 5 Waveform of UART

UART External Connection for Bluetooth

The UART in WS9625ABMC can be used to transport HCI (Host Controller Interface) packets for Bluetooth. The
HCI UART Transport Layer uses the following settings for RS232:

[Table 3] HCI UART Transport Layer settings

Baud rate manufacturer-specific
Number of data bits 8
Parity bit no parity
Stop bit 1 stop bit
Flow control RTS/CTS (Hardware Flow Control)
Flow-off response time manufacturer specific

The RS232 signals should be connected in a null-modem fashion.

The most expensive null modem cable is the null modem cable suitable for full handshaking. In this null modem

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WS9625ABSCF
cable, seven wires are present. Only the ring indicator RI and carrier detect CD signal are not linked. The cable is
shown in the following figure. DTR and DSR are not used in UART of WS9625ABSCF.

Figure 6 Null Modem Cable Connections

Connector 1 Connector 2 Function

2 3 Rx Tx
3 2 Tx Rx
4 6 DTR DSR
5 5 Signal ground
6 4 DSR DTR
7 8 RTS CTS
8 7 CTS RTS

In CTS/RTS flow, the RTS output of device1 signals device2 that device1 is capable of receiving information, so
device2 will send the data out when the RTS signal of device1 is set valid. Also, device1 will send the data out
when the RTS signal of device2 is set valid.

I2C Interface
2
WS9625ABSCF provides PROM_SCL and PROM_SDA for communication with EEPROM which comply with I C
protocol.

2
I C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of data exchange between
devices. It is most suitable for applications requiring occasional communication over a short distance between
2
many devices. The I C standard is a true multi-master bus including collision detection and arbitration that
prevents data corruption if two or more masters attempt to control the bus simultaneously.
2
The I C interface defines 2 transmission speeds:
 Normal: 100Kbit/s
 Fast: 400Kbit/s

Only 100Kbps mode and 400Kbps mode are supported directly.

FEATURES:
2
 Compatible with I C standard;
 Multi Master Operation;
 Supports 7 and 10bit addressing mode;
 Software programmable clock frequency, supports a wide range of input clock frequencies;
 Software programmable acknowledge bit;
 Interrupt or bit-polling driven byte-by-byte data-transfers;
 Arbitration lost interrupt, with automatic transfer cancellation;
 Bus busy detection;
 Clock Stretching and Wait state generation;

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WS9625ABSCF
Interface Timing Signal with I2C bus
System Configuration
2
The I C system uses the serial data line (SDA) and serial clock line (SCL) for data transfers. All devices connected
to these two signals must have open drain or collector outputs. The logic AND function is exercised on both lines
with external pull-up resistors.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line via a byte-by-byte basis.
Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the MSB being transmitted first.
An acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the
SDA line may be changed only during the low period of SCL and it must be held stable during the high period of
SCL. While SCL is high, the transition on the SDA line is interpreted as a command (sees START and STOP
signals).

I2C Protocol
Generally, a standard communication consists of four parts:
 START signal generation
 Slave address transfer
 Data transfer
 STOP signal generation

S A7 A6 A5 A4 A3 A2 A1 R ack D7 D6 D5 D4 D3 D2 D1 D0 nack P
W
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

Figure 7 I2C protocol

START Signal

When the bus is free/idle, that is no master device is engaging the bus (both SCL and SDA lines are high), a
master can initiate a transfer by sending a START signal. The START signal, usually referred as the S-bit, is
defined as a high-to-low transition of SDA while SCL is high. The START signal denotes the beginning of a new
data transfer.
Repeated START is a START signal without first generating a STOP signal. The master uses this method to
communicate with another slave or the same slave in a different transfer direction (e.g. from writing to a device to
reading from a device) without releasing the bus.
The core generates a START signal when the STA-bit in the Command Register is set and the RD or WR bits are
set. Depending on the current status of the SCL line, a START or Repeated START is generated.

Slave Address Transfer

The slave address is the first byte of data transferred by the master immediately after the START signal. This is a
seven-bits calling address followed by a RW bit. The RW bit signals the slave data transfer direction. The slave
address is unique; no two slaves in the system can have the same address. Only the slave with an address that
matches the address transmitted by the master will respond, it responds by returning an acknowledge bit which is
pulled by the SDA low at the 9th SCL clock cycle.
2
Note: The core supports 10bit slave addresses by generating two address transfers. See the Philips I C
specifications for more details.
The core treats a Slave Address Transfer as any other write action. Store the slave device‟s address in the
Transmit Register and set the WR bit. The core will then transfer the slave address on the bus.

Data Transfer

Once achieved the successful slave addressing, the data transfer can proceed on a byte-by-byte basis in the

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WS9625ABSCF
direction specified by the RW bit that sent by the master. Each transferred byte is followed by an acknowledge bit
on the 9th SCL clock cycle. If the slave signals a No Acknowledge, the master will generate a STOP signal to abort
the data transfer, or generate a Repeated START signal and then start a new transfer cycle.
If the master, as the receiving device, does not acknowledge the slave, the slave should release the SDA line for
the master to generate a STOP or Repeated START signal.
To write data to a slave, store the data in the Transmit Register to be transmitted and set the WR bit. To read data
from a slave, set the RD bit. The core set the TIP flag during a transfer, indicating that a transfer is in progress.
When the transfer is done the TIP flag is reset, and generates an interrupt. The Receive Register contains valid
data after the IF flag is reset. The user may issue a new write or read command when the TIP flag is reset.

STOP Signal

The master can terminate the communication by generating a STOP signal. A STOP signal, usually referred as the
P-bit, is defined as a low-to-high transition of SDA while SCL is at logical „1‟.

Arbitration Procedure
Clock Synchronization
2
The I C bus is a true multi-master bus that allows more than one master to be connected on it. If two or more
masters simultaneously try to control the bus, a clock synchronization procedure determines the bus clock.
2
Because of the wired-AND connection of the I C signals, a high-to-low transition affects all the devices that
connected to the bus. Therefore a high–to-low transition on the SCL line causes all concerned devices to count off
their low period. Once a device clock has gone low, it will hold the SCL line in low state until the clock high state is
reached. Due to the wired-AND connection, the SCL line will therefore be held low by the device with the longest
low period, and held high by the device with the shortest high period.

Start counting Start counting

low period high period
wait
state

SCL1 Master1 SCL

SCL2 Master2 SCL

SCL wired-AND SCL

Figure 8 Arbitration Procedure

Clock Stretching
Slave devices can use the clock synchronization mechanism to slow down the transfer bit rate. After the master
has driven SCL low, the slave can drive SCL low for the required period and then release it. If the slave‟s SCL low
period is greater than the master‟s SCL low period, the resulting SCL bus signal low period will be stretched, thus
inserting wait-states.

GPIO interface
The ports GPIO [15:1] / GPIO_A/ GPIO_B are general purpose IO, GPIO [15:13] / GPIO_B are used as LED.
GPIO [12:1] / GPIO_A are used as Buttons which indicate volume control, music play/stop, link statues display, etc.
The special function of each port can be configured in SW.
GPIO [4:1] is shared for UART connections. GPIO [4:1] is used for UART transport by configuring related register
by SW.
The PWR is voltage value high indication port and it is used as Multi function port. High level (BAT voltage) of this
port means the button is turned on; it can be used for powering on, powering down, or paging scan mode of chip
according of its high level and Duration of High level.
There are 17 GPIO in the GPIO module. GPIO module is used to process the transmission and receiving between
GPIO pad and the core and to generate the interrupt from GPIO pad.

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In WS9625, GPIO [4:1] are shared for UART connections. When GDMUX [4:1] is configured to 4‟b1111, GPIO [4:1]
is used for UART transport.
In WS9625, GPIO [6:5] are shared for ARM debugging port. When GDMUX [6:5] is configured to 2‟b11, GPIO [6:5]
is used for ARM debugging port (SWDIOTMS and SWCLKTCK) transport, which is their default setting. They are
pulling up pins (other GPIO are pulling down pins).
In WS9625, GPIO [8:7] are shared for I2C connections. When GDMUX [8:7] is configured to 2‟b11, GPIO [8:7] is
used for I2C transport, and now GPIO [8:7] can‟t used as Buttons.
In WS9625, GPIO [12:9] are shared for SPI connections. When GDMUX [12:9] is configured to 4‟b1111, GPIO
[12:9] is used for SPI transport, and now GPIO [12:9] can‟t used as Buttons.

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ELECTRICAL CHARACTERISTICS
RF Specifications
[Table 4] Receiver RF Specifications
Parameters Mode and Conditions Min Typ Max Unit
Frequency Range – 2402 – 2480 MHz
GFSK, 1Mbps, 0.1% BER – -92.0 -90.0 dBm
DQPSK, 2Mbps, 0.01% BER – -93.0 -91.0 dBm
Rx Sensitivity
8DPSK, 3Mbps, 0.01% BER – -86.0 -84.0 dBm
Maximum Input – – – -10.0 dBm
C/I CCI (GFSK, 0.1% BER) – – 11.0 dB
C/I 1MHz ACI (GFSK, 0.1% BER) – – 0.0 dB
C/I 2MHz ACI (GFSK, 0.1% BER) – – -30.0 dB
C/I ≥3MHz ACI (GFSK, 0.1% BER) – – -40.0 dB
C/I image channel (GFSK, 0.1% BER) – – -9.0 dB
C/I CCI (DQPSK, 0.1% BER) – – 13.0 dB
C/I 1MHz ACI (DQPSK, 0.1% BER) – – 0.0 dB
C/I 2MHz ACI (DQPSK, 0.1% BER) – – -30.0 dB

Interference Performance C/I ≥3MHz ACI (DQPSK, 0.1% BER) – – -40.0 dB

C/I image channel (DQPSK, 0.1% BER) – – -7.0 dB
C/I CCI (8DPSK, 0.1% BER) – – 21.0 dB
C/I 1MHz ACI (8DPSK, 0.1% BER) – – 5.0 dB
C/I 2MHz ACI (8DPSK, 0.1% BER) – – -25.0 dB
C/I ≥3MHz ACI (8DPSK, 0.1% BER) – – -33.0 dB
C/I image channel (8DPSK, 0.1% BER) – – 0.0 dB
30 MHz to 2000 MHz (GFSK, 0.1% BER) – -10.0 – dBm

Out-of-Band Blocking 2000 MHz to 2399 MHz (GFSK, 0.1% BER) – -27.0 – dBm
Performance (CW) 2498 MHz to 3000 MHz (GFSK, 0.1% BER) – -27.0 – dBm
3000 MHz to 12.75 GHz (GFSK, 0.1% BER) – -10.0 – dBm
Intermodulation Performance BT, Delta f = 5MHz -39.0 – – dBm

[Table 5] Transmitter RF Specifications

Parameters Mode and Conditions Min Typ Max Unit
Frequency Range – 2402 – 2480 MHz
Channel Spacing – – 1 – MHz
Maximum Output Power Class 2 +2 +4 +9 dBm
Output Power Range – -30 – >+4 dBm
±500 kHz – – -20.0 dBc
1.0MHz<|M – N|<1.5 MHz (EDR only) – – -26.0 dBc
In-Band Spurious Emission 1.5MHz<|M – N|<2.5 MHz (EDR only) – – -20.0 dBm
|M – N|>2.5 MHz (EDR only) – – -40.0 dBm
Lock time – 100 150 us
LO Performance Initial carrier frequency tolerance – ±25 ±75 kHz

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WS9625ABSCF
Parameters Mode and Conditions Min Typ Max Unit
DH1 packet – ±20 ±25 kHz
DH3 packet – ±20 ±40 kHz
Frequency Drift
DH5 packet – ±20 ±40 kHz
kHz/50
Drift rate – 10 20
us
00001111 sequence in payload 140 160 175 kHz
Frequency Deviation 01010101 sequence in payload 115 150 165 kHz

Power Consumption
[Table 6] Power Supply Current (With a normal 3.7V battery voltage)
Operating Mode Typical Unit
HV3 15.0 mA
EV3 15.0 mA
2EV3 14.3 mA
A2DP Active Mode: 2DH5, 350 kbps SBC 14.5 mA
Single HFP Sniff (500ms Interval) 350 µA
Deep Sleep (off) Mode 5.0 µA

Note :
The currents are measured without an audio signal present.
The currents are measured with LEDs off.
The sniff mode current is measured with the device operating in Slave mode.
The A2DP Active mode current is with the device operating in Slave mode.

Power Meter
Power meter measures power consumption of the battery and sends the current battery level to phones. Power
meter has 10 report levels. The following devices support power meter currently.
- iPhone 3/4/4S/5
- iPad 1/2/mini
- iTouch 3/4/5
- MiPhone 2/2S

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WS9625ABSCF

Figure 9 Power Meter Curve

PACKAGE INFORMATION

Figure 10 48-leads 7 x7 mm QFN Package

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WS9625ABSCF
[Table 7] Physical Dimensions in figure 9 (Unit:mm)
SYMBOL MIN NOM MAX
A 0.80 0.85 0.90
A1 0 0.035 0.05
A2 --- 0.65 0.67
A3 0.203 (REF)
b 0.20 0.25 0.30
D 7 (BSC)
E 7 (BSC)
e 0.5 (BSC)
J 5.55 5.65 5.75
K 5.55 5.65 5.75
L 0.35 0.40 0.45
aaa 0.1
bbb 0.1
ccc 0.08
ddd 0.1
eee 0.1

CONTACT INFORMATION
Vimicro WuXi Headquarter
10/F 530 Tower, QingYuan Road, TaiHu International Technology Park,
WuXi New District, 214135, China
Tel: 86-510-81816000 Fax: 86- 510-81816935
Web: www.vimicro.com

Vimicro Beijing
16/F Shining Tower, No.35 Xueyuan Road, Haidian District, Beijing 100191, China
Tel: 86-10-68948888 Fax: 86-10-68944075

Vimicro Shanghai
2-101, Zhangjiang Micro-electronics Port, 690 Bibo Road, Zhangjiang High-tech Park,
Pudong New District, Shanghai 201203, China
Tel: 86-21-50807000 Fax: 86-21-50807611

Vimicro Shenzhen
4/F T2-B Building, South District, High-Tech Industrial Park Shenzhen 518057, Guangdong
Prov, China
Tel: 86-755-26719818 Fax: 86-755-26719539

Vimicro USA Viewtel Corporation

19447 Pauma Valley Drive, Porter Ranch, CA, 91326 USA
Tel: 1-650-966-1882 Fax: 1-650-966-1885

Datasheet (V1.1) Copyright © Vimicro_wx, Inc. 1999-2014

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