Digital Chip Design and Verification

Archana Thomas

June 19, 2024

1 3 layer CNN
1.1 Design
module m n i s t c l a s s i f i e r (
input l o g i c [ 2 7 : 0 ] i m a g e i n ,
output l o g i c [ 9 : 0 ] c l a s s o u t
);

parameter IMG SIZE = 2 8 ;

parameter NUM CLASSES = 1 0 ;
parameter KERNEL SIZE = 3 ;
parameter NUM FILTERS LAYER1 = 1 6 ;
parameter NUM FILTERS LAYER2 = 3 2 ;

always comb begin

case ( i m a g e i n )
0 : c l a s s o u t = 1 0 ’ b0000000001 ; // Example
c l a s s i f i c a t i o n f o r image 0
1 : c l a s s o u t = 1 0 ’ b0000000010 ; // Example
c l a s s i f i c a t i o n f o r image 1
// Add more c a s e s f o r o t h e r images
// . . .
default : c l a s s o u t = 1 0 ’ b0000000000 ; //
Default to c l a s s 0
endcase
end

endmodule
Listing 1: 3 layer CNN

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1.2 Test bench

‘timescale 1 ns / 1 ps

module m n i s t c l a s s i f i e r t b ;

m n i s t c l a s s i f i e r dut (
. image in ( image in ) ,
. class out ( class out )
);

l o g i c [ 2 7 : 0 ] image in ;
logic [9:0] class out ;

i n i t i a l begin
$ d u m p f i l e ( ”dump . vcd ” ) ;
$dumpvars ( 0 , m n i s t c l a s s i f i e r t b ) ;
end

i n i t i a l begin

#100;

// P r i n t t h e o u t p u t c l a s s
$display ( ” Output c l a s s : %d” , c l a s s o u t ) ;

$finish ;
end

endmodule
Listing 2: cnn test bench

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1.3 EDA Playground

Figure 1: 3 layer CNN

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1.4 Output

Figure 2: Output of 3 layer CNN

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2 32 bit multiplier
2.1 Design

module m u l t i p l i e r (
input l o g i c [ 3 1 : 0 ] a ,
input l o g i c [ 3 1 : 0 ] b ,
output l o g i c [ 6 3 : 0 ] r e s u l t
);

logic [ 3 1 : 0 ] temp result [ 3 1 : 0 ] ;

generate
genvar i , j ;
f o r ( i = 0 ; i < 3 2 ; i = i + 1 ) begin : o u t e r l o o p
f o r ( j = 0 ; j < 3 2 ; j = j + 1 ) begin : i n n e r l o o p
always comb begin
temp result [ i ] [ j ] = a [ i ] & b [ j ] ;
end
end
end
endgenerate

always comb begin

result = 0;
f o r ( i n t i = 0 ; i < 3 2 ; i = i + 1 ) begin
r e s u l t = r e s u l t + ( t e m p r e s u l t [ i ] << i ) ;
end
end

endmodule
Listing 3: 32 bit multiplier

5
2.2 Test bench

module m u l t i p l i e r t b ;

parameter CLOCK PERIOD = 1 0 ;

logic [31:0] a;
logic [31:0] b;
logic [63:0] result ;

m u l t i p l i e r dut (
. a(a) ,
. b(b) ,
. result ( result )
);

logic clock = 0;
always #(CLOCK PERIOD / 2 ) c l o c k = ! c l o c k ;

i n i t i a l begin

a = 51;
b = 73;
#10;
$display ( ” Test c a s e 1 : a = %d , b = %d , r e s u l t = %d” ,
a , b, result ) ;

a = 13;
b = 20;
#10;
$display ( ” Test c a s e 2 : a = %d , b = %d , r e s u l t = %d” ,
a , b, result ) ;

a = 0;
b = 11;
#10;
$display ( ” Test c a s e 3 : a = %d , b = %d , r e s u l t = %d” ,
a , b, result ) ;

$stop ;
end
endmodule

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 Listing 4: multiplier test bench

2.3 EDA Playground

Figure 3: 32 bit multiplier

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2.4 Output

Figure 4: Output of 32 bit multiplier

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3 Ring Counter
3.1 Design

module c o u n t e r (
input l o g i c c l k ,
input l o g i c r e s e t ,
output l o g i c [ 3 1 : 0 ] count
);

l o g i c [ 3 1 : 0 ] next count ;

a l w a y s f f @( posedge c l k or posedge r e s e t )
begin
if ( reset )
count <= 3 2 ’ h00000001 ;
else
count <= n e x t c o u n t ;
end

always comb
begin
i f ( c o u n t e r == 3 2 ’ h80000000 )
n e x t c o u n t = 3 2 ’ h00000001 ;
else
n e x t c o u n t = count << 1 ;
end

endmodule
Listing 5: Ring counter

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3.2 Test bench

module c o u n t e r t b ;
localparam CLK PERIOD = 1 0 ;
logic clk ;
logic reset ;
l o g i c [ 3 1 : 0 ] count ;
RingCounter dut (
. clk ( clk ) ,
. reset ( reset ) ,
. count ( count )
);
always #CLK PERIOD c l k = ˜ c l k ;
initial
begin
clk = 0;
reset = 1;
# (CLK PERIOD ∗ 2 ) r e s e t = 0 ;
end

endmodule
module tb ;
logic clk ;
logic reset ;

RingCounter dut (
. clk ( clk ) ,
. reset ( reset ) ,
. count ( count )
);
l o g i c [ 3 1 : 0 ] count ;
always #5 c l k = ˜ c l k ;
i n i t i a l begin
clk = 0;
reset = 1;
#10 r e s e t = 0 ;
end
always @( posedge c l k ) $display ( ” Counter : %h” , count ) ;
endmodule
Listing 6: Ring counter test bench

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3.3 EDA Playground

Figure 5: ring counter

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3.4 Output

Figure 6: Output of ring counter

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4 Arithmetic Logic Unit
4.1 Design

module ALU(
input l o g i c [ 3 1 : 0 ] A,
input l o g i c [ 3 1 : 0 ] B,
input l o g i c [ 2 : 0 ] opcode ,
output l o g i c [31:0] result ,
output l o g i c zero
);

logic [ 3 1 : 0 ] temp result ;

l o g i c temp zero ;

always comb begin

case ( opcode )
3 ’ b000 : t e m p r e s u l t = A + B ; // A d d i t i o n
3 ’ b001 : t e m p r e s u l t = A − B ; // S u b t r a c t i o n
3 ’ b010 : t e m p r e s u l t = A & B ; // B i t w i s e AND
3 ’ b011 : t e m p r e s u l t = A | B ; // B i t w i s e OR
3 ’ b100 : t e m p r e s u l t = A ˆ B ; // B i t w i s e XOR
3 ’ b101 : t e m p r e s u l t = A << B [ 4 : 0 ] ; // L e f t s h i f t
3 ’ b110 : t e m p r e s u l t = A >> B [ 4 : 0 ] ; // R i g h t s h i f t
default : t e m p r e s u l t = 3 2 ’ b0 ; // D e f a u l t t o 0
endcase

t e m p z e r o = ( t e m p r e s u l t == 3 2 ’ b0 ) ;
end

assign r e s u l t = t e m p r e s u l t ;
assign z e r o = t e m p z e r o ;

endmodule
Listing 7: 32-bit ALU module

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4.2 Test bench
module ALU Testbench ;
parameter CLOCK PERIOD = 5 ;

logic [ 3 1 : 0 ] A, B ;
logic [ 2 : 0 ] opcode ;
logic [31:0] result ;
logic zero ;
logic clk = 0;

ALU uut (
.A(A) ,
. B(B) ,
. opcode ( opcode ) ,
. result ( result ) ,
. zero ( zero )
);

always #CLOCK PERIOD c l k = ˜ c l k ;

s t r i n g opnames [ 7 ] = {”ADD” , ”SUB” , ”AND” , ”OR” , ”XOR” ,

”LSHIFT” , ”RSHIFT” } ;

always @( posedge c l k ) begin

$display ( ”Time = %0t , A = %h , B = %h , Opcode = %b
(%s ) , R e s u l t = %h” , $time , A, B, opcode ,
opnames [ opcode ] , r e s u l t ) ;
end

i n i t i a l begin

A <= 3 2 ’ h10 ;
B <= 3 2 ’ h20 ;
opcode <= 3 ’ b000 ;
#10;

A <= 3 2 ’ h40 ;
B <= 3 2 ’ h20 ;
opcode <= 3 ’ b001 ;
#10;

A <= 3 2 ’hFF ;
B <= 3 2 ’ h0F0F ;
opcode <= 3 ’ b010 ;
#10;

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 A <= 3 2 ’ hF0F0 ;
B <= 3 2 ’ h0F0F ;
opcode <= 3 ’ b011 ;
#10;

A <= 3 2 ’hAAAA;
B <= 3 2 ’ h5555 ;
opcode <= 3 ’ b100 ;
#10;

A <= 3 2 ’hAAAA;
B <= 5 ;
opcode <= 3 ’ b101 ;
#10;

A <= 3 2 ’hAAAA;
B <= 5 ;
opcode <= 3 ’ b110 ;
#10;

$finish ;
end

endmodule
Listing 8: 32-bit ALU testbench

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4.3 EDA Playground

Figure 7: ALU

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4.4 Output

Figure 8: Output of ALU

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5 GPU
5.1 Design

module GPU (
input l o g i c c l k ,
input l o g i c r s t n ,
input l o g i c [ 3 1 : 0 ] operand1 ,
input l o g i c [ 3 1 : 0 ] operand2 ,
input l o g i c [ 1 : 0 ] opcode ,
output l o g i c [ 3 1 : 0 ] r e s u l t ,
output l o g i c z e r o f l a g ,
output l o g i c o v e r f l o w f l a g
);

l o g i c [ 3 1 : 0 ] accumulator ;

localparam OP ADD = 2 ’ b00 ;

localparam OP SUB = 2 ’ b01 ;

a l w a y s f f @( posedge c l k or negedge r s t n )
begin
i f ( ! r s t n ) begin
a c c u m u l a t o r <= 3 2 ’ h0 ;
end
e l s e begin
case ( opcode )
OP ADD: a c c u m u l a t o r <= operand1 + operand2 ;
OP SUB : a c c u m u l a t o r <= operand1 − operand2 ;
default : a c c u m u l a t o r <= 3 2 ’ h0 ;
endcase
end
end

assign r e s u l t = a c c u m u l a t o r ;
assign z e r o f l a g = ( a c c u m u l a t o r == 3 2 ’ h0 ) ;
assign o v e r f l o w f l a g = ( a c c u m u l a t o r > 3 2 ’h7FFFFFFF) ;

endmodule
Listing 9: GPU design

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5.2 Test bench
module tb ;

localparam CLK PERIOD = 1 0 ;

logic clk = 0;
logic rst n = 0;
l o g i c [ 3 1 : 0 ] operand1 = 3 2 ’ d20 ;
l o g i c [ 3 1 : 0 ] operand2 = 3 2 ’ d3 ;
l o g i c [ 1 : 0 ] opcode = 2 ’ b00 ;
GPU dut (
. clk ( clk ) ,
. rst n ( rst n ) ,
. operand1 ( operand1 ) ,
. operand2 ( operand2 ) ,
. opcode ( opcode ) ,
. result () ,
. zero flag () ,
. overflow flag ()
);

always #((CLK PERIOD) / 2 ) c l k = ˜ c l k ;

i n i t i a l begin
rst n = 0;
#100;
rst n = 1;
end

i n i t i a l begin

#200;

$display ( ” I n i t i a l Values : ” ) ;
$display ( ” Operand1 : %d” , operand1 ) ;
$display ( ” Operand2 : %d” , operand2 ) ;

#100;
opcode = 2 ’ b00 ;
#100;

$display ( ” A d d i t i o n R e s u l t : %d” , dut . r e s u l t ) ;

$display ( ” Zero Flag : %b” , dut . z e r o f l a g ) ;
$display ( ” Overflow Flag : %b” , dut . o v e r f l o w f l a g ) ;

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 #100;
opcode = 2 ’ b01 ;
#100;

$display ( ” S u b t r a c t i o n R e s u l t : %d” , dut . r e s u l t ) ;

$display ( ” Zero Flag : %b” , dut . z e r o f l a g ) ;
$display ( ” Overflow Flag : %b” , dut . o v e r f l o w f l a g ) ;

#100;
$finish ;
end

endmodule
Listing 10: GPU

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5.3 EDA Playground

Figure 9: GPU Code

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5.4 Output

Figure 10: Output of GPU

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6 32-bit SRAM memory
6.1 Design

module memory32 (
input c l k , w r i t e ,
input [ 3 1 : 0 ] d a t a i n ,
input [ 4 : 0 ] a d d r e s s , // 5− b i t a d d r e s s f o r 32
locations
output [ 3 1 : 0 ] d a t a o u t
);
reg [ 3 1 : 0 ] memory [ 3 1 : 0 ] ; // 32 x32−b i t memory

always @( posedge c l k ) begin

i f ( w r i t e e n ) begin
memory [ a d d r e s s ] <= d a t a i n ;
end
end

assign d a t a o u t = memory [ a d d r e s s ] ;
endmodule
Listing 11: 32-bit SRAM memory

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6.2 Test bench
‘timescale 1 ns / 1 ps

module memory tb ;

reg clk ;
reg write ;
reg [ 3 1 : 0 ] data in ;
reg [ 4 : 0 ] address ;

wire [ 3 1 : 0 ] d a t a o u t ;

t h i r t y t w o b i t m e m o r y uut (
. clk ( clk ) ,
. write en ( write ) ,
. data in ( datain ) ,
. address ( address ) ,
. data out ( data out )
);

i n i t i a l begin
clk = 0;
write = 0;
datain = 0;
address = 0;
#100;

write = 1;
d a t a i n = 3 2 ’hA5A5A5A5 ;
a d d r e s s = 5 ’ b00010 ;

#10;
write = 0;
a d d r e s s = 5 ’ b00011 ;
#10;
a d d r e s s = 5 ’ b00010 ;

#10;
i f ( d a t a o u t == d a t a i n ) begin
$display ( ” Test Passed . Data out i s %h” ,
data out ) ;
end e l s e begin
$display ( ” Test F a i l e d . Data out i s %h” ,
data out ) ;
end

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 #10;
$finish ;
end

always #5 c l k = ˜ c l k ;

endmodule
Listing 12: 32-bit SRAM memory

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6.3 EDA Playground

Figure 11: 32 bit memory

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6.4 Output

Figure 12: Output of 32 bit SRAM memory

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