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11_Simulate_Verilog_code_Fall24v1

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10 views5 pages

11_Simulate_Verilog_code_Fall24v1

Uploaded by

Nur Hasin Ahammad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

Enter the following URL for EDA Playground.

EDA Playground is an online interface that provides a


few of the industry-standard HDL simulators. It also provides open-source tool for Logic Synthesis and
Place and Route (PnR).
https://edaplayground.com

Click on Login

Page 1 of 5
You can log in with your Google account.
You will see the following web interface.

You need to insert your Verilog code for your design in design.sv tab. You can try the following code
for the 2-input XOR gate. Note that a statement starting with // indicates a comment.
module xor_2_to_1 (input wire A, B,
output wire Y);

//instantiate built-in gate primitive xor


//syntax is component_name instance_name (output1, output2,….,input1,input2,input3…);
xor X1 (Y, A, B);

endmodule

To verify the functionality of your design you need to apply a stimulus to the inputs. To do that you
need to insert your testbench code in testbench.sv tab.

`timescale 1ns / 1ps


//1ns is stimulus delay unit, 1ps is simulation precision
module xor_2_to_1_tb;

//Internal signals declarations:


reg A, B;
wire Y;

//Design (Unit Under Test (UUT)) is instantiated as component (sub-system) of the testbench
// UUT port map
//Syntax is UUT_name instance_name (.port1_name(signal1_name, .port1_name(signal1_name)…);
xor_2_to_1 U1 (.A(A), .B(B), .Y(Y));

//This block is needed for EDA playground


initial
begin
$dumpvars (1, xor_2_to_1_tb);
end

Page 2 of 5
//Stimulus

//This initial block generates A


//Every 50ns, value of A is toggled.
//Note that repeating (loop) behavior is provided by the forever loop.
//Technically initial block executes only once, but code inside them can be repeatedly executed if they
are inside a forever loop.
initial
begin
A = 0;
forever
begin
#50; //wait for 50 ns
A = ~A; //Toggle A (using not operation)
end
end

//This initial block generates B


//Every 100ns, value of B is toggled.
//Note that repeating (loop) behavior is provided by the forever loop.
//Technically initial block executes only once, but code inside them can be repeatedly executed if they
are inside a forever loop.
initial
begin
B = 0;
forever
begin
#100; //wait for 100 ns
B = ~B; //Toggle B (using not operation)
end
end

//This initial block is for simulation control


//It stops simulation at 200 ns
//200ns is chosen as the total simulation time
//as within this time all input values will be generated (00, 01, 10, 11)

initial
begin
#200; //wait for 200ns
$dumpfile("dump.vcd"); //needed for EDA Playground
$finish; //Stop the simulation
end

endmodule

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Select the SystemVerilog/Verilog as the chosen language from Languages & Libraries. Select the
simulator Aldec Riviera Pro 2022.04 from the Tools & Simulators option. Select Open EPWave after
run so that functional simulation (timing diagram) can be opened within the web browser. Make sure
the pop-up blocker in your browser is disabled.

Click Save. Then click Run.

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The functional simulation should be opened as shown below.

Project Link
https://edaplayground.com/x/8Z2f

Page 5 of 5

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