Digital Circuits

Final Solutions

1. Mix of Questions (30 points)

Answer the following 6 questions. Drawing waveform is enough for problem (a) to (e)
(reasoning is not required). Each of them worth 5 points.

(a) Draw the output of a gated D latch for the inputs in Figure 1. Assume Q is initially
HIGH
Solution:

Figure 1: Problem 1(a) Solution.

(b) Draw the Q output relative to the clock for a positive edge-triggering D flip-flop
with the inputs in Figure 2. Assume Q is initially LOW.
Solution:

Figure 2: Problem 1(b) Solution.

(c) Draw the Q output relative to the clock for a positive edge-triggering J-K flip-flop
with the inputs in Figure 3. Assume Q is initially LOW.
Solution:

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 Figure 3: Problem 1(c) Solution.

(d) The shift register in Figure 4 has SHIF T /LOAD and CLK inputs. The parallel
data inputs are D0 = 1, D1 = 0, D2 = 1, and D3 = 0 as shown. Assume the register
is cleared intially, and the serial data input (SER) is a 0. Draw the data-output
waveform in relation to the inputs.
Solution: Draw Q3 is enough!

Figure 4: Problem 1(d) Solution.

(e) A BCD decade counter is shown in Figure 5. The waveforms are applied to the
clock and clear inputs as indicated. Draw the counter output waveforms (Q0 , Q1 ,
Q2 , and Q3 ) in proper relation to these inputs. The clear input is asynchronous and
the counter is initially in the binary 0111 state (Q3 = 0, Q2 = Q1 = Q0 = 1).
Solution:

Figure 5: Problem 1(e) Solution.

(f) For the cascaded counter in Figure 6, determine the frequency of the waveform at
each point inticated by circled number.

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 Figure 6: Problem 1(f).

Solution:

• 1 : 100kHz/10 = 10kHz
• 2 : 10kHz/10 = 1kHz
• 3 : 1kHz/10 = 100Hz
• 4 : 100Hz/2 = 50Hz

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2. Design Problems (30 points)

(a) Design an asynchronous counter using four D flip-flops that counts from 0000 to
1110 (that has 15 states). (10 points)
(b) Design 4-bit serial in/serial out shift register with four J-K flip-flops. Specify how
your shift register takes data input and CLK. Also specify how your shift register
outputs the data. You are NOT allowed to use D flip-flops. (10 points)

Figure 7: J-K flip-flop.

(c) Design 4-bit Johnson counter with four J-K flip-flops. You are NOT allowed to use
D flip-flops. (10 points)

Solution: Shift Register.

(a) Asynchronous counter is given in Figure 8

Figure 8: Asynchronous Counter.

(b) Serial in/serial out shift register using four J-K flip-flops is given in Figure 9

Figure 9: 4-bit Shift Register.

(c) 4-bit Johnson counter using four J-K flip-flops is given in Figure 10

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 Figure 10: 4-bit Johnson Counter.

3. Design of Synchronous Counters. (40 points)

Design a counter to produce the following binary sequence using J-K flip-flops.
0, 2, 4, 6, 1, 3, 5, 0, 2, 4, 6, 1, 3, 5, . . . .
Please follow 6 steps to design the counter.
(a) Draw a state diagram. (5 points)
(Hint: We have 7 states from 000 to 110)
(b) Fill the next-state table. (10 points)
(Hint: Use don’t care when the present state is 111)
(c) Draw the flip-flop transition table. (5 points)
(d) Draw the Karnaugh maps. (10 points)
(e) Show the logic expressions. (5 points)
(f) Implement the counter (draw the circuit with flip-flops). (5 points)

Solution: Design of Synchronous Counters.

(a) The first step is drawing the state diagram. Note that we are using binary numbers
(for example, 001 for 1, 010 for 2, etc). The state diagram is given in Figure 11a.
(b) Then, the step 2 is filling the next-state table. This is given in Table 1.
(c) The step 3 is flip-flop transition table. Transition table of J-K flip-flop is given in
Figure 11b.
(d) The step 4 is Karnaugh maps. These are given in Figure 11c.
(e) The step 5 is Logic expressions. According to Karnaugh maps, we have
J0 =Q2 Q1 (1)
K0 =Q2 (2)
J1 =Q̄0 + Q̄2 (3)
K1 =1 (4)
J2 =Q1 (5)
K2 =Q0 + Q1 . (6)

(f) The final step (step 6) is counter implementation which is given in Figure 11d.

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 Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 1 0
0 0 1 0 1 1
0 1 0 1 0 0
0 1 1 1 0 1
1 0 0 1 1 0
1 0 1 0 0 0
1 1 0 0 0 1
1 1 1 x x x

Table 1: Step 2.

(b) Step 3.
(a) Step 1.

(d) Step 6.
(c) Step 4.

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