Design and Simulation of 2x1 NAND and NOR

Gates Using Cadence Virtuoso

Aman kumar
Department of Electronics and Communication Engineering
Indian Institute of Technology Roorkee
Enrollment Number: 22116012
Email: aman k@ece.iitr.ac.in
Team Members : 22116012, 22116010, 22116014

Abstract—This report describes the design and simulation of

2x1 NAND and NOR gates using Cadence Virtuoso. The report
covers the schematic creation, layout design, and the simulation
of both gates to verify their functionality. Essential checks such
as Design Rule Check (DRC), Layout vs Schematic (LVS), and
Parasitic Extraction (PEX) were performed to ensure design
accuracy.

I. I NTRODUCTION
NAND and NOR gates are fundamental building blocks
in digital logic design. These gates are often used due to
their ability to implement any logic function. The goal of this
project is to design 2x1 NAND and NOR gates using 180nm
CMOS technology, ensuring the design is optimized for rise Fig. 2. NOR Gate Schematic.
and fall time balance and overall performance. The design and
simulation were performed using Cadence Virtuoso.
• Layout: The layout was created based on the schematic
II. D ESIGN design, adhering to the DRC and LVS constraints. The
• Schematic Design: The NAND and NOR gates were layouts for the NAND and NOR gates are depicted below.
designed using Cadence Virtuoso. Each gate consists of
PMOS and NMOS transistors sized to ensure equivalent
rise and fall times. For the NAND gate, two NMOS
transistors are placed in series, and two PMOS transistors
are placed in parallel. For the NOR gate, two PMOS tran-
sistors are connected in series, and two NMOS transistors
are in parallel. The schematics for both gates are shown
below.

Fig. 3. NAND Gate Layout.

III. T OOLS
Cadence Virtuoso was utilized for schematic design, sim-
ulation, and layout creation. This tool enabled the transition
from schematic to layout and provided essential checks like
Design Rule Check (DRC), Layout vs Schematic (LVS), and
Parasitic Extraction (PEX).
IV. A NALYSIS
Fig. 1. NAND Gate Schematic. • Transient Response: Time-domain analysis was con-
ducted to examine the behavior of the gates. Both the
 Fig. 4. NOR Gate Layout.

NAND and NOR gates demonstrated correct functionality Fig. 6. DRC Check for NAND Gate.
by switching output values during transitions in the input
signals. The transient response for both gates is shown in
the figures below.
• Rise and Fall delay:-
The delay of a gate is defined as the time taken for the
output to reach 50% of its final value after the input
transition crosses 50% of its final value. The rise-delay
is the time between the 50% point of the input transition
(low to high) and the 50% point of the output transition
(low to high). The fall-delay is similarly defined for the
high-to-low transition.
• Rise and Fall time: The rise time of Nand gate is : 30.25
ps. The fall time of Nand gate is : 30.43 ps. The Rise
time of NOR Gate = 25.28 ns The Fall time of NOR Gate
= 31.49 ns Fig. 7. DRC Check for NOR Gate.

VII. R ESULTS
Both the NAND and NOR gates were successfully
designed and simulated using Cadence Virtuoso. The
schematic verified their proper functionality, and the
layouts were created following design rule guidelines.
DRC, LVS, and PEX checks were successfully passed.
The transient response confirmed the correct switching
behavior of both gates, validating their implementation
in digital circuits.
VIII. C ONCLUSION
This report outlines the design, implementation, and
Fig. 5. NAND Gate Transient Response. verification of 2x1 NAND and NOR gates using Cadence
Virtuoso. The process involved designing schematics,
V. V ERIFICATION generating layouts, and verifying functionality through
– DRC and LVS Checks: The layout design was extensive simulations. Key checks such as DRC, LVS,
verified using DRC and LVS to ensure that the layout and PEX were completed without issues, ensuring design
precisely matches the schematic design. Both checks accuracy. Future work could focus on optimizing the
confirmed no violations or discrepancies, ensuring gates for power efficiency and faster switching speed,
design integrity. improving their performance in real-world applications.

VI. PARASITIC E XTRACTION (PEX)

Parasitic Extraction was performed to account for par-
asitic resistances and capacitances in the layout. The
PEX results provided acceptable values for both gates,
confirming accurate modeling of parasitic components.
 Fig. 8. LVS Check for NAND Gate.

Fig. 9. LVS Check for NOR Gate.

Fig. 10. PEX Results for NAND Gate.

Fig. 11. PEX Results for NOR Gate.