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Analog Assignment 5

The document discusses the 555 timer IC, detailing its three modes: monostable, astable, and bistable, along with their respective circuit designs and simulations. It also covers the design of LDO voltage regulators, including both pMOS and nMOS configurations, with equations for output voltage and component selection. Each section includes circuit diagrams and simulation waveforms to illustrate functionality.

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ee23btech11029
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18 views9 pages

Analog Assignment 5

The document discusses the 555 timer IC, detailing its three modes: monostable, astable, and bistable, along with their respective circuit designs and simulations. It also covers the design of LDO voltage regulators, including both pMOS and nMOS configurations, with equations for output voltage and component selection. Each section includes circuit diagrams and simulation waveforms to illustrate functionality.

Uploaded by

ee23btech11029
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Assignment 5

Kanishk Devatwal - ee23btech11029


March 31, 2025

1 Introduction
The 555 timer IC is widely used in electronic applications for generating timing pulses
and oscillations. It functions in three primary configurations: monostable, astable, and
bistable. Each mode offers unique characteristics, making the 555 timer a versatile com-
ponent in circuit design.

2 Monostable Mode
In monostable mode, the 555 timer acts as a one-shot pulse generator, producing a single
output pulse in response to an external trigger. The duration of the pulse is determined
by a resistor-capacitor (RC) network.

2.1 Time Period Computation


The time period for the monostable mode is determined using the equation:

T = 1.1RC (1)

To set T = 5 ms, we select C = 1µF and calculate R as:

T 5 × 10−3
R= = = 4.5452kΩ (2)
1.1C 1.1 × 1 × 10−6

1
2.2 Circuit and Simulation

Figure 1: Monostable 555 Timer Circuit

The circuit consists of a trigger input, a timing capacitor, and a resistor determining the
pulse width. The output remains high for the duration determined by the RC network.

Figure 2: Simulation waveform

Using cursors, we can measure the time period, which is around 5ms.

2
Figure 3: Time period using cursors

Similarly, to achieve a time period of 200µs, the trigger pulse width would need to be
kept below 200µs.

3 Astable Mode
Astable mode enables the 555 timer to function as a free-running oscillator, generating a
continuous square wave output. The frequency and duty cycle are determined by external
resistor and capacitor values.

3.1 Frequency and Duty Cycle Computation


The oscillation frequency is given by:
1.44
f= (3)
(RA + 2RB )C

The duty cycle is:


RA + RB
D= × 100% (4)
RA + 2RB
For a 75% duty cycle, we derive:
RA = 2RB (5)
Choosing C = 0.03µF and solving for RA and RB at f = 2 kHz:

RB = 6kΩ, RA = 12kΩ (6)

3
3.2 Circuit and Simulation

Figure 4: Astable 555 Timer Circuit

The circuit operates continuously, generating a square wave at a fixed frequency and duty
cycle.

Figure 5: Output waveform

4
Figure 6: On time calculation

Figure 7: Off time calculation

Figure 8: Time period calculation

5
4 Bistable Mode
Bistable mode allows the 555 timer to function as a flip-flop, toggling between two stable
states upon receiving external triggers.

4.1 Circuit and Simulation

Figure 9: Bistable 555 Timer Circuit

The circuit maintains its output state until an external trigger is applied to toggle the
output.

Figure 10: Simulation waveform

6
5 Design of LDO Voltage Regulators
LDO regulators provide a stable output voltage with minimal dropout voltage. This
section covers both pMOS and nMOS-based designs.

5.1 pMOS-Based LDO


A pMOS transistor serves as the pass element, with a feedback mechanism ensuring the
output voltage follows the reference voltage (Vref ).
 
R2
Vout = Vref 1 + (7)
R1

For Vout = 6V with Vref = 3V :


R1 = R2 = 100kΩ (8)

Figure 11: Circuit Diagram

The circuit regulates the output voltage by controlling the pMOS transistor based on the
feedback network.

7
Figure 12: Simulation waveform

5.2 nMOS-Based LDO


In an nMOS-based LDO, the transistor operates in a common-source configuration, reg-
ulating Vout via gate control.

Figure 13: Circuit Diagram

8
Figure 14: Simulation result

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