DSP_lab_Experiment_4
DSP_lab_Experiment_4
1 Objective
The objective of this experiment is to design a bandpass FIR filter using MAT-
LAB, convert filter coefficients and input signals into Q(2,14) fixed-point format,
and implement the filtering process in Verilog. The output is then validated by
comparing MATLAB and Verilog results.
2 MATLAB Implementation
2.1 Filter Design
1. Open MATLAB and enter filterDesigner in the command window.
2. In the filter designer window, set the following parameters:
• Filter Type: Bandpass
• Filter Order: Minimum
• Density Factor: 20
• Frequency Specifications:
– Sampling Frequency: 48000 Hz
– Stopband Frequency 1: 500 Hz
– Passband Frequency 1: 1500 Hz
– Passband Frequency 2: 8000 Hz
– Stopband Frequency 2: 9000 Hz
3. Click on “Design Filter” to generate the filter response.
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2. Convert the coefficients into Q(2,14) fixed-point format and store them in
a file.
3. Generate four sine waves with frequencies 100 Hz, 2000 Hz, 6000 Hz, and
11000 Hz, each sampled at 48000 Hz for 5 cycles.
4. Convert these sine wave values into Q(2,14) fixed-point format and store
them in separate files.
5. Apply the designed FIR filter to the four signals using convolution (filter-
ing operation with the selected 20 coefficients).
6. Plot the filtered output signals for verification.
l o a d ( ’ f i l t e r c o e f f s . mat ’ ) ; % Load f i l t e r c o e f f i c i e n t s
c o e f f s = Num( 1 : 2 0 ) ; % Take f i r s t 20 c o e f f i c i e n t s
q c o e f f s = round ( c o e f f s ∗ 2 ˆ 1 4 ) ; % Convert t o Q( 2 , 1 4 )
f i l e I D = f o p e n ( ’ f i l t e r c o e f f s q 2 1 4 . txt ’ , ’w ’ ) ;
f p r i n t f ( f i l e I D , ’%d\n ’ , q c o e f f s ) ;
fclose ( fileID );
f s = 4 8 0 0 0 ; % Sampling f r e q u e n c y
c y c l e s = 5 ; % Number o f c y c l e s
f r e q s = [ 1 0 0 , 2000 , 6000 , 1 1 0 0 0 ] ; % Frequencies to generate
% Convert t o Q( 2 , 1 4 )
s i n e q = round ( s i n e w a v e ∗ 2 ˆ 1 4 ) ;
% Store into f i l e
f i l e n a m e = s p r i n t f ( ’ s i n e %dHz q2 14 . txt ’ , f ) ;
f i l e I D = f o p e n ( f i l e n a m e , ’w ’ ) ;
f p r i n t f ( f i l e I D , ’%d\n ’ , s i n e q ) ;
fclose ( fileID );
end
Matlab Code for filtered response(filtersinwave.m)
f s = 4 8 0 0 0 ; % Sampling f r e q u e n c y
f r e q s = [ 1 0 0 , 2 0 0 0 , 6 0 0 0 , 1 1 0 0 0 ] ; % F r e q u e n c i e s used
f i l e s = { ’ s i n e 1 0 0 H z q 2 1 4 . txt ’ , ’ s i n e 2 0 0 0 H z q 2 1 4 . txt ’ , ’ s i n e 6 0 0 0 H z q 2 1 4 . txt
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% Load t h e f i l t e r c o e f f i c i e n t s
q c o e f f s = l o a d ( ’ f i l t e r c o e f f s q 2 1 4 . txt ’ ) ; % Load Q( 2 , 1 4 ) f i l t e r coefficients
figure ;
% Apply t h e bandpass f i l t e r
output signal = f i l t e r ( q coeffs , 1 , sine q );
% Generate time v e c t o r
t = 0 : 1 / f s : ( l e n g t h ( s i n e q ) −1)/ f s ; % Match time v e c t o r l e n g t h
% P l o t t h e f i l t e r e d output
subplot (2 ,2 , i ) ;
plot ( t , output signal ) ;
t i t l e ( s p r i n t f ( ’ F i l t e r e d Output f o r %d Hz ’ , f r e q s ( i ) ) ) ;
x l a b e l ( ’ Time ( s ) ’ ) ;
y l a b e l ( ’ Amplitude ’ ) ;
g r i d on ;
end
d i s p ( ’ F i l t e r e d s i g n a l s saved s u c c e s s f u l l y . ’ ) ;
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Figure 1: BandPass filtered Output using Matlab
3 Verilog Implementation
Decimal to binary Conversion(dectobin.m)
First we convert the Q(2,14) int values of our 4 sine waves output and filter
coefficient values to binary values for verilog implementation.
% D e f i n e t h e i n p u t f i l e s ( i n t e g e r Q2 . 1 4 format )
i n p u t f i l e s = { ’ s i n e 1 0 0 H z q 2 1 4 . txt ’ , . . .
’ s i n e 2 0 0 0 H z q 2 1 4 . txt ’ , . . .
’ s i n e 6 0 0 0 H z q 2 1 4 . txt ’ , . . .
’ s i n e 1 1 0 0 0 H z q 2 1 4 . txt ’ , . . .
’ f i l t e r c o e f f s q 2 1 4 . txt ’ } ;
o u t p u t f i l e s = { ’ b i n s i n e 1 0 0 H z q 2 1 4 . txt ’ , ’ b i n s i n e 2 0 0 0 H z q 2 1 4 . txt ’ , ’ b i n s i n
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% Open output f i l e f o r w r i t i n g b i n a r y data
f i d = f o p e n ( o u t p u t f i l e s { f } , ’w ’ ) ;
% Convert i n t e g e r s t o b i n a r y and w r i t e t o f i l e
for i = 1: length ( x Q2 14 int )
b i n S t r = d e c 2 b i n ( x Q 2 1 4 i n t ( i ) , 1 9 ) ; % Convert t o 19− b i t b i n a r y
f p r i n t f ( f i d , ’% s \n ’ , b i n S t r ) ; % Write t o f i l e
end
% Close f i l e
fclose ( fid );
end
d i s p ( ’ C o n v e r s i o n t o b i n a r y completed s u c c e s s f u l l y . ’ ) ;
Now after converting these files in binary we will use them in our verilog
directory.
Implementation
1. Read the filter coefficient file and the four input signal files.
2. Implement a module in Verilog to apply the FIR filter on each input signal.
3. Compute the output values for each input signal and store them in sepa-
rate files.
4. Read the output files in MATLAB, plot the filtered signals, and compare
them with MATLAB’s directly computed outputs to ensure correctness.
// Load f i l t e r c o e f f i c i e n t s from f i l e
i n i t i a l begin
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$readmemb ( ” b i n f i l t e r c o e f f s q 2 1 4 . t x t ” , h ) ;
// I n i t i a l i z e d e l a y l i n e
f o r ( i = 0 ; i < NUM TAPS; i = i + 1 )
d e l a y l i n e [ i ] = 1 9 ’ b0 ;
end
always @( p o s e d g e c l k o r p o s e d g e r s t ) b e g i n
i f ( r s t ) begin
f o r ( i = 0 ; i < NUM TAPS; i = i + 1 )
d e l a y l i n e [ i ] <= 1 9 ’ b0 ;
y <= 1 9 ’ b0 ;
end e l s e b e g i n
// S h i f t d e l a y l i n e
f o r ( i = NUM TAPS−1; i > 0 ; i = i − 1 )
d e l a y l i n e [ i ] <= d e l a y l i n e [ i − 1 ] ;
d e l a y l i n e [ 0 ] <= x ;
end
end
always @( p o s e d g e c l k ) b e g i n
a c c = 3 8 ’ b0 ;
f o r ( i = 0 ; i < NUM TAPS; i = i + 1 ) b e g i n
acc = acc + ( d e l a y l i n e [ i ] ∗ h [ i ] ) ;
end
y <= a c c [ 3 3 : 1 5 ] ; // Adjust f o r Q( 2 , 1 4 ) format
end
endmodule
module Testbench ;
reg clk , r s t ;
reg signed [ 1 8 : 0 ] x ;
wire signed [ 1 8 : 0 ] y ;
i n t e g e r i n p u t f i l e , o u t p u t f i l e , scan ;
i f ( i n p u t f i l e == 0 ) b e g i n
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$ d i s p l a y ( ” E r r o r : F a i l e d t o open i n p u t f i l e : %s ” , i n p u t f i l e n a m e )
$finish ;
end
i f ( o u t p u t f i l e == 0 ) b e g i n
$ d i s p l a y ( ” E r r o r : F a i l e d t o open output f i l e : %s ” , o u t p u t f i l e n a m
$finish ;
end
s c a n = 0 ; // I n i t i a l i z e s c a n v a r i a b l e
x = 1 9 ’ b0 ; // Reset x b e f o r e r e a d i n g new f i l e
while ( ! $ f e o f ( i n p u t f i l e )) begin
s c a n = $ f s c a n f ( i n p u t f i l e , ”%b\n ” , x ) ;
#10;
$ f w r i t e ( o u t p u t f i l e , ”%b\n ” , y ) ;
end
initial begin
clk = 0;
rst = 1;
#10 rst = 0;
// Run t e s t f o r 100Hz
r u n t e s t (” bin sine 100Hz q2 14 . txt ” , ” f i l t e r e d o u t p u t 1 0 0 H z . txt ” ) ;
#10; // S h o r t d e l a y b e f o r e s w i t c h i n g f i l e s
// Run t e s t f o r 2000Hz
r u n t e s t (” bin sine 2000Hz q2 14 . txt ” , ” f i l t e r e d o u t p u t 2 0 0 0 H z . txt ” ) ;
#10;
// Run t e s t f o r 6000Hz
r u n t e s t (” bin sine 6000Hz q2 14 . txt ” , ” f i l t e r e d o u t p u t 6 0 0 0 H z . txt ” ) ;
#10;
// Run t e s t f o r 11000Hz
r u n t e s t (” bin sine 11000Hz q2 14 . txt ” , ” f i l t e r e d o u t p u t 1 1 0 0 0 H z . txt ” ) ;
$finish ;
end
always #5 c l k = ˜ c l k ;
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endmodule
To read the output files we got from verilog code we convert back the output
files from binary to decimal in Matlab using following code(bintodec.m):
% D e f i n e i n p u t ( b i n a r y ) and output ( i n t e g e r ) f i l e names
b i n f i l e s = { ’ f i l t e r e d o u t p u t 1 0 0 H z . txt ’ , . . .
’ f i l t e r e d o u t p u t 2 0 0 0 H z . txt ’ , . . .
’ f i l t e r e d o u t p u t 6 0 0 0 H z . txt ’ , . . .
’ f i l t e r e d o u t p u t 1 1 0 0 0 H z . txt ’ } ;
% Read a l l b i n a r y s t r i n g s from f i l e
binData = t e x t s c a n ( f i d , ’%s ’ ) ;
fclose ( fid );
% Convert b i n a r y s t r i n g s t o s i g n e d i n t e g e r s (Q2 . 1 4 )
b i n S t r i n g s = binData { 1 } ; % E x t r a c t c e l l a r r a y o f b i n a r y s t r i n g s
numValues = l e n g t h ( b i n S t r i n g s ) ;
i n t Q 2 1 4 = z e r o s ( numValues , 1 ) ; % P r e a l l o c a t e f o r s p e e d
f o r i = 1 : numValues
i n t Q 2 1 4 ( i ) = b i n 2 d e c ( b i n S t r i n g s { i } ) ; % Convert t o d e c i m a l
i f i n t Q 2 1 4 ( i ) >= 2ˆ18 % Check f o r n e g a t i v e v a l u e s ( s i g n b i t a t MSB)
i n t Q 2 1 4 ( i ) = i n t Q 2 1 4 ( i ) − 2 ˆ 1 9 ; % Convert t o s i g n e d i n t e g e r
end
end
% Save a s i n t e g e r v a l u e s
d l m w r i t e ( i n t f i l e s { f } , i n t Q 2 1 4 , ’ p r e c i s i o n ’ , ’%d ’ ) ;
end
d i s p ( ’ Binary t o I n t e g e r Q( 2 , 1 4 ) c o n v e r s i o n completed s u c c e s s f u l l y . ’ ) ;
Ploting Verilog results(verilogplot.m)
Now we plot the verilog output result in Matlab using following Matlab code:
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filtered 1 0 0 H z = l o a d ( ’ i n t f i l t e r e d o u t p u t 1 0 0 H z . txt ’ ) ;
filtered 2 0 0 0 H z = l o a d ( ’ i n t f i l t e r e d o u t p u t 2 0 0 0 H z . txt ’ ) ;
filtered 6 0 0 0 H z = l o a d ( ’ i n t f i l t e r e d o u t p u t 6 0 0 0 H z . txt ’ ) ;
filtered 1 1 0 0 0 H z = l o a d ( ’ i n t f i l t e r e d o u t p u t 1 1 0 0 0 H z . txt ’ ) ;
% Determine t h e l e n g t h o f each s i g n a l
len 100Hz = length ( f i l t e r e d 1 0 0 H z ) ;
len 2000Hz = length ( f i l t e r e d 2 0 0 0 H z ) ;
len 6000Hz = length ( f i l t e r e d 6 0 0 0 H z ) ;
len 11000Hz = length ( f i l t e r e d 1 1 0 0 0 H z ) ;
% Plot the f i l t e r e d s i g n a l s
figure ;
subplot (2 ,2 ,1);
p l o t ( t 100Hz , f i l t e r e d 1 0 0 H z , ’ b ’ ) ;
t i t l e ( ’ F i l t e r e d 100Hz S i n e Wave ’ ) ;
x l a b e l ( ’ Time ( s ) ’ ) ;
y l a b e l ( ’ Amplitude ’ ) ;
g r i d on ;
subplot (2 ,2 ,2);
p l o t ( t 2000Hz , f i l t e r e d 2 0 0 0 H z , ’ g ’ ) ;
t i t l e ( ’ F i l t e r e d 2000Hz S i n e Wave ’ ) ;
x l a b e l ( ’ Time ( s ) ’ ) ;
y l a b e l ( ’ Amplitude ’ ) ;
g r i d on ;
subplot (2 ,2 ,3);
p l o t ( t 6000Hz , f i l t e r e d 6 0 0 0 H z , ’ r ’ ) ;
t i t l e ( ’ F i l t e r e d 6000Hz S i n e Wave ’ ) ;
x l a b e l ( ’ Time ( s ) ’ ) ;
y l a b e l ( ’ Amplitude ’ ) ;
g r i d on ;
subplot (2 ,2 ,4);
p l o t ( t 11000Hz , f i l t e r e d 1 1 0 0 0 H z , ’m’ ) ;
t i t l e ( ’ F i l t e r e d 11000Hz S i n e Wave ’ ) ;
x l a b e l ( ’ Time ( s ) ’ ) ;
y l a b e l ( ’ Amplitude ’ ) ;
g r i d on ;
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s g t i t l e ( ’ F i l t e r e d S i n e Waves a t D i f f e r e n t F r e q u e n c i e s ’ ) ;
5 Conclusion
This experiment successfully demonstrated the design, implementation, and ver-
ification of a bandpass FIR filter. By utilizing MATLAB for filter design and
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Verilog for hardware implementation, we achieved a practical approach to digital
signal processing. The results validated the accuracy of the Verilog implemen-
tation when compared with MATLAB-generated outputs.
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