INTRODUCTION

This service manual provides a variety of service compatible computer. It can write as much as 700
information. Mbytes of digital data into CD-R/RW disc, and can
It contains the mechanical structure of the CD- read as much as 650 Mbytes of digital data stored
R/RW Drive and the electronic circuits in in a CD-ROM, CD-R and CD-RW disc.
schematic form. This CD-R/RW Drive was This CD-R/RW Drive can easily meet the
manufactured and assembled under our strict upcoming MPC level 3 specification, and its
quality control standards and meets or exceeds Enhanced Intelligent Device Electronics (E-IDE)
industry specifications and standards. and ATAPI interface allows Plug and play
This CD-R/RW drive is an internal drive unit integration in the majority of today’s PCs without
designed for use with IBM PC, HP Vectra, or the need of an additional interface card.

FEATURES
1. General
1) Enhanced IDE interface.
2) Internal 5.25 inch, halfheight CD-R/RW Drive.
3) 8 Mbytes (or 2Mbytes) buffer memory.
4) Audio CD like tray loading of a disc without using a caddy.
5) Power loading and power ejecting of a disc. The disc can also be ejected manually.
6) Supports Power saving mode and Sleep mode.
7) Vertical and Horizontal operation.
8) SuperLink Function.

2. Supported disc formats

1) Reads and writes data in each CD-ROM, CD-ROMXA, CD-I FMV, Video CD, and CD-EXTRA
2) Reads data in Photo CD (Single and Multi session).
3) Reads and writes standard CD-DA.
4) Reads and writes CD-R discs conforming to “Orange Book Part 2”.
5) Reads and writes CD-RW discs conforming to “Orange Book Parts 3”.

3. Supported write method

1) Disc at once (DAO), Session at once (SAO), Track at once (TAO), Variable packet, Fixed packet, and
Multi-session.

4. Performance
1) Random 100 ms average access time.
2) CD-R Record speed : 8X, 12X, 16X, 20X~40X (PCAV).
3) CD-RW Record speed : 4X, 10X, 12X.
4) CD-ROM : Max 6,000 KB/s(Max 40x) Sustained Transfer rate.
5) Supports real time error correction and real time layered error correction at each speed.
6) PIO Mode 4, Multi DMA Mode 2 .
7) Multimedia MPC-3 Spec compliant.
8) Support CD-TEXT read/write.

5. Audio
1) Output 16 bit digital data over ATA interface.
2) 8 Times Digital Filter for CD Audio
3) Software Volume Control
4) Equipped with audio line output and headphone jack for audio CD playback.
5) Front panel Volume Control for Headphone Output.

3
 LOCATION OF CUSTOMER CONTROLS

Front Panel

Emergency Eject Hole

WRITE
Disc Tray
READ

Stop/Eject Button

Volume
Control Drive Activity Indicators

Headphone Jack

1. Disc tray 5. Headphone jack

This is the tray for the disc. Place the disc on the This jack is for connecting headphones or mini-
ejected disc tray, then lightly push the tray (or speakers.
push the eject button) and the CD will be loaded.
6. Drive activity indicators
NOTE: Don’t pull out or push in the disc tray
Two colored LEDs are used to indicate the
forcibly. This might cause damage to the loading
operation of CD-R/RW Drive.
section of the drive.
(1) Read
2. Stop/Eject button The orange color is displayed when the spindle
This button is pressed to open the CD tray. motor begins the Spin up operation: accessing
This button works only when power is supplied to data, reading data, playing Audio, and up loading
the drive. tray.
If an Audio CD is playing, pressing this button will (2) Write
stop it, and pressing it again will open the tray. The green color is flashed during disc writing
sessions.
3. Emergency Eject Hole
Insert a paper clip here to eject the Disc tray
manually or when there is no power.
4. Volume control
This is used to adjust the output volume of the
headphone jack. It can’t be used to adjust the
output volume for the audio output connectors on
the rear panel.
NOTE : Turn the volume down before turning on
the power. Sudden loud noises can damage your
hearing.

6
 Rear Panel

Analog Audio Output Connector IDE Interface Connector

Jumper Connector
Power Connector

Digital Audio Output

Connector

1. Power Connector 3. Jumper Connector

Connects to the power supply (5-and 12-V DC) of This jumper determines whether the drive is
the host computer. configured as a master or slave. Changing the
NOTE : Be careful to connect with the proper master-slave configuration takes effect after
polarity. Connecting the wrong way may damage power-on reset.
the system (and is not guaranteed). Usually this
4. Analog Audio Output Connector
connector can only be attached one-way.
Provides output to a sound card (analog signal).
2. IDE Interface Connector Generally you need this to play a regular audio
Connect to the IDE (Integrated Device CD.
Electronics) Interface using a 40-pin flat IDE
5. Digital Audio Output Connector
cable.
Provides output to a sound card (digital signal).
NOTE : Do not connect or disconnect the cable
when the power is on, as this could cause a short
circuit and damage the system. Always turn the
power OFF when connecting or disconnecting the
cable.

7
 DISASSEMBLY
1. CABINET and CIRCUIT BOARD 1-3. Cabinet and Main Circuit Board
A. Remove the Cabinet in the direction of arrow (4).
DISASSEMBLY (See Fig. 1-3)
1-1. Bottom Chassis B. Release 2 hooks (a) and remove the CD Tray
A. Release 4 screws (A) and remove the Bottom Chassis drawing forward.
in the direction of arrow (1). (See Fig.1-1) C. Remove the Main Circuit Board in the direction of
arrow (5).
D. At this time, be careful not to damage the 4
connectors, are positioned at right side, of the Main
Circuit Board.

Cabinet

(1)
Hooks (a) (4)

(A)
Bottom Chassis (5)
(A)
(A) (A)
Fig. 1-1
Main
Circuit Board
1-2. Front Bezel Assy
A. Insert and press a rod in the Emergency Eject Fig. 1-3
Hole and then the CD Tray will open in the direction
of arrow (2).
B. Remove the Tray Door in the direction of arrow 2. MECHANISM ASSY DISASSEMBLY
(3) by pushing the stoppers forward. 2-1. Pick-up Unit
C. Release 3 stoppers and remove the Front Bezel Assy. A. Release screws (B).
B. Separate the Pick-up Unit in the direction of arrow (6).

Tray Door (B)

(B)

(3)

Stoppers Pick-up Unit

(6)

(2) CD Tray

Front Bezel Assy

Emergency Eject Hole Mechanism Assy

Fig. 1-2 Fig. 2-1

8
2-2. Pick-up
A. Release 2 screws (C) and remove the Pick-up.

Pick-up Unit

(C)
(C)

Pick-up

Fig. 2-2

9
 TROUBLESHOOTING GUIDE
1. Connect only the power cable

Power check
(Malfunction of LED and Tray)

Check the Reset (Pin 170, 122 of Check the input of oscillation (pin
Check the connection of 5V, 12V.
IC101, pin2 of IC401) 109 of IC401)

Check SCLK, SDATA, XLAT

(pin 122, 123, 124 of IC401)

IC 401
33.8688MHz

MCLK 109

MT1516 74 75
‘H ’
RF Amp /XRST 2 55
Wobble
ALPC SCLK
122 65
General port use
SDATA
EEPROM access 123 63 IC 101
XLAT
124 62
MT1508
IC 501
IC 103 DSP
Decoder
10 19 20 Encoder
AT49F002N ATIP Demodulator
54 32 512KB Write Strategy
BD7907FS Flash ROM Write S/H Signal
6Ch Servo DRIVE I/F
31
IC 202 Micro Processor
32 44 51

30 ‘L ’
3 Reset 2 170 PRST
‘H ’
/ HRST 122

1 3.3 V 3

41 44
IC 502
SDRAM
CN 100 12V 5V
IC 102

55
 Check the Reference voltage
(+/- 10%)

Check voltage of VREF(1.4V) Check VC (1.4V) of Drive IC

(pin 53 of IC101, pin 27 of IC501) (pin27 of IC501)

Check voltage of 2VREF(2.8V)

(pin 52 of IC101)

Check HAVC/PDVC(2.0V) Check FVREF/FPDVC (2.8V) Check FPDO(2.8V)

(pin 34 of IC401, pin 13 of CN201) (pin 52 of IC401, pin22 of CN201) (pin 54, 65 of IC401)

CN 201 IC 401

Optical 2.0 V
Pick-up PDVC 13 75 VHAVC IC 101
KRS-330B
34 HAVC 2.8 V
V28 76 52 2VREF
MT1516
2.8 V
FPDVC 22 74 VFVREF RF Amp 1.4 V
Wobble V14 76 53 VREF
52 FVREF
ALPC
General port use
2.8V EEPROM access MT1508
FPDO 19 54 FPDO
LD
Drive 65 FPDOLP
DSP
FPDVcc Decoder
20
Encoder
ATIP Demodulator
Write Strategy
IC 501 IC 506
Write S/H Signal
5V 1.4 V I/F
VC 27 1
NJM
3 Micro Processor
2 3414
BD7907FS
6Ch Servo DRIVE
3.3 V
2 2.5 V 3 17 28 76 134 180

IC 503

56
 Check the initial operation
(Power-on state)

• Check the operating signal of Sled

(pin 28, 29 of IC501 : SLIN1, 2)
Sled move to inside
• Check the output signal of Sled
• Check the Spindle signal
(pin 34, 35, 36, 37 of IC501)
(pin 24 of IC501 : SPIN) • Check /SLEDIN_SW.
• Check FG input
(pin 104 of IC401)
Spindle motor rotate
(pin 20 of IC101)
• Check the Hall signal
(pin 1, 2, 3, 4, 5, 6 of IC501)

Laser On Check the Laser • Check the control signal of Driver

IC(pin 22, 23 of IC501)
• Check the power of DRIVE IC
and VC
Focus up / Down Check the operation of Focus

Laser Off / Spindle Stop Check SCLK, SDATA, XLAT

(pin 122, 123, 124 of IC401)
2 times iteration

IC 401
(From pin 1 of CN402) SCLK
122 65
Optical /SL EDIN_SW MT1516
104 SDATA
Pick-up ALPC 123 63
KRS-330B General port use XLA T
124 62
Spindle
101 102
Motor
IC 101
DRV-MUTE2

DRV-MUTE1

STEP Motor
MT1508
DSP
I/F
34 35 36 37 22 23
U Micro
9 B- B+ A- A+ CTL1 CTL2
V Processor
11
SLIN1 28 26 FMO
W
18
IC 501 SLIN2 29 27 FMO2
HB
7
BD7907FS SPIN 24 25 DMO
HU+ , HU- 6Ch Servo
1 , 2
DRIVE 21 20
HV+ , HV- FG FG
3 , 4
HW+ , HW- 1.4 V
5 , 6 VC 27

57
1. Waveform when Sled moves to inside

SLIN1 When the sled moves to the inner position,

/SLEDINSW the sine wave(refer to Fig1) inputs to
A+ SLIN1/SLIN2 (the input pins of drive IC).
When Pick-Up unit approached to innermost
position, the /SLEDINSW signal(CN402 pin 1)
Zoom in becomes 0 V.
wave
The output pins A+ ,A-, B+, B- of the drive IC is
PWM waveform and drives the Stepping Motor.

Fig.1

2. Waveform of Spindle rotation

The output signal of Hall(HU+, HU-, HV+, HV,
HW+, HW-) comes from a Hall sensor of spindle
HU+ motor and they were inputted to pin 1, 2, 3, 4, 5, 6
HV+ of drive IC(BD7907FS) via CN402. When spindle
HW+
motor rotate, HU+, HW+, HV+ signals are
generated in a regular order with 1200 phase delay
Zoom in each other.(Refer Fig 2)
wave
If waveforms of HU+, HU-, HV+, HV-, HW+, HW-
different from Fig 2, check the pin 7(HB signal) of
Fig.2 drive IC. The HB signal must be about 5V.

Wave of U,V,W assigned to pin 9,11,18 of Drive

IC is a PWM waveform and they drive Spindle
motor.
When spindle motor rotate, U/W/V signals are
generated in a regular order with 1200 phase delay
Zoom in
each other. (Refer Fig 3)
wave

If waveforms different from Fig 3, check pin

27(VC), pin 51(VCC), pin22(CTL1), pin23 (CTL2),
R514, R512, R510, R511.
Fig.3

3. Waveform of Spindle Kick

When spindle kick, refer to Fig 4.

SPIN
FG
U

Zoom in
wave

Fig.4
58
 Check Tray operation

Check /EJECT KEY

(pin 11 of IC101)

• Check the control singal of Drive IC

Check the output signal of tray Check operating signal of tray (pin 22, 23 of IC501)
(pin 49, 50 of IC501) (pin 26 of IC501) • Check the power of DRIVE IC and
VC

Check operation S/W of tray

(/OPEN SW:pin 94 of IC401
/LOAD SW : pin 95 of IC401)

Check operating signal of LED (pin Check SCLK, SDATA, XLAT (pin
Check the LED
96, 98 of IC401) 122, 123, 124 of IC401)

LED1
LED102 Q802 96
IC 401
LED2
LED101 Q801 98
MT1516
RF Amp SCLK
General port use 122 65
/OPEN_SW
SW103 2 94 123
SDATA
63
XLA T
DETECTOR /LOAD_SW 124 62 IC 101
1 95
-TRAY
101 102 MT1508
FRONT

DRV-MUTE2 DRV-MUTE1
DSP
23
Decoder
22
Tray Motor TRAY - Encoder
49 CTL1 CTL2 PWMOUT I/F
LDIN 26 24

BD7907FS Micro
M 6Ch Servo DRIVE Processor
TRAY + 1.4 V
50 IC 501 VC 27

SW102
11
EJECT /EJECT_KEY
-SW

59
2. Connection of Power and ATAPI cable

Check identification of Drive CN101(ATAPI)

Pin no. Pin name Pin no. Pin name
39 DASP GND 40
Check the connection of ATAPI 37 CS1 CS3 38
cable
35 DA0 DA2 36
33 DA1 PDIAG 34
31 INTRQ IO16 32
Check the communication between
PC and MT1508 (IC101) 29 DMACK GND 30
27 IORDY CSEL 28
25 IOR GND 26
Check SDRAM 23 IOW GND 24
(IC102)
21 DMARQ GND 22
19 GND KEY 20
Check Flash ROM 17 HD0 HD15 18
(IC103) 15 HD1 HD14 16
13 HD2 HD13 14
11 HD3 HD12 12
9 HD4 HD11 10
7 HD5 HD10 8
5 HD6 HD9 6
3 HD7 HD8 4
33.8688MHz
1 /HRST GND 2

74 75

IC 103 IC 101
Address
MT1508
AT49F002N
512KB
Flash ROM Data DSP
Decoder I/F
cable H
Encoder O
ATIP Demodulator S
Write Strategy T
IC 102 Write S/H Signal
I/F
Address
8MB
SDRAM
SDRAM Data Micro Processor

60
Check the identification of CD-
ROM Disc (insert Disc)
In case of Focus Up/Down

• Check the drive signal of FCS-/+

• Check control signal of Drive IC
Check the operation of Focus (pin 1, 2 of CN201)
(pin 22, 23 of IC501: CTL1,2)
• Check drive input signal of Focus
• Check power and VC of DRIVE IC
(pin 53 of IC501 : FCIN)

• Check the input signal of FE

(pin 42 of IC101 : FEI) Check signal of A~H (pin 39, 38, 37,
• Check the input signal of SBAD 36, 30, 31, 32, 33 of IC401)
(pin 38 of IC101)

• Check the drive signal of TRK+/-

(pin 3, 4 of CN201)
Check the operation of Tracking • Check the signal of Tracking
(pin 52 of IC501 : TKIN)
• Check the signal of SLED
(pin 28, 29 of IC501 : SLIN1, 2)

Check the input signal of TE

(pin 40 of IC101 : TEI)

• Check the input signal of CSI (pin

Check the Jump action 41 of IC401)
• Check the input signal of RFZC (pin
60 of IC101 : HRFZC)

Optical FEO
42 42 FEI
Pick-up
KRS-330B A~D SBAD
49 38 SBAD
E~H
IC 401 45
TEO
40 TEI

IC 101
CN 201 MT1516 43
CSI
41 CSI
1 2 3 4 RF Amp
General port use 126
RFZC
60 HRFZC
FCS+

TRK+

TRK-
FCS-

MT1508
SCLK
122 65
45 46 47 48 DRV-MUTE2
SDATA
CTL1 22 101 123 63 DSP
DRV-MUTE1 Decoder
XLA T
CTL2 23 102 124 62
IC 501 Encoder
1.4 V I/F
VC 27
BD7907FS TRSO
Micro Processor
6Ch Servo TKIN 52 7
NJM
6 23 TRO
DRIVE 3404 FOSO
FCIN 53 1 2 22 FOO

SLI N1 28 26 FMO
IC 505
SLI N2 29 27 FMO2

61
4. Operation of Focus Up/Down

FE Waveform of Focus Search refer to Fig 5.

SBAD In Focus Search, FE signal and SBAD signal are
FCS+ used to Focus Servo On.
Therefore, in case of Focusing Fail, check the FE
signal and SBAD signal.
Zoom in
wave

Fig.5
Focus Search Focus Servo On

5. Waveform of Track Following

Waveform of Track Following(Sequential Read)

TE
refer to Fig 6.
EQRF
By Sled Servo, SLIN1, SLIN2 (pin 28, 29 of Drive
IC) drive the Sled Motor(Stepping Motor) for
CE
locating the lens on the center axis of Pick-up.
SLIN1

Fig.6

6. Waveform of Track Jump

TE Waveform of Track Jump refer to Fig 7.

RFZC
Center level of TE,CE is 1.4V.
CE
SLIN1 SLIN1, SLIN2 signal (pin 28, 29 of Drive IC)
assume the form of Pulse. And they drive the Sled
Motor(Stepping Motor).
Zoom in
RFZC(RF Ripple Zero Cross) signal is Pulse form
wave
and it lags behind TE signal 900.
Fig.7

7. Waveform of Spindle Servo On

SPIN
FG To maintain constant rpm(CAV) or linear
velocity(CLV), the drives control spindle motor.
U
The Fig 8 shows the waveforms when spindle
servo is on.

Zoom in
wave

Fig.8

62
 Check RF and Spindle Check EQRF input signal Check the signal of A~H (pin 39, 38,
(Insert CD-ROM Disc) (pin 45 of IC101) 37, 36, 30, 31, 32, 33, of IC401)

Check FG input
(pin 20 of IC101)

• Check the control signal of Drive IC

Check the operation signal of Spindle
(pin 22, 23, of IC501)
(pin 24 of IC501)
• Check power/VC of DRIVE IC

Check the identification of

CD-R Disc(Insert Blank CD-R) Check SCLK, SDATA, XLAT
(pin 122, 123, 124 of IC401)

Check the input signal of ATFG

(pin 69 of IC101)

Check the identification of CD-RW

Disc (Insert Blank CD-R)

EQRF
21 45
IC 401

Optical
MT1516 122
SCLK
65
Pick-up RF Amp SDATA
KRS-330B Wobble 123 63 IC 101
A~D XLA T
Spindle 124 62
General port use MT1508
Motor E~H
ATFG
116 69
STEP Motor DSP
101 102
Decoder
DRV-MUTE2 DRV-MUTE1 Encoder
I/F
22 23
U ATIP
9 CTL1 CTL2 Demodulator
V
11
W
18 SPIN 24 25 DMO
IC 501
HB Micro
7 Processor
BD7907FS
HU+ , HU- 6Ch Servo
1 , 2
DRIVE
FG 21 20 FG
HV+ , HV-
3 , 4
HW+ , HW- 1.4 V
5 , 6 VC 27

63
 Check point of Writing

Check the compatibility between

Drive and Tool

Check whether or not additional

Check whether or not Disc is Check Disc state (Fingerprint, writing is allowed.
writeable (CD-R/CD-RW) Scratch, Dust...) (Given in the Disc Info of writing tool)

Check Laser 1
(Check EEPROM)

Activate ‘Addition Func.’ window in

Test Tool(GGOOM4)

Execute ‘S/N’ (Identify Serial

Number)
(ALPC initial value before ‘Laser Power Setting’)

Execute ‘ALPC Parameters’ Check the communication line of

(Identify ALPC Parameters) EEPROM

Check whether or not ‘ALPC Execute ‘C. Laser Power setting’ in

Parameters is initial value Test Tool(GGOOM4)

IC 101

CS 1 110 EEP-CS IC 401 MT1508

IC 203 122
SCLK
65
SLK 2 108 EEP-CL K SDATA
MT1516 123 63 Decoder
AT93C86 Encoder
XLA T
2KB DI 3 124 62
107 EEP-SDATA ALPC
EEPROM
DO 4
Micro
EEPROM access Processor

64
 Check Laser 2 (No disc)

Execute ‘D. Laser Inspection’ in

Test Tool (GGOOM4)

NG
OFF LEVEL Check Reference voltage

NG
VRDC LEVEL FPD E
Check Read Laser
NG

E
VWDC1 LEVEL FPD F

NG

Execute ‘E.ALPC Test for AS’ in

VWDC2 FPD G
Test Tool (GGOOM4) (select
‘VRDC Loop’, and ‘Trigger’)

OK

Check the input of ENBL

(pin 33 of CN201 : ‘H’)

• Check the input of RLDON

Check the input of VRDC (pin 128 of IC401 : ‘H’)
(pin 25 of CN201 : 0.4~0.8V) • Check SCLK, SDATA, XLAT
(pin 122, 123, 124 of IC401)

Check the input of FPDO (pin 54,

Initial value of FPDO : 2.8V +/- 10%
65 of IC401 : FPDO~0.1V)

CN 201 IC 401 IC 101

Optical H
ENBL 33 5 ENBL MT1508
Pick-up SCLK
122 65
KRS-330B
SDATA Decoder
0.4~0.8V 123 63
VRDC 25 63 VRDCO MT1516 XLAT Encoder
124 62 Write Strategy
ALPC Write S/H Signal
FPDO-0.1V H
FPDO 19 54 FPDO RLDON 128 57
LD Micro
Drive 65 FPDOLP Processor

65
Inspection of CD-R Recording Laser Inspection of CD-RW writing Laser

F G

Execute ‘E. ALPC Test for AS’ in

Execute ‘E.ALPC Test for AS’ in
Test Tool (GGOOM4) (Select
Test Tool(GGOOM4) (Select
‘CD-RW Rec Mode’, and
‘CD-R Rec Mode’, and ‘Trigger’)
‘Trigger’)

Chect input of ENBL

(pin 33 of CN201 : ‘H’)

• Check input of VWDC1 • Check input of WLDON

(pin 26 of CN201 : 0.4~1.0V) (pin 27 of IC401 : ‘H‘)
• Check input of VWDC2 • Check SCLK, SDATA, XLAT
(pin 27 of CN201 : 0.1~0.5V) (pin 122, 123, 124 of IC401)

• Check input of WXR

(pin 30 of CN201 : Pulse)
• Check input of ODON
CD-R Recording Pulse
(pin 31 of CN201 : Pulse)

WXR CD-RW Recording Pulse

Check input of FPDO
(pin 54, 65 of IC401 : Pulse) WXR
ODON
Initial value of FPDO :
2.8V/-10%)
ODON
FPDO

FPDO

CN 201
Optical H
Pick-up
ENBL 33 5 ENBL IC 401 IC 101
SCLK
122 65
KRS-330B 0.4~1.0V
VWDC1 26 62 VWDC1O SDATA
123 63 MT1508
0.1~0.5V XLAT
VWDC2 27 61 VWDC2O
MT1516 124 62
Decoder
ALPC Encoder
FPDO 19 54 FPDO Write Strategy
H Write S/H Signal
65 FPDOLP WLDON 127 58
Micro
LD Processor
Drive WXR 30 13 WXR

ODON 31 15 ODON

66
 Check Audio signal
(Insert Audio Disc)

Identify playback of Audio Disc Check SCLK, SDATA, XLAT

(Play Mode) (pin 122, 123, 124 of IC401)

Check Output signal of AUIO L/R Check Output signal of AUDIO Check Output signal of
(pin 51, 54 of CN100) L/R (pin 165, 167 of IC101) /AUD-MUTE (pin 103 of IC401)

Check Output signal of AUDIO Check Input signal of AUDIO L/R Check Input signal of
L/R (pin 1, 7 of IC801) (pin 3, 5 of IC801) /AUD-MUTE (pin 3 of IC801)

Output of Headphone

IC 401 IC 101
SCLK
122 65
MT1516 SDATA
123 63
RF Amp
XLAT
General port use 124 62
SB MT1508
IC 801 103 DSP
Decoder
/AUD-MUTE
MUTE 3 Encoder
I/F
BH3544F
Micro Processor
LOUT AUDIO LOUT LOUT
JK101 1 3 Audio 165 LO
AMP
ROUT ROUT Mute ROUT
H-JACK 7 5 Circuit 167 RO

FRONT
51 54

L-CH R-CH
CN 100
AUDIO Line Out

67
 • How to use Test Tool (GGOOM4)
A. Start
1. Install GCE-8400B -> PC Power ON -> Execute Windows.
2. Execute GGOOM4.exe on Windows (GGOOM4.exe & GGOOM.cfg should be on the same Directory).
3. If you use GCE-8400B, “GGOOM4(Ver x.xx)” will be displayed on the Window Frame.
4. Select I/F Setup on the menu bar.
5. Select ATAPI I/F and then Click OK.
6. Select Target Select on the menu bar.
7. Select Number of Host(#0 or #1) appropriately, then “GCE-8400B” displays on Target Device.
8. Select “GCE-8400B” on Target Device, and then Click OK.

[I/F Setup Menu] [Target Select window]

B. Check ALPC Parameters

1. Select VIEW on the menu bar.
2. Click Addition Func. on VIEW window -> New frame will be displayed.
3. Click ALPC Para tab.
[ALPC Parameters]
1) CD-R READ Reference DAC : 50 ~143
2) CD-RW READ Reference DAC : 50 ~143
3) VWDC1 - VWDC1 Offset : 105 ~ 160
4) VWDC1 Offset : 30 ~ 165
5) VWDC2 - VWDC2 Offset : 190 ~ 384
6) VWDC2 Offset : -45 ~ 75
4. Close Calibration window.

[Additional Function Menu] [ALPC Parameters Menu]

68
C. Laser Power Setup (VWDC1 / VWDC2 re-setup)
1. Remove disc on the tray.
2. Select ALPC/OPC on the menu bar, and then select Laser Power Setup menu.
3. Setup LD Power meter (Frequency :780nm, Measure Range : 0.01mW unit).
4. Click VRDC button on the Laser Power Setup window. Laser beam will be emitted from LD.
5. Measure LD Power with LD Power meter. Type the result in the blank(Read Power box).
(If you don’t have LD Power meter, type the written value on pickup without decimal point including two
digits under the decimal point.)
[Ex] 11.34mW ->1134
6. Click VWDC1 button and follow above step 5. But VWDC1 result should be filled in the Write Power box.
7. Click Setup button, and result will be displayed with OK or NG.
8. Close Laser Power Setup window.

[Laser Power Setup window]

[Laser Power Setup Frame] [Laser Power Setup Result]

69
D. Laser Inspection (VRDC/VWDC/FPD Level check)
1. Remove disc on the Tray.
2. Select ALPC/OPC on the menu bar and select Laser Inspection menu, then Laser Power Test window
will appear.
3. Click Trigger button, then the result will be displayed with OK or NG separately.
4. Close Laser Power Test window.

[Laser Inspection]

[Laser Power Test Frame] [Laser Power Test Result]

70
 3.3 V
Optical F PD 33.868MHz 5V
Pick-up ABCD IC 401
Data, Clock, XLAT
KRS-330B EFGH
Reset 2.5 V 12V
MT1516
RF Amp IC 101
Wobble Servo S/H, Reset
STEP Motor
VWDC ALPC Write S/H Signal
FCS
Spindle VRDC General port use
TRK
Motor EEPROM access MT1508
EQRF,
RRF, DSP I/F
Writing H
LD FEI,TEI,CSI cable
Pulse Decoder O
Drive Encoder S
ATIP Demodulator T
Address/ Write Strategy
AT93C86 AT49F002N Write S/H Signal
Data
2KB 512KB I/F
Functional Block Diagram

BD7907FS EEPROM Flash ROM

6Ch Servo DRIVE Micro Processor
IC 203 SDRAM
IC 501 IC 103
FG Data
Address IC 102
Drive Mute
M
Tray Motor FOO Audio
TRO LED Control Audio L,R L,R
SLO Mechanism S/W Detect Mute
DMO
Circuit Line Out
PWM out

72
MAJOR IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTION
IC401 (MT1516) : CD-R/RW Analog Signal Processor
Block Diagram

MPXOUT2

MPXOUT1

VWDC1O
VWDC2O
WFPDSH
RFPDSH
WBLCLK

WLDON

VRDCO
VFVREF

RLDON
VHAVC
VDAC0

AGC1C

AGC3C
AGC2C
VDAC1
DVSS2
DVDD1
DVDD2

MCLK
DVSS1

VREF

ATFM
ATFG
V14

V28
AV S S 9
AV D D 9 VRDCN
Voltage P/B
AV S S 8 VRDC
AV D D 8 R e f & DAC Detect AT I P RREF
x1
VREFMPX

AV S S 7
VDAC0

VWDC1N
AV D D 7 MPX2B
MPX2

VWDC1
MPX2B
AV S S 6
MPX1
APC WREF1

ADBCO
BCO
AV D D 6

ADO
AV S S 5
AV D D 5 WRFSH 10-Bit
MPX2

CE FPDOLP
AV S S 4 RREF FE ADC FPDO
AV D D 4 WREF1 TE
VRDCO SBAD FVREF
AV S S 3
VWDC1O SBADOLP FPDOX
AV D D 3 VWDC2O FPDOX
AV S S 2 VWDC1B AU X 1
AV D D 2 VRDCB
MPX2 RFRP
AU X 2
AV S S 1 DRCLP
AUX3 AU X 3
AV D D 1 AUX2 SPPO
SUBGND AUX1 MPPO RFZC1
RFZC
MPX1

RFZC1
X L AT DIG. TELP TZC
TZC SHBC
S DATA DRCMO
REG. HSH RFZC1VC
SCLK DRCSO
GSH SHPC
TRCLOSE
RECDIN
RRFXLP
EQRF

RRFX

FVREF FSH
TROPEN
ATFMX MPX1 S E RV O
T R AYO U T # ESH
FPDO & SBADLP
T R AY I N # DSH
LED1 ROPCO Detection
DEFECT TEIN
CSH
LED2 RFAGCC
BSH SBAD
LIMIT# VCON
TE
ASH
FR CE
ENDM General FE
MUTE I/O DRCO2
SB
DEVSEL
E E P _ S DATA GAINUP
SBADO
FEO
MPPO
SPPO
ADO
BCO
ADBCO
VCON

RRFX

EEP_SCLK GAINUP DRCO

EEP_CS
ENBL HAVC HAVC HAVC
INH
ASPREQ EQRF S/H
GIO1~GIO7 IND IND IND ING
INC RRF ROPC INC
&
INC INF
Data INB INB M AT R I X
WRF

INB
RRF

Slicer INA INA INA INE

XRST
EQRF
RECDIN/RRFSUM

WRFSUM
ROPCC
RRFXLP
OSTCC

RRF/WRF
SLPFN

RFSUM
XDEFM
DEFM

RFAGCC
SLPFP

ROPCO
EQRF

H11T

INC
IND
EQBIAS

INB
WBLSH

HAVC
INA
SERVSH

39
• Pin Assignment
Pin
Symbol Type Description
Numbers
RF Signals & S/H Control Pulses
36 INA Analog Input Input of Main Beam Signal (A)
37 INB Analog Input Input of Main Beam Signal (B)
38 INC Analog Input Input of Main Beam Signal (C)
39 IND Analog Input Input of Main Beam Signal (D)
30 INE Analog Input Input of Side Beam Signal (E)
31 INF Analog Input Input of Side Beam Signal (F)
32 ING Analog Input Input of Side Beam Signal (G)
33 INH Analog Input Input of Side Beam Signal (H)
34 HAVC Analog Input Reference Voltage Input of Main and Side Beams (2.0V)
Digital Input (TTL),
120 SERVSH S/H Control Pulse of Main and Side Beam Signals
SMT
Digital Input (TTL),
118 WBLSH S/H Control Pulse of Wobble Signal
SMT
Focus/Tracking Error & Servo Control Signals
40 DRCO Analog Output Output of Differential Radial Contrast (DRC) Signal
41 DRCO2 Analog Input Re-Input of Differential Radial Contrast (DRC) Signal
42 FE Analog Output Output of Focusing Error Signal
45 TE Analog Output Output of Tr acking Error Signal
43 CE Analog Output Output of Center Error Signal
49 SBAD Analog Output Output of SBAD Signal
44 TEIN Analog Input Input of Out-of-Track Detection Circuit
50 SBADLP Analog Input Input of SBAD Signal after LPF for DEFECT Detection
46 SHPC Analog Output External Capacitor Connection for Peak Hold of RFRP Signal
47 RFZC1VC Analog Output Reference Voltage for RFRP Peak/Bottom Hold
48 SHBC Analog Output External Capacitor Connection for Bottom Hold of RFRP Signal
Digital Output
126 RFZC Output of RF Zero Crossing Binary Signal
(TTL), 4 mA Driving
EQRF (RF Equalizer Filter and Data Slicer) Circuit
19 RFSUM Analog Input Input of RF Summing Signal from PUH to EQRF Block
11 EQBIAS Analog Output External Bias Connection for Circuits in EQRF Block
External Capacitor Connection for Offset Cancellation Circuit of
13 OSTCC Analog Output
Equalizer Output
16 RFAGCC Analog Output External Capacitor Connection for RF AGC in EQRF Block
21 RFOUT Analog Output Output of RF EFM Signal after Equalizer Filter
Digital Output
4 DEFM Binary Output of EFM Signal after Slicing (Positive)
(TTL), 6 mA Driving
Digital Output
3 XDEFM Binary Output of EFM Signal after Slicing (Negative)
(TTL), 6 mA Driving
8 SLPFP Analog Input Input ( ) of Auto Slicing Level
9 SLPFN Analog Input Input of Auto Slicing Level
RRF & ROPC (Running OPC) Related Signals
RECDIN/ (1). Input of RF Signal for Recorded Area Detection
22 Analog Input
RRFSUM (2). Input of Read RF Summing Signal from PUH to RRF Block
70 RRFXLP Analog Output Low Pass Output of RRF Signal

40
 Pin
Symbol Type Description
Numbers
(1). Output of Read RF (RRF) Signal
24 RRF/WRF Analog Output
(2). Output of Write RF (WRF) Signal
26 WRFSUM Analog Input Input of Write RF (WRF) Summing Signal to ROPC Block
27 ROPCO Analog Output Output of Amplified B-Level of Write RF Signal
28 ROPCC Analog Input Vin(-) of Amplifier for Sampled B-Level of WRF Signal
Digital Input (TTL),
125 H11T S/H Control Pulse of WRF Signal
SMT
ATIP (Absolute Time In Pre-groove)
81 AGC1C Analog Output External Capacitor Connection for AGC1 in ATIP Block
82 AGC2C Analog Output External Capacitor Connection for AGC2 in ATIP Block
83 AGC3C Analog Output External Capacitor Connection for AGC3 in ATIP Block
85 ATFM Analog Output Output of Analog Wobble Signal
Digital Output
116 ATFG Digital Output of Wobble Signal after Slicing
(TTL), 4mA Driving
Digital Input (TTL),
114 WBLCLK External Clock Input for Wobble BPF (SCF)
SMT
APC (Auto Power Control for Laser)
54 FPDO Analog Input Input of Laser Monitor Voltage
65 FPDOLP Analog Input Input of Laser Monitor Voltage after Low Pass Filtering
52 FVREF Analog Input Reference Voltage of APC Loops
128 RLDON Digital Input (TTL) Laser Diode Control for Read Mode
127 WLDON Digital Input (TTL) Laser Diode Control for Write Mode
Digital Input (TTL),
112 RFPDSH S/H Control Pulse for Read APC Mode
SMT
Digital Input (TTL),
111 WFPDSH S/H Control Pulse for Write APC Mode
SMT
(1). Input of Power Setting Voltage for Read APC; (2). Output of
55 RREF Analog I/O
Read APC Reference Voltage Generated by Built -in DAC
59 VRDCN Analog Input Vin(-) of Midcourse Amplifier for Read APC Loop
58 VRDC Analog Output Midcourse Output of Laser Diode Controlling in Read Mode
63 VRDCO Analog Output Output Voltage of Laser Diode Controlling in Read APC
(1). Input of Power Setting Voltage for Write APC 1; (2). Output of
53 WREF1 Analog I/O
Write APC Reference Voltage Generated by Built-in DAC
57 VWDC1N Analog Input Vin(-) of Midcourse Amplifier for Write APC 1
56 VWDC1 Analog Output Midcourse Output of Laser Diode Controlling in Write APC
62 VWDC1O Analog Output Output Voltage of Laser Diode Controlling in Write APC
61 VWDC2O Analog Output Output Voltage 2 of Laser Diode Controlling in Write APC
Reference Voltages & DACs
75 VHAVC Analog Output Output of Voltage Reference (2.0V)
78 VREF Analog Output Output of Voltage Reference (2.0V)
77 V14 Analog Output Output of Voltage Reference (1.4V)
76 V28 Analog Output Output of Voltage Reference (2.8V)
74 VFVREF Analog Output Output of Voltage Reference (2.5V~3.0V)
69 VDAC0 Analog I/O Output of General Purposed 8-Bit DAC (0V ~ 2.0V)
51 VDAC1 Analog Output Output of General Purposed 10-Bit DAC (0V ~ 4V)
MPXOUT (Multiplexer Circuit for Various Signals) and Testing Interface
68 AUX1 Analog Input Auxiliary Input 1 for Signal Monitoring
67 AUX2 Analog Input Auxiliary Input 2 for Signal Monitoring
66 AUX3 Analog Input Auxiliary Input 3 for Signal Monitoring

41
 Pin
Symbol Type Description
Numbers
71 MPXOUT1 Analog Output Multiplexer Output 1 for Signal Monitoring
72 MPXOUT2 Analog Output Multiplexer Output 2 for Signal Monitoring
Serial Interface & Other Digital Control Signals
Digital Output ASP request signal output to MT1508 to send control signals via
1 ASPREQ
(TTL), 4 mA Driving serial interface.
Digital Input (TTL),
122 SCLK Clock Input for Register Setting
SMT
Digital I/O (TTL),
123 SDATA Data Input/Output for Register Setting
4 mA Driving
Digital Input (TTL),
124 XLAT Latch Input for Register Setting
SMT
Digital Input (TTL),
2 XRST Digital Input for Register Resetting
SMT
Digital Input (TTL),
109 MCLK Digital Input of Main Clock
SMT
Digital Input (TTL), Tr n Input, A Logical Low Indicates the Tr ay is IN. Feedback
95 TRAYIN# 50K Pull-Up, SMT Flag from Tray Connector.
Digital Input (TTL), Tr Input. A Logical Low Indicates the Tr ay is OUT.
94 TRAYOUT# 50K Pull-Up, SMT Feedback Flag from Tray Connector.
Digital Input (TTL),
99 LIMIT# Sledge Inner Limit Input, Active Low.
50K Pull-Up, SMT
Digital Input (TTL), Device Select. Cleared to ZERO Indicates the Driver is Master
106 DEVSEL 50K Pull-Up, SMT Device. Set to ONE Indicates the Driver is Slave Device.
Digital Input (TTL),
100 FR Spindle Motor Reverse Detection Input.
SMT
Digital Output
93 TROPEN Tray Open Output. Initial Output.
(TTL), 4 mA Driving
Digital Output
92 TRCLOSE Tray
(TTL), 4 mA Driving
Digital Output
96 LED1 LED Control Output. Initial Output.
(TTL), 4 mA Driving
Digital Output
98 LED2 LED Control Output. Initial Output.
(TTL), 4 mA Driving
Digital Output Enable/Disable Disk Motor. A Logical High Enables Disk Motor.
101 ENDM (TTL), 4 mA Driving Initial
Output.
Digital Output
102 MUTE Servo Control Power Driver Enable Output. Initial Output.
(TTL), 4 mA Driving
Digital Output
103 SB Spindle Motor Short Break Control Output. Initial Output.
(TTL), 4 mA Driving
Digital Output
110 EEP_CS EEPROM Chip Select Output.
(TTL), 4 mA Driving
Digital Output
108 EEP_SCLK EEPROM Tr ansmit Clock Output.
(TTL), 4 mA Driving
Digital I/O (TTL),
107 EEP_SDATA 50K Pull-Down, EEPROM Tr ansmit Data Input/Output.
4mA Driving
Digital Output
5 ENBL (TTL), Laser Diode Enable Signal Output
4 mA Driving

42
 Digital I/O (TTL),
50K Pull-Up, (1). General I/O 1 for Mass Production Use (Initial Input Mode)
88 GIO1
4 mA Driving (2). Output of Internal Digital Signal ( VWDC1 )

Pin
Symbol Type Description
Numbers
Digital I/O (TTL),
(1). General I/O 2 for Mass Production Use (Initial Input Mode)
89 GIO2 50K Pull-Up,
(2). Output of Defect Detection Signal ( DEFEC )
4 mA Driving
Digital I/O (TTL),
(1). General I/O 3 for Mass Production Use (Initial Input Mode)
90 GIO3 50K Pull-Down,
(2). Output of the State of Seeking ON Control Setting
4 mA Driving
Digital I/O (TTL),
(1). General I/O 4 for Mass Production Use (Initial Input Mode)
91 GIO4 50K Pull-Down,
(2). Output of Internal Digital Signal ( )
4 mA Driving
Digital I/O (TTL),
(1). General I/O 5 for Mass Production Use (Initial Input Mode)
104 GIO5 50K Pull-Up,
(2). Output of Out-of-Track Detection Signal
4 mA Driving
Digital I/O (TTL),
(1). General I/O 6 for Mass Production Use (Initial Input Mode)
105 GIO6 50K Pull-Up,
(2). Output of Out-of-Track Detection Signal ( XTOR )
4 mA Driving
Digital I/O (TTL),
(1). General I/O 7 for Mass Production Use (Initial Input Mode)
119 GIO7 50K Pull-Up,
(2). Output of Recorded Area Detection Signal ( RECD1
4 mA Driving
Power Supplies
86 , 87 SUBGND Analog Ground Ground Pin for Substrate Bias of Internal Digital Circuitry
29 AVDD1 Analog Power Power Pin for Internal Analog Circuitry (5V)
35 AVSS1 Analog Ground Ground Pin for Internal Analog Circuitry
60 AVDD2 Analog Power Power Pin for Internal Analog Circuitry (5V)
64 AVSS2 Analog Ground Ground Pin for Internal Analog Circuitry
80 AVDD3 Analog Power Power Pin for Internal Analog Circuitry (5V)
84 AVSS3 Analog Ground Ground Pin for Internal Analog Circuitry
20 AVDD4 Analog Power Power Pin for Internal Analog Circuitry (5V)
18 AVSS4 Analog Ground Ground Pin for Internal Analog Circuitry
23 AVDD5 Analog Power Power Pin for Internal Analog Circuitry (5V)
25 AVSS5 Analog Ground Ground Pin for Internal Analog Circuitry
79 AVDD6 Analog Power Power Pin for Internal Analog Circuitry (5V)
73 AVSS6 Analog Ground Ground Pin for Internal Analog Circuitry
10 AVDD7 Analog Power Power Pin for Internal Analog Circuitry (5V)
6,7 AVSS7 Analog Ground Ground Pin for Internal Analog Circuitry
14 AVDD8 Analog Power Power Pin for Internal Analog Circuitry (5V)
12 AVSS8 Analog Ground Ground Pin for Internal Analog Circuitry
15 AVDD9 Analog Power Power Pin for Internal Analog Circuitry (5V)
17 AVSS9 Analog Ground Ground Pin for Internal Analog Circuitry
121 DVDD1 Digital Power Power Pin for Internal Digital Circuitry (5V)
117 DVSS1 Digital Ground Ground Pin for Internal Digital Circuitry
113 DVDD2 Digital Power Power Pin for Digital I/O Pads Buffer Circuitry (5V)
115 DVSS2 Digital Ground Ground Pin for Digital I/O Pads Buffer Circuitry

43
IC101(MT1508) : CD-R/RW Encoder/Decoder/Write Strategy / DSP
/Interface /Micro Processor
Block Diagram

WSR_CFREQ
EFMLPFGND
EFMPLLVDD

EFMPLLVSS

WSR_ODON
FLAG_OUT1
FLAG_OUT2
EFMVCOIN
RFDTSLVN

WSR_WXR
RFDTSLVP

WFPDSH
WBLCLK

RFPDSH
SERVSH
WLDON

WBLSH
RLDON
SCON
SCOP

ATFG

H11T
RFIN
RFIP

TEST

Data Wobble EFMPLL

Wobble Signal Write Strategy Reset
Slicer Spindle (efmclk PRST#
Interface Logic Logic
Control synthesizer) Interface
DPLLVDD Logic
IREF
LPFIN
Sync. EFM
LPFIP FM Demodulator
DPLLVSS Data Protection Demodulator System XTALO
PLL Subcode & Bi-Phase data
LPFON Demodulator Clock XTALI
LPFOP Demodulator Generator
LPION Servo IPLLVDD
IPLLVSS
LPIOP status
ATIP Sync Protection & detection
PWM
DMO CRC check & circuit
DAC CLV/CAV system
ENDM Target MSF Search clock
Controller
FG

VPVDD Varipitch
VCOCIN CLV Clock CIRC
VPVSS CIRC Encoder
Generator Error Corrector C3 C3
DMU EFM modulatoin
Decoder Encoder
Subcode generator
TEZILP
RFZC/
TEI TEZC
HRFZC
Circuit
RD[15:0]
SRVADCVDD CDROM
FEI Servo Buffer
TEI Servo Sync r RA[11:0]
DSP Memory RAS#
CSI
ADC Detection CAS#
SBAD Controller
SRVADCVSS Descrambler CASH#/RWEH#
RWE#
ROE#
CLK
CKE
FOO 3K DQM
TRO BA(1:0)
FMO
PDM & CDROM Host ATAPI SRAM
FMO2 PWM DAC Audio/Effect
PWMOUT OPC/ROPC High-speed Data Packet
Interface
Computation Audio Playback FIFO FIFO
PDMVDD Unit Key/LED
PWM2VREF EJECT#/STOP#
PWMVREF
8032 Interface PLAY#/PAUSE#
PDMVSS
ASP Laser Power Time to Audio Host Interface Micro-controller
Control Control Digital Audio DAC Digital Out
Interface Logic Converter
ADGO
DACVDD
DACVSS
SLCK
XRST#
SDEN

CS1FX#
CS3FX#
DASP#

UPSEN#
DACVREF

DMARQ
DMACK#
PDIAG#
RO

UALE

UP3_7/URD#
IOCS16#
LO

URST
DIOR#
HRST#

UP2_7~UP2_0

UP3_5~UP3_4
UP3_1~UP3_0
HD[15:0]

UA16/UP1_0
UA17/UP1_1
UA18/UP1_2
UA[7:0]
HA[2:0]
SDATA

DIOW#

INTRQ
FLAG_OUT1

UP3_6/UWR#
IORDY

UP3_2/UNIT0#
UP3_3/UINT1#

UP0[7:0]/UAD[7:0]

44
• Pin Description
Pin Numbers Symbol Type Description
Data PLL Interface (9)
29 DPLLVDD Analog Power supply for data PLL and related analog circuitry.
Power(3.3V)
30 LPIOP Analog Output Data PLL VCO DAC positive output.
31 LPION Analog Output Data PLL VCO DAC negative output.
32 LPFOP Analog Output The positive output of loop filter amplifier.
33 LPFIN Analog Input The negative input terminal of loop filter amplifier.
34 LPFIP Analog Input The positive input terminal of loop filter amplifier.
35 LPFON Analog Output The negative output of loop filter amplifier.
36 IREF Analog Input Current reference input. It generates reference current for data
PLL. Connect an external 15K resistor between this pin and
PLLVSS.
37 DPLLVSS Ground Ground pin for data PLL and related analog circuitry.
Signal Amplifier Interface (13)
38 SBAD Analog Input Sub-beam add input (E+F+G+H).
39 TEZILP Analog Input Tr acking error zero crossing low pass input.
40 TEI Analog Input Tracki ng error input.
41 CSI Analog Input Central servo input.
42 FEI Analog Input Focus error input.
43 SRVADCVSS Ground Ground pin for servo ADC circuitry.
44 RFIN Analog Input RF negative signal input.
45 RFIP Analog Input RF positive signal input.
46 SRVADCVDD Analog Power supply for servo ADC circuitry.
Power(3.3V)
47 RFDTSLVN Analog Input Negative input for analog slicer.
48 SCOP Analog Output Positive low pass filter output for analog slicer.
49 SCON Analog Output Negative low pass filter output for analog slicer.
50 RFDTSLVP Analog Input Positive input for analog slicer.
Turbo 8032 Interface (37)
171 UP3_7 3.3V LVTTL I/O, Programmable bi-directional I/O.
/ URD# Slew rate, SMT, Alternate function : RD#. Data write signal.
4mA driving,
75K pull-up
172 UP3_6 3.3V LVTTL I/O, Programmable bi-directional I/O.
/ UWR# Slew rate, SMT, Alternate function : WR#. Data write signal.
4mA driving,
75K pull-up
173 UP3_3 3.3V LVTTL I/O, Programmable bi-directional I/O.
/ UINT1# Slew rate, Alternate function : INT1#. External interrupt 1.
4mA driving,
75K pull-up
174 UP3_2 3.3V LVTTL I/O, Programmable bi-directional I/O.
/ UINT0# Slew rate, Alternate function : INT0#. External interrupt 0.
4mA driving,
75K pull-up

45
 175 UP3_1 3.3V LVTTL I/O, Programmable bi-directional I/O.
/ UTXD Slew rate, Alternate function : TXD. Serial transmit data.
4mA driving,
75K pull-up
176 UP3_0 3.3V LVTTL I/O, Programmable bi-directional I/O.
/ URXD Slew rate, Alternate function : RXD. Serial receive data.
4mA driving,
75K pull-up
177 UALE 3.3V LVTTL I/O, Address latch enable output during internal mode, active
Slew rate, SMT, high. And as address latch enable input during ICE mode.
4mA driving,
75K pull-up
178 UPSEN# 3.3V LVTTL I/O, Programmable store enable output during internal mode,
Slew rate, SMT, active low. UPSEN# enables the external ROM output port.
4mA driving, And as input during ICE mode.
75K pull-up
189,188,186, UA[7:0] 3.3V LVTTL output, Lower address bus output for external device.
185,184,182, Slew rate, Alternate function : Internal monitored signal output.
181,179 2mA, 4mA, 6mA
8mA PDR,
75K pull-up
190,192,193, UP2_[7:0] 3.3V LVTTL output, Programmable bi-directional I/O.
194,195,197, / UA[15:8] Slew rate, Alternate function : A[15:8]. Upper address bus input/output.
198,199 2mA, 4mA, 6mA
8mA PDR,
75K pull-up
191 FLASH_WE# 3.3V LVTTL output, Flash memory write enable signal output, low active.
4mA driving
200 UP1_1 3.3V LVTTL output, Programmable bi-directional I/O.
/UA17 Slew rate, Alternate function : A17. Address bit 17 output.
2mA, 4mA, 6mA
8mA PDR,
75K pull-up
201 UP1_0 3.3V LVTTL output, Programmable bi-directional I/O.
/ UA16 Slew rate, Alternate function : A16. Address bit 16 output.
2mA, 4mA, 6mA
8mA PDR,
75K pull-up
202 FLASH_CS# 3.3V LVTTL I/O, Flash memory chip select signal output, low active.
Slew rate, SMT,
4mA driving,
75K pull-up
203,204,3, UP0_[7:0] 3.3V LVTTL output, Programmable bi-directional I/O.
4,5,6,8,9 / UAD[7:0] Slew rate, Alternate function : AD[7:0]. Lower address/data bus output
2mA, 4mA, 6mA for external device.
8mA PDR
205 UP1_2 3.3V LVTTL I/O, Programmable bi-directional I/O.
/UA18 Slew rate, Alternate function : UA18. Address bit 18 output.
4mA driving,
75K pull-up
Motor and Actuator Driver Interface (11)

46
 20 FG 3.3V LVTTL Input, Motor Hall sensor input. X
SMT, 75K pull-up
22 FOO Analog Output Focus servo output. PDM output of focus servo compensator.
23 TRO Analog Output Tr acking servo output. PDM output of tracking servo
compensator.
24 PWMOUT Analog Output General purpose PWM output.
25 DMO Analog Output Disk motor control output. PWM output.
26 FMO Analog Output Feed motor control. PWM output.
27 FMO2 Analog Output Feed motor 2 control. PWM output.
51 PDMVDD Analog Power supply for PDM circuitry.
Power(3.3V)
52 2VREF Analog input 2.90 V reference voltage input.
53 VREF Analog input 1.45 V reference voltage input.
54 PDMVSS Ground Ground for PDM circuitry.
Mega Interface (2)
11 EJECT# 3.3V LVTTL I/O, Eject/stop key input, active low. ZFA
75K pull-up,
4mA driving
12 PLAY# 3.3V LVTTL I/O, Play/pause key input, active low. ZFA
75K pull-up,
4mA driving
Varipitch VCO Interface (3)
155 VPVSS Ground Ground pin for varipitch circuitry.
156 VPVCOCIN Analog Input Connect capacitor for compensator loop filter.
157 VPVDD Analog power(3.3V) Power supply for varipitch circuitry.
IPLL VCO Interface (2)
104 IPLLVDD Analog power(3.3V) Power supply for IPLL circuitry.
105 IPLLVSS Ground Ground pin for IPLL circuitry.
EFMPLL VCO Interface (4)
207 EFMPLLVDD Analog power(3.3V) Power supply for EFMPLL circuitry.
208 EFMVCOCIN Analog input EFMPLL VCO input. For external loop filter connection.
1 EFMLPFGND Analog input EFMPLL LPF ground input.
2 EFMPLLVSS Ground Ground pin for EFMPLL circuitry.
Audio Output Interface (1)
163 ADGO 3.3V LVTTL I/O, Digital Audio Output. The signal is the Digital Audio Output ZFA
SMT, Slew rate, which supplies the IEC-958 digital audio data.
75K pull-up, Alternate function : HRST_ extension selection input during
4mA, 8mA driving power-on stage (PRST falling edge). A logical low input
indicates raw HRST_ is used. A logical high input indicates
extended HRST_ is used.
Internal Audio DAC Interface (5)
164 AUDACVSS Ground Ground pin for internal audio DAC circuitry.
165 LO Analog Output Left channel of audio.
166 DACVREF Analog Output Reference voltage for external audio filter circuit.
167 RO Analog Output Right channel of audio.
168 AUDACVDD Analog Power supply for internal audio DAC circuitry.
Power(3.3V)

47
 Write Strategy Interface (5)
13 WXR 3.3V LVTTL output, Laser diode write power control output. (Write/Read mode SW
Slew rate, signal)
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
15 ODON 3.3V LVTTL output, Laser diode over drive control output. (Over drive control SW
Slew rate, signal)
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
16 OUT1/OSCEN 3.3V LVTTL output, Internal flag output. Include : WSR_OSCEN signal
Slew rate,
8mA driving
18 OUT2/CMOD 3.3V LVTTL output, Internal flag output. Include : WSR_CMOD signal
Slew rate,
8mA driving
19 CFREQ 3.3V LVTTL output, Frequency selection signal output.
Slew rate,
8mA driving
Write strategy & ASP transmission Interface (16)
55 XRST# 3.3V LVTTL output, RF reset output. Active low.
4mA driving
56 ASPREQ 3.3V LVTTL Input, ASP request signal input from MT1516 to get RECD1, XTOR,
SMT, 75K DEFECT automatically.
pull-down
57 RLDON 3.3V LVTTL I/O, Read laser diode on control signal.
75K pull-down, Alternate function : ICE mode selection input during power-on
4mA driving stage (PRST falling edge). A logical low input indicates
internal is used. A logical high input indicates external
is connected.
58 WLDON 3.3V LVTTL output, Write laser diode on control signal.
4mA driving
60 HRFZC 3.3V LVTTL Input, High frequency RF ripple zero crossing input.
SMT, 75K pull-up
61 H11T 3.3V LVTTL output, EFM 11T indicator for ROPC sampling.
Slew rate,
8mA driving
62 XLAT 3.3V LVTTL output, Latch signal output for RF register setting.
4mA driving
63 XDATA 3.3V LVTTL I/O, Data signal output for RF register setting.
Slew rate,
75K pull-down,
4mA driving
65 XCLK 3.3V LVTTL output, Carrier clock signal output for RF register setting.
Slew rate,
8mA driving
66 SERVSH 3.3V LVTTL output, Sample pulse for servo signal (main beam/ side beam)
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR

48
 68 WBLSH 3.3V LVTTL output, Sample pulse for wobble signal. YFA
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
69 ATFG 3.3V LVTTL Input, Digital wobble signal (22.05 1 K Hz) input X
SMT
70 WBLCLK 3.3V LVTTL output, Wobble processing clock (432.18K Hz) output for MT1516. YFA
Slew rate,
4mA driving
71 RFPDSH 3.3V LVTTL output, Sample pulse control signal for RF read APC. YFA
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
72 WFPDSH 3.3V LVTTL output, Sample pulse control signal for RF write APC. YFA
Slew rate,
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
206 WRSTOP 3.3V LVTTL Input, Write procedure stop control input. X
SMT, 75K
pull-down
Miscellaneous Interface (4)
169 TEST_MODE 3.3V LVTTL input Test mode, active high X
170 PRST 3.3V LVTTL Input, Power on reset input, high active. X
SMT
74 XTALO Output X`tal output.
75 XTALI Input X`tal input. The working frequency is 33.8688 MHz.
Host Interface (31)
122 HRST# 3.3V LVTTL Input, Host reset input. The active-low input is referred to as X
SMT, 75K pull-up hardware reset and is used to reset this chip.
142,140,138, HD15 ~ HD0 3.3V LVTTL I/O, Host Data bus. This is the 8-bit or 16-bit bi-directional data ZFA
135,132,130, Slew rate, SMT, bus to the host. The lower 8 bits, HD0 D7, are used for 8-bit
127,124,123, 4mA, 8mA, 12mA, data transfers. Normally, data transfers are 16-bit wide.
125,128,131, 16mA PDR, Note : All pins except HD7 (no any pull) may be selectively
133,136,139, 75K PPU, 75K PPD pull-up or pull-down with 20K resistant.
141
144 DMARQ 3.3V LVTTL output, DMA request. This signal is used for DMA data transfers YFA
12mA driving between host and device and it shall be asserted by the tri
MT1508 when it is ready to transfer data to or from the host.
The direction of data transfer is controlled by DIOR# and
DIOW#.
145 DIOW# 3.3V LVTTL Input, Device I/O write. Stop ultra DMA burst. X
SMT, 75K pull-up For Device I/O Write, this signal is the strobe signal asserted
by the host to write device register or the data port.
For Stop Ultra DMA, this signal shall be negated by the host
before data is transferred in an Ultra DMA burst and is
asserted by host during an Ultra DMA burst to signal the
termination of Ultra DMA burst.

49
 146 DIOR# 3.3V LVTTL Input, Device I/O read. Ultra DMA ready. Ultra DMA data strobe. XF
SMT, 75K pull-up For Device I/O Read, this signal is the strobe signal asserted
by the host to read device registers or the data port.
For Ultra DMA ready, this is asserted by the host to indicate to
the device that the host is ready to receive Ultra DMA data in
burst to the host.
For Ultra DMA data strobe, this signal is the data out strobe
signal from the host for an Ultra DMA data out burst.
148 IORDY 3.3V LVTTL I/O, I/O Channel Ready. Ultra DMA ready. Ultra DMA data strobe. ZFA
SMT, Slew rate For I/O channel Ready, this signal is negated to extend the
16mA driving host transfer cycle of any register read or write when the
device is not able to complete the transfer.
For Ultra DMA Ready, this signal is asserted by the device to
indicate to the host that the device is ready to receive Ultra
DMA data out bursts from the host.
For Ultra DMA data strobe, this is the data in strobe signal
from device for Ultra DMA data in burst to the host.
149 DMACK# 3.3V LVTTL Input, DMA Acknowledge. This signal shall be used by the host in XF
SMT, 75K pull-up response to DMARQ to acknowledge that it is ready for DMA
transfers.
151 INTRQ 3.3V LVTTL I/O, Device Interrupt. This signal is used to interrupt the host ZFA
Slew rate, system. INTRQ is driven only when this chip is addressed.
12mA driving When not driven, INTRQ is in a high impedance state.
152 IOCS16# 3.3V LVTTL output, Device 16-BIT I/O. In PIO transfer modes 0, 1, and 2, YFA
16mA driving IOCS16# indicates to the host system that the 16-bit data port 0
has been addressed and that the device is prepared to send or 1 : tr
receive a 16-bit data word.
154 PDIAG# 3.3V LVTTL I/O, Passed Diagnostics. This signal is asserted by Device 1 to ZFA
12mA driving, indicate to Device 0 that it has completed diagnostics.
75K pull-up
159,153,158 HA2, HA0, HA1 3.3V LVTTL Input, Device Address. This is the 3-bit binary coded address pro- XF
SMT, 75K pull-up vided by the host to access an ATA register or data.
160 CS1FX# 3.3V LVTTL Input, Device Chip Select 0 (for 1Fxh/17xh). This is the chip select XF
SMT, 75K pull-up signal from the host to select the Command Block Registers.
161 CS3FX# 3.3V LVTTL Input, Device Chip Select 1 (for 3Fxh/37xh). This is the chip select XF
SMT, 75K pull-up signal from the host to select the Control Block Registers.
162 DASP# 3.3V LVTTL I/O, Device Active / Device 1 Present. This is a time-multiplexed ZFA
12mA driving, signal that indicates that a device is active, or that Device 1 is
75K pull-up present.
Buffer Memory Interface (38)
82 BA1 3.3V LVTTL SDRAM bank address 1 signal. When 4-bank SDRAM is ZFA
Output, used, this pin is used to select bank2 and bank3 space and
Slew rate, musts connect to pin of SDRAM.
2mA, 4mA, 6mA, When two 2-bank SDRAM are used, this pin is used as Chip
8mA, 10mA, 12mA, Select signal output for second SDRAM and musts connect
14mA, 16mA PDR, to CS# pin of second SDRAM.
When two DRAM are used, this pin is used as Row Address
Strobe signal output for second DRAM and must connect to
RAS# pin of second DRAM.

50
84 BA0 3.3V LVTTL SDRAM bank address 0 signal. For SDRAM application only. ZFA2G
Output,
Slew rate,
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR,
75K PPD
85 ROE# 3.3V LVTTL RAM Output Enable, low active. ZFA2G
Output, For SDRAM application, this pin is “Chip Select” signal output
Slew rate, connected to “CS#” pin of SDRAM. When two 2-bank SDRAM
2mA, 4mA, 6mA, are used, this pin musts connect to “CS#” pin of first SDRAM.
8mA, 10mA, 12mA,
14mA, 16mA PDR
87 RAS# 3.3V LVTTL RAM Row Address Strobe. This active-low output is the Row ZFA2G
Output, Address Strobe signal to the RAM.
Slew rate, For SDRAM application, this pin is “row address strobe” signal
2mA, 4mA, 6mA, output connected to SDRAM.
8mA, 10mA, 12mA,
14mA, 16mA PDR
88 CAS# 3.3V LVTTL Column Address Strobe Low / Column Address Strobe. When ZFA2G
Output, two column address strobe pins are used, this pin is the
Slew rate, Column Address Strobe Low signal for accessing the lower
2mA, 4mA, 6mA, bytes of a two-CAS# 16-bit RAM. When an 8-bit DRAM is
8mA, 10mA, 12mA, used, this pin shall be connected to CAS# of the DRAM.
14mA, 16mA PDR For SDRAM application, this pin is “column address strobe”
signal output connected to SDRAM.
89 RWE# 3.3V LVTTL RAM Write Enable/RAM Write Enable Low. RAM write enable ZFA2G
Output, signal, low active. When two write enable pins are used, it is
Slew rate, the Write Enable Low signal for writing the lower bytes of a
2mA, 4mA, 6mA, two-WE_ 16-bit RAM.
8mA, 10mA, 12mA, For SDRAM application, this pin is dedicated for “Write
14mA, 16mA PDR Enable” usage.
90 DQML 3.3V LVTTL SDRAM low-byte data output mask control signal, high active. ZFA2G
Output, For SDRAM application only.
Slew rate,
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR,
75K PPD
116 CASH#/ 3.3V LVTTL Column Address Strobe High / RAM Write Enable High. When ZFA2G
RWEH# Output, a 16-bit DRAM is used, this active-low pin functions as
Slew rate, Column address Strobe High for accessing the upper bytes of
2mA, 4mA, 6mA, a two-CAS# RAM, or as Write Enable High for writing the
8mA, 10mA, 12mA, upper bytes of a two-WE# RAM.
14mA, 16mA PDR For SDRAM application, this pin is changed to DQMH and is
used to as SDRAM high-byte data mask control signal, high
active.

51
 117 CLK 3.3V LVTTL SDRAM clock output. For SDRAM application only. ZFA2
Output,
Slew rate,
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR,
75K PPD
118 CKE 3.3V LVTTL SDRAM clock enable signal output. For SDRAM application ZFA2
Output, only.
Slew rate,
2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR,
75K PPD
106,107,108, RD15 ~ RD0 3.3V LVTTL I/O, RAM Data bus. These pins are the bi-directional upper Buffer ZFA2
109,110,112, Slew rate, RAM data bus to the external buffer memory.
113,115,92, 2mA, 4mA, 6mA,
93,94,95,96, 8mA, 10mA, 12mA,
97,98,99 14mA, 16mA PDR,
75K PPU, 75K PPD
119,81,120, RA11~ RA0 3.3V LVTTL RAM address bus. ZFA2
121,103,102. Output,
101,100,77,78, Slew rate,
79,80 2mA, 4mA, 6mA,
8mA, 10mA, 12mA,
14mA, 16mA PDR
Power Supply (27)
91,143,196 (3) DVDD33 Power (3.3V) Power supply for input pad buffer circuitry.
17,76,134,180 DVDD25 Power (2.5V) Power supply for internal digital circuitry and general pad
(4) buffer circuitry.
14,73,137,183 DVSS Ground Ground pin for internal digital circuitry and input pad buffer
(4) circuitry.
7,67,86,111, DVDD33 Power (3.3V) Power supply for output pad buffer circuitry.
129,150 (6)
10,64,83,114, DVSS Ground Ground pin for output pad buffer circuitry.
126,147,187 (7)
28 AVDD25 Power (2.5V) Power supply for dedicated digital circuitry in fully block.
21 AVSS Ground Ground pin for dedicated digital circuitry in fully block.
59 AVDD33 Power (3.3V) Power supply for dedicated digital circuitry in fully block.

52
IC501 (BD7907FS): Spindle Motor and 5ch Actuator Driver

Block Diagram

HU+ 1 54 DVCC

FG
HU- 2 53 FCIN

DETECT
REVERCE
HV+ 3 52 TKIN

HV- 4 51 VCC

HW+ 5 50 LDO+

SHIFT
LEVEL
47K
HW- 6 49 LDO-
BIAS
HALL

HB 7 48 TKO+
47K

SHIFT
LEVEL
94K
PGND1 8 47 TKO-
94K

U 9 SHIFT
46 FCO+
LEVEL
SPVM1 10 45 FCO-

V 11 44 AVM

GND 12 43 GND
OUT
PWM
MATRIX
3-phase

GND 13 42 GND
TSD
FF

GND 14 41 GND
COMP
Current

GND 15 40 GND
OSC
COMP
Polarity

GND 16 39 GND

PGND2 17 38 AGND
LIMIT
Current

W 18 37 SLO1+
LOGIC
PRE
FF

SPVM2 19 36 SLO1-

SPRNF 20 35 SLO2+
LOGIC
PRE
FF
FG

FG 21
OSC

34 SLO2-
CONTROL

CTL1 22
BRAKE

33 SLGND
STBY/

15K

CTL2 23 32 SLRNF2
15K

SPIN 24 31 SLRNF1
LIMIT

LIMIT

47K
94K

DGND 25 30 SLVDD
47K

47K
47K

LDIN 26 29 SLIN2

VC 27 28 SLIN1
47K

53
• Pin Description
Terminal Symbol Description Terminal Symbol Description
1 HU+ Hall amp.U positive input 54 DVCC PWM block control power supply
2 HU- Hall amp.U negative input 53 FCIN Focus driver input
3 HV+ Hall amp.V positive input 52 TKIN Tracking driver input
4 HV- Hall amp.V negative input 51 VCC BTL pre and Loading power supply
5 HW+ Hall amp.W positive input 50 LDO+ Loading driver positive output
6 HW- Hall amp.W negative input 49 LDO- Loading driver negative output
7 HB Hall bias 48 TKO+ Tracking driver positive output
8 PGND1 Spindle driver power ground 1 47 TKO- Tracking driver negative output
9 U Spindle driver output U 46 FCO+ Focus driver positive output
10 SPVM1 Spindle driver power supply 1 45 FCO- Focus driver negative output
11 V Spindle drive output V 44 AVM Actuator driver block power supply
12 GND GND 43 GND GND
13 GND GND 42 GND GND
14 GND GND 41 GND GND
15 GND GND 40 GND GND
16 GND GND 39 GND GND
17 PGND2 Spindle driver power ground 2 38 AGND Ground
18 W Spindle driver output W 37 SLO1+ Sled driver 1 positive output
19 SPVM2 Spindle driver power supply 2 36 SLO1- Sled driver 1 negative output
20 SPRNF Spindle driver current sense 35 SLO2+ Sled driver 2 positive output
21 FG Frequency generator output 34 SLO2- Sled driver 2 negative output
22 CTL1 Driver logic control input 1 33 SLGND Sled driver power ground
23 CTL2 Driver logic control input 2 32 SLRNF2 Sled driver 2 current sense
24 SPIN Spindle driver input 31 SLRNF1 Sled driver 1 current sense
25 DGND PWM block pre-ground 30 SLVDD Sled driver Power MOS pre-supply
26 LDIN Loading driver input 29 SLIN2 Sled driver 2 input
27 VC Reference voltage input 28 SLIN1 Sled driver 1 input

* Positive/negative of the output terminals are determined in reference to those of the input terminals.

• Functional description
O : ON, X : OFF

CTL1(22pin) CTL2(23pin) Spindle Sled Focus Tracking Loading

L L X X X X X ¥L
H L X X X X O ¥M
_ H O O O O X

CTL1(22pin) CTL2(23pin) SPIN > VC SPIN < VC

L H Forward-rotation mode Reverse-rotation braking mode ¥N

H H Forward-rotation mode Short-circuit braking mode ¥O

¥LStanby mode ¥M Drivers muting ¥N Reverse-rotation mode (spindle) ¥O Short-circuit braking mode (spindle)

54
 035 004
005
5 EXPLODED VIEW 008
013
006
014

009 015
PBM00 (MAIN C.B.A)

4
012

016

400
A01 010

3 011
031

001

034
026 027
007

025
400
430
2 400 419
A02 030
021 430 030 413

028
003 029
021 413
413
002 050
020
032
413
017 033
400
1
400
020

A B C D E F G H
11 12