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Virtual Sequence and Virtual Sequencer

The document discusses the implementation of virtual sequences and virtual sequencers in a testbench environment to enhance reusability and avoid path dependencies. It outlines the structure of classes for managing read and write agents, as well as the creation and execution of virtual sequences. Key components include the ram_virtual_sequencer and virtual_sequence_base classes, which facilitate the connection between various sequencers and sequences in a modular manner.

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99 views9 pages

Virtual Sequence and Virtual Sequencer

The document discusses the implementation of virtual sequences and virtual sequencers in a testbench environment to enhance reusability and avoid path dependencies. It outlines the structure of classes for managing read and write agents, as well as the creation and execution of virtual sequences. Key components include the ram_virtual_sequencer and virtual_sequence_base classes, which facilitate the connection between various sequencers and sequences in a modular manner.

Uploaded by

kollasunnykumar123
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Virtual Sequence and Virtual Sequencer

A testbench with multiple agents typically has


multiple sequencers
Fig 1.1
TOP

Ram_test ENV

Read_agent
M

S D

DUT

Write_agent
M

Example
class ram_test extends uvm_test;
`uvm_component_utils(ram_test) //factory registration
read_sequence read_seqh;
write_sequence write_seqh;
function new(string name=”ram_test”,uvm_component
parent)
super.new(name,parent);
endfunction
virtual task run_phase(uvm_phase phase);
phase.raise_objection(this);
read_seqh.start(ram_envh.write_agnth.seqrh);
write_seqh.start(ram_envh.write_agnth.seqh);
phase.drop_objection(this);
endtask
Test It is developed by testcase
writer
----------------------------------------------------
Env

Agent It is developed by
Testbench Developer
Sequencer

In Test run phase

read_seqh.start(ram_envh.write_agnth.seqrh);
write_seqh.start(ram_envh.write_agnth.seqh);
here testcase writer doesn’t know the
path of sequencer because it is developed by the testbench
developer. To avoid a path dependency we go to virtual
sequencer and virtual sequence.
Virtual Sequencer
 To generate a test cases independent of testbench env.
 Virtual sequencer is extended from a uvm_sequencer.
 It is parametrized with uvm_sequence_item.
 Virtual sequencer contain all the physical sequencers
handle.
Tb contain Virtual sequencer and Virtual Sequence

Test
Virtual Sequence Environment

m_sequencer Virtual Sequencer

Write Read
seqr seqr

virtual Sequencer

write read
seqr seqr Write agent Read agent
write read
seqr seqr

write Read
seqr seqr
write write read read
driver mon mon driver

Write Read
seq seq

DUT
Virtual Sequence
 To improve Reusability.
 Virtual sequence is extended from a uvm_sequence.
 It is parametrized with uvm_sequence_item.
 Virtual sequence contain
 Sequence handle
 Sequencer handle
 M-sequencer
 Virtual sequencer handle

Example

Virtual Sequencer
Class ram_virtual_sequencer extends uvm_sequencer
#(uvm_sequence_item);
`uvm_component_utils(ram_virtual_sequencer)
ram_wr_sequencer ram_wr_seqr_h;
ram_rd_sequencer ram_rd_seqr_h;
function new(string name="ram_virtual_sequencer",
uvm_component parent=null);
super.new(name,parent);
endfunction
endclass
virtual_sequence

class virtual_sequence_base extends uvm_sequence


# (uvm_sequence_ item);
uvm_object_utils (virtual_sequence_base)

//virtual sequencer handle


ram_virtual_sequencer ram_v_sqrh;
//local sub-sequencer handles
ram_wr_sequencer ram_wr_sqrh;
ram_rd_sequencer ram_rd_sqrh;
// no need to declare m-sequencer it will be inherit from
uvm_sequence
function new(string name="virtual_sequence_base");
super.new(name);
endfunction

//Assign pointers to the sub-sequencer in the base body method


task body();
if(!$cast (ram_v_sqrh, m_sequencer))
Note: fig 1.2 Green line indicate this connection
begin
`uvm_error (get_full_name(), "virtual sequence
Pointer cast failed");
end
wr_sqrh=ram_v_sqrh.ram_wr_seqrh;
rd_sqrh=ram_v_sqrh.ram_rd_seqrh;

Note : fig 1.2 Blue line indicate this connection


endtask
endclass
class random_virtual_seq extends virtual_sequence_base;
`uvm_object_utils(random_virtual_seq)

random_write_seq random_wseqh;
random_read_seq random_rseqh;

task body;
super.body;
rand_wseqh=random_write_seq::type_id::create
("rand_wsegh");
rand_rseqh=random_read_seq::type_id::create
("rand_rseqh");
repeat (20)
begin
random_wseqh.start(ram_wr_sqrh);
random_rsegh.start(ram_rd_sqrh);

Note :fig 1.2 black line indicate this connection


end
endtask
endclass
Environment
class ram_env extends uvm_env;

ram_write_agent write_agenth;
ram_read_agent read_agenth;
ram_virtual_sequencer ram_v_seqrh;

virtual function void build_phase(uvm_phase phase);


super.build_phase (phase);

//Build the subsequencers


Write_agenth=ram_write_agent::type_id::create
("write_agenth", this);
Read_agenth=ram_read_agent::type_id::create
("read_agenth",this);
//Build the virtual sequencer
ram_v_seqrh=ram_virtual_sequencer::type_id::
create ("ram_v_seqrh", this);
endfunction

//connect virtual sequencer to subsequencers.


function void connect_phase (uvm_phase phase);

ram_v_seqrh.wr_seqrh=write_agenth.seqrh;
ram_v_seqrh.rd_seqrh= read_agenth.seqrh;

Notes : fig 1.2 gray line indicate this connection

endfunction

endclass
TEST Case

class test_ram_virtual_seq extends uvm_test;

`uvm_component_utils(test_ram_virtual_seq)
//UVM automation and constructor
Function new(string name=“test_ram_virtual_seq”,
uvm_component parent);
super.new(name ,parent);
endfunction
//virtual sequence handle
random_virtual_seq virtual_test_seqh;
//environment handle
ram_env envh;
function void build_phase(uvm_phase phase);
super.build_phase(phase);
virtual_test_seqh=random_virtual_seq::type_id::
create("test_seqh");
envh=ram_env::type_id::create(“envh”,this);
endfunction
task run_phase (uvm_phase phase);
phase.raise_objection(phase, "start virtual
sequence");
//here virtual_test_seqh is driven by virtual
sequencer v_seqrh
virtual_test_segh.start(envh.v_seqrh);

Note :fig 1.2 orange line indicate the connection


phase.drop_objection (phase, "Done virtual
sequence");
endtask
endclass
NOTES
virtual_test_segh.start(envh.v_seqrh);

here using the virtual sequence and virtual sequencer the path
dependency can be avoided .

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