I/O Interface

The I/O devices can not communicate with the CPU directly. That’s why it needs some
connection point so that it can communicate with the CPU which is called the I/O
Interface.An I/O (Input/Output) interface is a mechanism that allows a computer or
other electronic system to communicate with external devices or peripherals. It serves
as a bridge between the system's internal components and external hardware, enabling
the transfer of data and commands.

There is a special need for additional hardware(Interface) to resolve the differences

between CPU and peripheral devices to supervise and synchronize all input and output
devices.

The major differences are as follows:

1.​ The nature of peripheral devices is electromagnetic and electro-mechanical.
The nature of the CPU is electronic. There is a lot of difference in the mode of
operation of both peripheral devices and CPU.
2.​ There is also a synchronization mechanism because the data transfer rate of
peripheral devices is slower than CPU.
 3.​ In peripheral devices, data code and formats differ from the format in the CPU
and memory.
4.​ The operating modes of peripheral devices are different and each may be
controlled so as not to disturb the operation of other peripheral devices
connected to the CPU.

I/O Mapping

I/O mapping refers to the method of organizing and accessing Input/Output (I/O)
devices within a computer system. It determines how the system's I/O operations are
translated into actions or data transfers between the CPU and peripheral devices. There
are mainly three types of I/O mapping: Separate buses, port-mapped I/O and
memory-mapped I/O.

Separate buses

The CPU uses separate data bus , address bus and control bus for Memory and
separate data bus , address bus and control bus for communicating with I/O devices.
But this technique makes the system very costly and big.
Port-mapped I/O or Isolated I/O

●​ The address and data bus are common but separate read and write control lines
are for memory and I/O
●​ Separate address space for I/O and memory

●​ separate read and write control lines are for memory and I/O
○​ IOR and IOW for I/O operations
○​ MEMR and MEMW for memory operations
●​ Special instruction ( IN & OUT ) is used for I/O operation
●​ MOV instruction is used for memory transfer
●​ Since it separates the I/O address from memory address that’s why it is called
isolated I/O

Advantage
 ➔​ Full memory space is available since I/O has separate space. So can store more
programs in the memory

Disadvantage

➔​ Need special instructions for I/O operation which makes it complex for
programming

Memory mapped I/O

●​ Address, data and control bus are common for I/O devices and memory
 ●​ uses the same address space for both memory and I/O devices

●​ I/O devices are assigned addresses within the system's memory space
●​ the same instructions used for memory operations are also used for I/O
●​ No special instruction such as IN and OUT is needed for I/O operation
●​ Uses only one set of read/write signals and does not distinguish between
memory and I/O

Advantage

➔​ Memory-mapped I/O uses standard memory access instructions (MOV, LOAD,

STORE), which simplifies programming. There's no need for special I/O
instructions, making code easier to write and understand.
➔​ Data can be transferred to and from I/O devices using the same mechanisms as
regular memory operations, which can be more efficient and faster.
➔​ I/O devices are mapped into the same address space as system memory. This
unified address space eliminates the need for separate address spaces for I/O
and memory, streamlining the design and implementation.

Disadvantage
 ➔​ The allocation and management of address space for both memory and I/O can
become complex, particularly in systems with large amounts of memory or
numerous I/O devices.
➔​ Careful management is needed to ensure that I/O device addresses do not
overlap with memory addresses used by the system.

Differences between memory mapped I/O and isolated I/O –

Isolated I/O Memory Mapped I/O

Memory and I/O have separate address

Both have same address space
space

Due to addition of I/O addressable

All address can be used by the memory
memory become less for memory

Separate instruction control read and Same instructions can control both I/O
write operation in I/O and Memory and Memory

In this I/O address are called ports. Normal memory address are for both
 More efficient due to separate buses Lesser efficient

Larger in size due to more buses Smaller in size

It is complex due to separate logic used Simpler logic is used as I/O is also
to control both. treated as memory only.

Modes of data transfer

We can transfer data between I/O devices and memory using three approaches

1.​ Programmed I/O

2.​ Interrupt driven I/O
3.​ DMA (Direct Access Memory)

Programmed I/O

Programmed I/O (Input/Output) is a method of data transfer between the CPU and
peripheral devices (like disk drives, printers, etc.) in computer systems. In Programmed
I/O, the CPU is actively involved in the transfer of data, which means it continually
checks the status of the I/O device and reads or writes data as needed.

Here’s a step-by-step explanation along with a simple diagram to illustrate how

Programmed I/O works:
 1.​ The I/O devices place information on the I/O bus and after placing the
information on the I/O bus, the corresponding I/O device enables the Data valid
line. This Data valid line specifies that some information is present on the I/O
bus.
2.​ There are mainly two types of registers in the interface. The first one is the Data
register and the second one is the Status register. In the Status register, we
maintain flag(F) bit. The value of the flag might be 1 or 0.
3.​ The information that is in the I/O bus, will be placed on the Data register. Once
the Data register contains some information, the flag bit will be set to 1 (F=1). So,
if the flag value is 1, it specifies that the data register has some information.
4.​ When the flag value is 1, the interface enables the data accepted line. Then the
information which is present on the data register will be sent to CPU with the help
of Data bus.
5.​ The CPU can access the I/O devices by specifying its address on the address
bus. Every I/O device contains a specific address.
6.​ Then the CPU reads the data with the I/O Read command line.
7.​ After the operation is done, the Data register is cleared, flag bit in Status register
is set to 0 and data accepted line is disabled.

Programmed I/O is a straightforward but potentially inefficient method of data transfer

because the CPU is heavily involved in managing I/O operations. It has to continuously
check the status of the I/O device and handle the data transfer directly.
Interrupt driven I/O

Interrupt-driven data transfer is a method used to improve the efficiency of data

transfer operations between the CPU and peripheral devices by using interrupts
to signal when data is ready to be processed.

●​ The CPU will ask for data from the specific I/O device through the address
bus
●​ That request will be received by the interface and will forward it to the
mentioned I/O device
●​ Based on this request, the specified I/O will give the data to the data
register through I/O bus.The CPU continues executing other tasks while
waiting for the transfer to complete
●​ When the data will be available on data register, the status register will be
set to 1
●​ When the flag bit of status register is 1, the interface will send a interrupt
request (INTR) to CPU
●​ Once the interrupt is received by the CPU, the CPU responds to the
interrupt by sending an interrupt Acknowledge(INTA) signal to the interface
●​ When the interface receives the INTA, it will place the data from the data
register on the data bus and the CPU will read it from the bus.

Follow the diagram for interrupt driven I/O that was explained in the classroom

DMA(Direct Memory Access)

DMA is a method that allows an I/O device to send or receive data directly to or
from the memory, bypassing the CPU to speed up the memory operation.The
steps are given below:

1.​ First, DMAC(Direct Memory Access Controller) sends a request by making

Bus Request(BR) line high.
 2.​ When a microprocessor receives high signal to HOLD pin, it first completes
the execution of current instruction and sends HLDA signal to the DMAC.
3.​ After receiving HLDA through Bus Grant(BG) pin of DMAC, the DMAC
takes control over system bus and transfers data directly between memory
and I/O device without involvement of CPU.
4.​ During DMA operation, the microprocessor is free to perform next job
which does not need system bus.
5.​ At the end of data transfer,the DMAC terminates the request by sending
low signal to HOLD pin and microprocessor regains the control of system
bus by making HLDA low.

Modes of DMA

Burst Mode: In this mode, buses are handed over to the CPU by the DMAC if the
whole data is transferred completely, not before that. It is the fastest mode.

Cycle Stealing Mode: In this mode, buses are handed over to the CPU by the DMAC
after the transfer of each byte. As a result of that, continuous request for the bus control
is generated by this mode.

Interleaving/ Transparent Mode: In this mode, DMAC gets the bus control only when
the CPU is executing the instruction which does not require the use of buses or CPU is
idle.It is the slowest mode.