Input output organization

• Peripheral Devices
– I/O Subsystem
• Provides an efficient mode of communication between the central system and the
outside environment
– Peripheral (or I/O Device)
• Input or Output devices attached to the computer
– Monitor (Visual Output Device) : CRT, LCD
– KBD (Input Device) : light pen, mouse, touch screen, joy stick, digitizer
– Printer (Hard Copy Device) : Dot matrix (impact), thermal, ink jet, laser (non-
impact)
– Storage Device : Magnetic tape, magnetic disk, optical disk
– ASCII (American Standard Code for Information Interchange) Alphanumeric Characters
• I/O communications are usually involved in the transfer of ASCII information
 Input-Output Interface
It provides a method for transferring information between internal storage and external
I/O devices. A communication link is used to resolve differences that exist between
the central computer and each peripheral.
• 1) A conversion of signal values may be required since peripherals are electro-
mechanical and electro-magnetic devices
• 2) A synchronization mechanism may be needed
– The data transfer rate of peripherals is usually slower than the transfer rate
of the CPU
• 3) Data codes and formats in peripherals differ from the word format in the CPU
and Memory
• 4) The operating modes of peripherals are different from each other
– Each peripherals must be controlled so as not to disturb the operation of
other peripherals connected to the CPU

To resolve these differences CPU

• Require special hardware components between the CPU and peripherals
• Supervise and Synchronize all input and output transfers

There are two types of interface -

CPU interface corresponds to the system bus
Input-Output interface depends on nature of input-output device
 Input-Output interface cont…
– I/O Bus and Interface Modules
I/ O bus
• I/O Bus Data
– Data lines Proc essor Address
– Address lines C ontrol
– Control lines
Processor places device address on address lines
to communicate with a device.
Each interface attached to the I/O bus contains a Interfac e Interfac e Interfac e Interfac e

address decoder to monitor address lines.

When interface detect its own address, it activates Keyboard
the path between bus lines and device that it and Magnetic Magnetic
Printer
controls. display disk tape
terminal
Processor provide function code on control lines.
The function code is referred as I/O command.
Input-Output interface cont…
• I/O command :
– Control Command
– Status Command
– Input Command
– Output Command

A control command is used to activate the peripheral and to inform it what to do.

A status command is used to test various status conditions in the interface and
peripheral.

In input command, the interface receives an item of the data from peripheral and
places it in its buffer register.

A output command causes the interface to respond by transferring data from the
bus into one of its registers.
 Input-Output interface cont…
– I/O Bus versus Memory Bus
• Computer buses can be used to communicate with memory and I/O
– 1) Use two separate buses, one for memory and the other for I/O
» I/O Processor
– 2) Use one common bus for both memory and I/O but have separate control
lines for each : Isolated I/O or I/O Mapped I/O
» IN, OUT : I/O Instruction
» MOV or LD : Memory read/write Instruction

* Control Lines
I/O Request, Mem Request, Read/Write
– 3) Use one common bus for memory and I/O with common control lines :
Memory Mapped I/O
» MOV or LD : I/O and Memory read/write Instruction

* Control Lines
Read/Write
 Input-Output interface cont…
- Isolated versus Memory-Mapped I/O

Many computers use one common bus to transfer information between memory or I/O
and CPU. The distinction between a memory transfer and I/O transfer is made
through separate read and write lines. The memory read and write control lines are
enabled during a memory transfer.

In isolated I/O configuration, CPU has distinct input and output instructions, and each of
these instructions is associated with address of an interface register. When the CPU
fetches and decode the opcode of an input and output instruction, it places the
address into the common address lines. At the same times, it enables I/O read (for
input) or I/O write (for output) control line. This informs the external components
that are attached to the common bus that the address in the address lines is for an
interface register and not for a memory word. On the other hand, when CPU fetching
an instruction or an operand from memory, it places the memory address on the
address lines and enables the memory read or write control line. This informs the
external components that the address is for a memory word and not for an interface.
This means that memory and I/O addresses has its own address space. The other
alternative is to use the same address space for both memory and I/O. For this only
one set of read and write signals is employ for both memory and I/O addresses. This
configuration is referred to as memory-mapped I/O.

In memory mapped I/O organization there are no specific input or output instructions.
The whole address space is reserved for interface registers. The CPU can
manipulate I/O data residing in interface registers with the same instructions that are
used to manipulate memory word. Each interface is organized as a set of registers
that respond to read and write requests in the normal address space.
 Modes of Transfer
Data transfer to and from peripherals may be handled in one of three possible modes -
1) Programmed I/O 2) Interrupt-initiated I/O 3) Direct Memory Access (DMA)

Programmed I/O operations are the result of I/O instructions written in the program. Each data item
transfer is initiated by an instruction in the program usually, is to and from a CPU register and
peripheral. Other instructions are needed to transfer to and from CPU and memory. Transferring
data under program control requires constant monitoring of peripheral by CPU. Once the data
transfer is initiated, CPU is required to monitor interface to see when a transfer can again be made.

In programmed I/O method, CPU stays in a program loop until I/O unit indicates that it is ready for data
transfer. This is time consuming process since it keeps the processor busy needlessly. It can be
avoided by using an interrupt facility and special commands to inform the interface to issue an
interrupt request signal when the data are available from the device. In the meantime CPU can
proceed to execute another program. The interface meanwhile keeps monitoring the device. When
the interface determine that the device is ready for the data transfer, it generate the interrupt
request to the computer. Upon detecting the external interrupt signal, the CPU momentarily stops
the task it is processing, branches to a service program to process the I/O transfer, and then
returns to the task it was originally performing.

In DMA, interface transfers data into and out of the memory unit through memory bus. The CPU initiates
the transfer by supplying the interface with the starting address and the number of words needed
to be transferred and then proceeds to execute other tasks. When the transfer is made, the DMA
requests memory cycles through the memory bus. When the request is granted by the memory
controller, DMA transfers the data directly into memory.
 Direct Memory Access (DMA)
The transfer of data between a fast storage device such as magnetic disk and memory is
often limited by the speed of CPU. Removing CPU from the path and letting the
peripheral device mange the memory buses directly would improve the speed of
transfer. This transfer technique is called DMA. During DMA transfer, the CPU is idle
and has no control of the memory buses.DMA controller takes over the buses to
manage the transfer directly between the I/O device and memory (Bus Request/Gran
t ).

The CPU may be placed in an idle state in a variety of ways. One common method
extensively used in microprocessor is to disable the buses through special control
signals. Figure shows two control signals in CPU that facilitate DMA transfer. The bus
request (BR) input is used by DMA controller to request the CPU to give-up
unwillingly control of the buses. When this input is active, the CPU terminates the
execution of the current instruction and places the address bus, data bus and read,
write lines into a high-impedance state. The CPU activates the bus grant (BG) output
to inform the external DMA that the buses are in the high-impedance state. When the
DMA terminates the transfer, it disables the BR line. The CPU disables the BG, takes
control of the buses and returns to its normal operation.

DBUS Address bus

BR BR High- impedanc e
Bus request ABUS Data bus
DMA (disable)
C PU when BG is
C ontroller
RD Read enabled
BG BG
Bus grant WR Write
 Direct Memory Access (DMA) cont..
When the DMA takes control of the bus system, it communicates directly with the
memory. The transfer can be made in several ways. In DMA burst transfer, a
block sequence consisting of a number of memory words is transferred in a
continuous burst while the DMA controller is master of the memory buses. This
mode of transfer is needed for fast devices such as magnetic disks, where data
transmission can not be stopped or slowed down until an entire block is
transferred. An alternate technique called cycle stealing allows the DMA
controller to transfer one data word at a time, after which it must return control
of the buses to the CPU. The CPU merely delays its operation for one memory
cycle to allow the direct memory I/O transfer to steal one memory cycle.
 DMA Controller
It needs the usual circuits of an interface to Address bus
communicate with the CPU and I/O device. In
addition, it needs an address register, a word
count register and a set of address lines. The
Data bus Address bus
address register and address lines are used for Data bus buffers
buffers
direct communication with the memory. The
word count register specifies the number of
words that must be transferred. The data
transfer must be done directly between the Address register

Internal bus
DMA select CS
device and memory under control of DMA.
Register select RS
Read RD Word count register
The registers are selected by CPU through address
bus by enabling CS and RS inputs. The RD and Write WR
C ontrol
WR inputs are bidirectional. When BG=0, CPU Bus request BR logic C ontrol register
communicates with DMA registers through data Bus grant BG
bus to read from or write to DMA registers. DMA request
Interrupt Interrupt
When BG=1, CPU give up buses and DMA can to I/ O device
communicate directly with the memory by DMA Acknowledge
specifying an address in the address bus and
activating RD or WR control. DMA
communicates with external peripheral through
the request and acknowledge lines.
 DMA Controller cont..
DMA controller has three registers : an address register, a word count register and a control register.
The address register contains an address to specify the desired location in memory. The address bits
go through bus buffers into the address bus. The address register is incremented after each word
that is transferred to memory.
The word count register holds the number of words to be transferred. This register is decremented
after each word transfer.
The control register specifies the mode of transfer.

All registers in DMA appear to the CPU as I/O interface registers. Thus CPU can read from or write
into DMA registers under program control via the data bus.

DMA is first initialized by CPU. After that, DMA starts and continue to transfer data between memory
and peripheral until an entire block is transfer. CPU initializes the DMA by sending the following
information through the data bus :-
1. Starting address of memory block where data are available (for read) or to be stored (for write).
2. The word count, which is the number of words in the memory block.
3. Control to specify mode of transfer such as read or write.
4. A control to start the DMA transfer.

The starting address is stored in address register. The word count is stored in word count register
and the control information in control register. Once the DMA is initialized, the CPU stops
communicating with DMA unless it receives an interrupt signal or if it wants to check how many
words have been transferred.
 DMA Transfer
– DMA Transfer (I/O to Memory)
• 1) I/O Device sends a DMA request
• 2) DMAC activates the BR line
• 3) CPU responds with BG line
• 4) DMAC sends a DMA
acknowledge to the I/O device
• 5) I/O device puts a word in the
data bus (for memory write)
• 6) DMAC write a data to the
address specified by Address
register
• 7) Decrement Word count register
• 8) Word count register = 0
EOT interrupt CPU
• 9) Word count register  0
DMAC checks the DMA request
from I/O device
 Input-Output Processor (IOP)
The IOP is similar to a CPU except that it is designed to handle the details of I/O
processing. Unlike DMAC that must be set up entirely by CPU, IOP can fetch and
execute its own instructions. IOP instructions are specifically designed to facilitate
I/O transfers. In addition, IOP can perform other processing tasks, such as arithmetic,
logic, branching and code translation.
• Communicate directly with all I/O devices
• Fetch and execute its own instruction
– IOP instructions are specifically designed to facilitate I/O transfer
– DMAC must be set up entirely by the CPU
• Designed to handle the details of I/O processing
The block diagram of a computer with two processors is shown in figure. The
memory unit occupies a central position and can communicate with each
processor by means of DMA. CPU is responsible for processing data needed in
the solution of computational tasks. IOP provides a path for transfer of data
between peripheral devices and memory unit. CPU is usually assigned the task
of initiating the I/O program. From then on the IOP operates independent of CPU
and continue to transfer data from external devices and memory.
Memory bus

C entral P ro c es s ing
unit (C P U )

P eripheral devic es
Mem o ry unit PD PD PD PD

Input- o utput
pro c es s o r (IO P ) I/ O bus

• Instruction that are read form memory by an IOP are called commands
– Distinguish from instructions that are read by the CPU
– Commands are prepared by experienced programmers and are stored in
memory
– Command word = IOP program
– CPU informs IOP where to find commands in memory and when it is
 CPU-IOP Communication
Memory units acts as a message center : Information
each processor leaves information for the other

C PU operations IO P operations

Send instruc tion

Transfer status word
to test IO P path
to memory loc ation

If status O K. , send
Message Center
start I/ O instruc tion Ac c ess memory for
to IO P IO P program

C onduc t I/ O transfer
C PU c ontinues with
another program
using DMA ; prepare
IOP Program
CPU Program
status report

I/ O transfer c ompleted
interrupt C PU

Request IO P status

Transfer status word

to memory loc ation

C hec k status word

for c orrec t transfer

C ontinue
 IBM 370 I/O Channel
• Channel = I/O Processor in IBM 370 computer
• Three types of channel
– 1) Multiplexer channel : slow-medium speed device, operating with a number of I/O
devices simultaneously
– 2) Selector channel : high-speed device, one I/O operation at a time
– 3) Block-Multiplexer channel : 1) + 2)
• I/O instruction format : Fig. (a)
– Operation code :
» Start I/O, Start I/O fast release (less CPU time),
Test I/O, Clear I/O, Halt I/O, Halt device,
Test channel, Store channel ID O peration C hannel Devic e
c ode address address
• Channel Status Word : Fig. (b)
– Always stored in Address 64 in memory (a) I/ O instruc tion format

– Key : Protection used to prevent unauthorized

access Key Address Status C ount
– Address : Last channel command word address
(b) C hannel status word format
used by channel
– Count : 0 (if successful transfer)
C ommand
Data address Flags C ount
c ode

(c ) C hannel c ommand word format

 • Channel Status Word : Fig. (c)
– Always stored in Address 72 in
memory
– Command Code
» Write : transfer data from
memory to I/O device Memory unit
» Read : transfer data I/O
device to memory
» Read backwards : read C hannel status word 64
magnetic tape with tape
moving backward Fig. (b) 
» Control : rewinding of tape, C hannel address word 72
positioning a disk-access 
mechanism (HDD head xxxx
control)
xxxx C hannel c ommand word 1
» Sense : inform the channel C hannel c ommand word 2 I/ O c hannel
program
status word to the address
64 (Status Read)
Fig. (a)  C hannel c ommand word 3

» Transfer in channel :
channel jump command
(Channel change)
• Location of information in the IBM 370 : C PU
Start I/ O instruc tion
 Address 72 I/O channel program Fig. (c)  program

Address (xxxx)
 CPU Start I/O
 I/O channel program
 Address 64
 C ontrol block Parameter block Task block

8086
C PU Busy CCW TB address

8089
PB address Memory address
IOP
attention
Interrupt

Channel
Select

B us System program
C ontroller bus
Memory unit Byte count

Device address

8089 Loc al bus Track and sector

IO P

Status
Interfac e Interfac e

Input devic e O utput devic e

 Location of Information :
 Channel Command Word (CCW)
Intel 8089 IOP : : message center
 CPU enables channel attention » Start command
 Select one of two channels of 8089 » Suspend command
 8089 gets attention of the CPU by » Resume command
sending an interrupt request » Halt command
 Serial Communication
– Difference between I/O Processor and Data Communication Processor
• I/O Processor
– communicate with peripherals through a common I/O bus (data, address,
control bus)
• Data Communication Processor
– communicate with each terminal through a single pair of wires
– Modem ( = Data Sets, Acoustic Couplers )
• Convert digital signals into audio tones to be transmitted over telephone lines
• Various modulation schemes are used (FM, AM, PCM)
– Block transfer
• An entire block of characters is transmitted in synchronous transmission
• Transmitter sends one more character (error check) after the entire block is sent
– Error Check
• LRC (Longitudinal Redundancy Check) : XOR
• CRC (Cyclic Redundancy Check) : Polynomial
– 3 Transmission System
• Simplex : one direction only
• Half-duplex : both directions but only one direction at a time
• Full-duplex : both directions simultaneously
– Data Link
• The communication lines, modems, and other equipment used in the
transmission of information between two or more stations
– Data Link Protocol
• 1) Character-Oriented Protocol
• 2) Bit-Oriented Protocol
 Character-Oriented Protocol
• Message format for Character-Oriented Protocol :

SYN SYN SO H Header STX Text E TX BC C

– TEXT :
– BCC : Block Check Character (LRC or CRC)
• ASCII Communication Control Character :
– SYN (0010110) : Establishes synchronism
– SOH (0000001) : Start of Header (address or control information)
– STX (0000010) : Start of Text
– ETX (0000011) : End of Text
 Bit-Oriented Protocol
• Transmit a serial bit stream (Frame) of any length without character boundaries
• Examples of bit-oriented protocol
– 1) SDLC (Synchronous Data Link Control) : IBM
– 2) HDLC (High-level Data Link Control) : ISO
– 3) ADCCP (Advanced Data Communication Control Procedure) : ANSI
• Frame format for bit-oriented protocol :
Flag Address C ontrol Information Frame c hec k Flag
01111110 8 bits 8 bits any number of bits 16 bits 01111110

• Zero Insertion
– Prevent a flag from occurring in the middle of a data frame
– Zero (0) is inserted by transmitting station after any succession of five
continuous 1’s
» Example of zero insertion : 01111110 (data) 011111010
– Receiver always removes a 0 that follows a succession of five 1’s
• Control field format :
1 2 3 4 5 6 7 8
In fo rm a tio n tra n s fe r : 0 NS P/ F Nr

S up e rvis o ry : 1 0 C o de P/ F Nr

U n um b e re d : 1 1 C o de P/ F C o de

NS S e n d c o un t P/ F P o ll/ fin a l

Nr R e c e ive c o un t C o de B in a ry c o d e
 – 1) Information Transfer : for ordinary data transmission
– 2) Supervisory : for ready, busy condition check, ...
– 3) Unnumbered : for initialization of link functions, reporting errors, ...
• Control Fields
– Ns : send frame count
– Nr : error free receive frame count
– P/F :
» P = 1 : primary station is finished and ready for the secondary station
to respond
P = 0 : each frame sent to the secondary station from the primary
station
» F = 1 : secondary station sends the last frame
F = 0 : secondary station responds with a number of frame (when
primary station is finished)
– Code : type of command/response