電磁平方實驗室

甘堯江 (Yao-Chiang Kan)

Department of Electrical Engineering Group B

yckan@saturn.yzu.edu.tw
 Outlines
Iterative Systems
Binary Decoders
Encoders and Priority Encoders
Multiplexers and Demultiplexers
Three-State Gate
Gate Arrays – ROMS, PLAS, and PALs
Testing and Simulation of Combinational
Systems
Larger Examples
2
 Large systems are usually designed by breaking them up
into smaller subsystems.
Systems that consist of a number of identical blocks. ( Iterative
systems.)
 Adders and other arithmetic functions are examples of this type of system.
 Delay issues
 Because signals in large systems pass through many layers of logic, the
small delay encountered as a signal passes through a single gate adds up.
 Common Types of Circuit
the binary decoder and encoder, and the multiplexer.
 Gate arrays, sometimes referred to as programmable logic
devices (PLDs)
 The issues of testing and simulation of combinational
circuits.
 Decimal Adder and a driver for a seven-segment display.

3
ITERATIVE SYSTEMS

4 4
Adders as an example of a system that can be
implemented with multiple copies of a smaller
circuit.
Use the adder to illustrate the issue of delay in
multiple-level circuits and then discuss other iterative
circuits.
One-bit full adder
 When we add two numbers by hand, we add the two least significant
digits (plus possibly a carry-in) to produce one bit of the sum and a
carry to the next bit.
 Such a (referred to as a full adder) is defined as CE3 and was designed
with NAND gates in Example 2.34 (Section 2.8).

5
An n-bit adder, we need only connect n of these.
 A 4-bit version is shown in Figure 5.1.

6
 Half Adder
1 The circuit needs two binary inputs and two binary outputs.
2 The true table 3 The simplified sum-of-products
𝑆 = 𝑥 𝑦 + 𝑥𝑦′
𝐶 = 𝑥𝑦

7
 Full Adder
1 The circuit forms the arithmetic sum of three bits.
 Two of the input variables represent the two significant bits to be
added.
 The third input represents the carry from the previous lower
significant position.

2 The true table

3 The simplified sum-of-products

8
4

9
 Full Adder using XOR

𝐶 = 𝑥𝑦 𝑧 + 𝑥 𝑦𝑧 + 𝑥𝑦 = 𝑧 𝑥𝑦 + 𝑥 𝑦 + 𝑥𝑦 = 𝑧 𝑥 ⊕ 𝑦 + 𝑥𝑦

half adder
half adder

10
Full Adder using NAND

11
 Delay in Combinational Logic Circuits
When the input to a gate changes, the output of that
gate does not change instantaneously, but there is a
small delay, Δ.
If the output of one gate is used as the input to
another, the delays add. 0 1
1 1
0

1 1
Finally, at time 5, both B and C change simultaneously. 0 0
The output F goes to 0 briefly when the change in C is
recognized (Δ after the change in C), and then F returns
to 1 when the change in B is propagated (2Δ after the
change in B).
This situation is known as a hazard or a glitch.

Timing Diagram
12
 Delay of Full Adder
Assume that all inputs are available at the same time

 The delay from the time inputs a or b change to the time that the sum is available is
6Δ and to the time that the carry-out is available is 5 Δ.
 If a and b are established,* the delay from the carry-in to the carry-out is only 2Δ
and , the delay from carry-in to sum is 3Δ.

13
 Delay of a n-bit Adder

The total time required is calculated as

 the delay from the inputs to cout (for the least significant bit, LSB) plus
 (n-2) times the delay from cin to cout (for the middle full adders), plus
 the longer of the delay from cin to cout or from cin to s (for the most significant
bit, MSB).
 For the multilevel adder, that equals 5Δ+ (n-2)×2Δ+3Δ= (2n+4)Δ.
 For a 64-bit adder, the delay would be 132Δ.

14
Adders
The previous approach to building an n-bit adder is to
connect together n 1-bit adders.
This is referred to as a carryr-ipple adder.
The time for the output of the adder to become stable may
be as large as (2n+4)Δ.
Speed-up approach I is to implement a multibit
adder with an SOP expression
After all, an n-bit adder (with a carry-in to the least
significant bit) is just a 2n+1 variable problem.
Speed-up approach II is the carry-look-ahead adder.
(Skipped)

15
 A 2-bit adder
Step 2. Bit 1 is the low order bit

𝑐
𝑎 𝑎
+ 𝑏 𝑏
𝑐 𝑠 𝑠

Step 1.
Five inputs and three outputs

16
 Step 3. Cout

𝑎 𝑏 𝑎

𝑎 𝑏 𝑏

𝑎 𝑏 𝑐

𝑎 𝑏 𝑐 𝑏 𝑏 𝑐
𝑎 𝑎 𝑐 𝑎 𝑏

17
s2

18
s1

19
Step 4. Implementation

The equations are very complex, requiring 23 terms

with 80 literals.
A two-level solution would require a 12-input gate for s1.
The multilevel solutions with fewer large gates can
be obtained using algebra, but that would increase
the delay.
There is a limitation on the number of inputs (called
fan-in) for a gate.
Gates with 12 inputs may not be practical or may
encounter delays of greater than Δ.

20
For the 2-bit adder, cout can be a2
b2

implemented with two-level logic a1

(with a maximum fan-in of seven).

b1
a2

Thus, the delay from carry-in to

a1
b1
b2

carry-out of every two bits is only cin

b1 cout
2Δ b2

For a n-bit adder cascaded by the 2- cin

b1
a2
bit adder, the total delay (other
than the first and the last 2-bit) is
cin
a1
b2

2Δ+(n/2-2)×2Δ+3Δ= (n+1)Δ cin

a1
about half that of the previous a2

solution.
21
 4-bit Adders
Commercially available 4-bit adders: the 7483,
7483A, and 74283.
Each is implemented differently, with a three-level circuit
for the carry-out.
The 7483A and 74283 differ only in pin connections;
produces the sum with a four-level circuit, using a
mixture of NAND, NOR, AND, NOT, and Exclusive-OR
gates.
Thus, the delay from carry-in to carry-out is 3Δ for each
four bits, producing a total delay of (3/4n+1)Δ (an extra
delay for the last sum)
The 7483 ripples the carry internally (although it has a
three-level chip carry out); it uses an eight-level circuit
for s4
22
When larger adders are needed, these 4-bit adders can
be cascaded.

23
Subtractors and Adder/Subtractors
A 1-bit full subtractor can be designed using the
general design procedure.
For n-bit subtractor, n 1-bit subtractors are
cascaded. (borrow-ripple subtractor)
Design a full subtractor, that is, a circuit that computes a-b-c,
where c is the borrow from the next less significant digit and
produces a difference, d, and a borrow from the next more
significant bit, p.

Step 1. Step 2.
Three inputs and two outputs

24
 Step 3.
𝑝 = 𝑎𝑏𝑐 + 𝑎 𝑏𝑐 + 𝑎 𝑏𝑐 + 𝑎 𝑏 𝑐 = 𝑏𝑐 + 𝑎 𝑏⨁𝑐
= 𝑐 𝑎𝑏 + 𝑎 𝑏′ + 𝑎 𝑏
= 𝑐 𝑎⨁𝑏 + 𝑎′𝑏
𝑑 = 𝑎 𝑏 𝑐 + 𝑎 𝑏𝑐 + 𝑎𝑏 𝑐 + 𝑎𝑏𝑐 = 𝑎⨁𝑏⨁𝑐
Step 4.

The delay from

borrow in to borrow
out is 5Δ
The timing would be the same as for the adder, except that the first
borrow out delay would now be 6Δ (an increase of 1).
25
 An adder/subtractor
𝐴+𝐵 =𝐴+𝐵
𝐴 − 𝐵 = 𝐴 + −𝐵 2’complement of B
1⨁𝑥 = 𝑥 𝑎𝑛𝑑 0⨁𝑥 = 𝑥
𝑎 ⁄𝑠 = 0

𝑎 𝑎 𝑎 𝑎
+ 𝑏 𝑏 𝑏 𝑏
𝑐 𝑠 𝑠 𝑠 𝑠

𝑎 ⁄𝑠 = 1 ⇒ 𝑐 =1
1
𝑎 𝑎 𝑎 𝑎
+ 𝑏 𝑏 𝑏 𝑏
4-bit adder 𝑐 𝑠 𝑠 𝑠 𝑠

26
Comparators
Compare two numbers, producing an indication if
they are equal or if one is larger than the other.
1-bit Comparator

2 Inputs and three outputs a b

a b a=b a<b a>b

0 0 1 0 0 =
0 1 0 1 0
1 0 0 0 1 >
1 1 1 0 0

𝑓 = 𝑎 𝑏 + 𝑎𝑏 = 𝑓 +𝑓 ′ <
𝑓 = 𝑎𝑏′
𝑓 = 𝑎′𝑏

27
 4-bit Comparator
Eight inputs and three outputs : General Design?
Equality
 Exclusive-OR produces a 1 if the two inputs are
unequal and a 0, otherwise.
 Multibit numbers are unequal if any of the input pairs
are unequal.

The output of the NOR or AND is 1 if the numbers are equal

28
Greater or less than
𝑎>𝑏
if 𝑎 > 𝑏 𝑀𝑆𝐵 𝒐𝒓 𝑎 = 𝑏 𝑎𝑛𝑑 𝑎 > 𝑏
𝒐𝒓 𝑎 = 𝑏 𝑎𝑛𝑑 𝑎 = 𝑏 𝑎𝑛𝑑 𝑎 > 𝑏
𝒐𝒓 𝑎 = 𝑏 𝑎𝑛𝑑 𝑎 = 𝑏 𝑎𝑛𝑑 𝑎 = 𝑏 𝑎𝑛𝑑 𝑎 > 𝑏
𝑎<𝑏
if 𝑎 < 𝑏 𝑀𝑆𝐵 𝒐𝒓 𝑎 = 𝑏 𝑎𝑛𝑑 𝑎 < 𝑏
𝒐𝒓 𝑎 = 𝑏 𝑎𝑛𝑑 𝑎 = 𝑏 𝑎𝑛𝑑 𝑎 < 𝑏
𝒐𝒓 𝑎 = 𝑏 𝑎𝑛𝑑 𝑎 = 𝑏 𝑎𝑛𝑑 𝑎 = 𝑏 𝑎𝑛𝑑 𝑎 < 𝑏

𝑥 =𝑎 𝑏 +𝑎 𝑏 𝑓𝑜𝑟 𝑖 = 1,2,3, 4
1, 𝑎 𝑎𝑛𝑑 𝑏 𝑎𝑟𝑒 𝑒𝑞𝑢𝑎𝑙
𝑎=𝑏 =𝑥 𝑥 𝑥 𝑥 =
0, 𝑜𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒
1
𝑎 >𝑏 =𝑎 𝑏 +𝑥 𝑎 𝑏 +𝑥 𝑥 𝑎 𝑏 +𝑥 𝑥 𝑥 𝑎 𝑏 =
0
1
𝑎 < 𝑏 = 𝑎 𝑏 +𝑥 𝑎 𝑏 + 𝑥 𝑥 𝑎 𝑏 + 𝑥 𝑥 𝑥 𝑎 𝑏 =
0

29
30
BINARY DECODERS

31 31
A binary decoder is a device that, when activated,
selects one of several output lines, based on a
coded input signal.
Most commonly, the input is an n-bit binary number,
and there are up to 2n output lines.*
Some decoders have an enable signal that activates it

32
 2×4 Decoder

𝑓 = 𝑎 𝑏 ⇒ 𝑓 = 𝑎′𝑏′ ′
𝑓 = 𝑎 𝑏′ 𝑓 = 𝑎 𝑏
𝑓 =𝑎𝑏⇒𝑓 = 𝑎𝑏 ′
𝑓 = 𝑎𝑏′ 𝑓 = 𝑎𝑏
𝑓 = 𝑎𝑏′ ⇒ 𝑓 = 𝑎𝑏′ ′
𝑓 = 𝑎𝑏 ⇒ 𝑓 = 𝑎𝑏 ′

33
 With Enable Input
0 0 All outputs are 0 This decoder has active high
0 1 output with a single active low
1 0 enable input or pin.
1 1

2 =8

34
Decoder with Active-Low Enable Input Decoder with Active-High Enable Input

Complement Output UnComplement Output

M0
D0 m4

A
M1
D1 m5
B

M2
D2 m6

D3 m7
M3
E

35
35
Decoder with Active-Low Enable Input Decoder with Active-High Enable Input

UnComplement Output Complement Output

m0 M4

m1 M5

m2 M6

m3 M7

D0
A 21 D1
B 20 D2
D3
36
36 E
 74138 (3×8) decoder
74154  4×16 decoder
74155  Dual 2×4 decoders

𝑀𝑆𝐵
𝑌0 = 𝐸𝑁1𝐸𝑁2 𝐸𝑛3 𝐶 𝐵 𝐴
⇒ 𝑌0 = 𝐸𝑁1𝐸𝑁2 𝐸𝑛3 𝐶 𝐵 𝐴 ′
One active high
(EN1) and the other
two are active low

37
 We have available 74138
decoders and wish to select
one of 32 devices.

38