Hacettepe University

ELE 225 Fundamentals of Digital

Systems

Chapter 4:
Combinational Logic

Assoc. Prof. S. Esen Yüksel

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 Slide Credits
 We would like to thank Prof. Chih-Peng
Fan
from National Cheng Kung University
for making his slides available.
 Most of the slides are modified from
Prof. Chih-Peng Fan’s lecture notes.

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Topics

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 Previously on ELE 225
We learned how to
Derive the Karnaugh map of a Boolean function.
Derive the prime implicants of a Boolean function.

Obtain the minimal SOP and the POS forms of a Boolean

function by simplifying directly from its K-map.

Use don’t care conditions to simplify a K-map.

Obtain two-level (multi-level) NAND/NOR and other two-

level implementations of a Boolean function.

Obtain multi-level implementations of a Boolean function.

Use XOR/XNOR functions in design of digital systems.

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 Chapter 4 Objectives
 Know how to analyze a combinational circuit
from its logic diagram.
 Understand the half adder, full-adder, binary
adder-subtractor, carry lookahead adder, BCD
adder, binary multiplier, magnitude comparator.
 Understand decoders, encoders, priority
encoders, multiplexers, demultiplexers and
three-state gates.
 Know how to implement a Boolean function with
a decoder and additional gates.
 Know how to implement a Boolean function with
a multiplexer.
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 4-2. Combinational Circuits
 Logic circuits for digital systems may be
combinational or sequential.
 A combinational circuit consists of input
variables, logic gates, and output variables.

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 4-3. Analysis procedure
 To obtain the output Boolean functions from a
logic diagram, proceed as follows:
1. Label all gate outputs that are a function of input
variables with arbitrary symbols. Determine the functions
for each gate output.
2. Label the gates that are a function of input variables and
previously labeled gates with other arbitrary symbols. Find
the functions for these gates.
3. Repeat step 2 until the outputs of the circuit are obtained.
4. By repeated substitution of previously defined functions,
obtain the output functions in terms of input variables.

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 Example
F2 = AB + AC + BC; T1 = A + B + C; T2 = ABC; T3 = F2’T1;
F1 = T3 + T2 = F2’T1 + ABC = A’BC’ + A’B’C + AB’C’ + ABC

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 Truth table from logic
diagram
 We can derive the truth table in Table 4-1 by
using the circuit of Fig.4-2.

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 4-4. Design procedure
1. Table 4-2 is a Code-Conversion example,
first, we can list the relation of the BCD and
Excess-3 codes in the truth table.

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 Karnaugh map
2. For each symbol of the Excess-3 code, we use 1’s
to draw the map for simplifying Boolean function.

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 Circuit implementation
z = D’; y = CD + C’D’ = CD + (C + D)’
x = B’C + B’D + BC’D’ = B’(C + D) + B(C + D)’
w = A + BC + BD = A + B(C + D)

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 4-5. Binary Adder-
Subtractor
 A combinational circuit that performs the addition of
two bits is called a half adder.
 The truth table for the half adder is listed below:

S: Sum
C: Carry

S = x’y + xy’
C = xy

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Implementation of Half-
Adder

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 Full-Adder
 One that performs the addition of three bits(two
significant bits and a previous carry) is a full adder.

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Simplified Expressions

S = x’y’z + x’yz’ + xy’z’ + xyz

C = xy + xz + yz
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Full adder implemented in
SOP

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 Another implementation
 Full-adder can also be implemented with two
half adders and one OR gate.
S = z ⊕ (x ⊕ y)
= z’(xy’ + x’y) + z(xy’ + x’y)’
= z’(xy’ + x’y) + z(xy + x’y’)
= xy’z’ + x’yz’ + xyz + x’y’z
C = z(xy’ + x’y) + xy = xy’z + x’yz + xy

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 Binary adder
 This is also called
Ripple Carry
Adder, because of
the construction
with full adders are
connected in
cascade.

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 Carry Propagation
 Fig.4-9 causes an unstable factor on carry bit, and
produces a longest propagation delay.
 The signal from Ci to the output carry Ci+1,
propagates through an AND and OR gates, so, for an
n-bit RCA, there are 2n gate levels for the carry to
propagate from input to output.

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 Carry Propagation
 Because the propagation delay will affect the output
signals on different time, so the signals are given enough
time to get the precise and stable outputs.
 The most widely used technique employs the principle of
carry look-ahead to improve the speed of the
algorithm.

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 Boolean functions
Pi = Ai ⊕ Bi steady state value
Gi = AiBi steady state value
Output sum and carry
S i = Pi ⊕ C i
Ci+1 = Gi + PiCi
Gi : carry generate Pi : carry propagate
C0 = input carry
C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0

 C3 does not have to wait for C2 and C1 to

propagate.
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 Logic diagram of
carry look-ahead generator
 C3 is propagated at the same time as C 2 and C1.

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 4-bit adder with carry
lookahead
 Delay time of n-bit CLA = XOR + (AND + OR) + XOR

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 Binary subtractor
M = 1  subtractor ; M = 0  adder
Mode input

This part is for

overflow

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 Binary subtractor
 Remember: A-B = 1’s comp (B) + 1 + A
 1’s complement can be implemented with
inverters  B ⊕ 1 = B’
 When M=0, circuit becomes an adder
 B⊕0=B
 Input carry C0 =0
 When M=1, circuit becomes a subtractor
 B ⊕ 1 = B’
 Input carry C0 =1
 B’+1+A = A - B
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 Binary subtractor Remember:
A-B = 1’s comp (B) + 1 + A

B ⊕ 1 = B’
M = 1  subtractor ; M = 0  adder

This part is for

overflow

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 Overflow
carry Sig
Sign bit n
bit

 1st example: The 8 bit result has a –ve

sign bit. WRONG! Carry became 0.
Problem: n+1 bits cannot be
accompanied by an n-bit word. The result
did not fit in.
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 Overflow

 2nd example: In the 8 bits that we have, it

is as if the result is +ve. WRONG! Carry
became 1.
 We may not be able to correct this, but we
can detect it and set a bit to indicate
overflow.
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 Overflow
 In the binary subtractor figure
 Observe C3 (carry bit into sign bit
position) and C4 (carry bit out of the
sign bit position)
 If C3 notequal C4  overflow occurred
 ie. C3 xor C4 = V = 1  overflow
occurred

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 Overflow
 It is worth noting Fig.4-13 that binary numbers in the
signed-complement system are added and subtracted
by the same basic addition and subtraction rules as
unsigned numbers.
 Overflow is a problem in digital computers because the
number of bits that hold the number is finite and a result
that contains n+1 bits cannot be accommodated.

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 Overflow on signed and
unsigned
 When two unsigned numbers are added, an overflow
is detected from the end carry out of the MSB
position.
 When two signed numbers are added, the sign bit is
treated as part of the number and the end carry
does not indicate an overflow.
 An overflow cannot occur after an addition if one
number is positive and the other is negative.
 An overflow may occur if the two numbers added are
both positive or both negative.
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 4-6 Decimal adder
BCD adder can’t exceed 9 on each input digit. K is the carry.

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 Rules of BCD adder
 When the binary sum is greater than 1001, we
obtain an invalid BCD representation.
 The addition of binary 6(0110) to the binary sum
converts it to the correct BCD representation and
also produces an output carry as required.
 To distinguish them from binary 1000 and 1001,
which also have a 1 in position Z8, we specify further
that either Z4 or Z2 must have a 1.
C = K + Z8Z4 + Z8Z2

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 Implementation of BCD
adder
 A decimal parallel
adder that adds n
decimal digits
needs n BCD
adder stages.
 The output carry If =1

from one stage

must be
0110
connected to the
input carry of the
next higher-order
stage. 35
 4-7. Binary multiplier
 Usually there are more bits in the partial products and it is necessary
to use full adders to produce the sum of the partial products.

And

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 4-bit by 3-bit binary
multiplier
 For J multiplier bits
and K multiplicand
bits we need (J x K)
AND gates and (J−1)
K-bit adders to
produce a product of
J+K bits.
 K=4 and J=3, we
need 12 AND gates
and two 4-bit adders.

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 4-8. Magnitude
comparator
 The equality relation of
each pair of bits can be
expressed logically with an
exclusive-NOR function as:

A = A 3 A2 A1 A 0
B = B 3B 2B 1B 0

xi=Ai Bi + Ai’ Bi’ for i =

0,1,2,3

(A=B) = x3x2x1x0

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4-8. Magnitude
comparator

A B | A>B
00 | 0
01 | 0
10 | 1
11 | 0
A’B

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 Magnitude comparator
 We inspect the relative
magnitudes of pairs of MSB. If
equal, we compare the next
lower significant pair of digits
until a pair of unequal digits is
reached.
 If the corresponding digit of A is
1 and that of B is 0, we
conclude that A>B.
(A>B)=
A3B’3+x3A2B’2+x3x2A1B’1+x3x2x1A0B’
0

(A<B)=
A’3B3+x3A’2B2+x3x2A’1B1+x3x2x1A’0B
0
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 4-9. Decoders
 A decoder is a combinational circuit that
converts binary info from n input lines to a
maximum of 2n unique output lines.

If the n -bit coded information has unused
combinations, the decoder may have less than 2n
outputs.

The decoder is called n-to-m-line decoder, where m
≤ 2n.

Decoders generate the 2n (or fewer) minterms of n
input variables.

The decoder is also used in conjunction with other
code converters such as a BCD-to-seven-segment
decoder.
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 Implementation and truth
table
3-to-8 line decoder: For each possible input combination,
there are eight outputs that are equal to 0 and only one that
is equal to 1.

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 Decoder with enable input
 Some decoders are constructed with NAND gates, it
becomes more economical to generate the decoder
minterms in their complemented form.
 As indicated by the truth table , only one output can be
equal to 0 at any given time, all other outputs are equal to
1.

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 Demultiplexer
 A demultiplexer is a circuit that receives info from
a single line and directs it to one of 2n possible
output lines.

A decoder with enable is called decoder/demultiplexer.

The truth table of demultiplexer is the same with decoder.

A B

D0
D1
E
Demultiplexer D2
D3
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implement the 4-to-16
decoder

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 Implementation of a Full
Adder with a Decoder
 From table 4-4, we obtain the functions for the
combinational circuit in sum of minterms:
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)

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 BCD-to-seven-segment
decoder
 A BCD-to-seven-segment decoder (converter) is
a combinational circuit that converts a decimal digit
in BCD to an appropriate code for the selection of
segments in an indicator used to display the decimal
digit.

The seven outputs of the decoder (a, b, c, d, e, f, g) select the
corresponding segments in the display.

Each digit of the display is formed from seven LED segments.

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 BCD-to-seven-segment
decoder
 Using a truth table and Karnaugh maps, we can design the BCD-
to-seven-segment decoder using a minimum number of gates.
The six invalid combinations should result in a blank display.

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 BCD-to-seven-segment
decoder
 Using a truth table and Karnaugh maps, we can design the BCD-
to-seven-segment decoder using a minimum number of gates.
The six invalid combinations should result in a blank display.

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 BCD-to-seven-segment
decoder
 Using a truth table and Karnaugh maps, we can design the BCD-
to-seven-segment decoder using a minimum number of gates.
The six invalid combinations should result in a blank display.

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 4-10. Encoders
 An encoder has 2n (or fewer) input lines and n output lines.
 An encoder is the inverse operation of a decoder.
 We can derive the Boolean functions from table 4-7
x = D4+D5+D6+D7 ; y = D2+D3+D6+D7 ; z = D1+D3+D5+D7

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 Encoders
 One problem with this octal-to-binary encoder is that
if more than one input are active simultaneously, the
output produces an undefined combination.
 We can establish an input priority to ensure that only one
input is encoded.
 Another ambiguity in this encoder is that an output
with all 0’s is generated when all the inputs are 0;
the output is the same as when D0 is equal to 1.
 This second discrepancy can be resolved by providing one
extra output to indicate that at least one input is equal to 1.

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 4-input priority encoder
V=0  no valid inputs
V=1  valid inputs
 If two or more inputs are = 1

at the same time, the input

with the highest priority will
take precedence.
 X’s in output columns

represent don’t-care
conditions.
 X’s in the input columns are

useful for representing a truth

table in condensed form,
instead of listing all 16
minterms of four variables.
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 4-input priority encoder
x = D2 + D3 ; y = D3 + D1D’2 ; V = D0 + D1 + D2 + D3

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 4-input priority encoder
x = D2 + D3 ; y = D3 + D1D’2 ; V = D0 + D1 + D2 + D3

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 4-11. Multiplexers
 A multiplexer is a combinational circuit that
selects binary info from one of many input
lines and directs it to a single output line.
 The selection of an input line is controlled by a
set of selection lines.
 There are 2n input lines and n selection lines
whose bit combinations determine which input is
selected.
 A multiplexer is also called a data selector.

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 2-to-1 Line Multiplexer
S = 0, Y = I0 Truth Table S Y Y = S’I0 + SI1
S = 1, Y = I1 0 I0
1 I1

A multiplexer is
basically a decoder that
includes the OR gate
within the unit.

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4-to-1 Line Multiplexer

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 Quadruple 2-to-1 Line
Multiplexer
 Multiplexer circuits can be combined with common selection inputs
to provide multiple-bit selection logic. Compare with Fig4-24.

I0
Y

I1

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 Boolean function
implementation
 A method of implementing a Boolean function of n variables is
to use a multiplexer with n selection inputs and 2n data inputs.

F(x, y, z) = (1,2,6,7)

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 Boolean function
implementation
 A more efficient method for implementing a Boolean
function of n variables is to use a multiplexer that
has n -1 selection inputs.
F(x, y, z) = (1,2,6,7)

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4-input function with an 8x1
MUX
F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)

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Implement with a 4x1 MUX
F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)

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 Three-State Gates

 Two of the states are equivalent to logic 1 and

logic 0.
 In Hi-Z state:
 The logic behaves like an open circuit, which means
that the output appears to be disconnected,
 The circuit has no logic significance, and
 The circuit connected to the output of the three-state
gate is not affected by the inputs to the gate. 64
 Three-State Gates
 A multiplexer can be constructed with three-state gates.

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Three-State Gates

buffer, enable high buffer, enable low

inverter, enable high inverter, enable low

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 Example
 Implement the function
 F(A,B,C,D,E) = AB’CD’E’ + AC’DE’ +
ABDE’ using only a single 4x1 MUX and
a single AND gate. Complements of
vrbs. and the logic levels 0 and 1 are
available.

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 Self study
 Implement the following Boolean
function with a 4x1 MUX and external
gates
 F(A,B,C,D) = sum
(1,2,5,7,8,10,11,13,15)

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 Example
 F = Sum( 0, 2, 3, 4, 6, 8, 10, 11)
 A) Find the minimal expression in SOP form
 B) Find the minimal expression in POS form
 C) Write F as a product of maxterms
 D) Implement F using NAND gates.
Complements are not available.
 E) Implement F using NOR gates.
 F) Using minimal number of 4x1 MUX
 G) Using minimal number of 2x4 decoders
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 F = Sum( 0, 2, 3, 4, 6, 8, 10, 11)
1 1 1
1 1

1 1 1

 F = b’c + a’d’ + b’d’

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 B) POS form: Take the 0’s. This gives
me F’.
 (F’)’  POS form
 F’ = ab + c’d + db
 (F’)’ = (a’+b’). (b’+d’) . (c + d’)

C) Product (1, 5, 7, 9, ….) =

M1.M5.M7.M9.M12.M13.M14 .M15
= (a + b+c+ d ’) (a+b’+c+d’) ….
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 F = b’c + a’d’ + b’d’

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74
75
 F = b’c + a’d’ + b’d’

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