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ELECH505 Project

The ELEC-H505 Project involves designing and testing a Chisel-based MMIO accelerator, with options for individual or team projects. Students are required to simulate the accelerator, connect it to a RISC-V CPU, and evaluate its performance against software implementations while considering security implications. Project ideas include neural network accelerators, AES encryption, image or signal processing, and original proposals, with deadlines for updates and final reports set for May 2025.

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Kamel Khalil
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10 views4 pages

ELECH505 Project

The ELEC-H505 Project involves designing and testing a Chisel-based MMIO accelerator, with options for individual or team projects. Students are required to simulate the accelerator, connect it to a RISC-V CPU, and evaluate its performance against software implementations while considering security implications. Project ideas include neural network accelerators, AES encryption, image or signal processing, and original proposals, with deadlines for updates and final reports set for May 2025.

Uploaded by

Kamel Khalil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ELEC-H505 Project

Chipyard MMIO Accelerator


Navid Ladner
contact: navid.ladner@ulb.be
April 2025

1 Context
You will design and test an accelerator using Chisel. Below we provide a few
ideas for such accelerators but we leave you with the option to propose your own
ideas. If you wish to develop an alternative idea, please send us an email with a
concrete outline of the proposed accelerator. As Chipyard already implements
a few accelerators, you can look at them to have an idea of how they implement
it. The project can be done individually or in teams of two students, depending
on the project (see section 4.)

The goal of this project is to first design an accelerator and evaluate its per-
formance. Then, you will be able to connect it to a RISC-V CPU using the
peripherals (or as a co-processor). Based on this design, you will test the cor-
rect functioning of the accelerator coupled to the CPU.

2 Requirements
• Design of a Chisel accelerator
• Simulation of the accelerator using testbenches & waveforms
• MMIO or RoCC (co-processor) connection to the processor (can be Rocket
or BOOM)
• Simulation of the complete system (processor, accelerator, peripherals,
. . . ) using different kind of tests.
• Using waveform and schematics, explain how the processor and the accel-
erator communicate.
• Compare the performance of the accelerator vs software implementation
(with a single core). Discuss the potential impact on the PPA (you don’t
need to implement it, just be critical about the design.)

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• Always consider security implications e.g, scenarios where distrusting ap-
plications would share the accelerator without revealing confidential or
meta data to each other.
• Optional: Physical implementation of your design using OpenRoad

• Optional: Any additional feature, ideas of analysis and/or implementa-


tion, ...

3 Deadlines & Project Defense


3.1 Project Update
To make sure that you are on the right track for the project, we ask you to send
us a project update report or to book a meeting so that we can discuss your
progress. Prepare a small description of the accelerator and its application (1-2
page max.)
• If you intend to send a report, it must be sent before Monday 05/05.
• If you intend to book a meeting, this will be take place in the week of
05/05.

3.2 Final Report


The final report must be submitted on the UV by Monday 26/05/2025. The
report must address all the requirements listed under 2.

3.3 Defense
The project defense will be held as an oral exam during the exams period, after
02/06.2025. In a presentation of about 10 minutes, you are expected to explain
each step of the project, specifically the functioning and implementation of your
accelerator, and how you could improve it. In the questioning part of the exam,
we will discuss your design and link your work to concepts developed across the
lectures and exercises of the course. You may prepare a few slides or bring your
project report to the exam.

4 Project Ideas
4.1 Neural Network Accelerator
This project idea aims at developing processor support to accelerate the oper-
ations required for neural network computations. As this kind of application is
highly data driven, computations within a general purpose processor are slow
and power consuming. To reach fast computation (for self driving car, virtual

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reality, . . . ), accelerators such as systolic arrays are commonly used.

For this project, you will design an accelerator depending on the specific kind of
neural network you want to accelerate. We recommend you to focus on Convolu-
tional Neural Network (CNN) using systolic arrays. Some references of systolic
arrays can be found on the UV page. You can choose to focus on training or
inference or both.

Some References
• C source code for different types of neural network with a dataset. For
CNN acceleration, you can look at cnn.c and mnist.c. In this repository,
you also have some source codes you can use for testing.
• Systolic Array Based Convolutional Neural Network Inference on FPGA
• A High-Performance Systolic Array Accelerator Dedicated for CNN
We recommend a team of 2 students for this project. Security aspect
must be discussed but no implementations are required.

4.2 AES Encryption


Similar to the project you did in ELEC-H409, Digital Architecture and Design,
you have to design an AES accelerator. The messages to encrypt must be sent
by the CPU and the encrypted cipher-text from the accelerator must be sent
back to the CPU. You need to implement at least one key size and one mode of
operation and test the implementation. The latter can be done with one of the
reference suggested below.

This module is critical in terms of security, therefore we ask you to consider


some vulnerabilities with this accelerator. Propose some ideas of keys manage-
ment as well as key storage that you can do. Implement at least one key size
and one mode of operation. Consider side-channel leakage and explain what
potential leakage you can mitigate.

Some References
• The Advanced Encryption Standard (AES) Cipher Algorithm
• Cryptographic Algorithm Validation Program

We recommend a team of 2 students for this project. Security aspect


must be discussed but no implementations are expected.

3
4.3 Image or Signal Processing
Currently, a lot of accelerators focuses on signal or image processing. For this
project, we expect you to build one type of accelerator to do at least 2 of the
following features:

• Image compressor (algorithm of your choice).


• Stenography: hide a picture within a picture and retrieve it.
• Convolution product.
• On-demand image dithering for a configurable target image size and color
scheme.
We recommend a team of 1 student for this project. Security aspect
must be discussed but no implementations are expected.

In case you want to work on this project in a group of up to two


students, you have to take the security aspect into account and im-
plement mitigations to potential attacks.

4.4 Original Ideas


If you have an idea of accelerator that you want to implement, we expect you to
send us a description of the accelerator and a bullet-point list of your objectives
for the project by email. We will then discuss the proposal with you during the
labs.

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