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 The circuit diagrams included in this manual are for illus-
tration of typical transistor applications and are not intended
as constructional information. For this reason, wattage ratings of
resistors and voltage ratings of capacitors are not necessarily given.
Similarly, shielding techniques and alignment methods which may
be necessary in some circuit layouts are not indicated. Although
reasonable care has been taken in their preparation to insure their
technical correctness, no responsibility is assumed by the General
Electric Company for any consequences of their use.

The semiconductor devices and arrangements disclosed herein

may be covered by patents of General Electric Company or others.
Neither the disclosure of any information herein nor the sale of
semiconductor devices by General Electric Company conveys any
license under patent claims covering combinations of semiconductor
devices with other devices or elements. In the absence of an express
written agreement to the contrary General Electric Company as-
sumes no liability for patent infringement arising out of any use
of the semiconductor devices with other devices or elements by any
purchaser of semiconductor devices or others.

Copyright 1964
by the
General Electric Company

li
 framer
manual
CONTRIBUTING
AUTHORS
R. E. BeIke
J. F. Cleary
U. S. Davidsohn
J. Giorgis
E. Gottlieb
E. L. Haas
D. J. Hubbard 2N2 14 -sere-
I). V. Jones
E. F. Kvamme
J. H. Phelps
W. A. Sauer »New,
teer.
K. Schjonneberg
G. E. Snyder
R. A. Stasior
T. P. Sylvan

EDITOR
J. F. Cleary

TECHNICAL EDITOR
J. H. Phelps
Manager Application Engineering

LAYOUT/DESIGN
L. L. King

PRODUCTION
F. W. Pulver, Jr.

EDITED AND PRODUCED BY

Semiconductor Products Department
Advertising & Sales Promotion
General Electric Company
Electronics Park
Syracuse, New York
 Progress /s Our Most Important Product

GENERAL ELECTRIC
 CONTENTS

Page
1. BASIC SEMICONDUCTOR THEORY 1
A Few Words of Introduction 1
Semiconductors 3
Atoms 4
Valency 6
Single Crystals 6
Crystal Flaws 8
Energy 8
Electronic 8
Atomic 8
Conductivity in Crystals 9
Thermal 9
Radiation 10
Impurities 10
N-Type Material 10
P-Type Material 11
Temperature 12
Conduction: Diffusion and Drift 13
Diffusion 13
Drift 13
PN Junctions (Diodes) 17
Junction Capacity 21
Current Flow 21
Diode "Concept" 21
Bias: Forward and Reverse 23
Transistor 25
Alpha 29
Beta 29
Base-Emitter Bias Adjustment 30
Transistor Switch 31
Transistor Amplifier 31
Symbols and Abbreviations 31
Leakage 32
Bias Stability 34
Thermal Spectrum 36
Transistor Abuses 36
Mechanical 38
Electrical 39
Some Things to Remember in the Application of Transistors 39
Aging 39
Current 39
Frequency 40
Leakage 40
Manufacturing Ratings 40
Mechanical 40
Power 40
Temperature 41
Voltage 41
References 41

III
 Page
2. SMALL SIGNAL CHARACTERISTICS 43
Part /—Low Frequency Considerations 43
Introduction 43
Transistor Low Frequency Equivalent Circuits 45
Generic Equivalent Circuit 45
"Black-Box Analysis" of the Four Terminal Linear Network 49
Open Circuit Impedance Parameters (z-Parameters) 49
Short Circuit Admittance Parameters (y-Parameters) 50
h-Parameter Equivalent Circuit 51
T-Equivalent Circuit 51
Basic Amplifier Stage 57
Input Resistance 57
Output Resistance 57
Current Amplification 59
Voltage Amplification 59
Maximum Power Gain 59
Transducer Gain 60
Maximum Power Gain (MPG) 62
Part 2—High Frequency Considerations 65
Addition of Parasitic Elements to the Low-Frequency
Equivalent Circuits 65
Junction Capacitances 65
Parasitic Resistances 66
Consideration of the Equivalent Circuit 71
Consideration of the Transistor's Frequency Limitations 74
Gain-Bandwidth Product 74
Alpha and Beta Cutoff Frequencies 76
The Use of Black-Box Parameters (h or y) 77
Calculation of Input Admittance (Common-Emitter) 79
Calculation of Output Admittance (Common-Emitter) 79
Calculation of Gain 79
Measurement of y-Parameters 80
References 80

3. LARGE SIGNAL CHARACTERISTICS

AND TRANSISTOR CHOPPERS 81
Parameters 81
Basic Equations 83
Active Operation 83
Saturated Operation 83
Cutoff Operation 86
Useful Large Signal Relationships 86
Collector Leakage Current ( ICEO ) 87
Collector Leakage Current (I cE8 ) 87
Collector Leakage Current ( IcER ) 87
Collector Leakage Current—Silicon Diode in Series With Emitter 87
Base Input Characteristics 88
Voltage Comparator Circuit 88
Junction Transistor Choppers 88
References 94

4. BIASING AND DC AMPLIFIERS 95

Biasing 95
Introduction 95
Single Stage Biasing 96
Biasing of Multistage Amplifiers 102
Nonlinear Compensation 106
Thermal Runaway 107
DC Amplifiers 111
Transistor Requirements 111
Single Stage Differential Amplifier 114
Two Stage Differential Amplifier 117
References 120

5. LOGIC 121
Switching Algebra 121
The Karnaugh Map 126
Number Systems 128
Arithmetic Operations 130
Memory Elements 131
Circuit Implications 134

IV
 Page
6. SWITCHING CHARACTERISTICS 139
The Basic Switch 139
The Basic Diode Switch 139
The Basic Transistor Switch 139
Static Parameters 141
Power 141
Leakage Current 144
Current Gain 145
Collector Saturation Voltage 146
Base-Emitter Saturation Voltage 149
Transient Response Characteristics 149
Definition of Time Intervals and Currents 149
Turn-On Delay 149
Collector and Emitter Transition Capacitances 151
Forward Base Current 152
Gain Bandwidth Products 153
Charge Control Concepts 156
Application of Stored Charge Concepts 158
Rise Time 159
Complete Solutions 162
Limitations 166
r. Specification 166
Calculation of Fall-Time 168
Summary of Results 169
Anti-Saturation Techniques 169
References 173

7. DIGITAL CIRCUITS 175

Introduction 175
Basic Circuits 175
Common Logic Systems 182
Flip-Flop Design Procedures 186
Saturated Flip-Flops 186
Non-Saturated Flip-Flop Design 188
Triggering 196
Special Purpose Circuits 199
Schmitt Trigger 199
Astable Multivibrator 200
Monostable Multivibrator 200
Indicator Lamp Driver 202
Pulse Generator 203
Ring Counter 203
DCTL 203

8. OSCILLATORS 205
Oscillator Theory 205
Phase Shift Oscillators 206
Resonant Feedback Oscillators 207
Crystal Oscillator 210
References 211

9. FEEDBACK AND SERVO AMPLIFIERS 213

Use of Feedback in Transistor Amplifiers 213
Negative Feedback 213
Positive Feedback 215
Servo Amplifier for Two Phase Servo Motors 217
Preamplifiers 217
Driver Stage 220
Output Stage 220
References 226

10. REGULATED DC SUPPLIES 227

Regulated DC Supplies 227
Precision Power Supplies Using Reference Amplifier. 228
Precision Regulated Voltage Supply 232
Precision Constant Current Supply 233
Parallel Inverters 234
DC to DC Converters 237
References 239

V
 Page
11. AUDIO AND HIGH FIDELITY AMPLIFIER
CIRCUITS 241
Part 1—Audio Amplifier Circuits 241
Basic Amplifiers 241
Single Stage Audio Amplifier 241
Two Stage RC Coupled Audio Amplifier 241
Class B Push-Pull Output Stages 242
Class A Output Stages 244
Class A Driver Stages 244
Design Charts 245
Part 2—High Fidelity Circuits 250
Introduction 250
Preamplifiers 251
Bass Boost or Loudness Control Circuit 254
NPN-Tape and Microphone Preamplifier 255
NPN-Phono Preamplifiers 258
Power Amplifiers 259
Silicon Power Amplifiers 261
8 Watt Transformerless Amplifier 262
21/ Watt Transformerless Amplifier
2 265
12 Watt Transformerless Amplifier 266
15 Watt Transformerless Amplifier 268
Stereophonic Systems 270
20 Watt Stereo With 8 or 16 Ohm Speakers 270
Stereophonic Systems Using Silicon Transistors 270
Stereo Headphone Amplifier 271
Tape Recording Amplifier With Bias and Erase Oscillator 274
Recording Amplifier 274
Tape Erase and Bias Oscillator 278
References .. 279

12. RADIO RECEIVER CIRCUITS 281

Silicon Transistors 281
Advantages 281
Line Operated Receivers 282
Radio Frequency Circuits 282
Autodyne Converter Circuits 284
IF Amplifiers 285
Emitter Current Control 286
Auxiliary AVC Systems 288
Detector Stage 289
Reflex Circuits 289
Complete Radio Receiver Diagrams 291
Notes 299
Additional Component Information 299

13. UNIJUNCTION CIRCUITS 300

Theory of Operation 301
Parameter—Definition and Measurement 303
Construction 304
Important Unijunction Characteristics 307
Peak Point 307
Peak Point Temperature Stabilization 307
Valley Point 310
Power Dissipation Ratings 312
Relaxation Oscillator 312
Circuit Operation 312
Oscillation Requirements and Component Limits 314
Transient Waveform Characteristics 314
Pulse Generation 315
Frequency Stability 316
Synchronization 316
Sawtooth Wave Generators 317
General Considerations 317
Temperature Effects 318
Improving Linearity 318
Linear Sawtooth Wave Generators 319
Precision Timing Circuits 320
Time Delay Relay 320
Precision Solid State Time Delay Circuits 320
Delayed Dropout Relay Timer 323

VI
 Page
Sensing Circuits 324
Voltage Sensing Circuit 324
Nanoampere Sensing Circuit With 100 Megohm Input Impedance 325
SCR Trigger Circuits 326
Simplified SCR Trigger Circuit Design Procedures 326
Triggering Parallel-Connected SCR's 328
Simplified SCR Trigger Circuits for AC Line Operation 329
Sensitive AC Power Switch 330
Sensitive DC Power Switch 331
High Gain Phase-Control Circuit 331
Triggering Circuits for DC Choppers and Inverters 332
Regulated AC Power Supply 333
Transistor Control of Unijunction 336
Shunt Transistor Control of Unijunction 336
Series Transistor Control of Unijunction 336
Hybrid Timing Circuits 337
Symmetrical Multivibrator (Square Wave Generator) 338
One-Shot Multivibrator 338
Non-Symmetrical Multivibrator 339
Non-Symmetrical Multivibrators (Constant Frequency) 339
Multivibrator 339
Frequency Divider 341
Miscellaneous Circuits 343
Regenerative Pulse Amplifier 343
Pulse Generator (Variable Frequency and Duty Cycle) 343
Staircase Wave Generator 345
One-Shot Multivibrator (Fast Recovery and Wide Frequency
Range) 345
Voltage-to-Frequency Converter 346
References 347

14. TUNNEL DIODE CIRCUITS 349

Tunnel Diode Oscillators 349
Tunnel Diode Micro-Power Transmitters 355
Tunnel Diode Converters 358
Various Industrial Special Uses of Tunnel Diodes 362
Tunnel Diode Amplifiers 363
Tunnel Diode Multivibrators 366
Hybrid (Transistor—Tunnel Diode) Multivibrators 367
Tunnel Diode Counters 368
Miscellaneous Tuned Diode Circuits 369
Tuned Diode Computer Circuits 370
References 373

15. EXPERIMENTER CIRCUITS 375

Simple Audio Amplifier "ru
Low Impedance Microphone Preamplifier 175
Direct Coupled "Battery Saver" Amplifier 175
Six Volt Phono Amplifier 376
Nine Volt Phono Amplifier 377
Code Practice Oscillator 378
Unijunction Transistor Code Practice Oscillator 378
Unijunction Transistor Metronome 379
Metronome 379
Unijunction Home Signal System 379
Ultra-Linear High Precision Tachometer 380
Audible Auto Signal Minder 381
Unijunction CW Monitor 382
1KC Oscillator 182
100KC Crystal Standard 382
Unijunction 100KC Crystal Standard 383
One Transistor Receiver 383
Two Transistor Receiver 383
Three Transistor Receiver 384
AM Broadcast Band Tuner 384
Superregenerative 27MC Receiver 184
FM Broadcast Band Tuner 385
Low Power AM Broadcast Band Transmitter 386
Low Power VFO CW Transmitter 386
Transistor Test Set 387
Transistor Tester 188
Transistor Tester Showing Readout Chart 389
Internal View of Transistor Tester 189
Regulated Power Supply 390

VII
 Page
16. SILICON CONTROLLED SWITCHES 391
Part 1—Understanding PNPN Devices 391
Introduction 391
The Equivalent Circuit 391
PNPN Geometry 392
Biasing Voltages 394
Basic Two Transistor Equivalent Circuit 395
Rate Effect 398
Forward Conducting Voltage 399
Holding Current and Valley Point 399
Transient Response Time 400
Recovery Time 400
Basic Circuit Configurations 401
Circuit Configurations Based on NPN Transistor 401
Circuit Configurations Using High Triggering Sensitivity 403
Threshold Circuits 404
Circuit Configurations for Turning Off the SCS 404
Circuit Configurations for Minimizing Rate Effect 407
Circuit Design "Rule of Thumb" 408
Measurement 410
DC Measurements 410
Transient Measurement 411
Part 2—SCS Characteristic Curves 413
Part 3—SCS Circuit Applications 425

17. SILICON SIGNAL DIODES & SNAP DIODES 437

Silicon Signal Diodes 437
Planar Epitaxial Passivated Silicon Diode 437
DC Characteristics 439
AC Characteristics 443
Diode Comparisons and Trade-Offs 448
Diode Assemblies 449
Stabistors 450
Snap Diodes 451
References 455

18. TRANSISTOR MEASUREMENTS 457

Introduction 457
Reverse Diode Characteristics 458
General 458
DC Tests 459
Current Measurements 463
Large-Signal (DC) Transistor Measurements 465
Large Signal Definitions and Basic Test Circuits 466
Some Test Circuits 467
Junction Temperature Measurements 470
Junction Temperature ( TI) 470
Thermal Impedance 470
Test Circuit for Junction Temperature Measurements 471
Small Signal Measurements (Audio) of Transistor Parameters 474
Common Base Configuration 475
Common Emitter Configuration 477
Common Collector Configuration 479
General 480
High Frequency Small Signal Measurements of
Transistor Parameters 482
General 482
Input Impedance 483
Output Admittance 485
Forward Current Ratio 487
Power Gain Measurement 493
General 493
Measuring Power Gain 494
Neutralization 497
Transistor Noise Measurements 499
General 499
Measurement of Noise Figure 499
Equivalent Noise Current and Noise Voltage 501
Measurement of (e N) % and (i N') % for Transistors 503
Measurement of Noise Factor Without Using Signal
Generator or Noise Diode 504
Transistor Noise Analyzer. 507

VIII
 Page
Charge Control Parameter Measurement 507
r., Effective Lifetime in the Active State 507
TB ,Effective Lifetime in Saturated State 508
CBE ,Average Emitter Junction Capacitance 509
Composite Circuit for r., rb,CBE 510
QB*, Total Charge to Bring Transistor to Edge of Saturation 510
Calibration of Capacitor, C, on QB*Test Set 512

19. THE TRANSISTOR SPECIFICATION SHEET

AND SPECIFICATIONS 514
Part 1—The Transistor Specification Sheet 516
General Device Capabilities 516
Absolute Maximum Ratings 516
Voltage 516
Current 520
Transistor Dissipation 520
Temperature 521
Electrical Characteristics 521
DC Characteristics 522
Cutoff Characteristics 522
High Frequency Characteristics 522
Switching Characteristics 522
Generic Characteristics 523
Explanation of Parameter Symbols 524
Symbol Elements 524
Decimal Multipliers 525
Parameter Symbols 525
Abbreviated Definition of Terms 529
Part 2—Specifications 533
GE Specification Charts Index 533
GE Semiconductor Charts 534
GE Outline Drawings 575
Registered JEDEC Transistor Types with
Interchangeability Information 590

20. APPLICATION LITERATURE_

SALES OFFICES 643
GE Application Notes and Article Reprints 643
GE Semiconductor Sales Offices 644
GE Full-line Semiconductor Distributors 645
Other General Electric Product Departments 648
GE Semiconductor Type Index 649

NOTE: For information pertaining to General Electric Sales Offices, Dis-

tributors, Related Departments, and GE Semiconductor Products —
Turn to back of book.

IX
 FOREWORD

The growth to maturity of the semiconductor industry is

paralleled by the growth of this General Electric Transistor Manual.
First published in 1957, the present Manual's more than 600 pages
is roughly 10 times the size of the first edition. The contents, how-
ever, retain the same basic orientation which is that of ahighly prac-
tical circuit book, one that can be used to advantage by electronic
design engineers as well as students, teachers, and experimenters.

This seventh edition contains new and updated material which

accounts for more than 80% of the contents. For instance: more
high frequency material has been added; the chapter on switching
has been completely rewritten; the number of circuits in the manual
has been almost tripled; also, the chapter for experimenters has
been greatly enlarged.

This is a book written not by theorists, but by experienced

men who are devising the practical solutions to some of the most
challenging, difficult problems encountered in electronic engineering.

As solid state devices contribute more and more to the won-

derful age of automated industry and electronic living, we at
General Electric sincerely hope that this Manual will provide
insight and understanding on how semiconductors might do the
job better and more economically.

L.
G ager
Se onductor Products Department
Syra use, New York

X
BASIC SEMICONDUCTOR THEORY

A FEW WORDS OF INTRODUCTION

Pushing the frontiers of space outward along the "space spectrum" toward both
ifinities has caused to be born in this century whole new technologies. Those related
t•outer space, and those related to "inner space." But not one stands alone, inde-
p ndent of another. All are related. It is this relationship, accumulating as it has down
trough the ages that has brought with it the transistor.
Just as the vast reaches of outer space — that infinite "land" of the sun and moon,
ti estar constellations and the "milky way," Mars, Venus, and all of the other mysteries
that exist there — has caused man throughout his history to wonder and ask questions,
so too has he wondered and asked about the vast reaches of "inner space" — the world
of the atom. But it has only been recently, during the 19th and 20th centuries in fact,
that some of his questions about inner space have been answered. Much to his credit,
many questions man has answered by mere observation and mathematical calculation.
Further to his credit he has devised "seeing eye" aids to help push the space boun-
daries still farther out.

ffle

41 3 di

GENERAL ELECTRIC DEVICES

Problems of "seeing" exist at both ends of space, and it is just as difficult to look
'in" as it is to look "out." Just as the outer space astronomer depends on his powerful

1
1 BASIC SEMICONDUCTOR THEORY

magnifying aids to help him see, hear, and to measure, to gather information and data
in order to comprehend; so too does the inner space "astronomer" depend on his mag-
nifying aids. Microscopes, mass spectrometers, x-ray and radiography techniques,
electric meters, oscilloscopes, and numerous other intricate equipment help him to
measure the stuff, the matter, that makes up inner space. From his search has devel-
oped many new technical terms. In fact, whole new technical languages have come
into existence: electron, hole, neutron, neutrino, positron, photon, muon, kaon, the Bohr
atom, quantum mechanics, Fermi-Dirac statistics. Strange terms to many, but terms
of the world that exist at one end of the infinite space spectrum, the atomic world.
Atomic physics as we know it today started far back in 400 B.C." when the doctrine
of atoms was in vogue in the Greek world of science. And no matter how unsophisti-
cated the atomic theories at the time, it was abeginning. The idea of "spirit" particles
too small for the unaided human eye to see was then postulated. It would take many
centuries before the knowledge of the physicist, the statistician, the metallurgist, the
chemist, the engineer — both mechanical and electronic — could and would combine to
bring into being aminute, micro-sized crystal that would cause to evolve acompletely
new and unusually complicated industry, the semiconductor industry.
The history of the semiconductor is, in fact, apyramid of learning, and if any one
example were to be cited, of the practical fruits of scientific and technical cooperation
over the ages, and especially over the past 100 or so years, near the head of the list
would surely be the transistor.
In 1833, Michael Faraday,( 2)the famed English scientist, made what is perhaps the
first significant contribution to semiconductor research. During an experiment with
silver sulphide Faraday observed that its resistance varied inversely with temperature.
This was in sharp contrast with other conductors where an increase in temperature
caused an increase in resistance and, conversely, adecrease in temperature caused a
decrease in resistance. Faraday's observation of negative temperature coefficient of
resistance, occurring as it did over 100 years before the birth of the practical transistor,
may well have been the "gleam in the eye" of the future.
For since its invention in 1948" the transistor has played asteadily increasing part
not only in the electronics industry, but in the lives of the people as well. First used in
hearing aids and portable radios, it is now used in every existing branch of electronics.
Transistors are used by the thousands in automatic telephone exchanges, computors,
industrial and military control systems, and telemetering transmitters for satellites.
A modern satellite may contain as many as 2500 transistors and 3500 diodes as part
of acomplex control and signal system. In contrast, but equally as impressive, is the
two transistor "pacemaker," a tiny electronic pulser. When imbedded in the human
chest and connected to the heart the pacemaker helps the ailing heart patient live
a nearly normal life. What a wonderful device is the tiny transistor. In only a few
short years it has proved its worth — from crystal set to regulator of the human heart.
But it is said that progress moves slowly. And this is perhaps true of the first
hundred years of semiconductor research, where time intervals between pure research
and practical application were curiously long. But certainly this cannot be said of the
years that followed the invention of the transistor. For since 1948 the curve of semi-
conductor progress has been moving swiftly and steadily upward. The years to come
promise an even more spectacular rise. Not only will present frequency and power
limitations be surpassed but, in time, new knowledge of existing semiconductor mate-
rials ...new knowledge of new materials ...improved methods of device fabrication
...the micro-miniaturization of semiconductor devices ...complete micro-circuits ...
all, will spread forth from the research and engineering laboratories to further influence
and improve our lives.
Already, such devices as the tunnel diode and the high-speed diode can perform

2
 BASIC SEMICONDUCTOR THEORY 1

with ease well into the UHF range; transistors, that only a short time ago were
limited to producing but a few milliwatts of power, can today produce thousands
upon thousands of milliwatts of power; special transistors and diodes such as the
u 'junction transistor, the high-speed diode, and the tunnel diode can simplify and make
more economical normally complex and expensive timing and switching circuits. Intri-
cate and sophisticated circuitry that normally would require excessive space, elaborate
cooling equipment, and expensive power supply components can today be designed
and built to operate inherently cooler within a substantially smaller space, and with
less imposing power components. All this is possible by designing with semiconductors.
In almost all areas of electronics the semiconductors have brought immense increases
in efficiency, reliability, and economy.
Although acomplete understanding of the physical concepts and operational theory
o the transistor and diode are not necessary to design and construct transistor circuits,
it goes without saying that the more device knowledge the designer possesses, whether
h be aprofessional electronics engineer, aradio amateur, or a serious experimenter,
emore successful will he be in his use of semiconductor devices in circuit design.
S ch understanding will help him to solve special circuit problems, will help him to
b tter understand and use the newer semiconductor devices as they become available,
a d surely will help clarify much of the technical literature that more and more
a ounds with semiconductor terminology.
The forepart of this chapter, then, is concerned with semiconductor terminology
a d theory as both pertain to diodes and junction transistors. The variety of semi-
c nductor devices available preclude a complete and exhaustive treatment of theory
a dcharacteristics for all types. The silicon controlled rectifier (SCR) is well covered
other General Electric Manuals;" treatment of the unijunction transistor (UJT)
ill be found in Chapter 13 of this manual, and tunnel diode circuits are shown in
hapter 14.'"' Other pertinent literature will be found at the end of most chapters
der references. Information pertaining to other devices and their application will be
fund by asearch of text books and their accompanying bibliographies. The "year-end
index" (December issue) of popular semiconductor and electronic periodicals is another
excellent source. Public libraries, book publishers, magazine publishers, and component
and device manufacturers are all "information banks" and should be freely used in any
srarch for information and knowledge.

.,EIVIICONDUCTORS
Semiconductor technology is usually referred to as solid-state. This suggests, of
ourse, that the matter used in the fabrication of the various devices is a solid, as
pposed to liquid or gaseous matter — or even the near perfect vacuum as found in the
termionic tube — and that conduction of electricity occurs within solid material. "But
ow," it might be asked, "can electrical charges move through solid material as they
ust, if electrical conduction is to take place?" With some thought the answer becomes
bvious: the so-called solid is not solid, but only partially so. In the microcosmos, the
orld of the atom, there is mostly space.'> It is from close study of this intricate and
•omplicated "little world," made up mostly of space, that scientists have uncovered the
asic ingredients that make up solid state devices — the semiconductors.
Transistors and diodes, as we know them today, are made from semiconductors,
o-called because they lie between the metals and the insulators in their ability to
onduct electricity. Asimple illustration of their general location is shown in Figure 1.1.
haded areas are transition regions. Materials located in these areas may or may not
•esemiconductors, depending on their chemical nature.
There are many semiconductors, but none quite as popular at the present time as
ermanium and silicon, both of which are hard, brittle crystals by nature. In their

3
1 BASIC SEMICONDUCTOR THEORY

HIGH SEMI LOW

CONDUCTIVITY CONDUCTIVITY CONDUCTIVITY
REGION REGION REGION

CONDUCTORS SEMICONDUCTORS NON-CONDUCTORS

(METALS) (CRYSTALS) (INSULATORS)
18
10 -6 10 5 10

RESISTANCE IN OHMS/CM 3
MATERIALS RESISTIVITY SPECTRUM

SEMICONDUCTORS ARE LOCATED IN REGION BETWEEN

CONDUCTORS AND INSULATORS
Figure 1.1

natural state they are impure in contrast, for example, to the nearly pure crystalline
structure of high quality diamond. In terms of electrical resistance the relationship of
each to well known conductors and insulators is shown in Table 1.1.

RESISTANCE IN OHMS PER

MATERIAL CENTIMETER CUBE CATEGORY
(R/CM 3)

Silver Conductor
Aluminum Io

Pure Germanium 50-60 Semiconductor

Pure Silicon 50,000-60,000

Mica 10' 2-10" Insulator

Polyethlene 10"-10"

Table 1.1

Because of impurities, the R/CM' for each in its natural state is much less than
an ohm, depending on the degree of impurity present. Material for use in most prac-
tical transistors requires R/CMs values in the neighborhood of 2 ohms/CM'. The
ohmic value of pure germanium and silicon, as can be seen from Table 1, is much
higher. Electrical conduction, then, is quite dependent on the impurity content of the
material, and precise control of impurities is the most important requirement in the
production of transistors. Another important requirement for almost all semiconductor
devices is that single crystal material be used in their fabrication.

ATOMS
To better appreciate the construction of single crystals made from germanium
and silicon, some attention must be first given to the makeup of their individual atoms.
Figure 1.2(A) and (C) show both as represented by Bohr models of atomic structure,
so named after the Danish physicist Neils Bohr (1885-1962).
Germanium is shown to possess a positively charged nucleus of +32 while the
silicon atom's nucleus possesses apositive charge of +14. In each case the total positive
charge of the nucleus is equalized by the total effective negative charge of the elec-
trons. This equalization of charges results in the atom possessing an effective charge
that is neither positive nor negative, but neutral. The electrons, traveling within their
respective orbits, possess energy since they are a definite mass in motion.* Each
electron in its relationship with its parent nucleus thus exhibits an energy value and
*Rest mass of electron = 9.108 X 10 -28 gram.

4
 BASIC SEMICONDUCTOR THEORY 1

VALENCE
BAND

NUCLEUS
VALENCE
BAND

CENTRAL CORE
OR KERNEL

GERMANIUM ATOM SIMPLIFIED

(A) (B)

SILICON ATOM SIMPLIFIED

(C) (0)

BOHR MODELS OF GERMANIUM AND SILICON ATOMS

Figure 1.2

functions at a definite and distinct cue, gy level. This energy level is dictated by the
electron's momentum and its physical proximity to the nucleus. The closer the electron
to the nucleus, the greater the holding influence of the nucleus on the electron and the
greater the energy required for the electron to break loose and become free. Likewise,
the further away the electron from the nucleus the less its influence on the electron.
Outer orbit electrons can therefore be said to be stronger than inner orbit electrons
because of their ability to break loose from the parent atom. For this reason they are
called valence electrons, from the Latin valere, to be strong. The weaker inner orbital
electrons and the nucleus combine to make acentral core or kernel. The outer orbit in
which valence electrons exist is called the valence band or valence shell. It is the elec-
trons from this band that are dealt with in the practical discussion of transistor physics.
With this in mind the complex atoms of germanium and silicon as shown in (A) and
(C) of Figure 1.2 can be simplified to those models shown in (B)and (C)and used in
further discussion. It should be mentioned that although it is rare for inner orbital
electrons — those existing at energy levels below that of the valence band — to break
loose and enter into transistor action, they can be made to do so if subjected to heavy
x-rays, alpha particles, or nuclear bombardment and radiation.
When an electron is freed from the valence band and moves into "outer atomic
space," it becomes aconduction electron, and exists in the conduction band. Electrons

5
1 BASIC SEMICONDUCTOR THEORY

possess the ability to move back and forth between valence and conduction bands.

VALENCY

The most important characteristic of most atoms is their ability to unite with other
atoms. Such an atom is said to possess valency, or be a valent atom. This ability is
dependent on those electrons that exist in the parent atom's valence band, leaving
the band to move into the valence band of aneighboring atom. Orbits are thus enlarged
to encompass two parent atoms rather than only one; the action is reciprocated in that
electrons from the neighboring atom also take part in this mutual combining process.

VALENCE CENTRAL CORE

ELECTRON OR KERNEL

INDEPENDENT
ATOMS

SHARED
ORBIT

COVALENT OR
ELECTRON-PAIR BOND
OF ATOMS

Figure 1.3

In short, through orbit sharing by interchange of orbital position, the electrons

become mutually related to one another and to the parent cores, binding the two
atoms together in astrong spaced locking action. A covalent bond (cooperative bond;
working together) or electron-pair bond is said to exist. This simple concept when
applied to germanium and silicon crystals will naturally result in a more involved
action, one the reader may at first find difficult to visualize. This important and basic
atomic action can be visualized as shown in Figure 1.3.

SINGLE CRYSTALS

In the structure of pure germanium and pure silicon single crystals the molecules
are in an ordered array. This orderly arrangement is descriptively referred to as a
diamond lattice, since the atoms are in alattice-like structure as found in high quality
diamond crystals."' A definite and regular pattern exists among the atoms due to space
equality. For equal space to exist between all atoms in such astructure, however, the
following has been shown to be true: the greatest number of atoms that can neighbor
any single atom at equal distance and still be equidistant from one another is four.' 0>
Figure 1.4 is atwo dimensional presentation of agermanium lattice structure showing
covalent bonding of atoms. (Better understanding and more clear spatial visualization
— that is, putting oneself in a frame of mind to "mentally see" three dimensional
figures, fixed or moving with time — of Figure 1.4 may be had by construction of a
three dimensional diamond lattice model using the technique shown in Figure 1.5.

6
 BASIC SEMICONDUCTOR THEORY 1

CENTRAL CORE
OR KERN L

A
ORBITING
/ \
VALENCE
•ELECTRON,
t.
•••• t.

/ \

TWO DIMENSIONAL CRYSTAL LATTICE STRUCTURE

Figure 1.4

TYPICAL MODEL OF ATOMIC CRYSTAL LATTICE STRUCTURE

(TYPIFIES SPATIAL VISUALIZATION)

Figure 1.5

7
1 BASIC SEMICONDUCTOR THEORY

Spatial visualization differs in individuals, and where some will have little trouble
forming aclear mental picture of complex theoretical concepts, others will have diffi-
culties. Whether electrons and holes and atoms in all their involved movements are
mentally pictured in terms of more graphic objects such as marbles, moth balls, base-
balls, automobiles, or whatever else that might come to mind, is of little consequence
and may even be helpful.) Figure 1.4 could just as well represent asilicon lattice since
the silicon atom also contains four electrons in its outer valence band. With all valence
electrons in covalent bondage, no excess electrons are free to drift throughout the
crystal as electrical charge carriers. In theory, this represents a perfect .and stable
diamond lattice of single crystal structure and, ideally, would be a perfect insulator.

CRYSTAL FLAWS
But such perfect single crystals are not possible in practice. Even in highly purified
crystals imperfections exist making the crystal a poor conductor rather than a non-
conductor. At the start of the manufacturing process modern and reliable transistors
require as near perfect single crystal material as possible. That is, crystal that exhibits
an orderly arrangement of equally spaced atoms, free from structural irregularities.
Crystal imperfections fall into three general classes, each acting in its own way to
influence transistor action.

ENERGY
Both light and heat cause imperfections in asemiconductor crystal. Disturbance by
light striking the crystal is dependent on the frequency and magnitude of light energy
absorbed. This energy is delivered in discrete and definite amounts known as quanta
composed of particles known as photons.
Heat, or thermal, disturbance is also absorbed by the crystal, in the form of vibrat-
ing waves. Interference is such that when the waves are absorbed, electronic action is
impaired through atomic vibration of the lattice structure; the effect is crystal heating
and destruction of the "perfectness" of the crystal. Thermal waves interfere with
charge movement, causing the charges to be scattered and diffused throughout the
crystal. In effect, the electrons are buffeted and jostled in various and indiscriminate
and indefinite directions as defined by the laws of quantum-mechanics."' Because of
this severe thermal encounter, the electrons gain thermal kinetic energy which is of
extreme importance in the practical operation of diodes and transistors.

ELECTRONIC
Too many or too few electrons also cause crystal imperfections. In short, in perfect
single crystal all electrons are assumed to be locked in covalent bond. Those that are
not are free and therefore constitute a form of imperfection. (Figures 1.6 and 1.7).

ATOMIC
Any atomic disorder in the lattice structure causes the crystal to be less than
perfect. Crystals of this nature are said to be polycrystal. They are characterized by
breaks in covalent bonds, extra atoms not locked in place by covalent bonds (inter-
stitial atoms), and missing atoms that leave gaps in an otherwise orderly crystal
structure (atomic vacancies). Such imperfections interfere with proper transistor
action by not readily allowing charge carriers to move freely.
Interference to carrier movement also occurs when the perfect lattice structure
appears as being interrupted. This can be viewed as crystal discontinuity, or as two
separate crystals not properly "fit" so as to form a perfect single crystal; the two
crystals appear at the point of joining as being improperly oriented to each other. This
form of imperfection is referred to as agrain or grain boundary. Flaws of this nature
cause impurities to be generated with consequent impairment of the perfect crystal.

8
 BASIC SEMICONDUCTOR THEORY 1

Electrons set free from covalent bondage move at some given velocity and for some
gi en time before arriving at adestination; the travel time involved is referred to as
¡me. While free and in motion the electron will experience numerous collisions
thin the crystal, with the result that electrons will not experience equal lifetimes.
ere an electron's lifetime is limited and cut short, the cause is theorized to be
a imperfection mechanism known as a recombination center (sometimes called a
"o eathnium center"). A recombination center acts to capture and hold an electron
u til an opposing carrier arrives to affect recombination and thus empty the center,
ti capture and then immediately release an electron, or to release an electron that has
e isted within the center thus producing a hole. The impurity causing the center
• ermines at what energy level capture takes place. The electron involved may not
cessarily be afree charge, but one from a covalent bond. In any case, the center
ts as an intermediate "holding" point of charge carriers.
Another imperfection more common to silicon than to germanium is the trap.
variation of the recombination center, the trap as the name implies captures acarrier
• nd holds it; emptying occurs only upon release of the first carrier, which may be
eld in the trap up to several minutes. Trapping is unlikely in germanium at normal
emperatures, but does appear around —80°C. In silicon, trapping is common at room
emperatures (25°C ).'"'
The effects of the various imperfections in semiconductor crystals are many, and
ot always easily explained. Although much is already known about semiconductor
mperfections, it is generally recognized that other imperfection mechanisms, as yet
ot known, may exist. Of importance, however, is that those working with diodes and
ransistors recognize that imperfections are both good and bad. They both hinder
and help, depending of course on the imperfections involved. Semiconductors would
not be possible without imperfections, yet by their very nature they act in many
devious and obscure ways.

CONDUCTIVITY IN CRYSTALS
As already mentioned, to be of practical use transistors require crystal material of
greater conductivity (lower R/CM° )than found in highly purified germanium and
silicon. Conductivity can be increased by subjecting the crystal to heat, to radiation,
or by adding impurities to the crystal when it is formed.

THERMAL
Heating the crystal will cause the atoms which form the crystal to vibrate. Occa-
sionally one of the valence electrons will acquire enough energy (ionization energy) to
break away from its parent atom and move through the crystal. Since the atom has
lost an electron, it will thus assume apositive charge equal in magnitude to the charge
of the electron. In turn, once an atom has lost an electron it can then acquire another
electron from one of its neighboring atoms. This neighboring atom may, also in turn,
acquire an electron from one of its neighbors. It is evident that each free electron
which results from the breaking of acovalent bond will produce an electron deficiency
which can move through the crystal as readily as the free electron itself. It is con-
venient to consider these electron deficiencies as positively charged particles called
holes. Each time acovalent bond is broken and anegative electron set free, apositive
hole is simultaneously generated. This process is known as the thermal generation of
hole-electron pairs. The average time either charged carrier, the hole or the electron,
exists as afree or mobile carrier is known as lifetime. Should afree electron join with
or collide with ahole, the electron will fill the existing electron deficiency which the
hole represents and both the hole and the electron will cease to exist as free charge
carriers. This joining or colliding process is known as recombination.

9
1 BASIC SEMICONDUCTOR THEORY

RADIATION
Transistor crystal material is very sensitive to radiation. Neutron bombardment,
gamma rays, beta rays, both slow and high energy particles in various forms can
effect semiconductor material. Their influence is to increase crystal lattice imperfec-
tions. Atoms, normally in space locked position within the crystal, are knocked out of
position and into interstitial positions where they come to rest. What was a perfect
lattice structure at that particular location in the crystal becomes imperfect by the
generation of atomic vacancies as well as extra atoms. The result is adrastic reduction
of minority carrier lifetime, and achange in conductivity. Moreover, how conductivity
changes depends on the nature of the semiconductor material; that is, whether n-type,
p-type, silicon, germanium, and so on.

IMPURITIES
Conductivity can also be increased by adding impurities to the semiconductor
crystal when it is formed. This is often referred to as doping. And doping level refers
to the amount of impurities added. These impurities, added in the form of atoms,
replace a few of the existing semiconductor atoms that make up the crystal lattice
structure. An impurity atom, depending on its nature (see Table 2), may either donate
afree electron to the crystal structure or it may accept afree electron from another
atom in the structure.

N-Type Material
As shown in Figure 1.6 should the replacement impurity atom contain 5 electrons
in its valence band, four will be used to form covalent bonds with neighboring semi-
conductor atoms. The fifth electron is excess, or extra. It is therefore free to leave its
parent atom. When it leaves it does not leave behind aspace, or hole, since the four
remaining electrons join covalently with electrons of the neighbor atoms and thus
satisfy all localized valency requirements. The donor atom is therefore locked in posi-
tion in the crystal. It cannot move. With the loss of the electron the donor's charge
balance is upset causing it to ionize. The donor impurity atom, therefore, can be
viewed as afixed-in-position positive ion.

A
/
7 N
7 N.
N
7N ..
.7,r ,
7 .7 N 7

\ / \ /
V DONOR ATOM i
/
/ \ / \

N 7
7 fT N 7
7\
7 N 7 7
\ e'
\
\ ,i EXCESS \
ELECTRON
/\ /

N 7 N 7
N 7
N .>`..,
7 7 N ,..

N-TYPE MATERIAL
Figure 1.6 / N

10
 BASIC SEMICONDUCTOR THEORY 1

Since, in practice, imperfections exist in the crystal, to some extent holes also will
ex st. But since the electrons greatly outnumber the holes, the crystal is negative in
na ure and called n-type semiconductor. Inasmuch as electrons and holes are present
in the crystal, both will contribute to the conduction process. Electrons, predominating,
ar the majority carriers; holes the minority carriers.

P ype Material
Should, on the other hand, as shown in Figure 1.7, the replacement impurity atom
contain only 3electrons in its valence band, all three will be used up in covalent bonds
with neighboring semiconductor atoms. Since a lack, or deficiency, of one electron
p evails an empty space will exist causing one bond to be unsatisfied. This empty
s ace in the impurity atom's valence band is called a hole and is positive in nature.
ssuch, it is able to accept an electron from the crystal in order to satisfy the incom-
ete bond. As in the case of the donor atom, this action contributes to locking the
ceptor in its lattice position. It cannot move. The gaining of an electron upsets the
cceptor's charge balance causing it to ionize; thus, the acceptor impurity atom, like
edonor, can also be viewed as afixed-in-position ion, but one of negative charge.
ice, in this case, ahole has been generated elsewhere in the crystal, positive holes
redominate and the material is called p-type.

'I \
A
/ \

N. ..---
N N r
..,- / N
... V ..,
, N
K ....\
\ /
\ / ACCEPTOR
ATOM
/\
/ \

•••

I HOLE \ /
• / /(ELECTRON \ /
\/ DEFICIENCY)

/ / \

/N

P-TYPE MATERIAL

Figure 1.7

In p-type material, just as in n-type, both holes and electrons exist and contribute
to the conduction process. Holes, predominating, are the majority carriers; electrons
the minority carriers. With two oppositely charged carriers in existence in both nand p
materials, two conduction (current) paths of opposite direction must exist. Both are
of great importance to transistor action.
To summarize, solid-state conduction takes place in semiconductor crystals by the
movement of charge carriers known as holes and free-electrons. These holes and elec-
trons may originate either from donor or acceptor impurities in the crystal, or from
the thermal generation of hole-electron pairs. During the manufacture of the crystal,
it is possible to control conductivity and make the crystal either n-type or p-type by

11
1 BASIC SEMICONDUCTOR THEORY

adding controlled amounts of donor or acceptor impurities (Table 1.2). On the other
hand, thermally generated hole-electron pairs cannot be controlled except by vary-
ing the crystal temperature.

ELEMENT GROUP IN NUMBER

APPLICATIONS IN
(SYMBOL) PERIODIC VALENCE
SEMICONDUCTOR DEVICES
TABLE ELECTRONS

Acceptors 3 Trivalent (3), or acceptor, elements

are used to form p-type semicon-
ductors. A trivalent atom replaces
boron (B)
a quadravalent atom in the lattice
aluminum (Al) III C) structure; lacking one electron in
gallium (Ga)
its valence band the trivalent atom
indium (In)
is thus able to accept one electron
from a neighboring quadravalent
atom to produce a hole.

Semiconductors 4 Quadravalent (4) elements are basic

semiconductor materials. When
germanium (Ge) combined with controlled amounts
silicon (Si)
IV
- e- of trivalent or pentavalent mate-
rial, p-type or n-type transistor
crystal, respectively, is formed.

Donors 5 Pentavalent (5), or donor, elements

are used to form n-type semicon-
ductors. A pentavalent atom re-
,...., - places aquadravalent atom in the
phosphorus (P)
- Q'V lattice structure; containing an
arsenic (As) V
- - excess electron in its valence band
antimony (Sb)
it is thus able to donate one free
electron to the crystal lattice
structure.

MATERIALS USED IN THE CONSTRUCTION OF TRANSISTORS

AND OTHER SEMICONDUCTOR DEVICES

Table 1.2

TEMPERATURE

Carriers move through asemiconductor by two different mechanisms: diffusion or

drift. In either case temperature plays a singularly important part. Atomic activity is
said to cease at absolute zero, but this is only an assumption. At absolute zero tem-
perature (—273.185°C) afinite amount of kinetic energy is known to exist. This ever-
so-small activity is known as zero-point energy and in modern physics can be located
only by extremely involved methods. It is well known that charged carriers in semi-
conductor material are strongly influenced by temperature and that as temperature
increases so too does the atomic activity. Atomic movement and motion is ever present,
and the extent to which such activity and agitation occurs is only a matter of degree.
In any lattice structure where all atoms are strongly bound together by covalent
bonds, the atoms are continually shaking and vibrating in their lattice positions due

12
 M411•1111111111111 BASIC SEMICONDUCTOR THEORY 1

to thermal effects. It is important to keep in mind that the atoms, whether semicon-
ductor or impurity, at all times remain locked in their lattice position due to the
co aient bonds. Any motion of the atom, no matter how extreme, is a vibratory and
ela tic motion. The atom's position does not change unless aflaw exisits in the crystal.
Electrons moving in their orbits also vibrate and become excited with temperature.
W h continued temperature increase, their vibration becomes more violent to the
ex nt that those possessing the most energy, break loose from parent atoms and fly
ou into the spaces of the lattice structure. This is especially true of valence band
el ctrons, since by nature they possess more energy and can operate at higher energy
le els. When such an electron flies free, ahole is generated and any free electron may
joi this hole.
Too, as mentioned under Crystal Flaws, thermal effects are characterized by the
a sorption of the thermal waves which interfere with electron movement. If it were
p ssible to look into the crystal, a constant movement and motion would be seen;
a ion of a highly complex nature, not easy to visualize nor to depict. On a grand
s le, therefore, at any given temperature there is always atomic activity occurring
i semiconductor material; the lower the temperature the less the activity, the higher
tetemperature the greater and more violent the activity.

CONDUCTION: DIFFUSION AND DRIFT

DIFFUSION
Since many charge carriers are actively moving throughout the crystal, at any
ven location aconcentration of carriers may occur. Whenever there is a difference
i carrier concentration in adjacent regions of the crystal, carriers will move in a
rndom fashion from one region to another. Moreover, more carriers will move from
gions of higher concentration to regions of lower concentration than will move in the
pposite direction. In the simplest illustration, this permeation, or spreading out of
arriers, throughout the crystal is shown in Figure 1.8 and is known as diffusion. The
rocess is not easily explained in terms of a single electron's movement. It can be
ought of as a sporadic, or random, or unorganized electron movement when the
rystal is free from the influence of an electric field.
The action of diffusion is an omnipresent process in a semiconductor, dependent
nthe impurity content, and on temperature.
The principles of diffusion, that is, the atomic penetration of one material by
nother, are used in semiconductor manufacture to advantage, being widely used to
orm pn junctions in semiconductors. Briefly, the process consists of exposing ger-
anium or silicon to impurity materials known as diffusants, generally in a furnace.
Both time and temperature are of extreme importance, as well as the type of impurity
diffusant (indium, antimony, etc.) used. Since each diffusant exhibits an individual
diffusion constant (D), the time and temperature required for a diffusant to reach a
given depth of penetration into the semiconductor will vary. Indium, for example, is
aslow diffusant while antimony is much faster.

DR IFT
Even when subjected to an electric field the process of diffusion persists. The
action is somewhat more defined and orderly, however, in that the field's influence
causes charge movement to occur parallel to the direction of the field. This is often
referred to as drift mobility and implies both thermal and electric field influences
acting on the charge carriers.
Drift is aprocess that accelerates charge movement within the crystal. Should a
battery, for example, be connected across the crystal, adefinite and deliberate move-
ment of carriers will begin. Direction of movement will depend on the polarity of the

13
 1 BASIC SEMICONDUCTOR THEORY

CONCENTRATION

SPREADING

b,b(cfcf
—0 0 0-- e--
,0‘P?qa,

DIFFUSED

O0000

ace co

O0000

ELECTRON DIFFUSION IN SEMICONDUCTOR

Figure 1.8

electric field generated by the battery. Where before the fields existence carrier move-
ment was random and sporadic — and a more or less overall state of electrostatic
equilibrium existed — with voltage applied, equilibrium is upset; charge carriers are
influenced, and electrical conduction takes place. This is illustrated in Figure 1.9(B)
where asingle conduction path in n-type semiconductor material is shown. (Figures
1.9 and 1.10 are illustrative only. Since they are two-dimensional models, presented
to help explain ahighly involved, and in many cases difficult to explain theory, they
should not be taken too literally. )
All atoms, semiconductor and donor impurity, are locked in their lattice positions
by covalent bonds as shown in Figure 1.9(A). Atoms cannot and do not leave these
. fixed positions. Prior to closing the switch electrons are in acontinuous state of thermal
diffusion throughout the crystal. Closing the switch produces an electric field through-
out the crystal which influences the diffusing electrons to drift around the circuit.
Referring to Figure 1.9(B), as electron 1 enters the semiconductor through the
left negative ohmic contact, electron 4 simultaneously leaves at the positive end.
A balance is thus maintained between the crystal and the external circuit by this
equal exchange of electrons into and out of the crystal. Electron 1jqins the hole left
by the departure of electron 2 into conduction. Since the donor atoms contain extra
electrons, these are also freed into the conduction process, or conduction band, to roam
the crystal.
During this instant several things, all important to transistor action, happen: ahole-
electron pair is generated, free charge carriers (electron and hole) exist for alifetime
to produce a portion of the overall conduction process, and, free charge carriers
(electron and hole) unite together in recombination. Here, in essence, is the process
of conduction in a semiconductor — generation, lifetime, and recombination. (It is
important to keep in mind, that in this process, only the valence electrons possess the
ability to leave the valence bands of their parent atoms and roam throughout the

14
(A)
OHMICJ
CONTACT

BATTERY SWITCH
ELECTRON DRIFT
o o
H IM *

_...e -
-
.7
HOLE'S SEMICONDUCTOR ATOM
LIFETIME HOLE -ELECTRON
RECOMBINATION ,
/,-
3 , / \

BASIC SEMICONDUCTOR THEORY 1

N
A j /ICI I + I
' ELECTRON'S r.7,-. ,
LIFETIME I ,s /
(B)
3,e/
‘....,,..".
A '4 ,.
oror -- '7.)-.- ----,
'''•
HOLE-ELECTRON ,fi''
GENERATION /
;'«'—...
''',4, ..... ,k,...r •eere
ELECTRON I 2'lli \ \r;e1 \ EXTRA .. .,,--i.

ENTERS .- ... 5 \ /...... ;

:
: ‘N
r i,A
,,
,AL
NED NcE ELECTR ?. K
...1,/ EE
L LA
EVCE
TSRON 4

j + P
C .'. .---ELECT
EXTRR
AON \& ELECTRON IN-1
‘...._, /I CONDUCTION

?DONOR IMPURITY ATOM BAND

MAJOR+0+ELECTRON MOVEMENT IS TOWARDS POSITIVE TERMINAL, ELECTRONS

MOVE INTO AND OUT OF N-TYPE MATERIAL.

MINOR D HOLE MOVEMENT IS TOWARDS NEGATIVE TERMINAL. HOLE DOES NOT

LEAVE VALENCE BAND,

DRIFT IN N-TYPE SEMICONDUCTOR

Figure 1.9
 1 BASIC SEMICONDUCTOR THEORY
(A)
OHMIC
CONTACT

BATTERY SWITCH
ELECTRON DRIFT
- 111111 +
o 0

___,e 3
HOLE'S SEMICONDUCTOR ATOM
LIFETIME HOLE-ELECTRON
RECOMBINATION •
N i
I /i c I
ELECTRON'S / ,
LIFETIME ,"-rL-As
p-' ,
,
l' Ail :•-)
HOLE \
(B)
:
HOLE-ELECTRON ..,','3
'''•':: - - ...... GENERATION /'' - - •-•e, 4 ,s...re

2 r/ ' VALE CE 4 \ s ':-..: ,dr"'

/-
\ \ If
r, \N.4 4,.../

......-' \
\,,,,2 — El ANON
0 ‘,
I — le—HOLE \ ELECTRON IN-\
...
2 //
/ ....._ .../ CONDUCTION

LACCEPTER IMPURITY ATOM

MAJOR D HOLE MOVEMENT IS TOWARDS NEGATIVE TERMINAL. HOLE DOES NOT

LEAVE ATOM'S VALENCE BAND
MINOR .0., ELECTRON MOVEMENT IS TOWARDS POSITIVE TERMINAL. ELECTRONS
MOVE INTO AND OUT OF P-TYPE MATERIAL

DRIFT IN P-TYPE SEMICONDUCTOR

Figure 1.10
 BASIC SEMICONDUCTOR THEORY 1

cry I; holes, being what they are — electron deficiencies — remain at the level of the
val nce band. Holes, therefore, cannot and do not exist outside of semiconductor
material.) In Figure 1.9(B) hole activity can be better followed by starting with
ele tron 4leaving atom C.
lectron movement, then, is an actual movement from negative to positive around
the total circuit while hole movement is from positive to negative, but only inside
the crystal.
Figure 1.10 depicts conduction in p-material. As shown in Figure 1.10(A) all
se iconductor and acceptor impurity atoms are locked in their lattice positions by
co alent bonds. Since the impurity atoms are acceptors, holes predominate. Electrons,
although in the minority within the crystal, are still basic to the conduction process.
In Figure 1.10(B), starting at the positive terminal, hole movement can be followed
through the crystal towards the negative terminal. Note that the impurity atoms accept
el ctrons from some other bond in the crystal, thus causing the acceptors to ionize and
b come negative. These electrons moving to the acceptors leave other holes behind.
eprocess is not unlike that depicted for n-type material except that in p-material a
eater number of holes exist in the semiconductor to contribute to current conduction.
le migration, then, is from positive to negative in the crystal; while electron conduc-
ti n is from negative to positive. Just as in n-type material, conduction within the
c stal is by generation, lifetime, and recombination of charge carriers.
For the single conduction paths illustrated in Figures 1.9(A) and 1.10(B) it is
iteresting to note that if the electrons and holes are counted, keeping in mind that
eectrons 1and 4equal one charge,* the following results.

Electron Holes

1-2-3
n-type semiconductor
Major conduction Minor conduction

1-2--3 1-2-3— 0— 0
1 p-type semiconductor
Minor conduction Major conduction

Circled numbers indicate extra electrons

and holes.

PN JUNCTIONS (DIODES)
Connecting the p-type and n-type materials of Figure 1.9 and 1.10 in series with a
single battery, as shown in Figure 1.11, is no different — from the viewpoint of the
external circuit — than connecting two resistors in series, with one exception. The
nature of conduction within each semiconductor material will be different, as already
explained. In the case of Figure 1.11, as voltage is increased alinear relationship will
prevail in accordance with Ohm's law.
Should the center ohmic contact be removed and an actual contact made between
p and nmaterials, action both inside the crystal and as viewed by the external circuit
will then differ radically from Figure 1.11. This change of character is brought about
by the forming of p and nmaterials into apn junction. (Note the word "forming" is
used, not "connected." Reliable and efficient pn junctions cannot be made by placing
pieces of p and n materials together. Tightly pressing, or even welding the materials
allows only small area surface contact to be made. Too, the exposed surfaces can be
contaminated by airborne impurities. For optimum control of conduction, pn junction
structure must be single crystal in nature. This means that single crystal material must
be continuous from n material through the junction and into the p material. This is

17
1 BASIC SEMICONDUCTOR THEORY

ELECTRON DRIFT ELECTRON DRIFT

11111 +
OHMIC
CONTACT

MAJOR HOLE MINOR HOLE

DRIFT DRIFT

N
MINOR MAJOR
ELECTRON ELECTRON
DRIFT

ELECTRON DRIFT

P-TYPE AND N-TYPE MATERIAL CONNECTED IN SERIES

Figure 1.11

accomplished by chemical means. Suffice to say that pn junction fabrication is highly

complex and specialized, and beyond the scope of this Manual. Figure 1.12, therefore,
is illustrative only.)
Prior to the pand nmaterials being joined, atomic activity within each is random.
Figure 1.12(A) is representative of this state. Since holes predominate in the p mate-
rial and electrons in the n, each material — although electrically neutral unto itself —
will exist at adifferent charge level from the other because of differences in nature
and impurity content. When the two dissimilar materials form, as shown in Figure
1.12( B), an energy exchange occurs as the materials try to equalize. This exchange
is shown by electrons 1and 2 moving across to fill the holes in the p-type material.
At this instant of brief conduction the donor and acceptor atoms change their charge
states and ionize. This is shown in Figure 1.12(C). (It should be kept in mind that
this is a two-dimensional, highly simplified illustration, and all action is in reality
three-dimensional with many more charged carriers involved.)
The electrical neutrality of both p and n materials (existing at different charge
levels), upset by this brief but dynamic exchange of electrons, tend to align with
each other (alignment of Fermi levels). During the forming, hole-electron recombina-
tions readily occur, and as the action progresses alimited area empty of free charge
carriers is produced. This "no free-charge land" is called by many names: barrier,
depletion region, dipole layer, junction barrier, potential barrier and sometimes space
charge region. But mostly it is referred to as apn junction or junction diode.
It would seem that during this brief forming process that all existing free charge
carriers should combine. If this did occur, assuming equal impurity content, a single
piece of neutralized crystal would result; it would be neither p nor n in nature. After
afew recombinations take place in the vicinity of the junction area, and a"no free-
charge land" produced, conduction decreases as an electric field builds up, generated
by — and located between — the newly created positive ions in the n-type material
and negative ions in the p-type material. Figure 1.12(D) attempts to illustrate the pn
junction after forming.
Total recombinations cannot occur, however, because of thermal generation of
hole-electron pairs, hole-electron recombinations, and the effects of recombination
centers and trap imperfections. All combine in a highly complex process to bring
about a barrier balance. The eventual culmination of this forming process can be
viewed as abalance of major and minor conduction currents as shown in Figure 1.13(A).
Perfect barrier balance is never completely possible because of external influences.
Much like the balancing of aset of delicate scales when astate of equilibrium exists,

18
 BASIC SEMICONDUCTOR THEORY 1

P-TYPE N-TYPE

ACCEPTOR ATOMS
DONOR ATOMS
PRE )0MINATE
PREDOMINATE

(A) PN JUNCTION JUST BEFORE FORMING

HOLE-ELECTRON 2 2 ELECTRONS 182

ELECTRONS Ia2 RECOMBINATION ,_ FLY FREE INTO
JON HOLES IN EXTRA ELECTRONS CONDUCTION BAND
LEAVE VALENCE BAAOS
VALENCE BAND CAUSING DONOR
CAUSING ACCEPTOR ATOMS TO BECOME
ATOMS TO BECOME POSITIVE (+) IONS
NEGATIVE (—) IONS

(B) PN JUNCTION AT INSTANT OF FORMING

POSITIVE
NEGATIVE REGION
REGION

(C) PN JUNCTION AFTER FORMING

ELECTRIC JUNCTION
FIELD CAPACITY

— •ss
‘.•

o+o,oeoeoo IMPERFECTIONS,
.1 (RECOMBINATION

+0000000e
CENTERS, TRAPS,
ETC.)

(3"de eeeCe
DONOR ATOMS

ACCEPTOR ATOMS

1-9(*)ooGo"c5 SEMICONDUCTOR

pdisoo00_e-
ATOMS
+ HOLES

— ELECTRONS
(D) PN JUNCTION
AT REST
EQUIVALENT
BATTERY

1
k— DEPLETION REGION
FREE CHARGES EXIST
DURING EQUILIBRIUM

PN JUNCTION FORMING

Figure 1.12

19
 i
MINOR I MINOR
MINOR I MINOR
REVERSE GENER-

MIOSHI 110IDIICINODINISS DISV£1

MINOR , MINOR REVERSE ELECTRON I HOLE
REVERSE GENERATION CURRENT ELECTRON I HOLE GENERATION ATION
LEAKAGE ELECTRON, HOLE LEAKAGE
Is 4-1
• Is
Is *
RECOM-
FORWARD
FORWARD FORWARD
MAJOR
414' MAJOR RECOMBINATION
CURRENT MAJOR , MAJOR BINATION
IF HOLE jELECTRON
CURRENT MAJOR I MAJOR RECOMBINATION CURRENT HOLE ELECTRON
IF HOLE ELECTRON IF
BARRIER UNBALANCED
BARRIER UNBALANCED
BARRIER BALANCED
E
F EE
LC I
DTR C

ELECTRIC FIELD JUNCTION

JUNCTION BARRIER HIGHER BARRIER
CAPACITY
CAPACITY LOWER
LARGER
SMALLER N

BARRIER,/ LL...EQUIVALENT
NARROWS E
- + BATTERY
- OHM C
-"I
I+EQUIVALENT SMALLER
BATTED'
CONTACT LARcityt 1
1111
1

4— • 4—
ELECTRON
ELECTRON ELECTRON
ELECTRON DRIFT DRIFT
DRIFT DRIFT

+ IF + IF

rf L
A V
IF LOW

V IF
, HIGHLY
EXAGGERATED
+V
V +V
av
Ge -I s re
aI s HIGH Ge -Is
-I s (
C)FORWARD BIAS
(B)REVERSE BIAS
(A) NO BIAS

PN JUNCTION BIAS

Figure 1.13
 BASIC SEMICONDUCTOR THEORY 1
so it is with apn junction. Although adepletion area exists, and in theory no charge
mi vement across the barrier is taking place, in reality the barrier balance is such that
oc asional charge carriers do diffuse to opposite regions to cause opposing currents
to exist. At any instant currents may be equal or unequal in magnitude since tempera-
tu eis always present.
J NCTION CAPACITY
With each side of the barrier at an opposite charge with respect to the other, each
si e can be viewed as the plate of a capacitor. In short, the pn junction possesses
c pacity. As illustrated in Figure 1.13 junction capacity changes with applied voltage.
F gure 1.14 graphically shows junction capacity variation with reverse voltage for two
dfferent device junctions.
Depending on the application, junction capacity can be an advantage, or adetri-
ent. To illustrate the former, the FM Tuner in Chapter 15 uses areverse biased 1N678
ti accomplish Automatic Frequency Control (AFC) of the oscillating converter. The
dode, in this case, is being used as adc voltage controlled variable capacitor. As a
riment, in high frequency amplifier applications where small capacity effects are
ore apparent, the same junction capacity would not be desirable since it limits the
tansistor's upper useful frequency of operation. Further, in intermediate and high
fequency amplifier applications excessive collector-base capacity can cause positive
fedback and undesirable oscillation. On the other hand, should the capacity be such
tat it is within the limits of the associated tuning circuit's required LC ratio, it might
e used to advantage as part of the capacitive component. Chapter 2 discusses in
eater detail device capacities in general, and their effects on high frequency
erformance.
The barrier's electric field is often referred to — and can be visualized — as aspace
harge equivalent battery. Since the field spans a specific distance it is said to have
idth, and since the field possesses an intensity it is said to have height. These effects
an be expressed in volts. A pn junction made from germanium, for example, can be
hought of as having an equivalent battery field voltage of about 0.3 volt; a junction
ade from silicon, about 0.6 volt. Both the width and height can be changed by
pplying an external voltage to the crystal. Herein lies the real importance for the
xistence of the pn junction in its relation to external circuitry. Depending on the
• larity of the applied voltage, the crystal will either pass or block current. In short,
twill rectify.
UR RENT FLOW
In the field of electronics one of the first great bewilderments of many students is
that of current flow. Not necessarily the physics of it, but its direction. One school of
thought has current flowing in the direction of electron drift, negative to positive.
Another has agreed that current flows positive to negative. This is known as conven-
tional current flow. The fact that two different and opposing flow directions are recog-
nized in electronics has always been confusing for students in general to cope with.
The arrival of the transistor compounded the confusion since it brought with it current
flow by hole movement, from positive to negative. Add to the foregoing such diverse
terms as: forward current, reverse current, saturation current, leakage current, etc.,
and it is understandable why semiconductors on first encounter can be confusing.
The question itself of "which way does the current flow?" is academic. In practical
circuit design it can even be atrivial consideration, except where accurate communica-
tions is involved; of real importance is that one try to be consistent. Consistency is
not always easy, however, when dealing with the semiconductor "world of opposites."
DIODE "CONCEPT"
With the "opposite" natures of npn and pnp transistors, the opposite voltage polari-

21
1 BASIC SEMICONDUCTOR THEORY

1.0

o
a.
4
-t-
o

0.90

IN3604 AN D IN 3607
o (S ILICON)
o
a TYPI CAL CAPA CITAN CE
VS
REVER SE VOLTAGE

0.80

(A)
0.01 0.10 I0 10 100

VR -VOLTS

ANODE NEGATIVE ,CATHODE POSITIVE

18

Cob VS Nice
16 2N2711, 2N27 I
2
(
SILICON EPDXY NPN )
•0
TA •25• C
f•IMC

(8)

2 4 6 8 10 20

Vc B IN VOLTS

COLLECTOR POSITIVE W I
TH RESPECT TO BASE

TRANSISTOR AND DIODE JUNCTION CAPACITY

Figure 1.14

22
 BASIC SEMICONDUCTOR THEORY 1

tie each require, and the opposite natures of hole and electron movement taking place
hin atransistor at the same instant, it is not surprising to find even seasoned circuit
d igners, especially in their first encounters with solid state devices, bewildered with
tr nsistor action. One way to overcome this first confusion and induce some sense into
p ctical circuit work is to apply the "diode concept" approach as an aid. This pre-
cl des, however, thinking in terms of charge carrier movement, for the moment at
le st, and requires visualizing by conventional current flow, positive (±) to negative
( ). The "diode concept" presents apn junction as shown in Figure 1.15.

ANODE IS
ALWAYS POSITIVE
ANODE P-MATERIAL ANODE

CATHODE
CATHODE CATHODE IS
ALWAYS NEGATIVE
N-MATERIAL

PN JUNCTION 'DIODE CONCEPT" DIODE SYMBOL

BLOCK DIAGRAM

"DIODE CONCEPT" OF PN JUNCTION

Figure 1.15

It is only necessary to keep in mind

1. Anode is always positive pmaterial.
2. Cathode is always negative nmaterial.
3. Conduction (passing of current) occurs when positive potential is applied
to positive p anode and negative potential to negative n cathode (forward
bias ).
4. Blocking occurs when negative potential is applied to positive p anode and
positive potential to negative nmaterial (reverse bias).
Figure 1.16 illustrates these simple points.

I. FLAWS I' BLOCKED

(A) FORWARD (8) REVERSE

BIAS OF PN JUNCTION

Figure 1.16

BIAS: FORWARD AND REVERSE

At this point it would be helpful to replace the junction diode, which, it should
be remembered is aunilateral (one-way) device, with a resistor, which is a passive
bilateral (two-way) component. The electrical difference between the two can be
shown by graphically plotting voltage vs. current.

23
1 BASIC SEMICONDUCTOR THEORY

Connecting a 1000 ohm resistor in the simplest form of electric circuit, a series
circuit, using acurrent meter (or a zero center galvanometer), and a 1volt power
supply, acurrent will flow causing the meter to deflect to I= E/R = 1/1000 = 1ma;
should the battery polarity be reversed and asecond reading taken, the current flow
would again cause the meter to deflect to 1ma, but in the opposite direction. Record-
ing aseries of voltage vs. current readings from zero voltage, first with the battery
connected in one direction, say the forward direction; then in the opposite direction,
say the reverse direction, will show alinear relationship between voltage and current.
This is illustrated in Figure 1.17. As shown, whether the resistor is forward or reverse
biased, alinear plot results. The variable battery, in theory at least, sees an unchanging
positive resistance of 1000 ohms. This is not true, as shown in Figures 1.13( B,C )and
1.17, when apn junction diode is subjected to forward and reverse voltages.

+ I, FORWARD BIAS

IF
Ge

Si I

RESISTOR

REVERSE
BREAKDOWN 1.0V
+V,

IMA 0.3 V as v ov
1. l
100011
e RESISTOR

REVERSE BIAS

DC CHARACTERISTICS OF RESISTOR ,GERMANIUM

DIODE ,AND SILICON DIODE UNDER INFLUENCE OF FORWARD
AND REVERSE BIAS VOLTAGE

Figure 1.17

Figures 1.13(B,C) and 1.17 represent the classical semiconductor diode curve. As
with other phenomena of the physical sciences, the pn junction is also governed by
natural laws of growth and decay. Charge diffusion across the barrier, charge lifetimes,
charge concentration, and temperature, all influence the shape of the curve. As with
many of the other phenomena in nature, the pn junction curve, under conditions of
variable bias, is characterized by "natural" logarithms, and the following well known
pn junction equation applies.
I
F= Is (eel"— 1)
where
I
F= forward current
= reverse, or saturation current
e= natural log 2.71828
q= electron charge 1.6 x 10 -'coulomb

24
 BASIC SEMICONDUCTOR THEORY 1

V = applied bias voltage

K = Boltzmann's constant (1.38 X 10 watt sec/°K )
T = absolute temperature in degrees Kelvin (at room temperature K = 300)
troom temperature the exponent KT/q = 0.026 volt, thus
IF= Is (e°•°"v— 1)
orward bias corresponds to positive values of V while reverse bias conditions corre-
s ond to negative values of V. In the case of reverse bias (negative V) the exponential
trm will diminish. Since the barrier is widened and charge movement at aminimum,
rrent flow will be small and relatively fixed by thermal energy absorbed by the
stal; for this reason Is is often referred to as reverse saturation current since it is a
xed variable, controlled only by design of the junction and thermal influences. IFwill
t erefore diminish towards zero, and Is remain relatively constant. With IF zero, Is
s all, and negative bias V large, the junction resistance will be very high.
With forward bias (positive V) the exponential term rapidly increases. This
auses I Fto take on the classical "natural" look. With I Flarge and V small, the junc-
ton resistance will be correspondingly very small. In practice Is is considered a
akage current tending to subtract from Ir. In germanium, reverse leakage is about
000 times greater than in silicon.

TRANSISTOR
If it were possible to simulate the circuit in Figure 1.18, useful work could be per-
rmed. Connecting resistor RI in series with the 10 volt battery by placing the switch
' position A would cause an ampere of current to flow, resulting in a power dissipa-
on in RI of 10 watts. If, when throwing the switch to position B, the same 1ampere
ould be made to flow through R2, a hundred-fold gain in power dissipation would
esult. Forgetting the drop in R1 and concentrating on R2, if R2 were in a position
offer alarge portion of the dissipated power to an external load where useful work
ould be performed, Figure 1.18 could be considered an active circuit because of its
bility to amplify power. This, in effect, is accomplished by the transistor.

RI =100 R2=10000

E 10
- - IAMP P2 I2 R2
RI 10
= 12 X 1000.1000 WATTS
E=I0V Pk I2RI
1000
=1
2 X10.10 WATTS
4,A POWER GAIN -
P
P21 = .100
10
' B

TRANSFER + RESISTOR = TRANSISTOR

Figure 1.18

By placing a second pn junction adjacent to the first, with the connecting semi-
onductor material common to both junctions, as shown in Figure 1.19, and by
orward biasing one junction and reverse biasing the other junction, the conditions
power gain are possible. Depending on which side of the existing pn junction the
econd junction is formed, will determine the transistor's type, PNP or NPN. And as
hown in Figure 1.20 the type will determine the polarity of the bias voltages. Figure
.22 shows the generally accepted circuit symbols used for NPN and PNP transistors.

25
1 BASIC SEMICONDUCTOR THEORY

MINOR I MINOR u MINOR GENERATION

ELECTRON1 HOLE ELECTRON
a a

MAJOR I MAJOR MAJOR RECOMBINATION

HOLE I ELECTRONI HOLE

BARRIERS BALANCED

OHMIC
CONTACT

(A)

MINOR MINOR ! MINOR GENERATION

HOLE ELECTRON' HOLE

MAJOR I MAJOR I MAJOR RECOMBINATION

ELECTRONI HOLE ELECTRON

BARRIERS BALANCED

JUNCTION
TRANSISTOR

Figure 1.19 OHMIC

CONTACT

(13)

Transistors operate by the mechanisms of injection, diffusion, and collection. It

will be noted in Figure 1.20 that the three elements are labelled emitter, base, and
collector, regardless of type. Should the emitter-base portion of the transistor be for-
ward biased, adrift-movement of charges will begin. Majority carriers, holes or elec-
trons, depending on the transistor type, will enter the base region to recombine with
opposite carriers. In effect these majority carriers can be thought of as being emitted
from the emitter and injected into the base region. Those charges escaping recombina-
tion near the junction area will penetrate further into the base region. Once in the
base, carriers spread out by the process of diffusion. Applying areverse bias of sufficient
magnitude from collector to base, as shown, will cause the carriers diffused throughout
the base region to continue into the collector region. Majority carrier movement will
therefore have taken place, originating within a low resistance region (emitter-base
junction) and by diffusion and collection through a high resistance region (base-
collector junction). The transistor therefore meets the conditions of Figure 1.18.

26
 BASIC SEMICONDUCTOR THEORY 1

EMITT ER BASE COLLECTOR

N P 2
REVERSE LEAKAGE
Is

FORWARD CURRENT
ROLES DIFFUSE THRU BASE TO COLLECTOR
o
•._
IF
2
PA RT OF MAJOR MAJORITY OF HOLE S INJECTED
HOLES CO M BI
NE I
NTO BASE, DIFFUSE THROUGH
WITH ELEC TRONS AN D COM BI
NE WITH ELECT RONS
TO PRODUCE FROM BATTE RY.HIGH NEGATIV E
EMITTER- BASE
POT ENTIAL ATTRACTS HOLES.
CURRENT.

REVERSE
BIAS

ELECTRON EL ECTR ON
DRIFT DRIFT

I
..'

EMITTER BAS E COLLECTOR i'

N P I N g.'
. L...
REVERSE LEAKAGE I I
I I
I I.
I V)

FORWARD CURRENT
ELECTRONS DIFFUSE THRU BASE 1
D COLLECT. 2
•
`,

PART OF MAJOR MAJ OR I

TY OF ELECTRONS I
N JECTED
ELECT RONS COMB IN E I
NTO BASE, DIFFU SE THROUGH AND
W ITH HOLES CO MBI
NE WITH HOLES GENERATED
TO PRODUCE BY ELECTRONS LE AVI NG COLLECTOR.
EMITT ER-B ASE HIGH POS I
TIV E POTENTIA L AT TR ACTS
CURRENT DIFFU SE D ELECTR ONS.

REVERSE
BIAS

ELECTRON ELEC TRON

DRI rT
DRI
FT

BIASED JUNCTION TRANSISTOR

(COMMON BASE CONNECTION)

Figure 1.20

27
 L
COMMON BASE (CB) COMMON EMITTER (CE) COMMON COLLECTOR (CC)

A.110aHl 110IDIKINODINUS DISVa

..--

a
N P N
L E' I IE.aI E
i+ COLLECTOR N EMITTER N
—. EMITTER
1 BASE COLLECTOR

+
TRANSISTOR - REVERSE FORWARD - - -

AS A DEVICE T
- 1
FORWARD j
18. REVERSE 'B.-
1-0
BASE P -4
+ I,
BASE P

- ---'
_ - - - - - REVERSE _...-
FORWAR D
(ARROWS INDICATE +1 COLLECTOR N
e
- EMITTER N
ELECTRON CURRENT +
FLOW. LOADS NOT a. 78 * o* (SEE TEXT)
- I lI c
SHOWN )
h FB ' I C/ 'E E 1- +

I,=IE - IB e
-

I, = IE - IB I, =IE - IB
h FE 'Sr IC/I Et h FC = 'E R B

V CB V BE
,..- CE V

BAS IC TRANSISTOR ., '\ RL *\

R
V,
CIRCUITS , IR+L 4.
V CE + -
\
SHOWING SIGNAL - () BE l V„ -

-......- " —
V
a
SOURCE AND LOAD (R L ) +T , - + +
_ ,.

(n YES
(-) POWER GAIN * YES YES (HIGHEST)
YES (APPROX. SAME CE) YES NO (LESS THAN UNITY)
VOLTAGE GAIN *

CURRENT GAIN NO (LESS THAN UNITY) YES YES

1 *

LOWEST ( L. 500 ) INTERMEDIATE (.-: 1.0K ) HIGHEST (e 300K)

b INPUT IMPEDANCE *
a INTERMEDIATE (e- 50K) LOWEST (2 3000)
(X OUTPUT IMPEDANCE * HIGHEST (a 1.0 MEG.)
a
x PHASE INVERSION NO YES NO
o
re re r rc re e
SIMPLE T-EQUIVALENT
NETWORK OF TRANSISTOR INPUT OUTPUT
IN PUT r OUTPUT INPUT r OUTPUT r
(DC ONLY -SEE CHAPTER
2 FOR SMALL - SIGNAL 8 o o
HIGH FREQ. EQUIV. CIRCUITS)

* DEPENDS ON TRANSISTOR, TERMINATIONS, ETC.

TRANSISTOR CIRCUITS AND CHARACTERISTICS

Figure 1.21
 BASIC SEMICONDUCTOR THEORY 1

Since the transistor is athree element, three lead device it is possible to use it in
•y of three different, and useful, configurations. The identification of each of these
idividual circuits is derived from the element "common" to both input and output.
•igure 1.21 illustrates this, showing the three configurations: common base, common
itter, and common collector; an often used variation is "grounded" emitter,
grounded" base, etc., since the common element is usually returned to the signal
ound point in acircuit.

LPHA
Since fewer carriers reach the collector than leave the emitter region, the collector
•
urrent IEwill be less than the emitter current I E. The ratio Ie/ I
E defines the total
orward current gain of the transistor as viewed from an external circuit, and is called
pha (a). This parameter is seldom greater than 1, and in practice falls between 0.95
obetter than 0.99.
Within the device several mechanisms contribute to the transistor's a. First, and of
eat importance in controlling alpha, is the emitter efficiency -y, i.e., how efficiently the
•
mitter injects carriers into the base region. The greater the forward emitter current
oving from emitter to base, in contrast to opposing "leakage" current, the higher y
11 be. This is brought about by agreater concentration of majority carriers existing
nthe emitter than are present in the base region.
A second mechanism contributing to the transistor's overall a is called the base
ransport factor p*. As carriers diffuse through the base after being injected from the
emitter, some will recombine in the base to form base current In. These carriers can be
•nsidered lost since they will never reach the collector region. If few recombinations
are to occur in the base region, either the diffusion length of the injected carriers must
be such that they penetrate across the base to the collector region, or the width of the
base must be made narrower. Base width as it relates to carrier penetration is therefore
critical if the greatest number of carriers injected into the base are to reach the col-
ector region. Transport factor #* is also acontrollable mechanism of importance in
transistor action.
The mechanism of carrier collection by the collector region is known as collector
multiplication factor a*. In general, it gives an indication of the level of current injec-
tion from base to collector region and is afunction of the relationship existing between
majority carriers present in the collector to those being injected. Normally, a* is
equal to unity.
By proper selection of each mechanism, through control of the nature and size
of pand nmaterials that make up the transistor, the ais controllable.
Alpha (a) is sometimes called dc alpha, or ar, to indicate forward current transfer
ratio, the de current gain of the device itself. Since this is astatic de measurement, it
tells little of the gain or impedance characteristics of the transistor when subjected to
signal conditions in an actual circuit. It does, however, offer some indication as to the
merit of the transistor as an active device; that is, whether it is capable of power gain.
Under dc conditions, de alpha (ar) is usually designated an; for the common-base
configuration. The capital letters F and B point out that static dc conditions prevail,
and that the forward current gain of acommon-base circuit is being defined. By the
matrix method of circuit analysis small-signal gain is abbreviated hfb, and sometimes
as hfi. This is discussed in Chapter 2.

BETA
As shown in Figure 1.21 for the common-base circuit, if the emitter current
1E = 1and I E = a the base current Ill = 1 — a. Connecting the transistor into a

common-emitter configuration and feeding signal into the base, forward gain would

29
1 BASIC SEMICONDUCTOR THEORY

then be

lc = a As an example, if a= .99, 99
1— a — .99 .01
thus the CE configuration is more useful in that it produces more gain than the common-
base circuit. The a/1 — aratio is referred to as beta, or p. The static de forward current
gain of atransistor in the common-emitter configuration is designated as "de beta," Pp,
1121 E ,or hFE. The latter two terms come from the matrix method of circuit analysis.

It should be noted that if a is high, the base current term 1 — a is quite small.
Therefore, the higher the transistor's alpha, the higher the impedance looking into the
base of a common-emitter configuration. Hence, by virtue of its combination of high
input impedance and high gain, the common-emitter configuration more readily meets
general amplifier requirements. (Chapter 6 discusses frequency limitations of CB and
CE configurations under Gain Bandwidth Product.)

BASE-EMITTER BIAS ADJUSTMENT

A useful rule-of-thumb common to both NPN and PNP transistors is presented in
Figure 1.22 for adjustment of base-emitter bias. Difficulty is often encountered in the
first practical transistor circuit work in recognizing that
1. Moving the base towards the collector voltage supply turns the transistor on.
2. Moving the base away from the collector voltage supply turns the tran-
sistor off.

TURNS
TRANSISTOR RL
ON
IN-COLLECTOR

:
P-BASE

N-EMITTER
TURNS
TRANSISTOR
OFF

NPN DI ODE "CONCEPT " NPN SYMBOL

(A)

TURNS
TRANSISTOR
ON
.11P-COLLECTOR SI
GNAL
OUT
IN-BASE VŒ

JI
P-EMITTER

TURNS
TRANSI STOR
OFF

PNP DIODE "

CONCEPT " PNP SY MBOL

(B)

BASE-EMITTER BIAS ADJUSTMENT TURNS TRANSISTOR "ON" OR "OFF"

Figure 1.22

As shown in Figure 1.22(A) by the "diode concept" method, when the base con-
nected slider A is moved toward the positive voltage supply, the anode of the base-
emitter diode goes positive with respect to the cathode. Since this forward biases the
diode, it conducts (IB) and the transistor turns on allowing collector current (1c) to

30
 BASIC SEMICONDUCTOR THEORY 1

ow. Moving slider A away from the positive supply voltage decreases forward bias
cross the base-emitter diode causing the diode, hence the transistor, to turn off.

RANSISTOR SWITCH
When turned fully on, the transistor is said to be operating in the saturation region.
hen turned fully off, it is said to be operating in the cut-off region. (The region be-
epn is often referred to as the transition region.) The transistor can therefore be
sed as aswitch by simply biasing the base-emitter diode junction off (cut-off) or on
(saturation). Chapter 6offers adetailed discussion of Switching Characteristics.

RANSISTOR AMPLIFIER
Adjusting base-emitter bias to some point approximately midway between cut-off
and saturation will place the transistor in the active, or linear, region of operation.
When operating within this region, the transistor is able to amplify. Figure 1.23 locates
the cut-off, active, and saturation regions of transistor operation on a typical set of
collector characteristic curves. For amplifier operation, base-emitter de bias will be
approximately 0.3 volt for germanium and 0.6 volt for silicon, shown as point B in
Figure 1.17.

.%50m 0

B . 04 0
ee4,411°0
.qz r e ,sks
•
Dc, *re ' 4e 6i
e, ipe a 04,
4,s, 4 sék,

eci'4>fre-
r ,,s,
18 .50iO3 .

I.25µ1:1
MUMIMI C ,
•0
1
4 s s 10 12 14
COLLECTOR VOLTAGE v„ IN VOLTS

CUT-OFF REGION
(TRANSISTOR TURNED OFF-I, LOW, I, LOW, Vc,

TYPICAL COMMON-EMITTER COLLECTOR CHARACTERISTICS

Figure 1.23

SYMBOLS AND ABBREVIATIONS

Chapter 2 discusses the transistor as asmall-signal low and high frequency device.
It should be noted that parameter symbols differ from those in Chapter 1where only
de conditions are considered. Inasmuch as the transistor encounters a variety of elec-
trical conditions, avariety of symbols is necessary to describe these conditions. Direct

31
1 BASIC SEMICONDUCTOR THEORY

current, no signal conditions — as discussed in this chapter — are defined by all capitals;
ac rms signal conditions by capital and lower case subscripts; instantaneous conditions
use all lower case letters. Examples of this mixture follows.

DIRECT CURRENT ALTERNATING CURRENT ALTERNATING CURRENT

(no signal) (rms conditions) (instantaneous conditions)

I
B, VCR, L:, etc. Ib, V,b, I„ etc. lb, v.13, h, etc.

More complete information on Letter Symbols and Abbreviation for Semiconduc-

tors is given in Electronic Industries Association (EIA) document RS-245. This is
available from the Engineering Department of EIA, 11 West 42nd Street, New York
36, New York, at anominal cost. Additional symbol information is presented in Chap-
ter 19 of this Manual.

LEAKAGE
As previously mentioned, the real importance of the pn junction is its ability to
pass or block current flow; that is, to function as aunilateral device. But this suggests
aperfect junction. In practice this is not the case.
Generation of hole-electron pairs by thermal influences causes a reverse leakage
to exist in any pn junction. Referred to as either Ico or IcBo in transistors (measured
from collector-to-base with emitter open, hence subscript CBO), leakage is generated
in four ways.
One component originates in the base region of the transistor. At any temperature,
a number of interatomic energy bonds will spontaneously break into hole-electron
pairs. When avoltage is applied, holes and electrons drift in opposite directions and
can be seen as Ico current. When no voltage is present, the holes and electrons
eventually recombine. The number of bonds that will break can be predicted theo-
retically to double about every 10°C in germanium transistors and every 6°C in silicon.
Theory also indicates that the number of bonds broken will not depend on voltage over
aconsiderable voltage range. At low voltages, Ico appears to decrease because the drift
field is too small to extract all hole-electron pairs before they recombine. At very high
voltages, breakdown occurs.
A second component of Ico is generated at the surface of the transistor by surface
energy states. The energy levels established at the center of asemiconductor junction
cannot end abruptly at the surface. The laws of physics demand that the energy levels
adjust to compensate for the presence of the surface. By storing charges on the surface,
compensation is accomplished. These charges can generate an Ico component; in fact,
in the processes designed to give the most stable Ico, the surface energy levels con-
tribute much Ico current. This current behaves much like the base region component
with respect to voltage and temperature changes. It is described as the surface
thermal component in Figure 1.24.
A third component of la) is generated at the surface of the transistor by leakage
across the junction. This component can be the result of impurities, moisture, or surface
imperfections. It behaves like aresistor in that it is relatively independent of tempera-
ture but varies markedly with voltage.
The fourth component of Ico is generated in the collector depletion region. This
component is the result of hole-electron pair formation similar to that described as the
first Ico component. As the voltage across the collector junction is increased, the deple-
tion region will extend into the base and collector regions. The hole-electron pairs
generated in the base portion of the depletion region are accounted for by the first Ico
component discussed, but those generated in the collector portion of the depletion

32
 BASIC SEMICONDUCTOR THEORY 1

BASE CONTACT
S,ICON DIOXIDE SURFACE
LAYER EMITTER THERMAL Ico
CONTACT

SURFACE
LEAKAGE
CURRENT

DEPLETION
REGION IN
COLLECTOR COLLECTOR

• = HOLE COLLECTOR DEPLETION

O = ELECTRON
LAYER COMPONENT OF 'co
==INDICATES DIRECTION OF
CARRIER DRIFT

CROSS SECTION OF NPN PLANAR PASSIVATED

TRANSISTOR SHOWING REGIONS GENERATING 1(..
(A)

NOTE.
CURVES A INDICATE THE BASE REGION Ico
CURVES B INDICATE THE SUM OF BASE REGION
AND SURFACE THERMAL Ica
CURVES C INCLUDE THE SURFACE LEAKAGE
COMPONENT
CURVES D INCLUDE THE COLLECTOR
DEPLETION REGION Ico
AND INDICATE THE MEASURED Ica

BREAKDOWN
LOW VOLTAGE VOLTAGE
REGION REGION 'co o 65°C
COLLECTOR
DEPLETION
REGION Ica

SURFACE
THERMAL
'co

'co

/1 II

....SURFACE I /
I u/I
/
LEAKAGE I/
íI
GON
REGION
COLLECTOR VOLTAGE COLLECTOR VOLTAGE

VARIATION OF h, COMPONENTS VARIATION OF I., COMPONENTS

WITH COLLECTOR VOLTAGE WITH TEMPERATURE
(e) (C)
Figure 1.24

region are not included. The number of pairs generated in the collector portion of the
depletion region and, thus, the from this region depend On the volume of the
depletion region in the collector. Inasmuch as this volume is a function of collector
and base resistivity, of junction area, and of junction voltage, the fourth component
of In, is voltage dependent. In an alloy transistor, this component of leo is negligible

33
1 BASIC SEMICONDUCTOR THEORY

since the collector depletion layer extends only slightly into the collector region due to
the high base resistivity and low collector resistivity. In a mesa or planar structure,
where the collector region is not too heavily doped, the depletion region extends into
the collector, and this fourth leo component may be appreciable. Since this mechanism
of Ico generation is hole-electron pair formation, this component will be temperature
sensitive as well as voltage dependent.
Figure 1.24(A) shows the regions which contribute to the four components. Figure
1.24(B) illustrates how the components vary with voltage. It is seen that while there is
no way to measure the base region and surface energy state components separately,
alow voltage ¡co consists almost entirely of these two components. Thus, the surface
leakage contribution to ahigh voltage ¡co can be readily determined by subtracting
out the low voltage value of Ico, if the collector depletion layer contribution is small.
Figure 1.24(C) shows the variation of ¡co with temperature. Note that while the
surface thermal component, collector depletion region component and base component
of ¡co have increased markedly, the surface leakage component is unchanged. For this
reason, as temperature is changed the high voltage 'co will change by asmaller per-
centage than the low voltage Ico.
Figure 1.25 shows typical variation of ko (Ingo) with temperature for germanium,
voltage and temperature for silicon.

.0

lcDo VS TEMPERATURE
NORMALIZED DuRvE
40.•-3V TOP 1,0 .4 25,A)

4,±Z525.reasr5Z1
UN6

44411 •
2.113

401
/1
(TYPICAL) •25µ4
T.,..(MAX) 10µ0 2413!1:4
03,3041

ic.. RS TEIPPERATWIE
(SILICON TYPES)

-40 -40 -40 o • o .40 •40 .44 One

1/1 •C
PO 11 eeo
COLLECTOR CUTOFF CURRENT VS
TEMPERATURE NORMALIZED TO 25°C P.P. 111 •C

REVERSE LEAKAGE VS. TEMPERATURE

Figure 1.25

BIAS STABILITY
In actual transistor circuit design one of the more important aspects of the design
is dc biasing (see Chapter 4). Since stable circuit operation is highly dependent on
temperature, thermal influences that may effect the transistor and therefore circuit
performance must be considered in design of the dc bias circuit.

34
 BASIC SEMICONDUCTOR THEORY 1

The three most important transistor parameters to be considered are de forward

current gain hFE, reverse leakage ken, and base-emitter voltage VB.. All vary with
temperature. All effect bias stability and must be accounted for if stable operation is
to result.
Figure 1.26 shows typical variation of de current gain hr., and ac current gain hf.
vs. temperature. Since de gain hrE is here defined as I c/IB, and since Ic is approxi-
mately equal to hp. (In ± Ico), it can be seen that FIFE is dependent on Ico. (IBrepre-
sents the current measured if an ammeter is inserted in the base.) If the base is open
circuited (I n = 0), collector current will continue to flow of magnitude Ic = hrB OPEN ICOt
since Ico is diverted through the emitter. The hFre OPEN term is defined as aN/1 — aN
where aN (alpha N) is the ratio of collector to emitter currents with zero collector to
base voltage, at an emitter current approximately the value of hPE OPEN Ico. As defined
here, hpE is infinite when I II = O.Dc gain hFE will rapidly increase with temperature
because of Ico.
In contrast, ac current gain hr. is relatively independent of Ire and generally in-
creases about 2to 1from —55° to +85°C. Figure 1.26 illustrates the variation of both
hi, and hr. with temperature.
MAGNITUDE OF hFE AND ht. COMPARED TO 25°C VALUE

2.6

24 AC —DC
CURRENT GAIN
2.2 VERSUS
TEMPERATURE h FE
2.0 FOR 2N524, 2N525, 2N526, 2N527
GERMANIUM TYPES
1.8

1.6
•lyEl 16 +10 31

1.4

1.2

1.0
.8
hFE
.6

.4

— 80 —60 — 40 —20 0 +20 +40 +60 +80

TEMPERATURE, TA ('C)
VARIATION OF h,, AND h,. VS .TEMPERATURE
Figure 1.26

Normal semiconductor properties tend to disappear at high temperatures with the

result that transistor action ceases. This temperature usually exceeds 85°C and 150°C
in germanium and silicon transistors, respectively.
When atransistor is used at high junction temperatures, it is possible for regenera-
tive heating to occur which will result in thermal run-away and possible destruction of
the transistor. For maximum overall reliability, circuits should be designed to preclude
the possibility of thermal run-away under the worst operating conditions. Thermal
run-away is discussed in detail in Chapter 4.
A major problem encountered in the operation of transistors at low temperatures is
the reduction in both the ac and de current gain. Figure 1.26 shows the variation of
hFB with temperature for the 2N525 and indicates that at —50°C the value of hrE

35
 BASIC SEMICONDUCTOR THEORY

drops to about 65% of its value at 25°C. Most germanium and silicon transistors show
approximately this variation of hEE and hn. with temperature. In the design of tran-
sistor circuits, the decrease of hEE and he., and the increase of VBE (see Figure 4.2) at
the lower temperatures must be accounted for to guarantee reliable circuit operation.
This is discussed in Chapter 6.
Variation of reverse leakage Into with temperature has already been discussed
under Leakage. Further and more specific information will be found in Chapters 4
and 6. Variation of base-emitter voltage Vi Ewith temperature is covered in Chapter 4
and illustrated in Figure 4.2.

THERMAL SPECTRUM
Figure 1.27 illustrates aportion of the thermal spectrum. Comparison temperature
scales appear in degrees Centigrade and degrees Fahrenheit. The illustration is attempt-
ing to show, in pictorial terms, the present semiconductor storage, operating, and circuit
design limits, and compare these limits with other known points throughout the tem-
perature spectrum.
Melting point temperatures of avariety of metals used in semiconductor manufac-
ture are also included, as well as prime semiconductor materials, germanium and silicon.
Many other materials important to semiconductor manufacture do not appear because
of space limitations.
Shaded areas point up the three generally accepted semiconductor circuit applica-
tion categories: entertainment, industrial, and military. All overlap to some degree
depending on individual circuit design specifications ; and in some instances circuit
applications from an "outer" category will fall within aless severe "inner" category.
In any circuit application involving semiconductors, consideration of temperature
is vital. As previously mentioned, reliable operation of a transistor over awide tem-
perature range requires that bias voltage and current remain reasonably stable. At the
outset of any circuit design a temperature range should be chosen over which the
circuit must reliably function. If the circuit is to be used in an electronic musical instru-
ment for home entertainment, for example, temperature limits from 0°C to 55°C
should more than suffice. This range allows some safety factor to insure against severe
temperature ambients that might occur. It would be required, from the standpoint of
reliability, that as temperature changed, circuit parameters such as frequency, gain,
power, distortion, etc., would not shift from a specified design center by more than
some allowed amount (% tolerance). Knowing his design centers, and ambient tem-
perature limits, the designer is then faced with selecting semiconductor devices,
associated circuit components, and acircuit design to meet the requirements. Figure
1.27 shows, that should the application fall within an "inner" category either germanium
or silicon transistors could be used. If temperature limits are increased, reliability would
be more difficult to "design in" with germanium devices. In this case either more
stringent circuit techniques must be called on, or lower leakage silicon devices used.

TRANSISTOR ABUSES
A manufacturer publishes a transistor specification sheet (Chapter 19) not only
to describe his devices, but more importantly, to warn the user of its limitations.
Naturally, in publishing his device specification the manufacturer assumes the user to
be somewhat familiar with the type of device described as well as the area of its appli-
cation. Where this knowledge is known to be lacking, additional information in the
form of application notes, technical tips, article publication in technical periodicals,
promotion material, manuals, and other sundry bits of educational material is usually
prepared.

36
 BASIC SEMICONDUCTOR THEORY 1

I J.

WELDING SILICON MELTS 1420 2588

COPPER MELTS

GOLD MELTS 1083 052 1925 1981

1000 1832
GERMANIUM MELTS 958.5 1754 --I SILVER MELTS

HAND SOLDER 820 1508

AND HIGH TEMP. SILVER SOLDERS MELT
BRAZING
ALUMINUM 675
MELTS 660 1220 1247
ANTIMONY MELTS 630 1166
600 1112

300 572

COMPLETE L1OUIFICATIONI— 213 200

SOLDER MELTS I 181 358

175 347
INDIUM MELTS I 156.4 314 USEFUL
RANGE OF
MERCURY
125 257 THERMOMETER

^100 212 STEAM POINT

85 185
75 167 HIGHEST
RECORDED
SILICON 57.8 136
55 WORLD TEMP
OPERATING 4 131
HUMAN BODY
SILICON ENTERTAINMENT? 37 98.6
GERMANIUM TEMPERATURE
STORAGE AND 25 77
OPERATING INDUSTRIAL /
GERMANIUM 1 ICE
o 32
STORAGE NDUSTR1AL AND POINT
MILITAR Y -17.8 25
-13 0
MILITARY --40 40
FREEZES
-55 -67
65 -85
DRY ICE TEMP
-78.5_ 88.3 126.9-109.3 LOWEST
(OR LOWER) RECORDED
--100 -148 WORLD TEMP

C5/9 (
°F-32 0) . F.(9/5 • C) +32*

-200 -328

ZERO-ENERGY POINT - --273165 -459.69 ABSOLUTE ZERO

I
CENTIGRADE
.
SCALE IN •C
FAHRENHEIT
SCALE IN°F

THERMAL SPECTRUM

Figure 1.27

37
1 BASIC SEMICONDUCTOR THEORY

It scarcely needs mentioning, however, that the manufacturer, no matter how care-
fully he prepares his specification sheet, cannot guarantee his device against handling
abuses. Such abuses fall under two main headings: mechanical and electrical.
Over the years transistors have acquired the reputation for being highly reliable
and rugged. Continuous reliability studies substantiate this built-in "toughness" — up
to apoint. It is these "points" or limitations that the designer must become familiar
with if he is to design reliable semiconductor circuits.
Following are some of the more common handling abuses that transistors are
subjected to.

MECHANICAL
Dropping — Semiconductor material is hard and brittle and can be damaged
by high impact shock. For example, dropping atransistor 412 "onto ahardwood
/
bench subjects the device to around 500g; a drop of 30" onto concrete may
increase the impact shock from 7000 to 20,000g; snapping a transistor into a
clip causes ashock of 600g; and the simple act of clipping atransistor's lead
may generate a shock wave of several thousand g. Any high impact shock,
therefore, can cause fracture of the semiconductor material, or lead breakage,
resulting in complete ruin of the transistor.
Lead Bending — Several sharp back and forth bends of awire will usually cause
it to break, or at least fracture. This is especially true of transistor leads at the
point where they enter, or attach to, the header. Some leads when bent during
testing and handling may easily break later since the "bending life" of the lead
has already been spent. Plated leads when subjected to excessive bending and
twisting can generate cracks at the header; such cracks offer openings for mois-
ture to enter and contaminate the device thereby causing gradual degradation
of gain and voltage characteristics. To insure against the foregoing it is always
well to remember: allow at least %2" to 1 / "clearance between the header and
2

the start of alead bend.

Overheating — If, during soldering, the maximum specified junction tempera-
ture of a device is exceeded, the device can be destroyed. Heat transmitted
over connecting leads and printed circuit board leads to the header can also be
destructive. Junctions can be shorted. Lead connections may open. Unequal
expansion between header and package may break the hermetic seal. Safety
precautions include: removal of the transistor from the immediate socket to
which heat is being applied, keeping in mind that the heat can quickly travel
along connecting wires to neighboring sockets; use heat shunts (clips, pliers,
etc.) connected between the heat source and the device; and, asoldering iron
of adequate heat delivery for the job to be done. Most small-signal transistor
circuit work can be accomplished by use of a20 to 50 watt iron. Larger irons
can be used, of course, with increased chance of device damage. At any rate,
it is always best to "heat shunt" to insure against damage. And, solder cleanly
and quickly.
Ultrasonic Cleaning — Depending on the frequency of the cleaning apparatus,
sympathetic vibration can induce unusually high stresses into transistor leads.
Lead breakage occurring at a particular frequency range can cause internal
opens. Where ultrasonic cleaning of transistorized equipment is being consid-
ered, the maximum average PSI (pounds per square inch) level in the tank
when cleaning action is taking place should be determined.
In most cases, an average level of 3PSI will adequately clean most equip-
ment without damaging the semiconductors; energy levels exceeding this value

38
 BASIC SEMICONDUCTOR THEORY 1

tend to induce damage, especially to semiconductors fabricated by germanium

techniques (alloy, grown junction, mesa). PSI level can be somewhat increased
for equipment using transistors fabricated by the latest silicon planar tech-
niques. Close monitoring of PSI energy level is always good practice, in any case.
ELECTR I
CAL
Excessive Voltage — Absolutely do not exceed the absolute maximum voltages
(usually specified at 25°C) as given by the manufacturer. In signal amplifier cir-
cuits this means peak-to-peak voltage swings should not exceed the transistor's
inter-element absolute maximum voltages. A good rule is to use asupply voltage
equal to half the maximum voltage rating. Maximum inter-element voltages
can also be exceeded by voltage transients (inductive or capacitive kicks, etc. )
when connecting atransistor into a"hot" circuit; when removing or replacing
atransistor in acircuit it is always safest to turn the power off first. Transistor
testing by use of an ohmmeter can also cause damage by application of exces-
sive voltage. Since the emitter-base reverse breakdown voltage for most tran-
sistors is from 1to 5volts, the transistor can easily be damaged when subjected
to the high voltage (many ohmmeters use 22 1 / volt batteries) ranges of an
2

ohmmeter. When measuring breakdown voltage, always use acurrent limiting

resistor. Voltage spikes can cause a build-up of impurities concentrated at a
point in the collector and emitter junctions and can result in punch-through
(internal short from collector to emitter) across the base region.
Excessive Power —Exceeding the maximum junction temperature of a tran-
sistor can permanently change the gain, the breakdown voltage, and can cause
opens and shorts in the transistor. To guard against such damage, when testing
for gain at excessive power dissipation levels, use aprotective heat sink or test
with alow duty cycle pulse.
Miscellaneous — When atransistor is used in the common emitter configuration,
opening the base lead while voltages are still applied can result in junction
heating, thermal-run-away, and eventual burn-up of the transistor. The right
conditions of applied voltage, current gain and reverse leakage can be destruc-
tive, particularly to germanium transistors where leakage currents may be a
1000 or more times greater than in silicon. With the base disconnected, collec-
tor-to-emitter leakage (Ice°, base open) equals the collector-to-base leakage
(IcBo, emitter open) magnified by the transistor's forward current gain (p).
High values of IcE0 can flow when inductive collector loads, exhibiting low
resistance paths, are part of the associated circuitry. Where current limiting is
not apart of the external circuitry, supply power should be disconnected when-
ever the base is opened circuited.

SOME THINGS TO REMEMBER IN THE

APPLICATION OF TRANSISTORS
AGING
Allow sufficient latitude in circuit design to accommodate some change in tran-
sistor's parameters with time. This is particularly important in high reliability
circuit design.
CURRENT
Generally, above afew milliamperes current gain decreases as operating cur-
rent increases (see Figure 6.7).
Limit collector current (Ic) so that maximum power dissipation will not be
exceeded.

39
1 BASIC SEMICONDUCTOR THEORY

Limit collector current (Ic) in breadboards by using aresistor or afuse.

FREQUENCY
fmAx., the maximum frequency of oscillation, is the upper frequency limit of
operation of atransistor.
Frequency cutoff for CE or CC circuits depends on forward current gain.
(fide = fhfb/life)•

Collector capacitance (Cob, Co.) contributes to poor transistor high frequency

response.
Collector capacitance varies inversely as 1/VC 2 for alloy devices and as 1/VC°
for diffused devices (mesa, planar, etc. ).
Transistor rise time (t,) and fall time (tr) are dependent on the base control
charge required to cause the transistor to conduct, as well as upon the currents
driving the transistor into or out of saturation.
Fall time (tr) is also limited by barrier capacitance (Cc ).
To minimize storage and fall time, do not overdrive the transistor or let it
saturate.
To eliminate oscillations in narrow band amplifiers, neutralize the transistors or
load down the tank circuits sufficiently.

LEAKAGE
Leakage currents increase exponentially with temperature (double every 8°C
to 10°C of temperature increase).
In switching circuits, remember that both the collector and the emitter leakage
currents flow in the base lead.
In common emitter circuits, Ice can vary from kilo to hFE X I
CBO•
Beware of unstable leakage currents at fixed temperature and voltage, due
most likely to contamination.
Minimize circuit resistance between base and emitter consistent with stage gain.

MANUFACTURING RATINGS
Compare ratings of different manufacturers of same transistor type number
when considering second source or replacement.
Apply derating factors to the manufacturer's ratings to insure reliable circuit
operation.

MECHANICAL
Use heat shunts when soldering.
Do not connect or disconnect transistors with power on.
Do not use an ohmmeter for checking transistors unless a"safe" voltage/current
range is used.
Keep sharp lead bends at least %2" to le away from the transistor body
(header ).

POWER
Do not store transistors at atemperature higher than the maximum rated junc-
tion temperature as specified by the manufacturer.
Use athermal derating factor for temperatures above 25°C.
Use the proper thermal derating factor for small signal transistors; this is about
1— 10 mw/ °C. For power transistors .25 — 1.5 W/ °C.

40
 BASIC SEMICONDUCTOR THEORY 1

Thermal resistance (RT, OE) given by the manufacturer does not include the
heat sink thermal resistance.
In a switching circuit, the peak power during the transition should not be
excessive.
Limit collector power dissipation to avoid thermal runaway (use of emitter
resistance helps ).
Maximum power dissipation is not always dependent on the device; the circuit
(or system )may limit the maximum power at which adevice may be operated.

TEMPERATURE
Limit maximum junction temperature to prevent excessive leakage currents.
Limit minimum junction temperature to minimize effects due to VII,: variation
(negative temperature coefficient of 2mv/°C for both germanium and silicon ).
Choose low values of stability factors. For example, use some emitter resistance
to improve stability. Also, keep the base-emitter shunting resistance in common-
emitter circuits as low as gain considerations will permit.
Choose large values of collector current (lc) to minimize the effect of Mc due
to temperature changes.
Use low values of source resistance driving the base circuit to keep the stability
factor low.
Stabilize emitter current by using a large value of emitter resistance or by
using aconstant current supply source.
For large temperature changes, the use of a differential amplifier will reduce
the effects of AVBE.
When using diodes and transistors in a temperature compensation circuit, use
acommon heat sink for all devices.
Design for minimum I
IFE over the operating temperature range.
Low stability factor does not improve ade amplifier's performance.

VOLTAG E
Do not exceed VcE maximum.
Do not exceed VEE maximum (reverse breakdown voltage ).
Do not exceed VcE maximum.
Minimize circuit resistance between base and emitter.
In push-pull applications, keep Vcc < 1/2 Veil.

Minimize transient voltages in circuitry.

Reverse breakdown of silicon decreases with increasing temperatures.

REFERENCES
(-)"Encyclopaedia Britannica," Encyclopaedia Britannica, Inc., Chicago, Illinois (1962).
11 Pearson, G.L., and Brittain, W.H., "History of Semiconductor Research," Proceedings of the IRE,
Vol. 43, pp. 1794-1806 (December 1955).
(3) Bardeen, J. and Brittain, W.H., "The Transistor, A Semiconductor Triode," Physics Review, Vol.
74, No. 2, page 230,(July 15, 1948).
(,) "Silicon Controlled Rectifier Manual," General Electric Company, Rectifier Components Depart-
ment, Auburn, New York (1964).
(5) "Silicon Controlled Rectifier Hobby Manual," General Electric Company, Rectifier Components
Department, Auburn, New York (1963).
(6) "Tunnel Diode Manual," General Electric Company, Semiconductor Products Department, Liver-
pool, New York (1961).

41
1 BASIC SEMICONDUCTOR THEORY

(7) Bush, G.L., and Silvidi, A.A., "The Atom — A Simplified Description," Barns & Noble, Inc., New
York, New York.
(8) Bragg, Sir William, "Concerning the Nature of Things," Dover Publications, New York, New
York.
0) Shockley, W., "Transistor Electronics: Imperfections, Unipolar and Analog Transistors," Proc.
IRE, Vol. 40, pp. 1289-1313 (November 1952).
(
10 )Phillip's, A.B., "Transistor Engineering," McGraw-Hill Book Company, Inc., New York, New
York (1962).
Warschauer, D.M., "Semiconductors and Transistors," McGraw-Hill Book Company, Inc., New
York, New York (1959).
"Basic Theory and Applications of Transistors," Department of the Army Technical Manual
TM11-690 (1959). Available from Superintendent of Documents, U. S. Government Printing
Office, Washington 25, D. C.

NOTES

42
 cc

SMALL-SIGNAL CHARACTERISTICS
x 2
Port 1— Low Frequency Considerations

INTRODUCTION

The transistor, like the vacuum tube, is anon-linear device and since it is capable
of gain, it can be defined as anon-linear active device.
Figure 2.1 illustrates that although slightly non-linear throughout its range, the
transistor's non-linearities become very pronounced at the very low and very high
current and voltage levels (below point A and above point B). Hence if, for example,
an ac signal is applied to the base of atransistor in the absence of any dc bias, con-
duction would take place only during one half cycle of the applied signal and the
amplified signal would be highly distorted. To avoid this problem, ade bias operating
point OP is chosen (see Figure 2.1 and Chapter 4 on Biasing). This bias moves the
transistor's operation to the more linear portion of its characteristics. There the linearity,
although not perfect, is acceptable, resulting in amplification with low signal distortion.
The application of adc bias, in itself, is still not sufficient. A transistor could be
biased right squarely in the middle of its linear range and be operated at such large
signal swings (see Figure 2.1 )that the signal encroaches upon the non-linear part of
the characteristics, resulting in increased distortion once more. This is quite common,
for example, in class A audio output (or driver) stages of radio or television receivers
where normal signal levels make the transistor operate linearly, but higher volume
music passages such as crescendos, fortissimos ... tv commercials ... may drive the
transistor into cut-off and/or saturation. This would, of course, result in severe clipping
distortion.
In a great number of transistor applications, normal operating signal levels are
small. Examples of such applications are the RF and most IF amplifier stages of radar,
radio, and television receivers. Even after detection, as in audio or servo preamplifiers,
signal levels can be moderate.
In low-level stages, signal swings run from less than 11.4v to about 10 mv under
normal operating conditions (for which these stages are generally designed). Therefore
it is important to analyze the transistor under conditions when the bias is such that the
largest ac signal to be amplified is small compared to the de bias current and voltage.
The transistor is then said to be operating in the small-signal mode. Transistors used in
this way are normally biased at currents between 0.1 and 10 ma and voltages between
2 and 10 volts. Insufficient biases can cause distortion while excessive biases exhibit
unnecessarily increased power dissipation and higher noise figures (the latter is pri-
marily important in input stages). If the bias is sufficiently increased to make the
stage operate in the high voltage non-linear region, distortion will once again be
increased.
A simple analysis of transistors under large signal conditions requires agreat deal
of approximations. More accurate analysis is mathematically complex as one deals with
non-linear equations. The restriction to small signal levels, will lead to more accurate
equivalent circuits composed of linear circuit elements and internal linear generators.
This allows the analyst the use of conventional linear-circuit analysis.

43
2 SMALL SIGNAL CHARACTERISTICSI

100 /
la.0.7MA
/
90 / /
/ / / / /
/ / / /
SO !
A/ // /
/ /
0.6MA
70 /
/
/
60
0.5MA /

50

04 MA 1
0P ,
40 1 , •

1 /
0.3MA /
1
30 1 I
i /
1
0.2MA
20
1 1 /
1

,,
1 1 C Ta •25.•C
1
1

r1
10 — 0.1MA
B
1
o 29 25 1 30 35 40 45 5
0 5 10 15 .

TYPICAL VI
CHARACTERISTICS
(A)
OF THE
SILICON PLANAR 2N1613
...... .

Figure 2.1 Ta•25.0

45

— _ — — — — — — — — — —
*3

I
35 1

30
OP .

25

VCE .5V

20 _ _ _ _ _ _ _ _ _ _

15 1
1

A i
l
10
1
1
5 1
I
OP' 1
—7
T1
00 02 04 ,
1
toe to , 14 16 1.8 2
VOLTS
1
1
1
1

I i
1
I .

(B)

44
 SMALL SIGNAL CHARACTERISTICS 2

TRANSISTOR LOW FREQUENCY EQUIVALENT CIRCUITS

There are three major approaches to the choice of equivalent circuits. First the
device designer wants a circuit which he can simply relate to the device physics.
Then there is the device manufacturer who wants to use an equivalent circuit whose
parameters can be easily and inexpensively measured and controlled in the manu-
facturing process. The third party to this plot is the circuits engineer who must handle
this equivalent circuit continually and who wants to use parameters fitting conveniently
into his circuit design. These parameters should be easy to measure and, if possible,
readily obtainable from the commonly used graphical characteristics. He is also
interested in controls and limits to those parameters relating directly to his circuit's
performance.
As aresult of these varying interests several equivalent circuits have been devel-
oped over the years. Some of these have retained their importance in modern transistor
circuits analysis, others have become less used and will only be mentioned for academic
reasons. The important thing is that every one of the equivalent circuits must fully
describe and accurately synthesize the device it represents.
Before getting into the discussion on the various equivalent circuits, it should be
remembered that all equivalent circuits have three useful connections; i.e., common
base, common emitter and common collector (see Chapter 1).

GENERIC EQUIVALENT CIRCUIT"'

The device designer looks at the transistor from aphysical mechanism viewpoint.
The circuit engineer also finds an understanding of these basic mechanisms of great
help, at least in the early stages of his circuit design work. The generic equivalent
circuit is acircuit composed of parameters identified with the basic transistor mecha-
nism and have been expressed in terms of the physical attributes of the device at a
given bias point and ambient temperature.

aoj
e

EMITTER COLLECTOR

BASE BASE
b

GENERIC EQUIVALENT CIRCUIT

Figure 2.2

Emitter Diffusion Resistance, I -.

To relate the current and voltage of the emitter junction one can define a small-
signal emitter resistance, r.. This relationship is nonlinear and is expressed as apartial
derivative with the collector voltage held constant. Thus,
dV. 1
r. = [di ] V. conatant = ge

This small signal emitter resistance turns out to be proportional to the de value of the

45
2 SMALL SIGNAL CHARACTERISTICS

emitter current and is given by

KT
r. =
qIEm
where T is the absolute temperature in degrees Kelvin (T = °C + 273), hence T is
about 300 at room temperature ;K is Boltzmann's constant (1.38 X 10 watt-seer C
and q is the charge of an electron (1.60 x 10 -19 coulomb). m is a constant whose
value is 1for germanium and varies between 1and 2for silicon transistors."' Hence,
r. 28/Is (I Eexpressed in milliamperes) for a germanium transistor; which makes
r. = 26 ohms at 1.0 ma, for example. One can thus see that r. changes with the de
bias operating point and the ambient temperature.
Base Resistance, rb
The flow of current from the base terminal to the active region of the transistor
is by majority carriers (electrons). These electrons flow by the drift process, so that
there is an ohmic drop associated with this current. The resulting resistance is defined
as the base resistance, rb. The geometry of this base current path (base resistance), is
very complex and can differ radically from one transistor structure to another.
Practically, this base resistance causes a power loss and a feedback path when
the base is common to input and output. It will be seen later in the high frequency
equivalent circuit analysis that since this resistance denies direct access to the intrinsic
base point b' (in Figure 2.2), it also obstructs efforts to accomplish broad-band neu-
tralization. The base resistance also varies somewhat with temperature and bias.

Collector Resistance,
The small-signal collector resistance, r., can be defined as the ac slope of the
reverse biased collector junction at aparticular voltage. This gives us

r. — Ie eonet•nt =
13
This collector resistance is generally very high, in excess of 1megohm, and is primarily
sensitive to bias.
Emitter Feedback Conductance, g.e
This feedback conductance results from the fact, that an increase in collector volt-
age results in an increase in emitter current even though the emitter voltage is held
constant. The physical cause of this is the base-widening effect's"' Schematically
this is represented as asmall-signal current generator across the emitter junction. The
value of this current generator is proportional to the small-signal collector voltage,
and since it relates current to voltage, it will have the dimension of transconductance,
where
d
g.. = [ Id Ve conetant
Ve

Current Amplification Factor, a

The cumulative effect of three basic mechanisms, emitter efficiency, transport
factor, and collector efficiency results in the current amplification factor, a (see
Chapter 1).
The relationship is

a= [ dI.
di'l V,,99.19,1

This avaries with de emitter current and collector voltage and generally has values
slightly smaller than unity. It is another parameter sensitive to bias and temperature
changes.
The first disadvantage of the generic equivalent circuit is that the use of the feed-

46
 SMALL SIGNAL CHARACTERISTICS 2
back generator go ovo is apoor choice since vo is not obtainable at the external terminals
of the transistor. Another disadvantage of this equivalent circuit is that it has two
current generators which essentially present two extra circuit meshes to our analysis.

1-Equivalent Circuit (tee)

This circuit has found widespread use in the literature due to its greater simplicity.
It still maintains close touch with the physical transistor mechanisms and is easily
analyzed. One schematic representation of the T-equivalent circuit is shown in
Figure 2.3.
ai.

T-EQUIVALENT CIRCUIT (COMMON-BASE) WITH CURRENT GENERATOR

Figure 2.3

This particular representation has acurrent generator (ai.) in the collector circuit.
Although this current generator is in fact athird mesh, this circuit is relatively simple
and has the advantage of great resemblance to the physical mechanism. The elements
which comprise this circuit are identified with the branch of the circuit in which they
are located. Thus here again we find abase resistance rb, an emitter resistance r. and a
collector resistance ro. It would be very confusing to identify these terms by other
than these characteristic symbols. It must be understood, however, that these T-equiva-
lent terms and the symbols used for the generic or any other equivalent circuit are
not at all the same resistances. This is avery important factor and must be thoroughly
understood to avoid ghastly confusion. To understand these differences, let us rigor-
ously analyze both the generic and the T-equivalent circuits by writing their mesh
equations and equating corresponding coefficients.
For the generic circuit shown in Figure 2.2, vo = (a. i, — io )ro and hence we have
i. (r. rb go. ro ro a.) io (— rb goo r
o r.) =vi

1. (rb + a. ro) -I- io (— rb — ro) =

For the T-equivalent circuit in Figure 2.3, we have
ie (re re) ic (— 11) = vi
j. (re a,.) (— r. — rt.) = y2

Equating corresponding coefficients we obtain the following relationship between the

T-equivalent parameters and their generic counterparts.
rb (tee) = ri, + g,. r
o ro

r. (tee) = ro — g,. ro ro (1— a.)

r
o (tee) = ro (1 — go oro)

a (tee) = a°— g" I .°

1— go. r.
By carefully defined valid approximations, the following simplifications can be
made: first, in agood transistor a, is close to unity. We can thus define anew param-

47
2 SMALL SIGNAL CHARACTERISTICS

eter, beta (p), such that

=
1 =
1
à 1— a.
(The present standard terminology defines fi as hf. and aas hie).
If g., = = 1
2A 2àr,

then g.. r
e— — P_ _ hf.

r t
and g.. r. — P--
re
2r, 2r.
A typical value of the parameter fl is approximately 50, corresponding to an alpha
(a.) of 0.98. The emitter resistance r. is rarely greater than 100 (r. 26/Is, hence
above 0.25 ma r, will be less than 100 ohms). The collector resistance r, is usually
very large, in the order of one or more megohms. Hence, we can further approximate
g.. r.<<1
Finally with these approximations, the simplified, yet sufficiently accurate tee-equiva-
lent parameters can be expressed as follows in terms of their generic counterparts:

rb (tee) = rb
2
r. (tee) = re
2
r. (tee) = r.
a (tee) = a.
It is important to note that the base resistance rb in the tee-equivalent circuit is the
sum of the extrinsic base resistance and Early's feedback term.'" <" Extrinsic base
resistance is generally of the order of several hundred ohms. The feedback term for
high alpha transistors may be several thousand ohms and dominates this expression.
Thus the n, of the tee-equivalent circuit does not reliably reflect the physical base
resistance value. Let us demonstrate this by a practical example of a typical PNP
germanium alloy junction transistor operated at a collector voltage of 5 volts, a
collector current of 1ma, and at an ambient temperature of 25°C. The generic param-
eters of this unit are
KT
r. = — = 25 ohms (r. here is the diffusion resistance)
qIE
rb = 250 ohms (rb here is n,', the base spreading resistance)
r. = 2megohms
hfb. = a. = 0.98 hence
hf. = 1 1
1— hfb„ = 1— 0.98 = 50

The equivalent tee-parameters of this same transistor are

25 (r. here is the "tee-equivalent
r. — 12.5 ohms hfo 0.98
2 emitter resistance" )
r. 2.0 megohms hf. 50

rb 250 (rb here is the "tee-equivalent

a_. 875 ohms
25 x 50
2 base resistance )
As one can plainly see there is very little resemblance between the generic rb of 250
ohms and the tee-equivalent value of 875 ohms.
The main shortcomings of both the generic and the tee equivalent circuits are

48
 SMALL SIGNAL CHARACTERISTICS 2

that their elements are difficult, in some cases even impossible to measure directly.
The electrical engineer then resorts to another analytical concept, consisting of meas-
uring and analyzing the black-box parameters of the device, which avoids having to
use any of the internal parameters.

"BLACK-BOX ANALYSIS" OF THE FOUR-TERMINAL

LINEAR NETWORK
This concept consists of analyzing adevice (or an entire circuit and/or asystem)
by writing two simultaneous equations expressing the input and output voltages in
terms of the input and output currents. If the equations relating these currents and
voltage are known, everything that is needed in alinear network calculation can be
determined from them.
The transistor is athree-terminal device. One of these terminals will be used as
common, the other two as input and output. In view of the wealth of information
available on the analysis of four-terminal devices, however, (i.e., one pair of input
and one pair of output terminals) it is more convenient to analyze the transistor as a
four-terminal device. Figure 2.4 illustrates that the three-terminal network is just a
special case of the four-terminal network, in which the common terminal serves in
both the input and output portions of the circuit.

FOUR-TERMINAL LINEAR NETWORK REPRESENTATION

OF THE TRANSISTOR (A THREE-TERMINAL DEVICE)

Figure 2.4

OPEN CIRCUIT IMPEDANCE PARAMETERS (z-PARAMETERS)

The generalized equations for the input and output voltages of ablack-box are
vi = i2 Z12

V2 = ii Z21 i2 Z22 (2a)

The open circuit impedance parameters, by definition, require that to measure z1 1 and
z., the output be open-circuited; while for the measurement of zi2 and z22, the input
be open-circuited. Hence one can see that for the open-circuited output case, where
ii =

zii = = input impedance

it
and
zi, — -
v -= forward transfer impedance
Il

while for the open-circuited input case, where i

i = 0,

zt,= -
-
v1 = reverse transfer impedance

49
2 SMALL SIGNAL CHARACTERISTICS

and
z22 = 21
‘.= output impedance
12

The input and output currents in this case are independent variables.
All electrical properties, such as current gain, voltage gain, power gain, etc., can
be calculated from these impedance parameters. The current gain Ai, for example, is
given by

A, — .

From equation (2a) it can be seen that v2 7.7_ i2 z22. Figure 2.4 shows that v2 also
equals
= RL
hence
—i2 RL= ii zn z22
and
A .= i2 = Z21

11 Z22 + RL
The z-parameters prove most useful to describe low impedance devices and/or
circuits. This is mainly due to the fact that when measuring high impedances, one's
test equipment must present ultra-high impedances to the device under test in order
not to load it down. Hence for alow to medium impedance "to be measured" (up to
several thousand ohms) a one megohm driving impedance can synthesize a virtual
open-circuit. Another difficulty in the z-parameter measurement is that at higher
frequencies atrue open circuit becomes even more difficult to achieve due to device,
as well as stray test circuit, capacitances.

SHORT CIRCUIT ADMITTANCE PARAMETERS (y-PARAMETERS)

The generalized equations for the input and output currents of the black-box are
= y1 yn y2 Y12 (2b)
i2 = vi y. + V2 Y22

where vi and v. are independent variables. Since these equations describe the short-
circuit admittance parameters it suffices to short-circuit the output (v. = 0) in order
to measure yii and y. Thus

yii = = input admittance

VI

and
y. = —
i2 = forward transfer admittance.
vi
To measure the output parameters, it suffices to short-circuit the input (vi = 0).
Hence

yi.= = reverse transfer admittance

y2
and
y. = — = output admittance. (2c)
v.
Once again, knowing these parameters, all other electrical properties of the black-
box can be derived. The y-parameters prove most useful to describe high impedance
devices and/or circuits. This is due to the fact that it is easier to virtually short-circuit
ahigh impedance circuit than a low impedance one. It must be realized that when
one talks of open-circuit or short-circuit that this is only true with respect to ac signal
frequencies, and that the necessity of applying dc biases prevents the application of

50
 SMALL SIGNAL CHARACTERISTICS 2

actual physical short or open circuits.

In general, since the transistor turns out to exhibit low input impedances and
high output impedances, the use of zand y parameters becomes awkward, especially
at high frequencies. As aresult the hybrid, or h, parameters have been found to pro-
vide the most useful tool in modern transistor circuit analysis. This is primarily due
to the fact that the h parameters are a combination of impedance and admittance
parameters ideally fitting the low input and high output impedances of the modern
transistor. As aresult they are also the easiest parameters to measure at both low and
high frequencies. Another advantage is that the h., h., and h22 terms approximate
the actual typical operating conditions even though the latter do not occur with either
input or output terminals shorted or open. (See Figures 2.8 and 2.9). For the
h-parameters, the black-box equations read
= i, h. -I- v. hl.
= i, h., + v.
Hence when the output is short-circuited, (v. = 0),

h. = YL= input impedance, (2d)

and
h. = 4—= forward transfer current ratio; (2e)
II

and with an open-circuited input circuit, (1, = 0),

h. = -
--= reverse transfer voltage ratio,
N7

y,
and
h. = output admittance.
y,

When going from the general four-terminal analysis to the specific transistor param-
eter work, it is usual to drop numeric subscripts such as h., h., h., and h,, in favor
of more descriptive letter subscripts. Therefore it has become customary for the first
subscript letter to indicate whether the particular parameter is an input, output, forward
transfer, or reverse transfer parameter; while the second subscript describes the tran-
sistor configuration. We will therefore refer to the common-emitter h-parameters as
hi. = common-emitter input impedance
hr. = common-emitter forward current transfer ratio
h,. = common-emitter reverse voltage transfer ratio
h.. = common-emitter output admittance.
For the common-base parameters, these will be referred to as hu,, hrb, hrb, and h.b;
while the common-collector parameters will be hi., hr., and h...

h-PARAMETER EQUIVALENT CIRCUIT

From the h-parameter equations, one can derive three equivalent circuits. See
Figure 2.5 (A), (B) and (C).

1-EQUIVALENT CIRCUIT
Another useful equivalent circuit capable of describing the h-parameters is the
tee-equivalent which enables one to get aphysical picture of the inside of the black-
box. In our previous discussion we saw that the tee-equivalent had certain shortcom-
ings. The main one was described as caused by the feedback term which made the
and r. terms look considerably different than their physical values. This is due to
space charge layer widening as explained by Early.( 3>")
In the h-parameter analysis, however, the output circuit is short circuited (v. = 0,
see equations (2d) and (2e) ). In this specific instance, then, the feedback term dis-

51
 2 SMALL SIGNAL CHARACTERISTICS

EMITTER COLLECTOR

e 1 b c
O.

ve, +0 hre Yee 0 1.4 ie

• e
BASE

(A) —COMMON —BASE

BASE COLLECTOR
h ie

t +
hf e ib
vce vee h, e vc.

o. • •
EMITTER
(B) — COMMON —EMITTER

BASE EMITTER

COLLECTOR
(C)—COMMON—COLLECTOR

HYBRID-EQUIVALENT CIRCUITS

Figure 2.5

(A)—COMMON—BASE

(B)—COMMON--EMITTER

T-EQUIVALENT CIRCUITS

Figure 2.6

52
 SMALL SIGNAL CHARACTERISTICS 2

(NUMERICAL VALUES ARE TYPICAL FOR THE 2N525 AT tMA, 5V)

SYMBOLS j COMMON COMMON COMMON T EQUIVALENT
CIRCUIT
IRE OTHER EMITTER BASE COLLECTOR (
APPROXIMATE )

I hib
hie hIle '1
, 1400 OHMS I+ bfb hic tb+ 1_,„

hi bhob _ re
hre h l2e' /"L bc' 3.
37 X 10 -4 h, I
- hre
li- hie (I-a) r
c
/re b

htb
hfe h21e' 8
44 -(1+hrc)
l+hfb 1-
aa

,
1 hob 1
hoe 27 X 10-6 MHOS hoc
h22e Z22e 1+hfb (1- o) rc

1 hie _ h,c
.
31 OHMS r
e +
h ib h 11 qii i+hf e htc

hI2 ' ,Li ec , hie hoe h hic hoc rb

h r"
, 5 X 10 -4 hrc - I
-
li- ht e re htc rc
/
--rb
1

hfb h21 ,
_ __Le_
h
- 0.978 -
l+hfc
1
ti e
- gric

I hoe h0C I
hob 0.60 X10 -6 MHOS
h22 'Z22 prhfe — h ic i-
c-

I
hic hfic ,y, ic hie 1400 OHMS
l+hfb rb ' I-.

h12e i.d. be ,
hre
I- hre I 1
LOO - r
e
(1-a)r c
P• rc

--(14-h ie ) _ I _ 1
hic h2lc taeb -45
14-hfb I-a

hob
hoc hoe 27 X10 -6 MHOS I
h22c.Z 22c
I i+hfb (1-a)rc

hf e Prht c
a --hfb 0.978
ii-h fe il k

ii-h fe 1-n rb _ lik

fc I67 MEG
hoe hobhoc

_
h
i_g , hrb „0-n I-hrc
re nib- —fbi
... %
12 5 OHMS
hoe hob hoc

rb hie - ---- (l+hfe) hic+ijc- (. -, .rc) 840 OHMS

hoe hob

APPROXIMATE CONVERSION FORMULAE h-PARAMETERS

AND T-EQUIVALENT CIRCUIT

Figure 2.7

53
2 SMALL SIGNAL CHARACTERISTICS

-0.5v BASE-EMITTER VOLTS 0

-V,
COLLECTOR VERTICAL
SWEEP AMPLIFIER

STEP •
HORIZONTAL
GENERATOR AMPLIFIER

,C.Vb
Ii

(A) INPUT IMPEDANCE, hi le , hi e

+2ma
COLLECTOR VERTICAL
SWEEP AMPLIFIER

STEP HORIZONTAL
GENERATOR AMPLIFIER

hi, ek i
0 EMITTER VOLTS +0 5v
(B) INPUT IMPEDANCE, hub , hi b

-50 v COLLECTOR-EMITTER VOLTS

COLLECTOR HORIZONTAL
SWEEP AMPLIFIER

-l
e
STEP VERTICAL
GENERATOR AMPLIFIER

6 ma
08 ma
.1 ma
(C) VOLTAGE FEEDBACK RATIO, hi2e ,h„

-V,
COLLECTOR HORIZONTAL
SWEEP AMPLIFIER

.04 mo —

.02 ma
+I + V, Olmo
STEP
e h Z-'2 X10 -4 p: -
VERTICAL
GENERATOR AMPLIFIER

AVe E= 0
,
h, b v-
c
1•••••••• ••1i

-50 v COLLEETOR-BASE %.70LTS • -O Iv

(D) VOLTAGE FEEDBACK RATIO, hi2b , Fi re,

Figure 2.8 h-PARAMETERS

54
 SMALL SIGNAL CHARACTERISTICS 2

V, -IV 0 EMITTER CURRENT +50mo

COLLECTOR HORIZONTAL
SWEEP -1. AMPLIFIER

COLLECTOR CURRENT
STEP VERTICAL
GENERATOR +10 AMPLIFIER

I, IC
hl. hFe

-50ma
a "'"• .98
(E) ALPHA CURVE, a, hvb ,hfb, hF B

-V, 2 ma BASE CURRENT O

COLLECTOR VERTICAL
SWEEP AMPLIFIER

-
STEP HORIZONTAL
- Ib
GENERATOR AMPLIFIER

NOTE BETA, hf. DECREASES AT 42 V, Iv

HIGHER CURRENTS.

(F) FORWARD CURRENT TRANSFER RATIO, BETA, 0, h2te ,hie ,hFE

,.0 .
-V, -50 v COLLECTOR-BASE VOLTS 0

et
COLLECTOR HORIZONTAL
SWEEP AMPLIFIER

COLLECTOR CURRENT
.02mo J

04 ma
STEP VERTICAL
GENERATOR AMPLIFIER .06mo .
X 10 -7 t-f-- [

.08mo'

.1 ma --- -4
100/.‘a

(G) OUTPUT ADMITTANCE, h22 ., hob

-V, -20 vCOLLECTOR-EMITTER VOLTS°

COLLECTOR HORI ZONTAL II
SWEEP AMPLIFIER
COLLECTOR CURRENT

Olmo
8..e 10' 5
STEP - VERTICAL .02 ma
GENERATOR AMPLIFIER

03 ma
Ale
h...

.04 ma
2ma

(H) OUTPUT ADMITTANCE, h22e , hoe

(Courtesy of Tektronix, Inc.)

AS OBTAINED ON TEKTRONIX MODEL 575 CURVE TRACER

55
2 SMALL SIGNAL CHARACTERISTICS

appears and the tee-equivalent parameters are equal to those of the physical circuit.
Hence in the circuits of Figure 2.6( A)and (B)
Alpha (a) is the fraction of the emitter current that becomes the collector cur-
rent and is typically 0.90-0.999.
r. is the incremental diffusion resistance of the forward biased emitter-to-base
diode: r. KT/qIE 26/IE at room temperature.
rE, is the ohmic resistance of the base contact plus that of the active base region.
r„ is the incremental resistance of the reversed biased collector junction.
The common-base and common-emitter tee-equivalent circuits are shown in Figure
2.6(A) and (B).
The table in Figure 2.7 gives the equations as well as numerical values for the
h-parameters of atypical transistor in the three configurations. This table also gives
approximate conversion formulae between h-equivalent and T-equivalent parameters.
Figures 2.8(A) through 2.8(H) illustrate the graphical data of the h-parameters
as obtained on the Tektronix 575 Transistor Curve Tracer.
Knowing any one set of established parameters, the others may be worked out,
or more conveniently, obtained from Figure 2.9.

FROM

—" [I]
[y]
[h] [g] [a]
TO

1 Y22 - Y12 Ah h12 I - 912 011 An

20 Z12 -
AY h22 h22 911 911 0 21 0 21

[z]
T Y21 Yll Th 21 I 921 Ag I °22
2 21 222 tà 2 te h22 h22 911 911 021 021

Z 22 -Z 12 1 -11 12 Ag 912 43 22 - Ph
AZ AZ Yil Y12 hI1 hil 922 Q22 012 012
[y] -2 21 zII v y h 21 A h - 921 I «I ° II

21 22 hII h1
i
AZ AZ
922 022 0 12 0 12

L Z12 I - Y12 922 '912 0 12 A°

h 11 h 12
g
0 22 0 22
A

2 22 2 22 Yil Yll

CÑ
A 9

Y2I AY , 'gm 911 — I 31

2L
h 21
"22 .9
222 Z22 Yll YII a &I 0 22 0 22

I 'Z12 .6, yI2 h22 "h12 g II

,, 021 'A°
v12
z11 211 Y22 Y22 Ah Ah Oi l
(111

[g] ,. ..
MATRIX
INTERRELATIONS
Z1 1 z
11 Y22 Y22 Ah Ah
Y21 Y22 dii Oil

Figure 2.9 Zu Pz 'Y22 -I -ti h 'hIl I 922 Oil 012

221 Z21 Y21 Y21 h21 h21 921 921

[a]
i 2 22 -2 -Yli -h22 -1 911 A° 021 022
2 21 2 21 Y21 Y2I h21 h21 921 921

NOTE A REPRESENTS THE DETERMINANT (A z Z„ Z22 Z21 Z 12 )

56
 SMALL SIGNAL CHARACTERISTICS 2

BASIC AMPLIFIER STAGE

How do the actual dynamic transistor parameters such as rix, rOUT, Ai, A., PG, etc.,
relate to the h-parameter measurements? Well, of course, when the source and load
terminations simulate those of the measurement conditions of the h-parameters then
= h11, rOUT = 1/h22, etc. Figure 2.10 illustrates the black-box of a basic amplifier
stage.

BLACK-BOX REPRESENTATION OF BASIC AMPLIFIER CIRCUIT

Figure 2.10

To keep this analysis general, in order to be able to apply it to all three transistor
configurations we return to the use of h-parameters with numeric subscripts.
It has already been established that when RL = O (short circuited output) the input
resistance rix = hn. For high values of load resistance, however, hn can be significantly
different than rix as can be seen by Figure 2.11. This follows from a matrix analysis
of the h-parametere" which result in the following equations:
(h. ± A° RL)
rIx = (2f)
(1 + h21 RL)
r (h n+ R.)
OUT -
(Ah Rg)
A. i2
— (1 ±
FG = / \• /fl 11 2 RL
ku ) (1 ± h21 RL) (hn ± RL)
where
A. is the determinant of h, A h = 11.2 — hn 1112)

INPUT RESISTANCE (r is)

Figure 2.11 shows that for high values of load resistance (RL/re>1)
(11,211.1
rn.; = hn
/
In terms of tee-parameters ris rb ± re rb.
In the common-base and common-collector configurations, the input impedance in-
creases for increasing RL due to negative values of hni, (ho,) and hn. (h..) as opposed
to positive values for hne (hr.).

OUTPUT RESISTANCE (rou T)

Similarly, for high values of source resistance it has previously been established
that the output admittance is equal to the h-parameter value of hn, hence when
R. co,
1
rour =

57
2 SMALL SIGNAL CHARACTERISTICS

But for low values of source resistance, when

R. 0,
hll 1
rouT = =
Ah h_ (Ian ho)
hn
Figure 2.12 illustrates the behavior of rouT as afunction of R..
10 M
r
INPUT RESISTANCE (r iN )IN OHMS

IN COMMON- COLLECTOR
IM rc'h re erc

100 K

10K
COMMON-
EMITTER
S+19 re
1 K rb Érb + re

( %h2)
22
100
COWMON- BArS
.F
.,/e
r
a +r, /0 10

I/0 .1/50
RiIr c
10 1
0 10 10 -2 10 1 ID ' I2 io 3 10 4 5 NUMERICAL
EXAMPLE
RL FOR TYPICAL
10
10 1K 10K 100K I
M
' 10M TRANSISTOR

INPUT RESISTANCE AS A FUNCTION OF LOAD RESISTANCE

Figure 2.11

10M
ouT)IN OHMS

rOUT COMMON-BASE
r
c
IM

100K
COMMON-EMITTER —
r
OUTPUT RESISTANCE (r

r
c (1/0+ re /rb ) r
ow.= re+ c/0
10K
'rc/a
1K
h22
100
COMMON-COLLECTOR
re + rb/ø
lo
R9 /r,
4
io 1
0
.1 10 2 ib 3 IO 4 io 5
R9
loon IK 10K1-1 IMO

OUTPUT RESISTANCE AS A FUNCTION OF SOURCE RESISTANCE

Figure 2.12

As the source resistance is increased the output resistance (rouT) goes towards its
open-circuited-input value of 1/h.. For low source resistances, the common-base and
common-emitter values of rouT are identical and equal to ro ( r./ro. It should be
noted, once again, that when departing from the h-parameter test conditions which
stipulate that the output be short-circuited with respect to signal (RL= 0), and the

58
 SMALL SIGNAL CHARACTERISTICS 2
input be open-circuited with respect to signal (R. = ), the tee-equivalent values
of rb, r., and ro (see limit conditions on Figures 2.11 and 2.12) are definitely affected
by Early's feedback term and hence are not the generic values.
One other very important factor to note from these figures is that both the input
and output resistances vary the least when the transistor is used in the common-emitter
configuration.

100
e- COMMON- COU_ECTOR'
AMPLIFICATION

/3
(- COMMON- EMITTER'......****N\
10

COMMON-BASE
.........
CURRENT

0.1
10 100 IK 10K 100K IM
RL/r 1
//3

10 -5 10-3 10-2 -1
10 1

CURRENT AMPLIFICATION VS . LOAD RESISTANCE

Figure 2.13

CURRENT AMPLIFICATION (A 1)
The forward current transfer ratio with the output short-circuited (RL= 0) is

A1 = h,, =

At the other extreme, when RL= cc, i2 = 0 and the current amplification factor or
forward current transfer ratio, as it is more exactly defined, is equal to zero. Figure
2.13 shows the typical behavior of AIwith variations of load resistance.
From Figure 2.13 it can be seen that the current amplification Ai is equal to beta
(13) in both the common-emitter and common-collector configurations up to the point
when FL becomes comparable to ro/fi. The only difference is that their sign is different,
as the common-emitter configuration does not exhibit a phase reversal between the
input and output currents, hence we have A, = -Ehro. In the common-collector con-
figuration A1 = —he,, while in the common-base configuration A1 = —hrb.

VOLTAGE AMPLIFICATION (A.)

The voltage amplification factor for both the common-base and common-emitter
configuration is about the same and is equal to ro/rb for high values of load resistance
(see Figure 2.14 ). In the common-collector configuration, Ay 1.

MAXIMUM POWER GAIN

It is obvious that no power gain can be obtained in either the open or short-
circuited conditions, as either the input or output power would be zero. Hence there
exists amaximum value of power gain, which is given by

PGbfAx =
(Vhn h22 Ver
at avalue of RLgiven by

RL=
hn a°

59
2 SMALL SIGNAL CHARACTERISTICS

10,000
VOLTAGE AMPLIFICATION (A v)
COMMON- EMITTER
yr b
1000 COMMON- BASE

100

10

COMMON -COLLECTOR

0.1

0.01

10 10 10 10
—2
10
-I 1
01
1
102 10 3 10 4 10 5

R Ir,

VOLTAGE AMPLIFICATION FACTOR (A,) AS A FUNCTION OF Rh

Figure 2.14

Figure 2.15 illustrates the behavior of atypical transistor. One can plainly see that the
highest gain configuration is the common-emitter, with common-base second, and
common-collector the lowest. It is also apparent that the power gain optimizes at
different values of load resistance (RL) for the three configurations.

1 I
40
COMMON
EMIT TER
30
IN db

I. AMMON -
CO
20
SE
POWER GAIN

10
COMMON -
COLLECTOR
o

10
10 100 IK 10K 100K IM

RL OHMS

POWER GAIN VS. LOAD RESISTANCE

Figure 2.15

TRANSDUCER GAIN
This gain is defined as the ratio of the output power to the maximum power avail-
able from the source. Thus it is a very useful figure of merit for specific source and
load resistance conditions. The transducer gain is
TG= R. = RL][1,, 4A,' RL (2g)
ee/4R,, (vi hRg) . 2= (riN 11.) 2

60
ELECTRICAL
COMMON-EMITTER (CE) COMMON-BASE (CB) COMMON-COLLECTOR (CC)
PROPERTY

RL OPT h
ih ie /h oe A e
h = 47 KI1 i hib /hob A b =322 KII ih io /h oo A h
o = 1075 Q.

A h hie hbe -h fe hre = 23 X 10 - 3 hib h0b --(- hit) )hrb = 5 X 10 -4 h„h oe — (-h ic )hio =-45

hib + ,O, h
b RL hio 4- A h
o RL

r1N
hre+ A h
e RL -
1100
a -16011 - 48.5 K.0
l+h oe RL 1+h ob RL I+h oo RL

SMALL SIGNAL CHARACTERISTICS

hie + Rg hib +R g hio + Rg
-47 KII - 322 KSI - 1050 0
rOUT
Ah
e + hR Ah + A tic + h. Rg
b hob Rg
eeg

hie (-h fb) (

-h fc)
Ai - 19.5 = 0.82 - 43.8
I+ hoe RL I+ hR I+ hoc RL
ob L

2 ,2 ,2
li fe RL (-h fb j RL P .1
1c ) RL

MPG - 42db - 31.4 db - 16.3 db

(I+ h08 R L) (h 8 +A h
e RL ) 0 + ho bRL)( hib +A RL ) (1 4- hocRL )( h ,c +Ah
cRL)

PROPERTIES OF THE IMAGE-MATCHED CONDITION

Figure 2.16

2
2 SMALL SIGNAL CHARACTERISTICS

MAXIMUM POWER GAIN (MPG)

From equation (2g) it becomes apparent that there are optimum values of source
and load resistances for which maximum power gain is obtained. These optimum
terminations are found to match the input and output resistances of the transistor.
When terminated such that fi g = ris and R1. = rorT, the transistor is said to be image-
matched, which is the condition of maximum (low frequency) power gain.
The table in Figure 2.16 gives the equations and typical values to determine such
electrical properties as input resistance, output resistance, current gain and maximum
power gain in the image-matched condition for the three configurations.
In practical low-frequency applications, the image-matched condition is not used
very often as it generally entails the use of input and output matching transformers.
In most applications, DC or RC coupling is used because of the lower component cost.
This presents the transistor with rather restrictive source and load terminations. Con-
sider achain of n-transistor stages. Since the input impedance of each stage is afunc-
tion of its load (see equation (2f) ), acomputation of the input impedance of any one
stage would require the computation of the input impedance of all the stages following
it. It can be shown, that except for the last few stages, the input impedance of each
stage becomes nearly equal to that of the stage preceding it. Such astage is called an
iterative stage.
The iterative input impedance may be computed by setting R. = rm. Note that this
condition is virtually equal to the output-short-circuited condition of the h-parameter
measurements since the ratio of Rill-, is smaller than 1 x 10 -e(see Figure 2.11).
Hence our calculations show that
common-emitter input resistance is rm, hi.
common-base input resistance is riNb es hib
common-collector input resistance is
In general, for an n-stage amplifier, all but the last stage may be considered itera-
tive for the CE and CB connections, while all but the last two stages of aCC chain
are iterative. Since R1. = rue, the iterative power gain is given by

PGI ter•tIve = ie = i2 ) 2
11. 1
riN (I -I- 1122RL) 2
Substituting the iterative input impedance for FIL,
PGcE ..... ti..) (h21.)' 32.8 db
PG cB (Iterative) (h2113) 2 0 db
PGee(it•..ti..)es 1es 0db
From the above, it can be concluded that only the common-emitter configuration
offers any gain in the iterative amplifier case. The common-base configuration only
offers a lower input impedance and higher output impedance, while the common-
collector connection offers high input and low output impedances. Hence the latter
two connections are rarely used and only in cases where special terminations are of
paramount importance. An example design of an image-matched amplifier is illustrated
in Figure 2.17.
Resistors RI and R2 form a bias voltage divider to provide the dc base bias
voltage. R3 provides the emitter potential to fix ade operating point. Since the choice
of bias components is the subject of the next chapter we will ignore the de design
considerations here and concern ourselves only with the signal operation of this stage.
Hence capacitors Cl and C2 will be considered ac short circuits at all signal frequen-
cies of interest, and points A and B are ac grounds. Transformers Ti and T2 match
11 5 to ris and R1. to rOUT, giving us an "image-matched" amplifier. The only discrepan-
cies between the calculated maximum available power gain and the gain obtained in

62
 SMALL SIGNAL CHARACTERISTICS 2

Figure 2.17 EXAMPLE OF IMAGE -

MATCHED AMPLIFIER STAGE

this circuit can be found in the transformer insertion losses (efficiencies). Figure 2.16
describes the calculations of the properties of such astage.

R9 RL

Figure 2.18 EXAMPLE OF ITERATIVE AMPLIFIER STAGE

In the design of an iterative stage (see Figure 2.18), all capacitors are considered
ac short circuits again, while resistors RI, R2, R3 and R4 are primarily there to provide
astable dc operating point. Here RLis equal to the input resistance of the next stage
which is identical (by our definition of iterative) to that of our example amplifier.
The source resistance R. is equal to the circuit output resistance of the previous stage
which again means it is equal to the output resistance of our example. In our iterative
stage, the r1. is equal to hi. which is typically 1400 ohms. Hence RLand R. are also
1400 ohms. Although rouT here can be calculated (as per Figure 2.16) to be about
45 K, the need to provide ade collector load resistance (R4) of small enough resistance
to stay in the linear bias region makes the effective circuit rOUT equal to R4. Usually
this resistance will not be too much larger than hi.. As aresult the typical calculated
iterative power gain of 32.8 db must be adjusted to account for the power losses in R4
(and, of course, the small losses in the de bias network components).
As might be expected from the earlier discussion, h-parameters vary with operating
point. Specification sheets often carry curves showing variation of the small-signal
parameters with bias current and voltage. Such curves are shown in Figure 2.19. These
are specifically for the 2N525 and are plotted with respect to the values at an operating
point defined by acollector potential of 5volts and an emitter current of 1ma.
Suppose, for example, the typical value of hob is required for the 2N525 at 1. = 0.5
ma and V. = 10 volts. From Figure 2.7 the typical value of hob at 1ma and 5volts is
0.6 X 10 mhos. From Figure 2.19 the correction factor at 0.5 ma is 0.6 and the correc-
tion factor at 10 volts is 0.75. Therefore,
hob (0.5 ma, 10 volts) = 0.6 x 10' x 0.6 X 0.75
= 0.27 x 10' mhos.

63
2 SMALL SIGNAL CHARACTERISTICS

hob

10

bib TA •25•C
Vc •-5V

14-htb

h,.

_ h, A
41, •

hf

hi.
bib

0.1
-0.1 -03 -10 -30 -10
EMITTER CURRENT IE lMA)

CHARACTERISTICS VS EMITTER CURRENT

— TA 25•C
___ IE mIMA
30 hob

o
I-0

ri

0.3
I

01
-30 -10.0 -30.0
COLLECTOR VOLTAGE, (V c

CHARACTERISTICS VS COLLECTOR VOLTAGE

VARIATION OF h-PARAMETERS WITH BIAS CONDITIONS

Figure 2.19

64
 SMALL SIGNAL CHARACTERISTICS 2
Once the h-parameters are known for the particular bias conditions and configura-
tion being used, the performance of the transistor in an amplifier circuit can be found
for any value of source or load impedance.
Figure 2.20 gives the equations for determining the input and output impedances,
current, voltage, and power gains of any black-box, including the transistor, when any
set of its four-pole parameters (z, y, a, h, or g) are known or have been calculated.

z y h g a
& +z„z 1 y22 +y l An+6 11 yi 922 -1•21 au zi +0 12
z,
1 22+ Z1 e Ilan h22+21 e +911z1 02121+022

e +.„;,, yip +y, 4+2, e +9,2y, 0..2 9+%

zo lu +2.
e +y,. YQ ie + h22z, gm + yg 02i 2, +011

221 z1 Y21 -6 21 21 21
- 921 11

AV Az +1 11 21 y22 4-yi h11 +ert 922 +2 1 an +0 11 11

221 - Y21Y1 -9 2121 921 1

Ai 222 ,21
eiliin h22+21 0+0 zt 022+021z1

PROPERTIES OF THE TERMINATED FOUR-TERMINAL NETWORK

Figure 2.20

Part 2— High Frequency Considerations

ADDITION OF PARASITIC ELEMENTS TO THE LOW-FREQUENCY
EQUIVALENT CIRCUITS

JUNCTION CAPACITANCES
As soon as the transistor is operated outside its low-frequency range (generally
above audio frequencies), the presence of reactive components within the transistor
becomes apparent. The barrier layers separating the emitter and collector from the
base are regions containing strong electric fields. This implies that there are capaci-

ai
e

TRANSISTOR T-EQUIVALENT CIRCUIT VALID FROM

LOW-THROUGH-MEDIUM FREQUENCIES

Figure 2.21

65
2 SMALL SIGNAL CHARACTERISTICS

tances associated with these regions. These are identified as barrier capacitances, also
sometimes referred to as junction, depletion layer, or transition capacitances (see
Chapter 1).
Figure 2.21 illustrates the addition of these capacitances to the low-frequency
T-equivalent circuit. The differences between this equivalent circuit and that in Figure
2.3 is that besides adding the junction capacitances C. and C., the base resistance ri,'
(from b-b' )and the emitter resistance r., are the generic values, with Early's feedback
term accounted for by the addition of the internal generator hm,' v.b. This manipula-
tion allows us to work with the feedback term independently and know that the emitter
diffusion resistance r. KT/q IEand rt, = rt,' (the physical value of the base spread-
ing resistance ).
There are actually two types of capacitances associated with any semiconductor
junction: transition capacitance (CT) and diffusion capacitance (CD).
Transition capacitance is due to the high electric field in the depletion region
caused by the voltage across the barrier. Hence the transition capacitance is voltage
dependant. The diffusion capacitance is due to the current flowing through the deple-
tion region. Hence Co is current dependant. The total junction capacitances (C. and
C.) are the sum of the transition (CT) and diffusion (CD) capacitances.
The collector capacitance C. is primarily made up of the transition capacitance
CTC as the diffusion capacitance is small in a reverse biased junction. The emitter
junction, being forward biased, will, on the other hand, primarily consist of the
diffusion component.

PARAS ITIC RESISTANCES

Base Spreading Resistance. r.'
The active portion of the base region of a transistor is not equipotential, but
exhibits an ohmic resistance to the flow of base current. This parasitic resistance is
called the base-spreading resistance, rt,'. (The term base-spreading resistance is due to
the shape of the base of an alloy junction transistor which "spreads out" as one
progresses from the center of the junction to the periphery of the transistor)."' The

NOTE: Although the sheet resistivity is uniform in the base, the width of
the base is modulated (Early effect) causing resistance RI, R2, and R3 to
become effectively non-equal. Resistors RI and R3 which are on the
periphery will be smaller than R2. The sum of RI, R2, and R3 make up
actual base spreading resistance re. Resistors R4 (material bulk or sheet
resistance) and R5 (base contact resistance) are in series with ri,'. Even
though these are extrinsic resistances and are not collector modulated,
they are generally considered an integral part of re. It is then convenient
to call this term rob' (total resistance from b to b'). The non-shaded
portion of this figure is the active base region.

PHYSICAL DIAGRAM OF ALLOY-JUNCTION TRANSISTOR

BASE RESISTANCE
Figure 2.22

66
 SMALL SIGNAL CHARACTERISTICS 2
prime in the nomenclature is due to the fact that rb' is defined as the resistance between
the external base contact and point b' (see Figure 2.21 )which is apoint in the active
region of the transistor which cannot be reached. (Sometimes this spreading resistance
is also designated as rbb' — or resistance from point bto b'. )

EMITTER LEAD BASE LEAD

EMITTER
BASE

COLLECTOR

(A) ALLOY JUNCTION (B) PLANAR PASSIVATED

CROSS SECTION VIEWS SHOWING DISTRIBUTED

NATURE OF r, 'AND C,

Figure 2.23

This base resistance is not purely resistive but takes on adistributed form (trans-
mission line) in many transistor structures. (See Figures 2.23 and 2.24.) In general,
however, in order not to excessively complicate the analysis, it will be assumed that
rbb' is resistive. As will be seen later, rbb' is a most objectionable parameter, since it
contributes to the deterioration of transistor performance in many ways.

Leakage Conductance
In all transistors, there exists a certain amount of leakage current from collector
to base. This effect can be represented by a corresponding leakage conductance go
connected in parallel with the collector capacitance. However, this leakage conductance
is extremely small for areliable modern transistor and is therefore generally ignored.
At one time this leakage component was actually thought to be the collector conduc-
tance ge. Early (s) suggested, however, that another phenomenon, presently called the
Early-effect, base-width-modulation, or space-charge-layer-widening was the cause of
the predominant portion of this collector conductance.
The Early-effect takes place in all transistors because the collector depletion region
extends into the bise. The depth of this penetration, and hence the base width, depends
on the, collector voltage. As a matter of fact, if the collector voltage is increased
sufficiently the depletion region can penetrate so deeply into the base region as to
reach all the way to the emitter causing punch-through, a condition describing the
fact that there isjan effective emitter-collector short-circuit. For small-signal voltages,
the effect will n tbe as drastic, but does cause added complexity in the equivalent
circuit. This added complexity was previously illustrated by the differences between
the "generic" and "effective" terms of re and rb, or if one wants to avoid confusion,
the use of the feedback generator term 11,2' veb.
There is also an effect on the collector resistance re since the magnitudes of aand
pare functions of base width. This base width is effectively modulated by the signal
at the collector causing a modulation in the current amplification. Hence the output
port of the transistor feeds energy back to the input port and vice-versa, giving us both
acapacitive term CTC as well as aresistive term re in the collector junction.

67
2 SMALL SIGNAL CHARACTERISTICS

ce

r'

+ R4 +R5 R4 + R5 e EXTRINSIC
RESISTANCES

EQUIVALENT CIRCUIT WITH DISTRIBUTED r

b'
(ALLOY JUNCTION MODEL)

Figure 2.24

Extrinsic Resistances (re', rb' and ro')

As can be seen in Figures 2.23 and 2.24 there is some series resistance associated
with bringing the active base region out to the transistor's external terminals (leads).
In the case of the base resistance in Figure 2.22 it is the slim of R4 and R5; specifically,
the sum of the resistances of the semiconductor base bulk-material, the contact resist-
ance at point B, and finally the resistance of the lead itself. The lead resistance will
generally be extremely small but both the bulk resistance and the contact resistance
can be appreciable. In high frequency transistors, having extremely small junctions,
such resistances can be as high as several hundred ohms. Generally such high values
are only found in series with the collector junction (collector saturation resistance),
since the collector region consists of high resistivity material in order to provide
reduced capacitance and increased voltage breakdown ratings. In the base and emitter
regions this extrinsic resistance is minimized by the use of relatively low-resistivity
material; hence, here afraction of one ohm up to afew ohms is more typical.
In general, then, one might be tempted to neglect the extrinsic base and emitter
resistances. This can lead to serious errors in some transistor structures, however. In
some diffused-base transistors the base region is so small that it becomes difficult to
make agood, solid electrical contact to it, resulting in an increased rbb'.
In transistors with extremely small geometry, like some UHF transistors, the same
problem exists in the emitter contact, hence an increased r.' occurs. When operated
in the common-emitter connection this r.' acts like an unbypassed (internal) emitter
resistance and results in decreased gain and increased noise figure. Figure 2.25 shows
these extrinsic resistances in the total equivalent circuit of the transistor. This model
consists of the intrinsic* transistor and all extrinsic* elements such as the depletion
layer (or transition) capacitances CTE (Ce) and CTC (C0) as well as contact and bulk
resistances such as r.', rb' and
*Intrinsic and extrinsic are used here in their general meanings as "belonging to" or "not belonging
to" the essence of the device.

68
t.. 1•C

FOR TO-18 CASE ,

Ce T CD.
Cpec 5 0.75 pfd, TYPICALLY 0.5 pfd.
Coen ≤ 0.75 pfd, TYPICALLY 0.5 pfd.
Cpoo≤ 0.75 pfd, TYPICALLY 0.5 pfd.
1...1.bB le‘ DEPENDING ON LEAD
LENGTH COULD BE AS HIGH AS 40 nh.
it, el k .TYPICALLY 2-5 nh.
roe TYPICALLY 2 OHMS, BUT COULD BE AS

SMALL SIGNAL CHARACTERISTICS

HIGH AS 20 OHMS.
1100, TYPICALLY 30-60 OHMS.
r,',TYPICALLY 8-10 OHMS.
CINTRINSIC TRANSISTORi
KT/cfl EIS 25 OHMS AT Imo
(ROOM TEMPERATURE"..300 ° K
r,•1-2 MEGOHMS.
L ACTUAL TRANSISTOR PELLET rb,'• 10-300 OHMS

TRANSISTOR CAS75

MODEL OF REASONABLY COMPLETE HIGH FREQUENCY TRANSISTOR WITH TYPICAL VALUES

(IN HF T-EQUIVALENT CIRCUIT)

Figure 2.25

2
2 SMALL SIGNAL CHARACTERISTICS

Lead Inductances
Up to this point, one only has the model of the transistor proper before it is placed
into a package. Leads must now be used to connect the transistor structure to the
header, hence the inclusion of inductances 18., lib and L. The header itself is gener-
ally made of metal with tiny glass-passages for the leads, giving us lead-to-case and
lead-to-lead capacitances Cpeb, Cpbe and C00 0. Emerging from the transistor case are
three leads, which can of course be cut very short to reduce the external lead in-
ductances L, Lb and L.
As can be imagined, the lead inductances are very small, in the order of a few
nanohenries and therefore they only become important for operation in and beyond
the VHF band. At and above VHF these inductances act as rf chokes, having
appreciable impedance in some cases. For instance, the inductive reactance of 20 nh
at 500 mc is in excess of 62 ohms. If this inductance were situated in the emitter lead
connection, the effective increase in input impedance, and hence drop in gain, could
be appreciable. Let us assume that we operate below 50 mc, however, and that we
minimize the external lead inductance of the transistor (while we hope the manu-
facturer has reduced the internal lead inductances) then all transistor inductances
can be neglected in the calculations. Before we attempt to eliminate all stray re-
actances, however, let us say aword about the stray package capacitances. 1"

Header Capacitances
The TO-18 transistor package, presently extensively used for high frequency
transistors, typically exhibits about 0.5 pfd for Cpeb, Cpbc and Coo.. If one works with
high capacitance transistors, having CTE and CTC in excess of 5 pfd, this does not
represent an appreciable amount of added parasitic capacitance. For good high fre-
quency units (VHF and UHF transistors) having only 0.5 — 2 pfd of CTE and CTC,
these parasitic capacitances may become excessive. In acommon-emitter VHF ampli-
fier, for instance, the collector-to-base package capacitance can add directly to the
transition capacitance. This adds feedback to the transistor since it returns a portion
of the output (collector) signal to the input (base) connection thereby making the
transistor more bilateral. External neutralization can generally eliminate this added
package capacitance since one has reasonably close access to points e", b", c"'
assuming the external leads are cut short. This is unfortunately not quite the case
with the internal transition capacitances CTE and CTC. The latter are isolated from
points e", b" and c" by ro', rb' and ro' making perfect unilateralization (signal flowing
only in the forward direction) very difficult to achieve.
In general, one can summarize the case for (or maybe we should really say —
against...) the parasitic reactances in the following manner: as the operating fre-
quency increases, all parasitic elements must be minimized, be they resistive as ro', rb'
and ro' or reactive as CTE and CTE; be they an integral part of the transistor or of the
package as all Co's and l's shown in Figure 2.25.
Part of this reduction can only be accomplished by the device manufacturer, as
only he can design both the device and its package for minimum parasitics. Part of
this reduction must be assumed by the user by making an educated choice of the
optimum device to be used for agiven application at agiven frequency, and how to
best connect it into the circuit.
Therefore our first simplifying assumption is to neglect all device inductances,
which should not create appreciable inaccuracies below 200 mc if we cut external
lead lengths to a bare minimum. The second simplification is to lump the existing
extrinsic resistances in with their intrinsic relatives, hence rbb', r
o and ro are the lumped

sum of the various resistances in each branch of the structure. The third simplification
will be to lump the package and device capacitances. Such approximations will not

70
 SMALL SIGNAL CHARACTERISTICS 2
give us the epitome of exactness but will allow us to predict the performance of our
circuit in the mid-frequency range (from above audio to the low VHF frequencies)
with reasonable accuracy.

CONSIDERATIONS OF THE EQUIVALENT CIRCUIT

The variety of equivalent circuits used at medium and high frequencies, range
from the simple but not very accurate, to the accurate but very complex representation.
Neither extreme is very useful and one should therefore use areasonably accurate but
analytically manageable equivalent circuit.
One of the most popular high-frequency equivalent circuits is the hybrid-ir
common-emitter circuit of Giacollettow Figure 2.26 illustrates this circuit which has
the advantage of closely tying the electrical parameters to the physical structure of the
device. Figure 2.26(A) shows the general form of this equivalent circuit, Figure
2.26(B) shows the high-frequency simplification of this equivalent circuit. Since the
bulk of small signal amplifier circuits use the transistor in the common-emitter con-
figuration, this equivalent circuit sees frequent use.

rbb'

cr e I
g be ' re - h, e r
e

CDe 2, f
1, re

V be
Vbe
gce'

-
gcb -e gc

C„ c

I
e

(A) MEDIUM FREQUENCIES

rbb ' b.
(Crc)
r +a r' I
r
bb+r,
I— ae

b Cb e

be (cDe)

INCREASING
FREQUENCY

NOTE: AT AND ABOVE VHF NOTE: WHEN APPROACHING f, ,THE

THE SERIES LEAD-INDUCTANCES REACTANCE OF Cb'
e BECOMES A
MUST BE CONSIDERED ALSO.
SHORT ACROSS gb'
e LEAVING ONLY

A Relh„I rb Ç.
e

(B) SIMPLIFICATION AT HIGH FREQUENCIES

HYBRID-7 EQUIVALENT CIRCUIT (C) CHARACTERISTICS OF THE SHORT

CIRCUIT INPUT IMPEDANCE

Figure 2.26 VERSUS FREQUENCY.

The base spreading resistance rbb' in this hybrid-ir equivalent circuit, is the actual
base resistance appearing between the active region (point b') and the external base

71
2 SMALL SIGNAL CHARACTERISTICS

contact (point b). The emitter conductance g.'. is not merely the reciprocal of the
emitter diffusion resistance (r.) here, but since the base current appears amplified by
hf. in the emitter ge'. becomes 1/hf. r.. The emitter capacitance, however, is not
affected by this mechanism, thus C.', is approximately equal to the emitter diffusion
capacitance

Ce = --
274 tr.

The hybrid-,r collector conductance (gr.') and capacitance (Cr.') are the afore-
mentioned Early-conductance (gr) and transition capacitance (Cm) of the collector
junction. There remain two elements to consider in this equivalent circuit: collector to
emitter conductance, g„.; and the current generator, g.

Collector to Emitter Conductance (g o.)

As previously explained, it is generally more convenient to deal with an equivalent
circuit composed of mostly generic parameters and then account for Early's base-
width modulation by afeedback generator (L NO added in the emitter branch. In the
hybrid-r, we can take account of this feedback term, by inserting aconductance (gr.)
between the collector and emitter. This conductance will have avalue of

g— =-
e-
r„.
since
Vep..
r.
for constant ve',..
Current Generator (g o.ve'.)
The value of this current generator depends on the internal base voltage ve'.. Thus,
gm is determined by aL, = g., ve', which yields the transconductance
g . = al:

V. e
since
1
V,,', r.
a 1 hr.
gm =
r. rix — r..'
where gm is the intrinsic transconductance. Any internal series resistance or reactance
such as the extrinsic emitter resistance r.' (or even an external unbypassed emitter
resistor), or the series-lead inductance in the emitter(' will reduce the effective value
of transconductance which we shall define as gm', where

gm'= (2h)

The intrinsic transconductance is constant over an appreciable frequency range.

At high frequencies, the emitter-to-base capacitance C.'. effectively shunts ge'r, thus
reducing gm and giving us atransconductance cut-off frequency (where gm is reduced
to .707 of its low frequency value). This frequency is
re.
''± ree
fgm = (2i)
2r rb'. Cb 'e rbb '

In this equation re'. = —17= r1N —

g.

and 1
zw• re 'e fhi.
C, ' .

72
 SMALL SIGNAL CHARACTERISTICS 2
At high frequencies, the emitter lead inductance also starts reducing gm' as the
following example shows. If g. m 1/r.., g., .04 mhos at 1ma. Assuming aseries in-
ductance of 10 nh and r„' of 5ohms, g.,' = .04/ 1 .04 (5 j6.28) .03 mho.
The parasitic elements have reduced g,. by 25% at 100 mc. Furthermore, if the tran-
sistor is operated at several milliamperes (Ir) the effect will be much more drastic
since gm is higher as current is increased. To summarize what has been illustrated so
far on the subject of transconductance
g„. is relatively constant from low through medium-frequencies.
gm has acut-off frequency given by equation (2i) whose only reactive element
is G,'„.
Total measured transconductance is the intrinsic transconductance (gm 1/r„)
modified by the extrinsic terms in series with the active device as illustrated by
equation (2h). Therefore the extrinsic emitter resistance, and any external
unbypassed emitter resistance as well as both internal and external emitter
inductances must be minimized for good high-frequency operation.

Transconductance enters into both the voltage and power gain equations in the
following manner:
Voltage Gain
A. gm'
— 2
Power Gain
p . g.' )
2rix R.

— 4
Now let us reflect for a moment on the hybrid-ir equivalent circuit and decide
what values its elements should have for good high-frequency operation.

Base spreading resistance rid,' forms alow-pass filter with Cje, hence both rim'
and Cb'e must be reduced as much as possible.

Emitter capacitance also shunts g.'„ (see graph of hn versus frequency in

Figure 2.26(B) )thus reducing gm at high frequencies, hence once again Ci,'„
should be minimized.

Transconductance is essentially equal to hf./rix 1/re. The effective transcon-

ductance is reduced by extrinsic device and unbypassed external emitter re-
sistance and inductance. These latter must therefore be minimum, both in the
device and the external circuit.

Collector capacitance, Orr, provides a feedback path between collector and

base (b'). A large collector capacitance increases the feedback with resulting
lack of stability (determined by the ratio of forward to reversed gain, the
so called loop gain).

At low-to-medium frequencies it suffices to know gm, riz and rOUT to equate voltage
gain and power gain. As the transconductance cut-off frequency can be determined
from equation (2i), one can see when an appreciable error would result by using the
low-frequency gm value. The input and output impedance at low-to-medium fre-
quencies can be calculated (or measured) and from these one can calculate the power
gain, voltage gain, and stability factor. The input and output impedances will soon
start to be affected by their reactive components, however, and at medium frequencies
(in relation to the capabilities of the transistor) they will become complex and difficult
to determine analytically.

73
2 SMALL SIGNAL CHARACTERISTICS

As a matter of fact, the use of equivalent circuits is more useful to the device
designer than to the circuit designer. The former must optimize the structure for its
applications. The latter finds to his disappointment that the manufacturer does not
specify all the elements of the equivalent circuit. The reason for this, as the circuit
designer soon finds out, is that the elements of the various equivalent circuits are
difficult to measure accurately. In desperation both device and circuit designer gen-
erally turn to the black-box parameters (as these can be measured accurately). Plug-
ging the measured values into well established two-part analysis gives all the necessary
information for circuit design. Before we fully abandon the equivalent circuit tech-
niques, however, it should be noted that afull grasp of the equivalent circuit is useful,
if not necessary, to evaluate device limitations as well as to compare one device to
another. For example, two devices with equal input impedance may have appreciably
different values of hf., rbb' and re', thereby yielding radically different performances.

CONSIDERATIONS OF THE TRANSISTOR'S FREQUENCY

LIMITATIONS
GAIN-BANDWITH PRODUCT
When operated at low frequencies in the common emitter configuration the tran-
sistor exhibits ashort-circuit current gain (R,.<<roirr) of h,,.. This value may vary
in modern transistors from alow of 20 to ahigh of several hundred. As the signal
frequency is increased, the magnitude of h,. decreases and its phase shift increases.
This is due to the fact that when carriers are injected into the base-emitter junction

COLLECTOR

C.

o
rt;
BASE oc SHORT CIRCUIT

i\J INPUT
SIGNAL

EMITTER

VARIOUS TIME-CONSTANTS LIMITING THE GAIN -

BANDWITH
PRODUCT OF THE TRANSISTOR
Figure 2.27

they will take a certain time to cross into the collector region. As a matter of fact,
if we look at aphysical picture we see (Figure 2.27) that there are three* time con-
stants limiting the speed of the injected carrieren: emitter time-constant re Ce, collec-
tor time-constant re CTC (since the collector is shorted to the emitter), and base transit-
time rB.
Lindmayer et al 10 'defines the sum of these three constants as the gain-bandwidth
product f t,since it is the frequency at which 'hr.' falls to unity, thus

f= 1
2ir [rB -I- r
e (Ce Ce)]
*If the collector bulk resistance is appreciable afourth time constant X Ore must be added.

74
 SMALL SIGNAL CHARACTERISTICS 2
It can be said that even if C. (Cb'. )and C. (CTc) were made very small, the base
transit-time would still limit the frequency response of the transistor. Therefore one
must design high gain-bandwidth (ft) transistors with extremely thin base regions
and/or add an accelerating field into the base region. A good modern high-frequency
transistor might have
r, Ci,'. of 25 x 1x 10' 2 = 0.025 nanoseconds
r. CTc of 25 x 0.4 x 10 = 0.010 nanoseconds
Tb of 125 X 10' = 0.125 nanoseconds
Total time for carriers to reach collector = 0.160 nanoseconds
1 1
Hence f
t= 1.0 kmc
TCtot.i 6.28 x 160 x 10'
A large collector bulk resistance will add afourth time-constant of r.' CTc, which if
r.' = 100 ohms and CTC = 0.5 pfd gives the carriers another delay of 100 X 0.5 X 10 -"
= 0.05 nanosecond, reducing ft to 760 mc. Thus a good high frequency transistor
should also exhibit low extrinsic collector series resistance (r.'). In epitaxial transistors,
r.' is small and this fourth time-constant can be made negligibly small.
Let us plot hf., hfb, and maximum available power gain (MAG) versus frequency
for atypical 2N918 UHF transistor.

Ihf.41
feo MAG
- 40db
MAG

1.0 hf, o
3db
-
0.707 3 - - te
30db if

fh, e

Ih ie1 2.r eep

MAG

20db hfbo

1+ fhtb

10db ft •fh te x

Odb
-3db 1
htbl
—
I I
I I

-10db
I I
II
II I
-20db
fli fe 511:t fe fffb MAX
h f

011mc LOmc I0.0mc I00.0mc 1Kmc 1.6Kmc 10Kmc

MAG, Ih,. I, Ihn, VS .FREQUENCY OF TYPICAL UHF TRANSISTOR

Figure 2.28

The first deduction we can make is that there is an exact relationship between ft
and hf.. (hf.. X flif. = fa, both values generally supplied by the transistor manu-

75
2 SMALL SIGNAL CHARACTERISTICS

facturer. Secondly at a frequency 5 times this beta cutoff frequency (flit.), a 6

db/octave slope has been reached. Along this 6 db/octave slope the product of Ihf.1
and its corresponding frequency is aconstant, defined as the so-called gain-bandwidth
product. The constant has the dimension of afrequency, is called ft, and is attained
when Ihr.! = 1.

ALPHA AND BETA CUTOFF FREQUENCIES

We have seen in the gain-bandwidth discussion that the beta-cutoff frequency
(fhf.) can be used as an aid to locate the proximity of the 6db/octave slope. Actually,
modem transistor circuit analysis has done away with the formerly much used "alpha
cutoff frequency" (fht,) and "beta cutoff frequency" (fht.)."" As Pritchard pointed
out in an earlier editorial,'tm the modern transistor is primarily frequency-limited by its
emitter, base, and collector time-constants, and may not be usable at fhf, (as amatter
of fact, due to feedback, there may not even be an fht.). We shall therefore satisfy
ourselves to only define these two frequencies, and use flit, only as an aid to locate
the end of the 6db/octave slope.
Alpha cutoff frequency is the frequency at which the common-base current gain a,
falls to 0.707 of its low frequency value (hrbo). In modem transistors film is usually
somewhat above f t.

Beta cutoff frequency is the frequency at which the common-emitter current gain p,
more recently identified as ht., falls to 0.707 of its low frequency value (ht..).
Transconductance cutoff frequency f, is the frequency at which gm falls to 0.707
of its low-frequency value, as previously seen in our discussion of the hybrid-jr equiva-
lent circuit.
Maximum frequency of oscillation f..«, is the frequency at which the maximum
available unilateralized power gain (MAC) falls to unity. Looking at the equation for
MAC in Figure 2.28, it can be seen that as 114.1 drops to unity there still is apower
gain given by ro.,/4r,.. (impedance ratio of output to input impedance). Hence f...
will be generally higher than f,. f..,, is sometimes also referred to as the (power
gain)" (bandwidth) product"); stated as VPG X BW which gives us a 6 db
PG/octave slope, but should not be confused with f,. As a matter of fact, we can
draw some other interesting conclusions from the MAC equation. The series input-
impedance ri.. is the real part of hi., which as we approach f, (on the 6 db/octave
slope) is approximately equal to rb,', see Figure 2.26(B). The parallel output-impedance
ro.,, is really the reciprocal of go.„ (the real part of the output admittance yo..) and is
approximately equal to

ro., 1
ft CTC
since
2-1 rm.' (2k)

and 114.1' = (11 )2 (along the 6db/octave slope)

fo
f, r 1

fo f 2 fC
MAC = 1•••-• (to determine f..., f., = f..)
4rbb'
ft
or MAC tir (rbb' C IT) (21)
therefore
f... = ft (2m)
8rbb CTC
'

76
 SMALL SIGNAL CHARACTERISTICS 2

Several conclusions can be drawn from the above equations. Providing one operates
the transistor in the 6db/octave slope, which extends from ft back to about 5fhf., a
knowledge of
ft
hr..
rbb'
or at least the rbb' CTC product
CTC
gives us areasonable figure of merit of the transistor, as we can easily derive approxi-
mations for
(see equation (2k ))
r... (see equation (2j ))
MAG (see equation (21) )
(see equation (2m ))
The manufacturer of high-frequency transistors will usually give the four required
parameters, as they can be measured (relatively) easily. It can be said that the high-
frequency performance of atransistor is primarily determined by the four parameters:
ff', rbb', CTC (Cb r) and CTE (Ch e). CTC imposes an upper limit on output impedance
' '

(r,), rbb' alow limit on input impedance (rt..), CTE limits ft while ft in turn limits
ihf.1 at the operating frequency.
Figure 2.29 is anomagram which relates the various parameters to make possible
arapid determination of the maximum available unilateralized power gain (MAC )at
frequencies above 5fhf, (with reduced accuracy down to fhf.).
Step 1consists of placing astraight edge to join the values (generally specified
by the manufacturer) of f, and rm.' Ore and thereby locating In the example
on the nomogram an ft of 1kmc and an rid,' Ore time-constant of 15 psec gives
an fmAx of approximately 1.6 kmc.
Step 2 then consists of placing the straight edge on the operating frequency
( 100 mc in the example) and joining f, with the determined in step 1
(1600 mc). The maximum available (unilateralized) power gain is then read off
the MAC scale. In our 100 mc example, the MAC is approximately 24.5 db.

THE USE OF BLACK-BOX PARAMETERS (h Or Y)

One other method of high frequency characterization is to use two-port parameters,
considering the transistor simply as ablack-box having one input and one output port.
This analysis is much more exact, since it uses the terminal properties of the tran-
sistor, rather than the internal parameters of an approximate equivalent circuit. This
method applies to any linear two-port active device and is amenable to matrix analysis.
The main disadvantage is the lack of direct relationship to the physical equivalent
circuit, although this is generally of little concern to the circuit designer. He finds the
use of black-box parameters attractive because the manufacturer gives them on his
high-frequency transistor specification sheets. Furthermore, both the manufacturer and
user can measure the black-box parameters more easily than the elements of the
equivalent circuits. The two-port parameters of the linear active network completely
describes its performance. It is thus possible to derive complete and accurate gain and
stability expressions at any frequency, "plug-in" the measured values of the parameters
and "crank-out" the results.
In general, any of the many sets of two-port parameters (z, g, h, y, aand b) could
be used. Because at high frequencies it is more convenient to measure the y-parameters,
the latter seem to be used predominately on manufacturer's specification sheets. Refer-

77
2 SMALL SIGNAL CHARACTERISTICS

NAG r
bt; C
TC f f
db PICOSECONDS MEGACYCLES

33 -

32 -_ 2000 -

31 1.2
1500 -
30
1200
29 --2

28% 2.5 1000 -

900 -
27 3 800 -
700 -
26 %4
25 % 600 -
MAGa 24.5db-. " fMAX
24 6 500 -
MEGACYCLES 450 -
23 400 -
-8
350 -
22 4000 -
21 -\..12 3000 - " 0 3000
2500 - 250 r 2500
20 ie Cle l5 Psee
r
aI600 mc -2000
200-- 1500
19`- 20 STEP
1500 - -1200
18% 25
1200 - eeep 1000 f.1Kmc
17 ,-30 800

600
1000 150

16% 800 120

10
40
00,4c
15- 600 400
-50 500
90 — 300
14 60
400 80-, 250
I3-,70 70 _, 200
-80 300
250 - 150
12 60 %
-100 120
200
11 -120 so< 100
150 45 80
10 --I50
120 40 -- 60
100 35
9 200 5°
80 - 40
8 250 30 30

7 -300
60 25 _r 25
50 - 20
6
400 40 20 15
5 --500 30 - 12
25 - 10
4 -600 15 -
3,- 700 20
-800 12 -
15
2
-1000 10 -
1- 10

NOMOGRAM TO DETERMINE MAG AS A FUNCTION OF r

bb', CTC AND ft

Figure 2.29

ring back to equations (2b) and (2c), the four y-parameters are short-circuit param-
eters and are given as

yil = —= input admittance

vi

y. = —
is = forward transfer admittance
vi

y,, = k= reverse transfer admittance

V2

=-
4-= output admittance
V2
Any admittance y can be resolved into its components of conductance g, and sus-
78
 SMALL SIGNAL CHARACTERISTICS 2
ceptance b, in the following format:
y= g+ jb
hence the input admittance (common-emitter) is
Ylle = yle = gle ible
output ac short-circuited
= y.. = g,. 031.
y12. jbre
= input ac short-circuited
= yr. = gre
y.. g.. iboe
Y'..

The manufacturer's specification sheet will generally show both the real and imagi-
nary components of the y-parameters at agiven frequency and operating point (bias).
Sometimes there may be graphs of these parameters covering the frequency range for
which the transistor has been designed. The next step consists of determining from
these measured values the actual dynamic parameters of the transistor.

CALCULATION OF INPUT ADMITTANCE (COMMON-EMITTER)

YINe
= yi. y'.,
Yfe

Yoe
where n is the load admittance. Since the highest power gain is attained in the
conjugate match* condition, we will make
b.. = —13L
hence
YI
,..
= Yle Yfe yr.

g.. + gt.

CALCULATION OF OUTPUT ADMITTANCE (COMMON-EMITTER)

yut., = -
y'. ± Y.
where
y. = source admittance, if (gi. + g. )> > (bi. -I- b. ),
then
Yfe yr.
YOUTe = Yoe
gi. + g.

CALCULATION OF GAIN

Current gain = yr. yr.

yi. (Y.. YL) — yr. Y..

Voltage gain = — Yr"

y..

Power gain = Yf• 2 gL

y.. -F
To determine stability, the loop gain is calculated. This loop gain is essentially the
ratio of forward to reverse gain and hence should be as large as possible.

Loop gain =Yee Yfe

(n+ Yoe) (n + y.)
if
(gi. + g.)>(bi. + b.) and (g.. + gL) >(b.. + bL);
*A linear four-terminal network is conjugate matched if the generator is the complex conjugate (equal
magnitude — opposite sign or phase) of its input impedance and the load is the complex conjugate
of its output impedance.

79
2 SMALL SIGNAL CHARACTERISTICS

then the
yfe Yre
loop gain =
(gi. + g.) (go. +

MAC = IY"I 2
4gi. g..
Assume a2N918 transistor has the following specified parameters at 200 mc:
lyre' = gf. bf. = Re lyi.1-1- 1m lyi.1 = (20 + j50) 10'
g,. = R. ly1.1 = 8X 10 mho
g.. = Re 0.4 x 10" mho
th en its MAG 2900 X 10' 2900 227 23.6 db
4 X 8 X 10' X 0.4 X 10' — 12.8

The loop gain would be very high, since ye. is minimized (perfect neutralization is not
feasible) in this neutralized condition. Naturally losses in tuned circuits, poorly
bypassed resistors, etc., would subtract from the MAG so that the actual circuit power
gain will be somewhat smaller than this "maximum" amount of power gain.

MEASUREMENT OF y-PARAMETERS
Short-circuit y-parameter measurements can be made by using simple bridge tech-
niques. Readily available commercial equipment such as the Boonton RX Meter*
(range 1-250 mc ), the Wayne Kerr B801 VHF Admittance Bridge (range 1-100 mc ),
and the General Radio Immittance Bridge B-1601 (range 30-1500 mc )will do the job.

REFERENCES
(»Dewitt D. and Rossoff, A.L., "Transistor Electronics," McGraw-Hill, New York 1957.
(5) Pritchard, R.C., "Advances in the Understanding of the P-N Junction Triode," Proceedings of the
IRE., Vol. 46, June 1958.
(8) Early, J.M., "Effect of Space Charge Layer Widening in Junction Transistors," Proceedings of
the IRE, Vol. 40, pp. 1401-1406, November 1952.
to ((Design Theory of Junction Transistors," Bell Telephone System Technical Journal, Vol. 32,
pp. 1271-1312, November 1953.
(5) Shea, R.F., "Transistor Circuit Engineering," John Wiley and Sons, Inc., New York, 1957, (page
74 and Appendix).
( 3) Shea, ibid, page 31.

(7) Gottlieb, Erich, Electronic Design, June 8, 1964.

(* )Giacolletto, L.J., "Study of PNP Alloy Junction Transistors from DC Through Medium Frequen-
cies," RCA Review, Vol. 15, pp. 506-562. December 1954.
(0)Rheinfelder, W.A., "Extending the High-Frequency Response of Transistor Amplifiers," Electronic
Design, December 6 and 20, 1961.
00) Lindmayer, J., Wrigley, C.Y., "Beta Cutoff Frequencies of Junction Transistors," Proceedings of
the IRE, February 1962, pp. 194-198.
("Pritchard. R.L., "Old Parameters Just Slowly Fade Away," Editorial, Solid State Design, October
1963, pp. 8-13.
02) Pritchard, R.L., "Transistor Alpha-Cutoff Frequency," Editorial, Solid State Design, September
1961, pp. 11-12.
(' 8)Early, J.M., "Structure-Determined Gain-Band Product of Junction Triode Transistors," Proceed-
ings of the IRE, December 1958, pp. 1924-1927.

NOTES

* For details see Boonton "The Note Book" No. 19, 1958.

80
 cc
LARGE SIGNAL CHARACTERISTICS
AND TRANSISTOR CHOPPERS
C.3

The large signal or d-c characteristics of junction transistors can be described in

many cases by the equations derived by Ebers and Moll. 1"These equations are useful
for predicting the behavior of transistors in bias circuits, switching circuits, choppers,
d-c amplifiers, etc. Some of the more useful equations are listed below for reference.
They apply with ahigh degree of accuracy to germanium and silicon junction tran-
sistors operated at low current and voltage levels.

PARAMETERS
The parameters used in the following large signal equations are listed below and
indicated in Figure 3.1.

IE

PARAMETERS USED IN LARGE SIGNAL EQUATIONS

Figure 3.1

'CO LBO Collector leakage current with reverse voltage applied to the collector,
and the emitter open circuited (leo has apositive sign for NPN tran-
sistors and anegative sign for PNP transistors ).
IlO I
EBO Emitter leakage current with reverse voltage applied to the emitter,
and the collector open circuited (I E
0 has a positive sign for NPN

transistors and anegative sign for PNP transistors).

as Normal alpha, the d-c common base forward current transfer ratio
from emitter to collector with output short circuited (a has apositive
sign for NPN transistors and PNP transistors). In practice, best results
are obtained if the collector junction has afew tenths of avolt reverse
bias. Since ais afunction of emitter current, the value at that particular
value of emitter or collector current should be used in the large signal
equations.
ai Inverted alpha, same as as but with emitter and collector interchanged.
rE', rE', re' Ohmic resistance internal to the transistor and in series with the base,
emitter, and collector leads respectively.
1E, 1E, lc D-C currents in the base, emitter, and collector leads respectively;
positive sense of current corresponds to current flow into the terminals.
çbc Bias voltage across collector junction, i.e., collector to base voltage
exclusive of ohmic drops (across rE', re'); forward bias is considered
apositive polarity.

81
3 LARGE SIGNAL CHARACTERISTICS AND TRANSISTOR CHOPPERS

rpE Bias voltage across emitter junction, i.e., emitter to base voltage exclu-
sive of ohmic drops (across rE', rE' ); forward bias is considered a
positive polarity.
VgB, Vc5, VEE Terminal voltages: emitter to base, collector to base, and collector to
emitter respectively.
A— cr 1/A = 26 millivolts at 25°C for n= 1.
— e
Electronic charge = 1.60 X 10 coulomb.
Boltzmann's constant = 1.38 x 10" watt sec/°K.
Absolute temperature, degrees Kelvin = °C + 273.
A constant of value between 1 and 2 (n tends to be nearly 1 for
germanium transistors and varies between 1 and 2 for silicon tran-
sistors ).<"
A can be determined from a semi-log plot of the junction forward characteristic
(the semi-log scale is used for the current, while the linear scale is used for the volt-
age). A portion of the plot will be linear, from which A can be determined

A = ln (3a)
AV
where AV is the corresponding change in voltage for a AI change in current on the
linear portion of the plot. This is shown in Figure 3.2 for the emitter-base junction of
agermanium alloy and asilicon planar transistor. Curves are shown for the case of an
open collector and for the case of aone volt reverse bias of the collector-base junction.
Notice that the slope is different for these two cases. The best correlation between
theory and practice results when the A obtained with the reverse bias is used." )

SW
VI

0.160 - 060
— V
=--
/ /
Vg
VEB ,VOLTS (2N634)

0.140 / 058

e/
2
-
0120 056
e
. cb• (0
t
-J
"'At o
„
t. .1,('

0.100 .• *)
054

\ e'
;`'

0.08 032

/
0.06 030
10 100 000
1E ,p.

V, VS. I, FOR A GERMANIUM ALLOY AND A SILICON PLANAR

TRANSISTOR AS A FUNCTION OF AN OPEN CIRCUITED OR
REVERSE BIASED COLLECTOR JUNCTION

Figure 3.2

82
MN LARGE SIGNAL CHARACTERISTICS AND TRANSISTOR CHOPPERS 3
BASIC EQUATIONS
The basic equations which govern the operation of transistors under all conditions
of junction bias are
aNIEo = adco (3b)
1E = E0
I (e Ao, 1) ± ai Ica (eAo ,_ 1)
(3c)
1— aNal 1— aNal

Ic = aN I
N° (eMbE 1) 'CO (ell« —1) (3d)
1— aNal 1— aNai
IN± Ia ± I C= (3e)
The above equations are written for the direction of current flow shown in Figure 3.1
and the sign of IE 0 and lao as given above under Parameters. The three possible areas
of transistor operations are: 1) one junction forward biased and one junction reverse
biased (active), 2) both junctions forward biased (saturated), 3) both junctions
reverse biased (cutoff ).

ACTIVE OPERATION
The transistor behaves as an active device if one junction is forward biased and
the other is reverse biased. Under normal operation, the collector is reverse biased so
tpa in equations (3c) and (3d) is negative. If this bias exceeds afew tenths of avolt,
etc <<1, and it can be eliminated from the equations. The collector current can then
be solved in terms of the leakage currents, current gains, and emitter-base potential,
thus giving the large signal behavior of the device.

SATURATED OPERATION
The transistor can be operated in the normal (grounded emitter) or the inverted
(grounded collector) connection as seen in Figure 3.3. The equations which are devel-
oped for each respective configuration will be labeled "normal" and "inverted." The
directions of base, collector, and emitter current respectively are taken as into the
transistor. Where acurrent flows out of the transistor, it is to be given aminus sign.
When a (±) sign proceeds the equation, the plus applies to a PNP transistor while
the minus applies to an NPN transistor.

(a) Normal (b) Inverted

THE NORMAL AND INVERTED CONNECTIONS
Figure 3.3

The transistor in saturation can be represented by an equivalent circuit as shown

in Figure 3.4. re' and rE' are the collector and emitter bulk or body resistances from

83
3 LARGE SIGNAL CHARACTERISTICS AND TRANSISTOR CHOPPERS IM

the junction to the terminals. The collector to emitter voltage due to transistor action,
0, is determined by the connection:

El [1 T
IC (1 aN
,1 /ix
(Normal ) VeS = \ J—
A , (3f)
[ 1 (1 — al)]

aN [1 (1—
al al )]
(Inverted ) 4, EC = ( --
A-In (3g)
[1 +-- (1 — aN)

Notice that equation (3g) can be obtained from (3f )by replacing I c by Is, ax by ai in

the numerator, and ai by ax in the denominator. If the ratio of load current to base drive,
I
S I
S
or is very small or zero, equations (3f) and (3g) respectively reduce to

(Normal ) 4.CE In al (3h)

(Inverted ) aficc ) 1 In a, (3i)

A

E
nI L UI L
r•¿
.

°CE OEC

ibrc' Ibrc

(a) OA NORMAL (c) INVERTED

CONNECTION CONNECTION

EQUIVALENT COLLECTOR-EMITTER CIRCUIT OF

A SATURATED TRANSISTOR
Figure 3.4

Thus the collector to emitter voltage or "offset voltage" becomes (for an npn transistor)
y
(Normal ) VcE = — -- .n a/ -e ab rE' (3j)
A

1
(Inverted ) Vsc = — an ax -I- Is re' (3k)
A

Since ax and at are functions of base drive, the offset voltage will change as I B is
varied. This is shown in Figure 3.5 which shows the inverted connection offset voltage
of a planar epitaxial transistor as a function of base current. From zero, the offset
voltage decreases with increasing base drive because ¡LE is increasing. At some base
drive, the offset voltage becomes aminimum. Above this, the offset voltage becomes
a linear function of I 13 since the I
Bre' drop predominates. The slope of VEC VS. I B
curve in this region (with IE = 0) gives r e'. Likewise, by operating the transistor

in the normal connection (with Ic = 0) the slope of Ves VS. I Scurve at the higher
values of base current (I B> 1ma) gives rE'.

84
IM LARGE SIGNAL CHARACTERISTICS AND TRANSISTOR CHOPPERS 3

08

06

04

SLOPE. r• .
0811

02 -

O I0 20 30

Ia rO

V, VS . I FOR 2N2152

Figure 3.5

Since at < ax for most transistors, the offset voltage of the inverted connection
will be less than that of the normal connection. Thus in low level chopper circuits, the
inverted connection is always used. Examination of equations (3f) and (3g) shows
that the sign of ("ice and cpEc can be made to reverse by forcing a load current from
collector to emitter for aPNP transistor and from emitter to collector for a NPN tran-
sistor. Thus, the emitter to collector terminal voltages VEc or VcE can be made zero.
The transistor in either mode of operation will remain saturated as long as the
bracketed terms in the numerator or denominator of equations (3f) and (3g) remain
larger than one. Thus, the transistor behaves as a"closed switch," and the load current
can flow through the transistor from collector to emitter or emitter to collector, depend-
ing upon the polarity of the load supply. If either the numerator or denominator term
which is bracketed becomes zero, the log becomes infinite and the transistor comes
out of saturation. Since al < ax, it can be seen from equations (3f )and (3g), that both
the normal and inverted configurations will become unsaturated respectively at lower
Ic IE
ratios of —
IB & if the load current passes from collector to emitter in aPNP tran-

sistor, and from emitter to collector in an NPN transistor.

By differentiating equation (3f) and (3g) respectively with respect to Ic and 1E,
and adding the bulk resistances, the dynamic impedance of the saturated transistor can

be found. If (1-- aN Is ( 1— al
are much less than 1, then
aN ) and

1 (1— at ax)
(Normal) rdx r
E' ro'
A\ at

(Inverted ) rdi 1 \1— at aN)

A IB rE' rd

and rdt = ax
— —
raN ai

if rE' rc' <G ay

A \ IB ax /

85
3 LARGE SIGNAL CHARACTERISTICS AND TRANSISTOR CHOPPERS

For base currents where the above inequality holds, the dynamic impedance is in-
versely proportional to the base current as shown in Figure 3.6. Also, the dynamic
impedance of the inverted connection is larger than that of the normal connection
since ax < al. (This is in contrast to the offset voltage where it is smaller for the in-
verted mode than for the normal connection.)

loo )

eo
-- TRUE HYPERBOLIC IFUNCTION —

60 MEASURED
C
TU
AL
NA
cT
EE,O
rd .orl
A

40 \\ DYNA —
MIC TRESIS

‘
1 FUNCTION OF BASE DRIVE

20

\
\\

\
\
10

......„.............

Figure 3.6
.4 .6 .8 10 1.2 14 1.6 18 2.0

19 ma

CUTOFF OPERATION
By reverse biasing both emitter and collector, equations (3b), (c), and (d) can
be solved for the emitter and collector currents
(Normal ) Iv = Io1
0(1 — al)
— asai (30)

(Inverted ) I
FO (1 — ax)
=
(3P)
— axai
Equations (3o) and (3p) indicate that with both junctions reverse biased, the col-
lector current will be less than Iv,, and the emitter current will be less than IE0. Also,
the inverted connected will result in the lowest leakage current in the load. While this
is true for germanium transistors, it is not true for most silicon transistors. The reason
for this is that the alphas of the silicon transistor are almost zero at collector or emitter
currents given by the leakage currents. Leakage currents for well made signal planar
transistors at low voltages are below a nanoampere.

USEFUL LARGE SIGNAL RELATIONSHIPS

The relationships given with an asterisk *(opposite page) apply only to germanium
transistors and not to signal silicon transistors because of the reasons given in the pre-
ceding section of this chapter.

86
 LARGE SIGNAL CHARACTERISTICS AND TRANSISTOR CHOPPERS 3
COLLECTOR LEAKAGE CURRENT ( I
co )*

For the direction of current flow shown

'CO
1
, Tao
'CEO —
1— (ix (3q)
IVOLT

ICED is the collector leakage current with the base open-circuited and is generally
much larger than lc°.

COLLECTOR LEAKAGE CURRENT (IcEs)*

For the direction of current flow shown

ICES ¡CO
las =
1— axai (3r)
VOLT

is the collector leakage current with the base shorted to the emitter and equals
the leakage current the collector diode would have if the emitter junction was not
present. Accurate values of ax and al for use in the equations in this section are best
obtained by measurement of ¡co, ICE() and I,Es and calculation of ax and al from equa-
tions (3q) and (3r). The value of IED may be calculated from equation (3b ).

COLLECTOR LEAKAGE CURRENT (I,ER)*

For direction of current flow shown
v
cE >-o 'VOLT icER (1 ± AIE0R) ¡co
ICES 1— axai ARIE0 (1—ax)
(3s)

IcE. is the collector leakage current measured with the emitter grounded and aresistor
R between base and ground. The size of the resistor is generally about 10 K. From
equation (3s), it is seen that as R becomes very large, Ira. approaches ICED—equation
(3q). Similarly, as R approaches zero, Ie approaches icKe—equation (3r).

COLLECTOR LEAKAGE CURRENT —SILICON DIODE IN SERIES WITH EMITTER"

For direction of current flow shown
(1 ± AIE011 — a,AV D)I
C.
I
C=
1— axai ARIE0 (1—ax) (3t

This circuit is useful in some switching applications where a low collector leakage
current is required and a positive supply voltage is not available for reverse biasing
the base of the transistor. The diode voltage VD used in the equation is measured at a
forward current equal to the Ir. of the transistor. This equation holds for values of Ir
larger than ku.

87
3 LARGE SIGNAL CHARACTERISTICS AND TRANSISTOR CHOPPERS MI

BASE INPUT CHARACTERISTICS

for I. ,=

VBE= I
D(RE+ RE) -I- ln (_-_+ 1) (3u)

for W E> —.1 volt

RE ) ± 1 in [IB(1 —axai) ± 1 ± ax (1—al (3v)

VBE = I
B fin ±
1— ax A IE0 (1 ax)
— a,(1—aN)

A comparison of equations (3u) and (3v) indicates that they are approximately
equal if REis small and ax is smaller than al. For this condition, the base input charac-
teristic will be the same whether the collector is reverse biased or open-circuited.

VOLTAGE COMPARATOR CIRCUIT

ye, r
for Vo = Nice
VCC
ax 1— ai
(3w)
RT. L ai

If an emitter follower is overdriven such that the base current exceeds the emitter
current, the emitter voltage can be made exactly equal to the collector voltage. For
example, if asquare wave with an amplitude greater than Vcc is applied to the base
of the transistor, the output voltage V., will be a square wave exactly equal to Vcc.
Equation (3w) gives the base current required for this condition and indicates that the
transistor should be used in the inverted connection if the required base current is to
be minimized. This circuit is useful in voltage comparators and similar circuits where
aprecise setting of voltage is necessary.

JUNCTION TRANSISTOR CHOPPERS

Transistor choppers are used in the amplification of low level d.c. signals, as well
as in the conversion of d.c. signals to asynchronous a.c. voltage for driving the control
phase of two phase servo motors. The chopper converts the d.c. signal to asynchronous
a.c. voltage whose magnitude is proportional to that of the d.c. signal, and whose phase
relationship to the reference a.c. voltage is either zero or 180°, depending upon the
polarity of the d.c. voltage. This can best be seen by referring to Figure 3.7(A). The
chopper contacts close during the positive half cycle of the a.c. reference and open
during the negative half cycle. With the switch in position 1, the positive voltage Es is
tied to the resistor R as shown in Figure 3.7(B) during the positive half cycle of the
reference. During the negative half cycle of the reference, the chopper contacts are
open and the voltage across R is zero. The capacitor removes the d.c. level such that e.,
is now an a.c. square wave which in phase with the reference a.c. If the switch is in
position 2, the negative voltage E. is applied to R during the positive half cycle of the
reference voltage, and as can be seen in Figure 3.7(C), the output is 180° out of
phase with the reference a.c.
Figure 3.8 shows a single transistor replacing the mechanical chopper. When the
base voltage is made positive with respect to the collector (NPN transistor), the tran-
sistor behaves as aclosed switch, and the d.c. input voltage is connected to R. During
the half cycle of the reference voltage when the base is made negative with the supply,

88
 LARGE SIGNAL CHARACTERISTICS AND TRANSISTOR CHOPPERS 3
CHOPPER
‘R CONTACTS
O,. WITCH me
um o t

2 ,.....,-.
I
A.C. SWITCHING
+ O VOLTAGEl el.... R

(A)

REFERENCE +
A. C

Es o

o
+l OR 0

et;e1TL=F:=Ed•
WAVE FORMS FOR WAVE FORMS FOR
SWITCH IN POSITION I SWITCH IN POSITION 2
(B) (C

HALF-WAVE CHOPPER

Figure 3.7

the transistor behaves as an open switch, and the voltage across R is zero. However,
the transistor is not aperfect switch, and an error voltage and current are respectively
superimposed on the d.c. source. During the half cycle that the switch is closed, the
error voltage introduced by the transistor is
VEc = .026 In ax -F Ii, rc' (3x)
where as is the normal alpha as defined at the beginning of this chapter and re' is the
collector bulk or body resistance. The error current which is introduced when the
transistor is an open switch is
Ice° ai (1 — as)
= (3y)
as (1 — as ai)
where ai is the inverse alpha and is the leakage current as defined earlier in this
chapter.
0

to
INPUT
10K
I BA I R

Ac.
REFERENCE

2N2192
OR 2N2195
Eg .5 VOLTS PEAK
SINE OR SQUARE WAVE

SIMPLE SERIES TRANSISTOR CHOPPER

Figure 3.8

89
 3 LARGE SIGNAL CHARACTERISTICS AND TRANSISTOR CHOPPERS MI

The error voltage introduced by the transistor during the "on" half cycle can be
minimized by using two transistors whose offset voltages cancel one another as shown
in Figure 3.9. The transistors must not only be matched at room temperature but
must track over the required ambient temperature extremes. This is no problem with
transistors such as the 2N2356 and the 2N3082 where two transistor pellets are
mounted in one header. The initial offset voltages are matched to 50 and 75 miciovolts
respectively. Drifts of less than ±-100 microvolts over an ambient temperature of
—55 to 125°C are easily obtainable. The low drift results primarily from the low initial
offsets of each transistor (due to the very high aN and low re') and to the negligible
temperature difference between the transistor pellets. Some of the important param-
eters of Ihese chopper transistors is given in Table 3.1.

TYPE NUMBER G.E. G.E. G.E. G.E.

2N2356 2N2356A 2N3082 2N3083 UNITS

BVen,, 25 25 25 25 volts, min

BVEEg. 20 20 volts, min
BVER 7 7 10 10 volts, min
Differential Offset
Voltage, 25°C 50 75 /.2 volts, max
Differential Offset
Voltage change with
temperature
—55 to 25°C 100 100 ea volts, max
25 to 50°C 100 100 µvolts, max
Differential Offset
Voltage,
—55 to 125°C 50 75 µ volts, max
Differential Offset
Current, 25°C 9 2 5 2 namp, max
"On" Dynamic
Resistance,
151 = 152 = 1 ma 40 40 40 40 ohm, max
Collector Capacitance
(VER = 0V) 8 8 pf, max
Emitter Capacitance
(VER = 0V) 8 8 pf, max

PARAMETERS OF CHOPPER TRANSISTORS

Table 3.1

A chopper configuration' which can be used to advantage for a low source

impedance input is shown in Figure 3.10. During the half cycle when Q, is "on," Q2
is turned "off" because its collector-base junction is reverse biased, and R is tied to the
d.c. input. On the next half cycle when Q, is turned "off," Q2 is turned "on," shorting R,
The leakage current due to Q1 does not flow through R during this half cycle since Q.
essentially short circuits R. During the alternate half cycle when Q2 is turned "off," its
leakage current will flow primarily through Q, (its turned "on") and the input circuit

90
MI LARGE SIGNAL CHARACTERISTICS AND TRANSISTOR CHOPPERS 3
if R is made much larger than the source impedance. Thus, the drift due to leakage
current is minimized. In addition, the offset voltages of the two transistors effectively
cancel, even though they occur on separate half cycles. The reason for this is that they
form ad.c. voltage which is not chopped and which is not passed by the capacitor, C.
An advantage this circuit has over the chopper circuits discussed above is that it is less
sensitive to noise pickup because the load always looks back into alow impedance.

NOTE:
I. ()IA QIB -GE 2N2356,2N2356A,2N3082 OR 2N3083 (TWO MATCH-
ED TRANSISTORS IN ONE PACKAGE)
2. ELECTROSTATIC SHIELDING BETWEEN PRIMARY AND SECONDARY
WINDINGS OF TRANSFORMER T MAY BE REQUIRED.
3. R8 -10K, Eel() VOLT PEAK (SINE OR SQUARE WAVE ).
4. DI .1N3604

AN IMPROVED SERIES TRANSISTOR CHOPPER

Figure 3.9

DC
INPUT

1
STATIC -
ELECTRO
SHIELD
AC REFERENCE
•

01= 02=GE 2N2I92, 2N2I95, OR 01,Q2• 2N2356, 2N2356A,

2N3082 OR 2N3083
NOTES:
I. ROOK, EB =7.5V SINE OR SQUARE WAVE
FOR 2N2I95, 2N2I92, 2N2356, 2N2356A
2. RB =50K, EB 5V SQUARE WAVE FOR
2N3082, 2N3083

SERIES-SHUNT CHOPPER

Figure 3.10

Figure 3.11 shows actual drift performance obtained with this circuit using the
2N2356A as the chopper transistor'". The chopper drift was less than -
±60 /Iv from
—55 to 150°C.

91
3 LARGE SIGNAL CHARACTERISTICS AND TRANSISTOR CHOPPERS

GE
2N2356A ▪F
e- IN OVEN

Es = 12 Vp_ p, 400 SINE WAVE

UNIT rI 0

20

UNIT* 2

o 100 150
•C

-20
UNIT* 3 /

UNIT* I
-40
•••••
•••„„

-60 •••••

UNIT* 2
134413
-80

-100

TYPICAL TEMPERATURE DRIFT OF SERIES—

SHUNT CHOPPER USING GE 2N2356A
Figure 3.11

DC INPUT
RL .0
IN 3604 2K

AC INPUT

02
IN3604

NOTES:
I. Rs CAN BE SOURCE IMPEDANCE OF 50K
TO SEVERAL MEGOHMS
2.E. 10 VOLT PEAK SINE WAVE FOR
GE 2N2195,R B .10 K.
3. RelOOK FOR 12X IIII,EB .10 VOLT
PEAK SQUARE WAVE.

SHUNT CHOPPER FOR HIGH IMPEDANCE SOURCES

Figure 3.12

92
MI LARGE SIGNAL CHARACTERISTICS AND TRANSISTOR CHOPPERS 3

Figure 3.12 shows a transistor chopper used for high source impedance applica-
tions or those where the d.c. input cannot be loaded. Although Rs is shown as part of
the chopper circuit, it can be the d.c. source impedance.
Operation of this chopper is basically one of shorting node A to ground each half
cycle when the base of the transistor is made positive with respect to ground (the
collector). A zeroing adjustment for removing the transistor's offset voltage is pro-
vided by D,, Rz, and R, which causes a current to flow during the half cycle from
collector to emitter [see equation (3g)]. In some applications where the 12X1111 and
2N2192 are used, the offset voltage is small enough (less than amillivolt) so that the
balance network can be eliminated.
On the half cycle of the supply which would normally reverse bias the collector-
base junction of Q, the diode D, prevents this from occurring. The collector-base poten-
tial is then zero; however, Chapin. and Owens'" have shown that the emitter-collector
impedance is given by
0.026
rEe = ,a5/al — 2aN) (3z)
Ira°
Thus the dynamic impedance is approximately 26 mv. divided by the IcBo. For silicon
transistors (even at high temperatures) this impedance can be made larger than the
load impedance so that the current at node Adue to the input d.c. voltage flows into
the load during this half cycle. The maximum value of the load is then determined by
the minimum value of rEr obtained from equation (3z ). Also, any drifts which normally

100 150 .-T, •C

- -0.2

r100K
--04

0 C INPUT
- -06 2
G.E. 2N2192
ISD160 OR2X1111
- -08

-10 5K

20V2_, L =_ IN OVEN
400- SINE WAVE

CHOPPER DRIFT WITH 2N2192

Figure 3.13

93
3 LARGE SIGNAL CHARACTERISTICS AND TRANSISTOR CHOPPERS IIIIM

would have been caused by the transistor leakage currents have been eliminated.
For the condition that rEc> >RI., the peak to peak load current is given by
2ED.0 . (3aa)
I
I' =
Rs + 2RI,
The equivalent input current drift due to drift in transistor offset voltage (AV) is
shown to be

Io = f
or R8» sAL (3bb)

A second component of the chopper drift is due to transient current spikes which
occur when the transistor switches "on" and "off." The net area (charge) of the tran-
sients develops apotential on the capacitor C which, to the circuit, appears as an input
signal. In order to zero the output, ad.c. input current (integrated over one-half cycle)
must be provided. The 12X1111 is ideal for this application because of its low junc-
tion capacitances (< 8pf at 0volts) and low initial offset (< 250 AV at I B= .1 ma).
Temperature drift tests made using 2N2192's show that with the entire chopper of
Figure 3.12 exposed to temperature, the required d.c. input necessary to zero the out-
put is less than 10' amperes from —55 to 125°C. This is equivalent to 1 mv of drift
referred to the input for R8 = 100 K.

REFERENCES:
(1)Ebers, J. J., "Large — Signal Behavior of Junction Transistors," Proceedings of the IRE, Vol. 42,
December 1954.
(5) Pritchard, R. C., "Advances in the Understanding of the P-N Junction Triode," Proceedings of the
IRE, Vol. 46. June 1958.
(2) Giorgis, J., "Some Large Signal Properties of Planar and Planar Epitaxial Transistors," G. E. Appli-
cation Note 90.13.
(4) Kruper, A., "Switching Transistors used as a Substitute for Mechanical Low Level Choppers,"
AIEE Transactions, Vol. 74, part I. March 1955.
(5) Giorgis, J., and Thompson, C. C., "Silicon Transistor Performance in a Chopper Application,"
Applications and Industry, #37, July 1958.
Giorgis, J., "Silicon Transistor Choppers for Low Impedance Sources," Solid State Design, Vol. 4,
No. 5, May 1963.
") Chaplin, G. B., and Owens, A. R., "Some Transistor Input Stages for High-Gain D.C. Amplifiers,"
The Proceedings of the IEE, Vol. 105, part B, No. 21, May 1958.
Giorgis, J., "A Transistor Chopper for High Impedance Sources," Electronic Equipment Engineer-
ing, Vol. 11, No. 1, January 1963.

NOTES

94
 cc

BIASING AND DC AMPLIFIERS a_

C.)
4
BIASING
INTRODUCTION
One of the basic problems encountered in the design of transistor amplifiers is that
of establishing and maintaining the proper de emitter current and collector to emitter
voltage (called the bias conditions of the circuit). The biasing problem is due pri-
marily to the change of transistor parameters (hrE, 6), VI1 ) with temperature and the
variation of these parameters between transistors of the same type. This can readily
be seen by referring to Figure 4.1(a) where the transistor is operated in the common
emitter mode and is biased by aconstant base current, IB. Figure 4.1( b)shows the
common emitter collector characteristics of two different transistors with the saine
collector load line superimposed on them. For the transistor characteristic shown with
solid lines and abase current lin, the operating point is at A. On the other hand, if a
higher gain transistor is used, or the original transistor's gain and leakage current are
increased due to an increase in temperature, the transistor characteristic shown with
dashed lines could result. For the same base current, I'm, the bias point is at B and
distortion would result since the transistor begins to saturate during the positive half
cycle of the signal base current.

V
CC

(a)

(b)

SIMPLE BIAS CIRCUIT

Figure 4.1

The factors which must be considered in the design of transistor bias circuits,
whether operating class A or class B, and single or multi stage include
1. The specified maximum and minimum values of current gain (4E) at the oper-
ating point for the type of transistor used.

95
4 BIASING AND D.C. AMPLIFIERS

2. The variation of hEE with temperature. This will determine the maximum and
minimum values of hFE over the desired temperature range of operation. The
variation of hFE with temperature is shown in Figure 1.26 for the 2N525
transistor.
3. The variation of collector leakage current (Ito) with temperature. For most
transistors, ¡co increases at approximately 6.5-8%/°C and doubles with atem-
perature change of 9-11°C. In the design of bias circuits, the minimum value of
¡co is assumed to be zero and the maximum value of ¡co is obtained from the
specifications and from a curve such as Figure 1.25. In low level stages and
when silicon transistors are used, leo can usually be neglected if the junction
temperature is below about 100°C. This is not true, however, if the emitter bias
current is in the microampere region.
4. The variation of base to emitter voltage drop (V8E) with temperature. Under
normal bias conditions, VBE is about 0.2 volts for germanium transistors and 0.7
volts for silicon transistors and has atemperature coefficient of about —2.5 milli-
volts per °C. Figure 4.2 shows the variation of VBE with collector current at
several different temperatures for the 2N525. Note that for some conditions of
high temperature it is necessary to reverse bias the base to get a low value of
collector current.
5. The tolerance of the resistors used in the bias networks; tolerance of the supply
voltages.

.40
-65°C

0°C

25°C

°C
70°C
EMITTER TO

+10o -2 -3 -4 -5 -6
EMITTER CURRENT-I E -MILLIAMPERES

INPUT CHARACTERISTICS OF 2N525 (V c.= 1V)

Figure 4.2

SINGLE STAGE BIASING

Several bias circuits are shown in Figure 4.3(a) through 4.3(d) which have been
used to stabilize the emitter current and collector to emitter voltage. There are a
number of methods by which each circuit can be analyzed and synthesized, and the
methods chosen depend upon the requirements of the application and the aptitude
and preference of the designer. For example, the circuit of Figure 4.3(c) roughly can

96
 BIASING AND D.C. AMPLIFIERS 4
be biased for low level applications which operate near room temperature. The VCE ,
VCC and ICare selected by the designer — generally it is advisable to choose VCE and
IEat the values given on the specification sheet for the measurement of the small signal
parameters. IB is then IE/hEE Ice; and VA, the voltage at point A of Figure 4.3(c),
is then IE VBE. (VBE is approximately .2 volts for germanium and 0.7 volts for
silicon.) IE Rs is chosen to be at least five times larger than VBE, and the current
through 112 is chosen to be at least five times I
B. 112 is then VA/
I2, and Rs is
VCC — VA
132 -
I-LI
The load resistance is then
VCC VCE VCC VCE R3
or I
IE,

V CC

(b)

vcc

(d) (e)

VARIOUS CLASS A BIAS CIRCUITS

Figure 4.3

Most applications require operation in an ambient other than room temperature

so that amore thorough analysis must be done. Rather than analyzing each circuit
individually, ageneral one battery circuit as shown in Figure 4.3(e) can be analyzed.
Each of the other circuits in Figure 4.3 can be obtained by setting the appropriate
resistor in 4.3(e) to zero or infinity. For example, the circuit of Figure 4.3( b) is
obtained by setting Flu and Rs equal to zero and 112 equal to infinity.
By means of Thévenin's theorem, any of the circuits in Figure 4.3 can be converted
into another general circuit which consists of athree resistor and two battery circuit
as shown in Figure 4.4."' This allows the designer to use the simple circuit of Figure
4.4 to analyze the bias circuit and determine the values of RE, Re, RB, VB and Vc.

97
4 BIASING AND D.C. AMPLIFIERS

Once these are obtained, then the resistance values and the supply voltage of any of
the bias circuits of Figure 4.3 can be determined.

C
•ca E +1CO
I,a hFE IB +(hFE +1)I ii

h -
IL
I
FE —.

Rs

GENERAL TRANSISTOR BIAS CIRCUIT

Figure 4.4

Thus, for the circuit of Figure 4.4, the following equatiGns apply

JE = (hFE + 1) ( + I
CO) (4a)

Ry In + VBE I
CO RB (4b)
= [(hEER8 1)

VC= 1E (RE + aRo) -F Vop: (4c)

(The currents in the above equation and as shown in Figure 4.4 are those which
would be measured if an ammeter were inserted in that circuit.)
Considering bias conditions at the temperature extremes: at the minimum tem-
perature, IE will have its minimum value, and the worst conditions would occur for
hEE = hFE mI, VBE = VBEm", ¡co = 0, or, at the lowest temperature

v. =rhFic"""1-1
R. +RE] 'En"» VBE""' (4d)
L

At the highest temperature of operation II.: will have its maximum value and the worst
conditions would occur for hEE = 1 1FE'", VBE = VBErn
- ICO = 100". At the highest
temperature

RE
VE = [ II m ± 1 + RE IE"'" + — ICOm" RB. (4e)
FE s

From these two equations the value of RE can be calculated by equating the two
expressions, thus

RB = (IEn"' — le") RE + VBE' — VBErn"

h max
(4f)
00 1-
hFe" ± 1 hFe'n +1

98
 BIASING AND D.C. AMPLIFIERS 4
From equation (4c) the minimum collector to emitter voltage with no signal is

wen.= veon „,.. ( ± R)

C— max
(R R
, e+rErF R I: e
r (4g)

where i. is the peak emitter current due to the signal, and rE and rE are the a.c. im-
pedances respectively between the emitter and ground and the collector and ground.
The bias conditions (IE, WE) may be determined by the application. For example,
the transistor may be biased to obtain the lowest noise figure, optimize the gain, or
the lowest possible supply drain. Because of the variations of small signal parameters
and noise with operating point, the range or tolerance of the bias conditions may be
determined by the amount the noise performance or gain are allowed to degrade. If
the application does not determine the bias conditions, and if wide ambient tempera-
tures are encountered, it is desirable to bias the transistor near the operating conditions
given for the measurement of the small signal parameters.
Regardless of how the bias current is determined, the extremes of operating point
are ultimately limited by the requirement that the transistor does not cut-off (IE = 0)
or saturate (VEE = 0) under conditions of maximum input signal. The a.c. impedances
seen by the collector and emitter are used in calculating the additional voltage drop
due to the signal.
The procedure for determining the resistors and voltages of Figure 4.4 can best
be described by asample bias design.
1. Select the transistor type to be used (2N525 ).
2. Determine the required range of temperature.
0°C to + 55°C
3. Determine Ire'''.
From the electrical specifications the upper limit of I
E. is 10 eia at 25°C and
from Figure 1.25(A), 1E0 will increase by afactor of 10 at 55°C, thus Imm"
= 10 x 10 = 100 ga.
4. Determine the values of hEEm'n and hrEm"
From the electrical specifications, the range of hEE at 25°C is 34 to 65. From
Figure 1.26 hEE can change by afactor of 0.83 at 0°C and by afactor of 1.45 at
+55°C.
Thus hEE'" = 0.83 X 34 = 28, and hEE"'" = 1.45 X 65 = 94.
5. Determination of IE and the range of Is.
The nominal bias condition is selected as 1ma and 5volts because the small
signal parameters are specified here and the temperature range involved. The
range of IE is selected to be 0.6 ma to 1.4 ma since the change in small signal
parameters is small over this current range. If we assume that the maximum
input signal is 8 microamperes peak to peak, the maximum emitter current
swing due to the signal occurs at 55°C and is (hr.' + 1) Ib = 65 X 1.3 X
1.1 x 8 = .75 ma peak to peak or .375 ma peak. Thus the minimum value of
bias current that has been selected is sufficient to keep the transistor from
cutting off.
The allowable range of emitter current must be narrowed to take into
account the tolerance of the bias resistors. If the bias network has three resistors
with a5% tolerance, then
Jmmn = (1+ 3 X .05) (.6) =.69 ma and

IEM" = (1 3X .05 )(1.4) 7-- 1.2 ma.

99
4 BIASING AND D.C. AMPLIFIERS

6. Since the VBE temperature coefficient is about 2.5 mv/°C, VBE Inn: — VBE rn 10 can
be estimated to be 2.5 x 10 X 55 = .135 volt.
7. Calculate the value of RBfrom equation (4f),
RB= 4.6 RE— 1.2K.
8. Using the equation from step 7, choose a suitable value of RBand RE. This in-
volves a compromise since low values of RErequire a low value of RBwhich
shunts the input of the stage and reduces the gain. A high value of REreduces
the collector to emitter bias voltage which limits the peak signal voltage across
RL, or for the same collector-emitter voltage, requires ahigher Ve.
Choose RE= 2.7K for which RB= 11.2K.
9. Calculate VBusing equation (4d)
VB= 2.32 volts
10. Determine Ve and R.
RLand Ve must be chosen so that with the maximum bias current and peak
signal the transistor does not saturate. However, an upper limit is set on Ve by
the BVeme rating of the transistor and the allowable power dissipation at the
highest operating temperatures. The load resistor, Re, is chosen to be as large
as possible with the constraints given above.
In our example the emitter is assumed to be bypassed so that the emitter
to ground a.c. impedance is negligible. In addition, the collector is assumed to
be a.c. coupled to a 500 ohm load. To effect a maximum transfer of signal to
the load, Re > > 500 ohms. Rc is thus selected to be 5K. Since the peak signal
current is .375 ma and using equation (4g)
Vemin > (1.05) (5K ± 2.7K )(1.4 ma )± .375 ma X 453 0 (1.05)
or
Ve nun > 11.4 ± .18 11.6 volts

Vcc
L
C

R3

(a) (b)

Rs RI RL R5 Rc

Vcc 'V c
Vc
R2 -Vc -Vs (R B-R s)

Vc
(c ) (d) RI = —
Vs
(R -R )
8 S

R3= RE

RL . Rc

CONVERTING GENERAL BIAS CIRCUIT

TO VOLTAGE DIVIDER TYPE
Figure 4.5

100
 BIASING AND D.C. AMPLIFIERS 4
Vo is selected to be 15 volts. Once RB, RE, Re, Ve and VBof the general bias
circuit are determined, the resistor and supply voltage of aparticular bias circuit
can be calculated. This is accomplished by equating between the bias circuits:
1) the transistor open circuit terminal voltages, and 2) the equivalent terminal
resistances with the supply voltages shorted. For example, Figure 4.5 shows how
the voltage divider bias network of Figure 4.3(c) is determined in terms of the
general bias circuit. The open circuit collector-emitter voltages are Vcc and Vc,
respectively, while the open circuit base-emitter voltages are (112/R1 -I- R2) Vcc
and VB, respectively. The equivalent resistance network of the circuits with the
power supplies shorted are shown in Figure 4.5(c) and (d). From inspection
Re = RE., R3 = RE, and 118 + RIR2/111 + R2 = RB. Using these relationships
and the voltage relationship given above, the values of the bias resistors and
voltages are calculated as shown in Figure 4.5(d). The same relationship for
other types of bias circuits are given in Figure 4.6.

, v
CC

RL = RE RI =R e

R I= Re R3 = RE

v
cc •Ve• VC RL =RC
Vœ =V =V
B C

, ,

(a) (b)

, v„ V R
CC B •
RI =
V8
RL + R3= RE V R
R2 -
B CC
RI=RB VC -VB

VCC' V s 'VC
R3 R .I VCC \R
L VCC -v8 l C
—
VA
(d I R3 R (-=—
E VB -VC )RC
li t
V =V + ve
c R 13
e

BIA S CIR CUI T VALU ES I

N TERMS OF
GENERAL BIA S PARAME TER S

Figure 4.6
4 BIASING AND D.C. AMPLIFIERS

this is that the VBE characteristic of silicon transistors has asteeper slope than it does
for germanium transistors. The disadvantage of this circuit, however, is that the stage
gain and bias point are more susceptible to hEE variations. Another approach to biasing
silicon transistors for this type of application is to use aseparate battery for the bias
supply. Since the drain is greatly reduced, the life of the bias battery will be several
times larger than that of the collector supply battery.

BIASING OF MULTISTAGE AMPLIFIERS

Frequently, in biasing an amplifier, it becomes necessary to use techniques by
which higher input impedance or better stability are obtained than afforded by the
circuits already shown. Many different schemes have been used to accomplish these
purposes and the degree of complexity of any one method depends largely upon the
factors listed earlier in this chapter. In any design, however, considerations similar to
those in the example shown above must govern the circuit values chosen. Some of the
bias methods for two and three stage direct coupled amplifiers are shown in Figures
4.7, 4.8, and 4.9.

OUT

DIRECT COUPLED AMPLIFIER

Figure 4.7

In Figures 4.7 and 4.8, biasing techniques are used which will improve the input
impedance of the amplifier being designed. In Figure 4.7, the ac feedback through
R1 is essentially eliminated by the existence of C2. R2 can therefore be quite small in
order to obtain good temperature stability for the amplifier. In Figure 4.8 bootstrapping
techniques are used. Here the ac and de feedback are quite large. Temperature
stability and input impedance can be optimized but the gain of the circuit is sacrificed
for increased input impedance.

102
 BIASING AND D.C. AMPLIFIERS 4

I
N

BOOTSTRAPPED AMPLIFIERS
Figure 4.8

V„

OUTPUT

RF

3-STAGE COMMON EMITTER

DIRECT COUPLED AMPLIFIER
Figure 4.9

Two-stage Biasing Analysis

As an example of biasing considerations for a direct coupled amplifier, the circuit
of Figure 4.7 is considered. As with single stage circuits, the bias can be established

103
4 BIASING AND D.C. AMPLIFIERS

using a"rule of thumb" procedure (as shown in Chapter 9) or it can be done ana-
lytically. /n the analytical derivation for Figure 4.7 which follows, R. and R7 are com-
bined and called R.' since only the dc conditions are of interest. Nodal equations can
be written for this bias scheme:
(4h)
(4i)
(4j)
(4k)
Again, these currents are those which one would measure in the lines in which they
flow. In addition to these equations, two more equations can be written which depend
upon the transistor's action.
= hFci (hpci ± 1) 'col (41)
Ic2 = 11E52 1112 -I- (11PE2 + 1) ICO2 (4m)
The relationships between the voltages, resistors, and currents in the circuit are

12 = Vo — Vci (4n)
R2
Vt — VBI
I
B1 = (40)

y VIII (4p)
lEi = 1:76 -

Vo VC,
IC2 = Re (4g)

y VE2 — VI (4r)
1E2 =
Re
y v, (4s)
=
R«
Substituting these voltage and resistor values into the node equations, and eliminating
Ici and 182 by use of the transistor equations (41) and (4m), the following results
— V — y
R2 = IIFE1 `) %HEM 1C01
+ VO— VC2 (11FE2 ± 1) /c02
(4t)
h0F2 R4 110E2
C01) = _
(1 -I- 11001) (V,— VBI -I- I
V-----
E1
(4u)
112 112

(Ve
‘.
R4 V02
— /cm )(i + hFE,,) = hh002 fV52 — VI
Re
\
)
(4v)

VE,— VI — VIRI ± VI (4w)

112 Re'
To these equations, other transistor voltage relationships can be written
VE, + VCE1 = VC1 (4x)
VE, VCE2 = VC2 (4y)
VE, VBE1 = VB1 (4z)
VE2 VBE2 = VB2 = VC1 (4aa)
There are now eight independent equations (4t) through (4aa) relating the voltage
and resistance values of the circuit. The circuit requirements of the particular design
now govern the remainder of the design procedure. All of the above equations are true
at all temperature extremes. The stability problem arises since the values of Ico and
1103 change as a function of temperature. As these values change, the voltage and

104
 BIASING AND D.C. AMPLIFIERS 4

current relationships within the circuit must also change so that equations (41) through
(4aa) are satisfied. In practical design, for example, the specifications for the amplifier
normally demand that the output be capable of aspecific voltage excursion. This peak
to peak allowable swing at the collector of the output transistor can theoretically equal
the supply voltage, if the bias voltage, Vc2, is exactly V0/2. Maintaining Vc2 exactly
over the range of hrE and I co is essentially impossible, and thus the output voltage

excursion must be somewhat less than the supply voltage so that limiting does not
occur on the output waveform as the bias level changes. At the lowest temeperature of
interest, the emitter currents will be aminimum and the worst conditions would occur
for hrE = hFE mI0, VBE"'", and Ico = O. At high temperature, the emitter currents will
have amaximum value, and the worst case is encountered for hrE = hFE"'”, VBE =
VBE", and Ico =
The choosing of resistor values throughout the circuit is normally accomplished by
considering circuit requirements in conjunction with transistor operating conditions.
Equations (4h) through (4s) may also be of value in selecting resistors. A perfectly
general biasing scheme is difficult to describe since individual circuit requirements
play an important role in every amplifier. A general method of checking the values of
resistance chosen could be worked out by solving equations (4t) through (4aa) for Vea
by eliminating all voltages except VO, VBEI, and VEE2. The resulting equation will be
of the form
= K, V0 + K2 VBE, K3 VBE2 + K4 I C01 + K5 ICO2
VC2 (4bb)

If no approximations are made, these constants can be quite lengthy. For the case of
Figure 4.7 the constants are

K, = 1 + h' ) R eIR- (1 -1-b) + RA± liFF:t R2] RA(hFE. (4CC)

R4 " R.
K2= — hrE2 (hFEI R2 — ) (4dd)

K3 = liFE2 RA (4ee)

K. = hrE2 (1 + hrE1) (RB + RIR2) (4ff)

K2 = — (1 + hr00) [(1 + hrE:) (R3 113 RB) (
RIR2 -I
- Re)] (4gg)

= 1+hy02) RaI R2 (1 + R A )± RA + FIE, Ra] ± (RA+ R02)R2 (4hh)

R.
where,
RA= R, + (1 + hrE,) R, (4ii)

RE = R2 112 + R2 R0' + 113 Re' (41i)

Rc = RIRs -I- RIR.' + R2 R0 (4kk)

By calculating the value of Vc2 using the worst case values for hFE, VBE, and Ico at
the temperature extremes the variation in Vc2 with temperature can be checked. Though
this procedure is tedious, one is able to determine the stability of any given amplifier
using steps similar to those outlined for the circuit of Figure 4.7.
Because of the circuit configuration used in this example, other types of bias
schemes can also be analyzed by setting some of the resistor values at zero. Two
different bias schemes would call for the following resistor changes: R. = 0; or 110 = 0,
and R. represents resistance seen at the base by the first transistor.

Three-stage Biasing Analysis

A general purpose 3-stage direct coupled amplifier is shown in Figure 4.9. The pur-
pose of the zener diodes VE, and VZ2 is to provide sufficient collector to emitter voltage

105
4 BIASING AND D.C. AMPLIFIERS

for the preceding stage. In some cases they could be eliminated, or replaced by a for-
ward biased diode. Using the method of analysis given for the two stage amplifier, the
collector voltage of Q. is

Vc.=,-,1 [K. Yee + K2 VEB1 + K3 VI+ 1C4 V2 K5 I

C01 + Ke Icces 1C7 (411 )

where Vi = VEB2 VE. and V2 = VEB3 VZ2

The coefficients Ko K2 are given in Table 4.1. For the case where R1 >>
hFE2 R4y Re > > hFE. R., and hF131 R2 > > ROy the expression becomes

VC3 = (RF RO)(V R, „E. + Ro RIV2 ) RF (RO R2) I

COI
CC
Ro 114 R2 e hFE3 R2 R3 RO
+ R2 (R., Ro )( i 1CO3
CO2 hrE., (4mm)
Ro
The ac gain and frequency stability considerations are given in Chapter 9.

K. = 1-I- (f31 R2 ± RO) +ZFIL

(#1 R2 + RO)RF pt ROR2

IC4 = 1+ [AI(Re — R4) — Pe lit

(RI+ fie R4 )(R. A- 13. R3)
K2 = RL (RO RF Z Ro
Ro R2 -I- R() )Re ± fil R. RO
K3 = (Ri :2114/34 xRLR.R4+
i is. R5)

IC4 = R I•
R3 +/33 R.
K5 = RI, RF (RO R2) Z
RO
Ke (R. + R4) (14, Rs 132(33)
— (114 ±PeR4) (Re -1-P3R5)
= 03 R3 RL
R. -I- P. R.
where Z= Ro R, R. fit 132P3
[R2 Ro RF (R. -I- ROM& + /32 RI) (R3 ± 1
3311 3)
and
PI= hFEI
03 = hFE2
Pa = hFE3 Table 4.1

NONLINEAR COMPENSATION
In the previous section, the bias point was maintained by employing feedback. It is
possible to stabilize the bias point for temperature variations by using nonlinear com-
ponents or another transistor (as shown under DC AMPLIFIERS ). The nonlinear com-
ponents to be discussed in this chapter compensate only for temperature changes and
are not effective for the variation of transistor parameters between units or with life.
Figure 4.10(a) shows a circuit where a thermistor, R2, in parallel with a fixed
resistor R. is used to compensate for the transistor leakage current, VBE, and gain
variation with temperature. Since the thermistor has anegative temperature coefficient,
it will reduce the base-emitter voltage with increasing temperature. The temperature
coefficient and values of resistors are usually determined experimentally.

106
 BIASING AND D.
C.AMPLIFIERS 4

(a) (b) (c)

NONLINEAR TEMPERATURE COMPENSATION

Figure 4.10

A similar compensation technique which can be used with germanium transistors

is shown in Figure 4.10( b). Diode D, (asilicon diode) is forward biased and compen-
sates for the transistor VRE variations. D2 is a germanium diode (it could be the
collector-base junction of atransistor of the same kind that is being used) which com-
pensates for Ico variations. Because Ico is voltage sensitive, more perfect compensation
is obtained if point B of D2 were returned to aminus voltage equal to the collector
voltage of the transistor. If silicon transistors are used, diode D2 could be eliminated.
Because of the low impedance presented by D1, the signal would have to be inserted
in series with the base — this can be accomplished with transformer coupling.
Diodes can also be used to compensate for Vac variations of push-pull amplifiers
as shown in Figure 4.10(d). The stages are generally biased Class AB in order to
eliminate crossover distortion. If the stages were biased Class B (no quiescent current )
the input signal would have to exceed the transistor VBE before any appreciable col-
lector current would flow. The d.c. current through the diode must be larger than the
maximum peak signal current if the diode is not to cut off during the negative half
cycle of the signal. By placing another diode as shown by the dotted line, the diode
bias current can be reduced since the second diode will conduct for the negative half
cycle of the signal.

THERMAL RUNAWAY
When atransistor is used at high junction temperatures (high ambient temperatures
and/or high power dissipation) it is possible for regenerative heating to occur which will
result in thermal run-away and possible destruction of the transistor. In any circuit the
junction temperature (ri) is determined by the total power dissipation in the transistor
(P), the ambient temperature (TA), and the thermal resistance (K).
= TA ICP (4nn)
If the ambient temperature is increased, the junction temperature would increase an
equal amount provided that the power dissipation was constant. However, since both
hrE and Ico increase with temperature, the collector current can increase with increas-
ing temperature which in turn can result in increased power dissipation. Thermal run-
away will occur when the rate of increase of junction temperature with respect to the
power dissipation is greater than the thermal resistance (PT3/PP > K).
Thermal run-away is generally to be avoided since it can result in failure of the
circuit and possibly in destruction of the transistor. By suitable circuit design it is
possible to ensure either that the transistor can not run away under any conditions or
that the transistor can not run away below some specified ambient temperature. A dif-

107
4 BIASING AND D.C. AMPLIFIERS

ferent circuit analysis is required depending on whether the transistor is used in a

linear amplifier or in aswitching circuit.
In switching circuits such as those described in Chapter 6, it is common to operate
the transistor either in saturation (low collector to emitter voltage) or in cutoff (base to
emitter reverse biased). The dissipation of atransistor in saturation does not change
appreciably with temperature and therefore run-away conditions are not possible. On
the other hand, the dissipation of atransistor in cutoff depends on Ico and therefore
can increase rapidly at higher temperatures. If the circuit is designed to ensure that the
emitter to base junction is reverse biased at all temperatures (as for the circuit of Fig-
ure 4.11 )the following analysis can be used

'co
Vcc —30V

+ IV

Figure 4.11

The transistor power dissipation will be

P = IcoVcm = Ico(Vcc — IcoRL) = Ico Vcc — 'CO 2 RL (400)
The rate of change of power dissipation with temperature will be

dP dP „dIco — (Vcc — 2IcoRL) 8Ico (4pp )

dT dIco dT
where oes 0.08 is the fractional increase in I
co with temperature. The condition for

run-away occurs when dP/dT = 1/K or,

(Vcc — 2IcomRL) aIcœm = 1/K (4qg )
where 'cola is the value of 1(.0 at the run-away point. Solving for I
co m gives

Icom = Vcc (Vcc)* — (

8RL)/(8K) (4rr)
4RL
In this equation the solution using the negative sign gives the value of Icom, while the
solution using the positive sign gives the value of I
co after run-away has occurred. It is

seen from the equation that the value of Ic o after run-away can never be greater than
Vcc/2RL so that the collector voltage after run-away can never be less than one half of
the supply voltage Vcc. If the term under the square root sign in the above equation is
zero or negative, thermal run-away cannot occur under any conditions. Also, if thermal
run-away does occur it must occur when the collector voltage is greater than 0.75Vcc,
since, when the term under the square root sign is zero, Icom RLequals 0.25 Veo. As RL
goes to 0, the solution for 'cou using the negative sign is indeterminant, i.e., equal to
0/0. In this case Equation (7mm) is used and

1 (4ss)
lc" — oK Vcc
Since no RL exists, the current after thermal runaway is theoretically infinite, and the
transistor will be destroyed unless some other current limiting is provided. Once the
value of Icom is determined from Equation (4rr) or (4ss) the corresponding junction
temperature can be determined from agraph such as Figure 1.25. The heating due to
Icom is found by substituting Icom for Ico in equation (400). Finally, the ambient tem-

108
 BIASING AND D.C. AMPLIFI
ERS 4
perature at which run-away occurs can be calculated from Equation (4nn).
In circuits which have appreciable resistance in the base circuit such as the circuit
of Figure 4.12 the base to emitter junction will be reverse biased only over alimited
temperature range. When the temperature is increased to the point where the base to
emitter junction ceases to be reverse biased emitter current will flow and the dissipation
will increase rapidly. The solution for this case is given by

I
e
VB .+ IV
VCC' -30V

RB

Figure 4.12

kw& — (V cc — 2111.hr eI.) ± V(Vec — 214.14.Ix) 2 — (

8RL)/(aK)
(4tt)
4Ri.lit.
where I„ = VB/RB. When RLapproaches O.
1
kw: = (4uu)
heE 8K Vec
In the analysis of run-away in linear amplifiers it is convenient to classify linear
amplifiers into preamplifiers and power amplifiers. Preamplifiers are operated at low
signal levels and consequently the bias voltage and current are very low particularly in
stages where good noise performance is important. In capacitor coupled stages alarge
collector resistance is used to increase gain and alarge emitter resistance is used to
improve bias stability. Accordingly, thermal run-away conditions are seldom met in
preamplifier circuits.

In contrast, power amplifiers invariably require transistors to operate at power

levels which are near the run-away condition. The conditions are aggravated by the
use of biasing networks of marginal stability which are required for power efficiency
and by the use of transformer coupling to the load which reduces the effective collector
series resistance. Since thermal run-away in power stages is likely to result in destruc-
tion of the transistors, it is wise to use worst case design principles to ensure that
thermal run-away cannot occur. The worst case conditions are with 111. —, 00, VBE = 0,
RE = 0, and l e° = Ice'''. If these conditions are applied to atransistor in the general
bias circuit shown in Figure 4.13 the total transistor dissipation is given by:

VB x
2V

Figure 4.13

P=VcEIc = (Vec — VB ICORB) (ICO ± VB + ICORB )

(4vv)
RE

109
4 BIASING AND D.C. AMPLIFIERS

Equating dP/dT with 1/K and solving for Icox as before,

= (Vcc — RNLI) -± V(Vcc —Va) 2 — (R2)/(8K)

Irom (4ww)
4RE
where
R=
I RE+ 2R B R- 8Rella
RE± RB 2 RE±

As before, the solution of equation (4ww) using the negative sign gives the value of
Icom, while the solution using the positive sign gives the final value of Ic after run-away
has occurred. If the quantity under the square root sign is zero or negative, run-away
cannot occur under any conditions.
In class B power amplifiers the maximum transistor power dissipation occurs when
the power output is at 40% of its maximum value at which point the power dissipation
in each transistor is 20% of the maximum power output. In class A power amplifiers
on the other hand, the maximum transistor dissipation occurs when there is no applied
signal. The maximum power dissipation is obtained by substituting 'cold in equation
(4vv) and the maximum junction temperature is obtained from equation (4nn).
In the design of power amplifiers the usual procedure is to design the circuit to
meet the requirements for gain, power output, distortion, and bias stability as described
in the other sections of this manual. The circuit is then analyzed to determine the
conditions under which run-away can occur to determine if these conditions meet the
operating requirements. As a practical example, consider the analysis of the class-A
output stage of the Three Transistor Reflex Receiver shown in Chapter 15. The tran-
sistor is the 2N241A for which K = 250°C/watt and ire" = Meta at 25°C and 25
volts. Calculating the circuit values corresponding to Figure 4.13 and equation (4ww)

Vcc = 9v, RE= 100 n

(1000) (9) (1000) (4700) _ 825

v.. 138 v RB=
1000 ± 4700 1000 -I- 4700

100 -F 2(825) _ 1 89 R. = 8(100) (825) _ 713

RL=
100 -I- 825 100 825

Calculating 'col, from equation (7ss )

6 ± V0.47
Icom = 3300 — 1.61 ma or 2.02 ma

Since the quantity under the square root is positive, thermal run-away can occur. The
two solutions give the value of Ian, (1.61 ma) and the value of Ico after run-away has
occurred (2.02 ma). The fact that these two currents are very nearly equal indicates
that the change in power dissipation when run-away occurs will not be very large.
Using the value Icom/Icom" = 100 the junction temperature at run-away from Figure
1.25 is about 92°C. The dissipation at run-away, calculated from equation (4vv ), is
about 187 milliwatts. The rise in junction temperature due to this power dissipation
is (0.25) (187) = 46.7°C. The ambient temperature at run-away is then calculated to be
92 — 46.7 = 45.3°C. The above value of maximum transistor power dissipation is
calculated under the assumption that the series collector resistance is zero. In the cir-
cuit under consideration the transformer primary will have asmall de resistance (RT)
which will reduce the transistor power dissipation by approximately (Ic)'lIT where Ic is
given by the second term in equation (4vv ). Assuming that the de resistance of the
transformer is 20 ohms the reduction in power dissipation for the case just considered
will be 18.8 milliwatts and the ambient temperature at run-away will be increased
to 50.0°C.

110
 BIASING AND D.C. AMPLIFIERS 4
DC AMPLIFIERS

TRANSISTOR REQUIREMENTS
In the previous section of this chapter it was shown that the variation of transistor
de parameters with temperature and life produced a corresponding change in the
transistor bias conditions. Thus the transistor base current and/or voltage must be
changed to return the collector voltage and current to their original value. It is this
drift (the input necessary to return the output to its original value) that usually limits
the minimum detectable dc signal. Feedback does not reduce the drift in a de ampli-
fier since the gain is also reduced proportionally.
Drift is reduced by compensation; and the most effective method found to date is
the use of asecond transistor in the emitter coupled circuit of Figure 4.14. The circuit
will amplify single ended inputs (by setting ea = 0) or it will amplify the difference
of isolated inputs (e a — ea ). One feature of the circuit is that it tends to amplify
only the difference of the two input signals and reject the signal common to both
inputs. This property has been given the name of common mode rejection; it is defined
as the amplifier gain with adifferential input divided by the amplifier gain with both
inputs tied together. It is usually given in db.

e,

EMITTER COUPLED DIFFERENTIAL AMPLIFIER

Figure 4.14

Inspection of Figure 4.14 shows that both single and differential outputs are avail-
able. The single ended output presents more of a drift problem; however, the drift
can be minimized by using multistage amplifiers with common mode feedback and a
constant current emitter supply.
The transistor parameters which contribute to the drift are:
1. Leakage current. For silicon planar transistors, the leakage current can be as
low as 1 na at I00°C (Vel. = 10V). Leakage current becomes a secondary
drift factor unless the source resistance is very large.
2. DC current gain. Since In = Ic/heE -I- 1, a change in current gain results in a
change in base current, which, multiplied by the source impedance, produces
an equivalent voltage drift. The drift contribution of the hFE variations can be
reduced by the matching of the transistor current gains, by operating at low bias
currents, and by using low source impedances. Planar transistors are available
which have acurrent gain of 100 or more at collector currents of 10 and 100 A.
The current gains of two transistors can be matched to better than 10%.

111
4 BIASING AND D.C. AMPLIFIERS

3. Base emitter voltage. The base emitter voltages tend to cancel one another in
the differential amplifier. However, the difference of the base emitter voltages
is in series with the signal and cannot be distinguished from it. It is important
not only to match the base emitter voltages, but to keep the transistors at the
same temperature since the VBE temperature coefficient is 2.5 mv/*C.
A method of maintaining the transistors of the differential amplifier at the same tem-
perature is by mounting the transistor pellets on isolated islands of a header as shown
in Figure 4.15. The degree of Vi Ematching and the calculated temperature coefficient
of one such transistor is shown in Figure 4.16. Notice that an initial VHS match of
2.5 mv and atemperature coefficient of 3 i.av/*C for the match are typical. Figure 4.17
shows how well the base emitter voltages and the current gains track with life. The
percentile curves are shown for the severe life tests of 500 mw operating life and
300°C storage.

TO-5 PACKAGE
(a)

FLAT PACKAGE
(b)

DIFFERENTIAL AMPLIFIER PACKAGE

Figure 4.15

! I I
10

95th PERCENTILE

50th PERCENTILE

5th PERCENT ILE

—55 -25 0 +25 +50 +75 +100 +125

TA -° C

(o) vim MATC H VS . TEMPERATURE FOR 2N2480

DI FFERENTIAL AMPLIFIER

Figure 4.16 (a)

112
 BIASING AND D.C. AMPLIFIERS 4
10
95th PERCENTILE

8
T1. — 55"C

7 72. +25 °C

73. +125•C

3
50th PERCENTILE

5th PERCENTILE

o
VBE VBE 2 — VBE 2
V1 -V 2I

171 —T2 I I72 — T3 I ITI-T31

(b) VE,
E TEMPERATURE COEFFICIENT

FOR 2N2480 DIFFERENTIAL

AMPLIFIER

Figure 4.16 (b)

- 600 MV OPERATING LIFE

- 300°C STORAGE LIFE

90%

50%

4 6 8 10 12
TIME X100 HOURS

-600 MW OPERATING LIFE

- - -300°C STORAGE LIFE

1.1 ••• 90%

1.0 50%

0.9
10%

4 6 8 10 12
TIME X100 HOURS

TYPICAL VB. AND h,. MATCH LIFE TEST DATA

Figure 4.17

113
4 BIASING AND D.C. AMPLIFIERS

Table 4.2 shows some of the important parameters and the degree of matching for
three typical differential amplifier transistors which are commercially available.
Thus, with the excellent initial matching and tracking of silicon planar transistors
with temperature and life, it is possible for most applications to design high perform-
ance dc amplifiers without resorting to chopped stabilization techniques.

G.E. G.E. G.E.

TYPE NUMBER 2N2480 2N2652 A 2N2920
VCEO mIn( VOItS ) 40 60 60
ICB0 ma: (na)
at 25°C
(Vcc > 30V ) 50 2 2
hFE min
at Ic = 10 ga — — 150
at Ic = loo »a 20 35 225
at Ic = 1ma 30 50 300
hcc match, max
at Ic = 10 µa — —
at Ic = 100 µa 20% 10% 10%
at Ic = 1ma 20% 10% —
Vcc match, max
at Ic = 10 ga — — 5mv
at Ic = 100 pa 10 mv 3mv 3mv
at Ic = 1ma 10 mv 3mv 5mv
'Wine Temp
Coefficient, max 15 gv/°C 10 etv°/C 10 pv°/C

TYPICAL DIFFERENTIAL AMPLIFIER CHARACTERISTICS

Table 4.2

SINGLE STAGE DIFFERENTIAL AMPLIFIER

The circuit of Figure 4.14 has been analyzed in detail in the literature.<3." The
single ended output voltage, E.,, for adifferential input is given by's )

[(ec2— eri
)-I- (Vim — VBE2) + Ri pIco2 — Re Icoi— (,Lte- ± RBI) ,
V"
nFE1 nEE Io. Rt.,
R R R. R.
R.1 -I- R.. g2
hrE2 hFEI hFEI hFE2 Rze
(4xx)

The differential output voltage )

E. — EO, = K [( egi — ea )+ (Vcc2 — Vcci) -F (Re. I

C01 — Rg2— Io.)

(
hFEI
Re R e' ± — RR..\-]— ICO2 RL2 4yy
where
RLI RL2
= Re2 *-11 RutRg2
hFE2 hrEl hFE1 hFE2 REE

114
 BIASING AND D.C. AMPLIFIERS 4
If the transistors and external resistors are equal, the differential gain
Addo = En. — = 2R1.
eg,— egg R. ± R. 1 (R. y (4zz)
111 1: REE
, "W E/

where RE = RE rE, and rE is the base-emitter junction dynamic impedance

nKT/qIE. For the case where R./hEE << RE, the gain becomes for adifferential output

A40
Ad -
2 ft" (4aaa )
RE
If BEE > > RE, the input resistance for adifferential input is

• (hEE 1) RE 4bbb)
For a differential input and single ended output, or a single ended input and
differential output, the gain is one half of that given by equations (4zz) and (4aaa).
For asingle ended input (e2 = 0) the input resistance

• = (hEEI + 1)2RE, -I- Re (4ccc )

(hEE2 + 1)

RL1Rg2
The common mode gain for adifferential output is given by (e gi= = eg)
E02 E01 - r RI.2 R., 1
(4ddd )
e. + RI.2) BEE L hevs J
In the derivation of equation (4aaa) it was not assumed that the R. << hrE RE.
If the circuit is perfectly balanced and the transistors are exactly alike, then the
common mode gain is zero. If the source impedance and external resistances are equal,
but the current gains are different, equation (4ddd) becomes

Aede = En, — Em K 1 1 (4eee)

e, = 2REF: ‘11F1:2 hF1:1
and the common mode rejection then becomes
CMR = Differential Cain = 2REE 1 1FEI hFE2
.
(4fff )
Common Mode Gain R. (hE EI—
For asingle ended output the common mode gain is

• =
REI ± 2BEE (4hhh)
if 2BEE h,, > > R..
The common mode rejection becomes for BEE > > RF:1

CMR = 2RE.
(4iii
REI RE2
Thus to reduce the common mode gain and improve the common mode rejection,
for both the single ended and differential output, BEE should be as large as possible.
As REE is increased, the operating currents must be decreased or VEE must be in-
creased. Another solution is to replace BEE and VEE by a constant current source as
shown in Figure 4.18. For RI= R2, I.. = VEE/2 R., and the diodes Di and D. com-
pensate for the VBE variation of the transistor with temperature.
Because the temperature coefficient of aforward biased junction is astrong func-
tion of de current for silicon (see Chapter 17), it is important that some care be
exerted in selecting the transistors, the diodes, and current levels if an optimum com-
pensation is desired. If the transistor is diffused and non-gold doped, the diodes should
be the same and the current through the diodes should be selected to be equal to IEE.

115
4 BIASING AND D.C. AMPLIFIERS

Ro".;

CONSTANT CURRENT SOURCE

Figure 4.18

The resistance shown in dashed lines is the output impedance of the circuit and is
approximately the ho, of the transistor. At low collector currents it is at least several
megohms.
The common mode rejection as given in equations (4fff) and (41ü) assumed that
only the current gains were not equal. The mis-matching of resistors also contribute
to the common mode rejection; however, such adiscussion is beyond the scope of this
manual. For such adiscussion the reader is referred to reference 4.
Examination of equation (4aaa) shows that the differential gain is proportional to
RL/RE if R5/h5 << RE. Thus an upper limit on gain and an upper limit on source
impedance are set by the inequality. The gain or source impedance can be increased
by increasing the current gain of the transistor. Figures 4.19 and 4.20 show circuits
where the gain is increased by using additional npn and pnp transistors respectively. In
the Darlington configuration of Figure 4.19, it is important that Q2' and Q2' have good
current gain hold up at very low currents, have low collector capacitance, and low
leakage. RE of equations (4yy) and (4zz) becomes 2rE2 REI where rE, = n KT/q I El.

DARLINGTON SINGLE STAGE DIFFERENTIAL AMPLIFIER

Figure 4.19

116
 BIASING AND D.C. AMPLIFIERS 4

V EE

NPN -
PNP SINGLE STAGE DIFFERENTIAL AMPLIFIER
Figure 4.20

The current gain becomes hFE, hria', where the current gains are measured at the respec-
tive bias currents of the two transistors. Since the base currents In, and In have been
reduced by the gain of Q,' and Q2' respectively, the drift due to current gain variation
is considered reduced.
A complimentary circuit arrangement is used in Figure 4.20 to increase the gain.'
The breakdown diodes D, and D2 are chosen to have apositive temperature coefficient
which cancels the base-emitter coefficients of Q, and Q2'. The current gain of the
transistor pair Q, and Q,' is

hpE = hPEI IIFE1 4iii)

I‘
Thus to increase the gain, R, should be made large to reduce I,. In the limit, it
becomes infinite so that the base current of the pnp transistor becomes the collector
current of the npn transistor, and the need for high current gain at low collector cur-
rents for the npn is also required. The input impedance of this circuit is also high since
the collector current of the pnp transistors flows through the external emitter resistors.

TWO STAGE DIFFERENTIAL AMPLIFIER

A basic two stage npn differential amplifier is shown in Figure 4.21. The emitters
of the first and second stages have been returned respectively to terminals A and B
since there are quite anumber of possible terminations as shown in Figure 4.22. Some
of the possible terminations when no common mode feedback is desired are shown in
Figure 4.22(a) while some of the common mode feedback circuits are shown in Figure
4.22( b). Which of the terminations in Figure 4.22(a) are used depends upon the
circuit applications, i.e., whether or not common mode signals exist, the magnitude
of the input, etc.
The differential gain of the two stage amplifier is
2h... RI.3
(4kkk)
Vol — Vo, —
Addo =
egt — eg2 RE,

where RE, = R.i r, and it is assumed that current gains and resistors on either side
are equal, i.e., hr., = hf.,, R.1 = R,2 etc. Another assumption is that the input im-

117
4 BIASING AND D.C. AMPLIFIERS

pedance seen at the base of Q, and Q., is larger than the source impedance, R. Voltage
gains of several thousand are possible since transistors with current gains of 100-400 at
currents of 10-100gA are commercially available.
For most applications which require a single ended output, the circuit provides
sufficient gain — one half of that given by (41:1:k) — so that succeeding stages can be

Vcc
RL3 . RL4 . 5K

RLI =RL2.5IK RL3

Rei rR e2'.0.5K

Vcc .I8V
Rg2

0 92
Re2

1 E2

A
(SEE FIGURE4 22 FOR CIRCUIT CONNECTIONS TO POINTS AAND BI

B
BASIC NPN TWO STAGE DIFFERENTIAL AMPLIFIER
Figure 4.21

VEE

VEE
1. B

V EE
(OR GROUND)

(al) (02) (03) (a5) (o6) (07)

"A" TERMINATIONS "B" TERMINATIONS

(a) TERMINATIONS FOR NO FEEDBACK CASE

A
R5
D2
REFERENCE
AMPLIFIER

R6
R6 Îl6

DI

VEE VEE VE E

(bl (1,2) (b3)

(b) TERMINATIONS FOR COMMON MODE FEEDBACK

EMITTER TERMINATIONS FOR POINTS A AND B

OF TWO STAGE DIFFERENTIAL AMPLIFIERS (FIG. 4.21)
Figure 4.22

118
 BIASING AND D.C. AMPLIFIERS 4
single ended. For example, the emitter-base junction of a single ended third stage
reflects back to the input adrift of only 1-2 et v/°C. With asingle ended output, the
causes of drift are the power supply variations (especially the minus supply) and the
variation of the emitter bias currents with temperature. The temperature drift of the
bias circuits can be reduced significantly by the common mode feedback circuit of
Figure 4.22( bl ). This can best be explained by referring to the complete circuit dia-
gram given by Figure 4.23.

Vcc

RL.2

R ,

e51
e62
Re2

Vcc .18v
VEE .-12V
Rei .R.2.510a

Ru s RL2.5IK
05 Rs RL4 .5.1K
REFERENCE R5 .5.1K
AMPLIFIER
R6 .3.5K
Q5 .RA2B

01-02 mG.E. 2N2652

VEE
Q3-04.G.E. 2N2652

TWO STAGE DIFFERENTIAL AMPLIFIER

WITH COMMON MODE FEEDBACK
Figure 4.23

The voltage drop across R. clue to the emitter currents of Q. and Q. is compared
to the reference diode plus emitter-base voltage of the reference amplifier, Q.. This
latter voltage, VR, is extremely stable with temperature and with life (a detailed
explanation of the reference amplifier is given in Chapter 10). The error between VR
and the voltage drop across R. is converted into a current IRby Q.. This current is
essentially the collector currents of the first stage of the differential amplifier, which
in turn determines the emitter current of Q, and Q.. If the RA2 series of reference
amplifiers is used, the external zener current, Iz, is not required, and the bias currents
of QL and Q. must be 250 ILA. If the RA3 series is used, then a 5 ma external zener
current must be supplied and Qi and Q. must be biased at 50 ;LA for optimum
performance.
If the temperature coefficient of the reference amplifier is r%/°C and the reference
voltage is VR, then the single ended output voltage temperature gradient is
W O2 VRT RL1
(4111)
AT — AT — 100 \2 R./
Thus for an RA2B and with the values of resistances given in Figure 4.23, the drift
contribution due to the reference amplifier is only .25 m V/°C at the single ended

119
4 BIASING AND D.C. AMPLIFIERS

output or 0.25 1.2v/°C at the input if the amplifier gain is athousand.

Because the voltage at point B in Figure 4.21 or 4.23 is proportional only to a
common mode input voltage but does not change for a differential input, it can be
amplified and fed back to the input so that the common mode gain is reduced but the
differential gain is not affected. The feedback occurs via R., R«, the reference amplifier,
Q2 and Q2, and the base-emitter circuit of Q. and Q.. The reference amplifier provides
the circuit gain since Q2 and Q. operate in the grounded base mode in this loop. The
common mode loop gain is calculated by opening the circuit at some point, such as
X-Y in Figure 4.23, with point Y terminated in an impedance equal to the input im-
pedance of the reference amplifier. The loop gain is then the ratio of the current which
flows in this terminating impedance to acurrent injected into point X. The common
mode loop gain is
GC--- heel Rn 1Re (4mmm )
2[115 Re + (R5 + Re)]
or
RIA Re Rin (4nnn )
GC
2[R5 Re ± Rin (Rs + R5)]
where gm, 14.., and R1. are respectively the transconductance, ac current gain, and
input resistance of the reference amplifier.
Without the common mode feedback (point X in Figure 4.23 returned to a de
voltage which biases the circuit properly) the common mode gain for asingle ended
output is approximately
A,.. = R22 R2,2 h., (4000 )
4Ra'
where
Re Rin
R.' = R.
RO RI.
and h., is the output admittance of the reference amplifier.
With common mode feedback, the common mode gain for a single ended output
becomes
A...' = A... • 4PPP
I+ Gc
In practice, the common mode gain obtained may not be as low as that given by
equation (4ppp) because of amis-match in hr. of Q2 and Q.. Even so, common mode
gains as low as 3 x 10 and common mode rejections in excess of 100 db are easily
obtained for the single ended output case.

REFERENCES
(1) Hellerman, H., "A Generalized Theory of Transistor Bias Circuits," Paper 57-1023, presented at
the AIEE Fall General Meeting, 1957.
(2) Snyder, G. E., "A High Performance Silicon Transistor for the Entertainment Industry," IEE
Transactions on Broadcast and Television Receivers, Vol. BTR-9, No. 2, July 1963.
(a) Okada, R. H., "Stable Transistor Wide-Band D-C Amplifier," Communications and Electronics,
March 1960.
(0 Middlebrook, R. D., "Differential Amplifiers," John Wiley & Sons, New York, New York (1963).

(5)Hilbiber, D. F., "A New DC Differential Amplifier," 1961 International Solid State Circuits
Conference, pp. 44-45.

NOTES

120
 Lu
LOGIC

An understanding of the manner in which each circuit in aradio receiver operates

is almost all that is required to achieve an understanding of how areceiver operates.
The remaining residue of information needed to complete understanding is the order
in which the circuits are connected. For the example chosen, the order is so obvious
and simple that it could conceivably be deduced from an understanding of the circuits
alone. Naturally other examples, such as radio transmitters, various test equipment, etc.,
could have been used.
More elaborate systems cannot be understood solely in terms of circuit operation.
In general, as systems become more complex, understanding must be based more and
more on the way in which circuits are interconnected and less attention need be given
to the fine details of circuit operation. The particular circuit is only important to
understanding as far as the function (amplify, oscillate, shape, etc.) it performs and
not on how it performs that function.
The classical approach to electronic equipment has been to teach circuit theory
and operation as fundamental and, if time permits, to use asimple block diagram to
show how the circuits are interconnected. As aresult, most of us are oriented in such
amanner that we allot adisproportionate importance to circuitry and tend to consider
organization as being of nominal importance.
Digital systems are representative of aclass of systems where an understanding of
the organization of circuitry is of far greater importance than an understanding of
the circuit details. That is, acomplete and thorough study of each individual circuit
in adigital system will give virtually no clue to the operation of the system. A typical
diagram of a portion of the system will contain "black" boxes labelled AND, OR,
FLIP-FLOP, etc. It is totally immaterial to an understanding of the system whether
the functions are synthesized with relays, vacuum tubes, magnetic cores, cryotrons,
hydraulic valves, transistors, etc. Which of these devices will be used is determined
by such things as size, cost, weight, power, and speed. Furthermore, quite different
digital equipments can be built using identical circuits.
The purpose of this section is to discuss some of the concepts and techniques
utilized in digital work in order to aid the circuit designer in visualizing some of the
constraints and conditions placed upon switching circuits by the intended usage.

SWITCHING ALGEBRA

Consider the switch arrangement in Figure 5.1(a). If either switch A, or switch

B, or both are operated, then the output will be the input voltage E. More than
one switch may be operated to cause an output equal to the input as the only require-
ment is that at least one of the switches be thrown to obtain an output at F. This
type of switch arrangement is called an OR gate. Figure 5.1( b)is one way of symbol-
izing any circuit which performs an OR function. Such a box need not be made up
of mechanical switches only, but may be synthesized in many ways.
If atable is made of the possible combinations of switches A and B and the value
of the output F for each of these combinations it would appear as shown in Figure
5.2(a). Since aswitch has only two possible conditions or states, either closed or open,
and the network can either have a closed or open path between input and output,
it is common to use the symbol "0" to represent an open condition and a"1" to repre-

121
5 LOGIC

SWITCH A

F.

A OR EI

E VOLTS (OUTPUT)

2_
(o) MECHANICAL SWITCH (b) BLOCK DIAGRAM
ARRANGEMENT FOR REPRESENTATION FOR
OBTAINING THE OR THE OR FUNCTION USEFUL
FUNCTION FOR ELECTRONIC CIRCUITS

THE OR FUNCTION
Figure 5.1

sent the closed condition. This use of "0" and "1" is different from that normally
encountered in that these symbols do not represent numbers. They are simply used
as a short hand for indicating the presence or absence of a conducting path. In a
similar manner, the symbol "+" is used to indicate OR rather than the usual "plus"
of ordinary arithmetic. The table of Figure 5.2( b), using these conventions, is some-
times called atruth table as well as átable of combinations. This is borrowed from
abstract logic where "0" and "1" represent "false" and "true" respectively and
F = A ± B would be interpreted as "statement F is true if either statement A or
statement B (or both) is true."

A e F A 13 F=A+13

OPEN OPEN 0 VOLTS 0 0 0

CLOSED OPEN E VOLTS I 0 I

OPEN CLOSED E VOLTS 0 I I

CLOSED CLOSED E VOLTS I I I

(a) (b)

TABLE OF COMBINATIONS FOR THE

SIMPLE OR GATE
Figure 5.2

Consider now the case of series switches as shown in Figure 5.3(a). There will
be a conducting path between input and output if, and only if, both A and B are
closed. The symbol "." is used to indicate the AND and again care should be used
to prevent confusing this symbol with ordinary algebraic multiplication.
With the above concepts in mind, it is quite possible to set up an "algebra" to
describe various switching arrangements. Keeping in mind that "0" represents an
open path and "1" represents aconducting path we may write the first six results of
Table 5.1 from the truth tables of Figures 5.2( b)and 5.3(c).
Notice, in Table 5.1, that 1± 1= 1does not appear at all like ordinary algebra.
If we read "a conducting path or aconducting path is aconducting path," however,
and visualize short circuits in place of the two switches in Figure 5.1( a), it is amean-
ingful and logical statement.

122
 LOGIC 5

SWITCH SWITCH
A e
F•

A AND B

E VOLTS (OUTPUT)

(a) MECHANICAL SWITCH (b) BLOCK DIAGRAM

ARRANGEMENT FOR REPRESENTATION OF
OBTAINING THE AND THE AND FUNCTION USEFUL
FUNCTION. FOR ELECTRONIC CIRCUITS.

A F•A•B

O o
o
o O

(al TABLE OF COMBINATIONS

FOR THE AND FUNCTION.

SIMPLE AND FUNCTI ON

Figure 5.3

SIMPLE RELATIONS

I. 0+0 .0 5. 0.1=0 9. A + A •A 13. 0+A=A

2. 0.0.0 6. 0+1=1 10. A•A • A 14. 0•A =0
3. 1+1=1 7. o =) II. Tt•A =0 15.1+4=1
4. 1.1=1 8. T.0 I2.À+A =I 16. I•A•A

LAWS

COMMUTATIVE ASSOCIATIVE DISTRIBUTIVE

17. A+B • B+A 19.(A+8 )+C =A+(B+C) 21.A4B+C)=A•B+A•C

18. A•13 •B•A 20. (A•01•C •A•( B•C 1

SIMPLIFICATION RULES

22. A+A•B =A 25. (A•B )= —A+Éi (NAND) De MORGAN'S

23. A +74.0 =A-+ B 26. (A+B) =-
Ii•ii (NOR ) THEOREM

24. A•( A+ B )= A

USEFUL RELATIONSHIPS
Table 5.1

Since "0" and"1" are the only two possible values we may have, it follows that
"not 0" (written Ô) must be "1" and "not 1" (written i) must be "O." Negation in
this manner is sometimes called INVERT or simply NOT. T N. would be aswitch which
was closed whenever A was open and open whenever A was closed.
Table 5.1 tabulates some of the more useful rules for this form of algebra. Most
of these can be demonstrated with simple switch arrangements or by use of a table
of combination or both.

123
5 LOGIC
To illustrate the usefulness of the relations given in Table 5.1, refer to Figure
5.2( b). F is "1" whenever we have the combination "A AND not B, OR not A
AND B, OR A AND B." That is, F = A •13- 4- À • B + A • B. To simplify we
first use (21) from Table 5.1 to obtain F = A •Ij + B •(À + A). By using first (12)
and then (16) from the table we arrive at F = A •1 3+ B •1= A •173 + B. Finally,
-

from application of (23) we obtain F = A B. Figure 5.4 shows the black box
arrangement for each of these steps.

F.A•ii+ À•B +A•B.

A iii-( À+A) El= Al-B

(a) F=A+ B IN UNSIMPLIFIED FORM

FAB+B•( À+A)=A•b+B
=A+B

(b) FIRST STEP IN SIMPLIFICATION

A—› AB
•
F= A É
S+B=A+B

(c) SECOND REDUCTION DUE TO A+ =I

F=A+B

(d) SIMPLEST FORM

DIFFERENT WAYS OF OBTAINING THE SAME FUNCTION
Figure 5.4

One of the basic problems in digital design is obtaining the minimum number of
circuits to synthesize a given function and hence much of the work in this area is
devoted to simplification techniques. It is beyond the scope of this book to describe
the many simplification methods which have been developed and, therefore, only the
Karnaugh Map will be discussed.
The following example is given to illustrate the ideas discussed above as applied to
areal problem.
Consider asimplified hot air heating system using oil as afuel. It is desirable to
control the fan for circulating the air and the motor-ignition system for turning on the
furnace automatically.

124
 LOGIC 5

The first condition that must be met is that the furnace is to be turned on when
the temperature in the building falls below a certain value. A thermostat remotely
located with respect to the furnace can be used to provide a variable T which will
have the value 0when the temperature is too low and the value 1when the tempera-
ture is above that desired.
A second condition is that the fan should not operate until the furnace is warm
enough to heat the air. This lower temperature limit can be obtained from athermo-
stat connected to the furnace itself. Let this variable be designated L and have the
value 1when the temperature of the furnace is sufficiently high, and 0otherwise.
A third variable might be introduced for preventing overheating of the furnace.
Let this variable, H, be 0 as long as the temperature of the furnace is not excessive,
and 1otherwise. Naturally if H is 1then L must be 1also.
There are three variables (T, L, and H) involved and two functions, the fan F
and the motor-ignition M, which must be controlled. Table 5.2 is a listing of all
possible combinations.

VARIABLES FUNCTIONS
TLHFM

00001

0 0 1 NOT POSSIBLE
0 I 0 I 1

0 I I I 0
10000
I 0 1 NOT POSSIBLE
1 I 0 1 0
I I I 1 0

TRUTH TABLE FOR SIMPLE FURNACE SYSTEM

Table 5.2

Ignoring those combinations which cannot happen (i.e. the furnace at an exces-
sively high temperature, H = 1, but not hot enough to turn on the fan, L = 0) it can
be seen that M = 1when

From Table 5.1, relation 21, this expression may be factored to obtain
M ="i• rl •(L L).
L L = 1, M may be written as
Since relation 12 gives
= i. Ñ •1=-T•
where the last step is obtained by applying relation 16 from Table 5.1.
In asimilar manner we may obtain
F=T•L•Ii ±T•L•H
L. ±H) +T. L. (
Ï4+ H)
=P.L. 1-1-T•L• 1=T•L+T•L
= L•("T T) = L•1= L
This arrangement of switches is shown in Figure 5.5. Although this example is
very simple, it does illustrate the simplification which is possible by the application
of avery few rules.

125
5 LOGIC

DIRECTION OF
INCREASING
THERMOSTAT TEMPERATURE

ROOM FURNACE
FAN
THERMOSTAT THERMOSTAT
MOTOR

FINAL SIMPLIFIED CONTROL CIRCUITRY

FOR BASIC FURNACE
Figure 5.5

THE KARNAUGH MAP

It is sometimes convenient to arrange the truth table in asomewhat different way.
Consider the four-variable table of Figure 5.6(a). Glancing at this table it can be
seen that there are four rows where CD =_ 00 (C = 0 and D = 0), four rows where
CD =. 10, four rows where CD -= 01, and finally four rows where CD = 11. Not
quite so obvious is the fact that the same statements could be made about any two
variables such as AB, BC, AC, etc.
Now consider achange in switch values. Let us say that CD goes from CD =_ 00
to CD = 11. This implies that two variables, C and D, must change. A similar case

00
VARIABLES
A BCDF ( e
10 CD 01
0000f 0
I 0 0 0 f1
0 I 0 0 f,
I I 0 0 f, (b) A CYCLIC SEQUENCE WHERE
0 0 I 0 f. ONLY ONE VARIABLE AT A TIME
I 0 I Of. CHANGES AT EACH STEP
ABCD•0110
x.f. ---* 0 I I Of.
I I I 0 fi AB
000 I f. CD 00 01 11 10

1 00 1 f.
00
0 1 0If, 0
1101 f.
01
0011 f,.
1011 f,,
0111 f,.
1111 fu,
ID

O OF 1 DEPENDING ON
THE VALUE DESIRED ABCD.0110
FOR FAT THE th ROW f.

(0) A FOUR VARIABLE TABLE (C) A MAP OF ALL POSSIBLE

OF COMBINATIONS COMBINATIONS OF ABCD
ARRANGED IN CYCLIC
ORDER

CONSTRUCTING A KARNAUGH MAP

Figure 5.6

126
 LOGIC 5
occurs for CD = 10 to CD = 01 where C must go from C = 1to C = 0and D must
change from D = 0to D = 1. It is desirable to choose a sequence of combinations
where only one variable at atime changes. Such asequence is CD = 00, 01, 11, 10,
00, 01 etc. This is illustrated in Figure 5.6( b). This same sequence is used for
both AB and CD in the map shown in Figure 5.6(c). Consider the square marked
with an X. This square is in the position AB = 01 and CD = 10 or it corresponds to
the combination ABCD = 0110 in the truth table of Figure 5.5(a). Reference to the
truth table reveals that F should have the value f6 for this combination of variables.
Hence the value f6 should be placed in the box indicated by an X. The map, called a
Karnaugh map, is thus asomewhat more compact way of writing atruth table.
The Kamaugh map is of great value in simplification of switching functions. This
comes about because any two adjacent squares differ by only one variable. Consider
the three variable map of Figure 5.7( a). Here the values for the f1have been filled in.
F is true when
F=À•É•é+À•B•é-I-A•É•é+A•711•C
Consider the first two terms A. ft •é and A. B • These terms correspond to the
case where AB = 00 and C = 0for the first term and AB = 01 and C = 0 for the
second. The only variable which is different for these two terms is B. AC = 00 for
both terms. As amatter of fact, wherever A = 0 and C = 0on the map, F is 1and
we may replace the first two terms of the expression for F with AC. Similarly the last
two terms occur when A = 1and B = 0regardless of the value of C and hence they
can be replaced with Abl. F becomes
F=À•é+A•i;
\AB
CD 01 10
1
00 1/ o o \1
_
,.
à- 5
oI 0 T—
I CI 0
<
l BD
!I
0 11 0
•._ ._,

10 I\ 0 0, I
1

(o) THREE VARIABLE MAP (b) FOUR VARIABLE MAP

SIMPLIFICATION ON KARNAUGH MAPS
Figure 5.7

Of course, the above expression could have been obtained by using the relations
in Table 5.1 and juggling the expression for F until it had simplified. It is not always
easy to see which of the expressions to use, however, and the map does give a
convenient way of visualizing simplifications. It is also interesting to note that the
square where AB = 00 and C = 0 and the square where AB = 10 and C = 0 are
actually "adjacent" in that B is the only variable that is different in these two positions.
Hence we could also write
F=X•é-FA•U-1-U•é-
The last term, •é, is however redundant and therefore not necessary since the
l's covered by B *è are also covered by X •é ± A •B. The important point is that the
map may be pictured as folded to form a cylinder with the first and last columns
adjacent at the seam.

127
5 LOGIC
In asimilar manner, agroup of four l's which are adjacent can be combined. This
is indicated in the four variable map shown in Figure 5.6(b). The center group of
units are covered by B •D (B = 1, D = 1) and the corner units by ii •D (B z-- 0,
D = 0) so that
F=B•D-Fili•15
On this four variable map the upper and lower rows are considered adjacent as
well as the left and right columns of the map.

NUMBER SYSTEMS
The ordinary, every day number system has the base, or radix, 10. There are ten
digits, 0through 9, which are used to express any quantity desired depending on the
order in which they are placed. A decimal number N, such as 2904 is really a con-
traction for
N = (2 X 108)-I- (9 X 102)± (0 X 10 1)± (4 x 10°)
Suppose, however, that instead of the ten digits, 0 through 9, with which we are
familiar, only 8digits, or 5digits, or 3digits, or even only 2digits had been invented.
How would counting be established? A possible way of counting is shown in Table 5.3
and in each case the method is identical in nature to that followed in the ordinary
decimal system.

BASE 10 8 5 3 2

NAME DECIMAL OCTAL OUINARY TERT IARY BINARY

o o o o o
I
1 I I I
2 2 2 2 10

3 3 3 10 II

4 4 4 II 100

5 5 10 12 101

6 6 II 20 110

7 7 12 21 III
6 10 13 22 1000

COMPARISON 9 II 14 30 1001

OF VARIOUS 10 12 20 31 1010

COUNTING SYSTEMS 11 13 21 32 1011

12 14 22 100 1100
Table 5.3 13 15 23 101 1101

14 16 24 102 1110

15 17 30 110 1111

16 20 31 11I 10000

Notice that in the decimal system, the least significant digit goes from 0through 9
and then begins the procedure all over again. A unit before the least significant digit
indicates that one cycle of 0 through 9has been completed. In asimilar manner, the
least significant digits in the octal system, cycle through digits 0 through 7 and then
repeat. A digit before the least significant bit indicates how many cycles have already
been used.
Using asubscript to indicate the particular number system being used, we may
convert from any number system back to the decimal system. For example
(1111)2= [(I X 22)± (I X 22)-I- (1 X 21)± (I X 2°)Lo
= [8 ± 4+ 2+ 11,0 = (15)10
or
(23)2= [(2 X 51)± (3 X 5”122 = [10 -F 3]ao = (13)12

128
 LOGIC 5
The ordinary procedures of everyday arithmetic, namely: addition, subtraction,
multiplication, and division, can be carried out in the same manner as for the common
decimal system. Naturally, a new multiplication and addition table must be used for
each system. Fortunately, as the number of digits becomes smaller the tables become
simpler. Table 5.4 and Table 5.5 contain the addition and multiplication tables,
respectively, for the decimal, quinary and binary systems.

+ 0 1 2 3 4 5 6 7 8 9

0 0 1 2 3 4 5 6 7 8 9
1 1 2 3 4 5 6 7 8 9 10
2 2 3 4 5 6 7 8 9 10 II
3 3 4 5 6 7 8 9 10 II 12
4 4 5 6 7 8 9 10 II 12 13
5 5 6 7 8 9 10 II 12 13 14
6 6 7 8 9 10 1I 12 13 14 15
7 7 8 9 10 II 12 13 14 15 16
8 8 9 10 II 12 13 14 15 16 17
9 9 10 II 12 13 14 15 16 17 18

(a) DECIMAL ADDITION

+ 0 1 2 3 4 O
COMPARISON OF
0 0 1 2 3 4 O O
ADDITION TABLES
1 1 2 3 4 10 10
FOR SEVERAL
2 2 3 4 10 II
NUMBER SYSTEMS
3 3 4 10 II 12
(c) BINARY ADDITION
Table 5.4 4 4 10 II 12 13

(b) OUINARY ADDITION

X 0 1 2 3 4 5 6 7 8 9
0 0 0 0 0 0 0 0 0 0 0
I 0 1 2 3 4 5 6 7 8 9
2 0 2 4 6 8 10 12 14 16 18
3 0 3 6 9 12 15 18 21 24 27

4 0 4 8 12 16 20 24 28 32 36
5 0 5 10 15 20 25 30 35 40 45
6 0 6 12 18 24 30 36 42 48 54
7 0 7 14 21 28 35 42 49 56 63
8 0 8 16 24 32 40 48 56 64 72
9 0 9 18 27 36 45 54 63 72 81

(a) DECIMAL MULTIPLICATION

COMPARISON OF
X 0 I 2 3 4 X o
MULTIPLICATION
0 0 0 0 0 0 o o O
TABLES FOR
1 0 I 2 3 4 O
SEVERAL NUMBER
2 0 2 4 II 13
SYSTEMS (0 BINARY
3 0 3 11 14 22 MULTIPLICATION
Table 5.5 4 0 4 13 22 31

(b)OUINARY MULTIPLICATION

129
5 LOGIC
It is very obvious that, of all the systems here suggested, the binary system is the
simplest. Because there are only two digits, 0 and 1, the multiplication and addition
tables are much less complex than for the decimal system. Again, the fact that there
are only two digits means that any device with only two distinct states can be used
to represent binary numbers. The simplest such device is amechanical switch which
is either in aclosed position or an open position. It follows that binary numbers can
be represented by very simple devices. A four place binary number such as 1101 can
be represented by four switches, three of which are closed and one is open.

ARITHMETIC OPERATIONS
In general, arithmetic operations are carried out just as in ordinary decimal arith-
metic. These can best be described by comparative examples. The first two examples
are written in considerable detail to clarify the carry and borrow operation while the
last two examples assume the carry and borrow is understood.

Addition
Carry Note (1) Carry Note (1111 )
46 101110
+28 + 10110
74 1000100
Subtraction
Borrow (1) Borrow (1)
42 101010
—18 — 10010
2A 011000
Multiplication
42 101010
21 10101
42 101010
84 000000
882 101010
000000
101010
1101110010
Division
3.75 11.11
16 V60.00 10000 V111100.00
48 10000
120 11100
112 10000
80 11000
80 10000
10000
10000

Division obviously can produce answers which are fractional. The binary point
need cause no confusion, however, if it is kept in mind that adecimal number 3.75
means
(3.75 )10 = (3 X 10°)10 + (7 X 10 -1 )10 ± (5 X
By direct analogy then, abinary number 11.11 means
(11.11) 2 = (1 x 21)10+ (1 X 2°)10+ (1 X 2') -I- (1 x 2').

130
 LOGIC 5
MEMORY ELEMENTS
Just as there are many types of switching elements, so there are many types of
memory elements which may be used. Briefly, amemory element is an element whose
present state depends on what has happened in the past. A simple delay line can be
used as amemory element for the output at any given moment depends on what the
input was at some previous time. Magnetic materials are frequently used as memory
elements as the direction of magnetization at the present moment is determined by
the direction of current flow through acoil. This current flow may have occurred quite
some time ago and thus the memory is not limited in time as adelay line is. In elec-
tronic circuitry, astandard bistable flip-flop with some means of triggering to cause a
change of state can be employed as amemory element.
A relay is used as amemory element in Figure 5.8 as this is a very simple and
versatile element familiar to almost everyone associated with electronics. Switch S
is used to turn on the lamp and switch R is used to turn the lamp off. Whenever S
is closed, the lamp will light and relay A will be activated through either a normally
closed relay contact (X) or the normally closed (F) switch. Of course, once the relay
is operated, normally open contact A provides an alternative path for the current
which flows through the relay and the lamp. Therefore, even if switch S is released,
the lamp will stay lit.

A S R LAMP RELAY A

0 0 0 o 0
0 0 o 0
0 I 0 I
0 I I I
I 0 0 I I
I 0 I 0
I I 0 I I
I I I I 0

LAMP

E VOLTS LAMP , A+S

RELAY
A= Ar2 + Sr? + AS

A SIMPLE MEMORY ELEMENT UTILIZING A RELAY

Figure 5.8

131
5 LOGIC
Once relay A is operated, the normally closed contact (X) is open and thus only
the normally closed position of R (R) provides areturn path for current. Closing R
(or opening 'A) removes exitation from relay A, thereby turning off the lamp provided
S is off. Thus the relay acts as amemory element for the lamp enabling the circuit
to "remember" which switch, Sor R, was last operated.
There are many variations of memory element of which the above was chosen
because of its extreme simplicity. Practical circuits are discussed in the chapter on
digital circuits. This section will discuss very briefly some common applications of
memory elements.
Figure 5.9(a) is asymbol frequently used for memory elements. The output line
is labelled Q and in some circuits, such as the Eccles-Jordan flip-flop, the complement,

1 2 3 4 3
2 4
(RESET)
CONTROL f (SET)M OUTPUT
OR
INPUT
(PULSE)

(a) A SIMPLE REPRESENTATION (b) A SIMPLE TECHNIQUE FOR

FOR MEMORY ELEMENTS GENERATING PULSES FROM
RECTANGULAR WAVES

SIGNAL
PULSES
(c) MEMORY ELEMENTS INTERCONNECTED
TO FORM A SIMPLE BINARY COUNTER

AFTER BEFORE MEMORY ELEMENTS DECIMAL

PULSE PULSE c B A EQUIVALENT

I 0 0 0 0
0 — N rn e u-, o 1.-

2 0 0 I I
3 0 I 0 2
4 0 I I 3
5 I 0 0 4
6 I 0 I 5
7 1 I 0 6
8 I I I 7

(d) COMPLETE SEQUENCE FOR THE COUNTER

IN TRUTH TABLE FORM

COUNTING WITH BINARY ELEMENTS

Figure 5.9

or "not Q" (( ), is also available. The 1' signal is usually a"clock" or chain of uniformly
separated pulses which enable the memory element to change state. In effect, the P
pulses are ANDed with each of the input lines R and Sso that the element can respond
to the input lines only at discrete intervals of time coinciding with the presence of a
clock pulse.

132
 LOGIC 5
Sometimes asquare wave is used as the clock in which case it is frequently con-
venient to use an RC differentiating network to cause the flip-flop to respond to either
the leading or trailing edge (never both) of the clock signal P. This is also indicated
in Figure 5.9( b).
The R line, commonly called areset, is used to set the memory element to azero
(Q-+ 0when R = 1). The S line is used to cause the memory element to assume a
"one" state (Q—> 1when S= 1). Due to the internal ANDing of the P line with both
R and S, neither input can have an effect until aclock pulse appears. It is also true
that it is quite meaningless to make R and Sboth unity and then apply aclock pulse
as this is logically equivalent to asking the Q line to become 0 and 1simultaneously.
Figure 5.9(c) shows aparticular way of connecting three such memory elements.
Assuming that the P inputs do use differentiating RC networks and that the elements
are sensitive only to positive going pulses on the Plines, then quite obviously whenever
À changes from 0to 1, an active pulse will be applied to input Pa on element B and
this pulse will cause flip-flop B to go to whatever state is being asked for by the con-
trol lines RBand SB. The same remark applies to the connection from it" to Pc.
The outputs of each element are fed back to the inputs. Whenever, for example,
the A line is a1, then the reset line RAis also aone so that the next pulse at PAmust
set A = 0. When - À is a 1, A is 0 and hence the set line SAwould not be energized
under this condition. Since A can never be equal to À, there can never be acase where
both RAand SAare one (or zero) simultaneously, thus avoiding an illogical possibility.
The manner of interconnection on each of the flip-flops is such that they will
change state each time apositive going signal enters aPline. Assume that the elements
are all in the zero state (A = B = C = 0). The first signal pulse into PAwill cause A
to change state so that A = 1. This means that À must change from À = 1to À = O.
Since this would cause a negative going pulse into PR, the B element will not be
affected and the state of the flip-flops CBA is 001. By following this analysis for a
number of pulses, the truth table of Figure 5.9( d) may be obtained. If these combina-
tions are compared with the binary column of Table 5.3, it can be seen that each
combination represents a binary number equivalent to the number of signal pulse
which have entered PA. (Recall that zero's to the left of anumber are not meaningful).
An arrangement such as that in Figure 5.9(c) is frequently referred to as acounter.
With only three memory elements, such acounter can only count from 0to 7and then
must repeat itself. By adding more stages, the counter can be used to count as high
as desired.
A slightly different arrangement of elements is given in Figure 5.10(a). In addi-
tion, to memory elements, small delay units, D, are also used. In many practical cases,
there is an inherent delay from the instant asignal is applied to an R or S line to the
moment this signal becomes effective (or recognized) inside the memory element.
In these cases, the external delay elements may be eliminated. In any event, the total
delay time must be less than the interval between clock pulses. The purpose of the
delay elements is only to prevent the input lines, R and S, from changing while a
clock pulse is actually present. It can be seen that all elements receive the same clock
pulse and apossibility for confusion exists if the inputs to B are changing, for example,
at the instant Pg is energized.
In order to understand the operation of this arrangement, consider the case where
all elements are in the zero state (A = B = C = 0), and SA= RA= 0. Let SAbecome
1just long enough for one clock pulse to enter element A and cause the flip-flop to
go to the one state. Thereafter, let SAreturn to 0. When SAreturns to zero, let RA
become 1long enough to catch aclock pulse and thereafter let RAgo to 0and remain
there. This sequence of events is depicted graphically in Figure 5.10( b).

133
5 LOGIC
Before the first clock pulse, the setting of the three elements were all zero (ABC =
000). After the first pulse, but before the second pulse, we have ABC = 100. Between
the second and third pulse ABC = 010, between the third and fourth ABC = 001,
and after the fourth pulse ABC = 000. The effect is that a 1has been propagated
from left-to-right in Figure 5.10(a), advancing one step with each clock pulse. Such
an arrangement of memory elements is commonly termed ashift register. When the
output (in this case C and E) is tied back to the input (in this example SAand Re),
the arrangement is termed acirculating register or aring counter.

sA
A t> A 4D

1
-1
PA
Pe PC
CLOCK
PULSES

D =DELAY

(a) SIMPLE SHIFT REGISTER INTERCONNECTION

CLOCK

54

.0

FLIP -FLOP I
O 0 0 0
A

1
SB

FLIP -FLOP .
O 0 I 0 0
8 o j I

sc
0
HI-HD
FLIP -FLOP .
O o Io o

TIME

(b)TIMING C HAR T FO R THE SH IFT REG ISTER

SHIFT REGISTER
Figure 5.10

CIRCUIT IMPLICATIONS
In order to discuss the areas which have a bearing on the design of circuitry, a
problem common to many digital computers will be illustrated. Suppose that it is
desirable to design a "black box" which will add two binary numbers together and
have as an output the sum of the two numbers. A coarse diagram is given in Figure
5.11 which indicates one possible way in which this task might be performed.

134
 Locic 5
CLOCK CLOCK
PULSES PULSES

SHIFT REGISTER A
SHIFT REGISTER
NUMBER A RESULT
R=A PLUS B
SHIFT REGISTER
ADDER
NUMBER 0
C,
MOST LEAST
SIGNIFICANT SIGNIFICANT
BIT BIT

PREVIOUS NEW
DELAY
CARRY 4 CARRY

ONE METHOD OF PERFORMING BINARY ADDITION

Figure 5.11

The two numbers, A and B, are each stored in shift registers in the manner indi-
cated so that the least significant bits of the numbers will be first into the box labelled
Adder. The Adder must do two things. It must produce a bit for the result register
and must also determine whether or not acarry would result that should be applied
to the next set of bits from A and B. The result register is used to accept and store
the sum as it is developed by the Adder. It should be kept firmly in mind that only
one bit of each number is present at any one time at the input to the Adder.

PRESENT PRESENT
PREVIOUS NEW RESULT
BINARY BINARY
CARRY CARRY VALUE
VALUE VALUE
C CN R
A B o

O. 0 0 0 0 0

0 0 I 0 I

2. 0 I 0 0 I
3. 0 I I I 0

4. I 0 0 0 I

5. I 0 I I 0

6. I I 0 I 0

7. I I I I I

Table 5.6

Table 5.6 lists all possible combinations of carry and bit values for A and B which
can occur at the input of the Adder. In line 3, for example, bit A is a0, B is a 1, and
the previous addition had produced acarry. Since
O+ 1+ 1= (10)2
the result R must be 0 and the new carry should be 1. In line 7, all three bits are 1
and since 1+ 1+ 1= (11)2, the result should be R = 1and CN= 1.
From Table 5.6, it is seen that
R = À •É •C. + À •B • ± A •i3 • ± A •B •Cp
CN=A•BA-A•Cp+B•C,

135
5 LOGIC

The complete logic arrangement of the Adder is shown in Figure 5.12. Instead of
delaying the carry with a delay line, amemory element in the form of a flip-flop is
used to store the new carry. This allows the carry to change with the same clock pulses
used to shift the registers thus avoiding the need for a delay and clock with very
tight tolerances.
The Cp line of the C flip-flop in Figure 5.12 is attached to four AND gates while
the complement line C. is attached to two AND gates. To the circuit designer this
means that the flip-flops must be designed so as to be capable of driving these gates
without undue loading. If all flip-flops are to be identical (to save on engineering
effort) rather than individually designed for each trivial variance in use, then one
must also be able to make ashift register with them. In the counter shown in Figure
5.9(c), the flip-flops must be capable of driving the P line as well as an input Sline.
Although the AND circuits need drive only one input on an OR gate, the OR gate in
Figure 5.12 must be capable of driving at least an Sline on aflip-flop and an INVERT
circuit. It follows that no circuit should be designed to operate only without a load.
Every circuit has at least one load and frequently has more than one.
It is customary to consider the current required to drive one input on alogic gate
(OR or AND) as a unit load. The maximum current available from any circuit for
driving other circuits is divided by the current required by aunit load. The resulting
number is the number of logic gates that the circuit can drive and is called the "fan-
out" capability of the circuit. In general, the fan-out should be three or greater
although special cases may not require this.
A study of Figure 5.12 reveals that the AND gates can be divided in two groups
according to the number of inputs. Four of the gates have 3 inputs and three have
2 inputs. One of the OR gates has 4 inputs and the other has 3 inputs. The number
of inputs is called the "fan-in" of a circuit. Frequently the circuits are built as
3input, 5input, and 9input gates. If a4input AND is needed, for example, a5input
AND is used with one of its inputs tied to avoltage which represents the 1level as
A•B•C•D•1=A•B•C• D. Thus the number of different types of circuits
which must be manufactured for agiven machine is minimized.
Beside fan-in and fan-out considerations, there is one rather subtle point that is
not directly apparent from Figure 5.12. Current flow can be either into or out of a
circuit. The output of the 3input OR gate in Figure 5.12, for example, indicates an I,
which flows into the circuit and an I. which flows out of the circuit. A current out of
the output of acircuit, I., is considered as flowing in apositive direction whereas L is
considered as flowing in anegative direction.
In a similar fashion an input may be driven either by "pulling" current out or
‘`pushing" current in as shown by I. and L respectively. A current entering the input
is considered as a positive flowing current while a current leaving the input is con-
sidered as anegative flowing current. Since it is desirable that circuits be capable of
driving each other and in particular that any logic circuit be capable of driving another
circuit like itself, it is necessary that all currents be positive or that all currents be
negative. A set of circuits for which this is true is called acompatible set.

A compatible set is called complete if it is possible to generate any arbitrary

switching function whatever and includes a general-purpose compatible memory
element. The AND, OR, INVERT circuits with the R-S flip-flop of Figure 5.12 form
acomplete set. Actually, it is possible to eliminate either the AND or the OR gate
(but not both) from this set without affecting its completeness. In general, the circuit
designer must produce acomplete set if his efforts are to be usable.

136
 SHIFT REGISTER A •
Cp
AN
-- -
N INTE_ReElp1TE A,
NP
__

•
CLOCK SHIFT REGISTER —I
PULSES'
-
RN INTERMEDIATE
SHIFT REGISTER B
I II+
t>_ _ STAGES _ >
r
•

CLOCK I
. T
SN _ INTERMEDIATE -
INPUT I PULSES
c,BIL STAGES __ _ __

CLOCK' I's •
PULSES

A
IS —• N
X 7(
. INVERT OR
Cp • I -
14 4— NOT CIRCUIT
12

Cp •

S NEW
Cp
CARRY
LOGIC DETAILS OF CN
RC éN
THE BINARY ADDER Pl

Figure 5.12 CLOCK

PULSE
5 Locic
NOTES

138
 cc

6
IsJ

SWITCHING CHARACTERISTICS
C.)

Semiconductor transistors and diodes have rapidly become the most useful, versa-
tile, and widely used devices in switching applications. Among the many devices which
are used and will continue to be used in this area, only semiconductors have so broad
acombination of desirable features. Among these are low power consumption, high
speed, small size, no filament power, low cost, good fan-out, and remarkably long life.
Any number of devices may have superior qualities in any one area but not in all
these areas. A relay, for example, has much greater fan-out capabilities (many relays
may be operated by asingle relay contact) but is poor in speed, power, and life com-
pared to atransistor. Relays will be life tested many hours for several million opera-
tions without failure to qualify as highly reliable while a good transistor switch can
make a million or more operations in one second without impairing its useful life.
Furthermore, problems of contact bounce and arcing are non-existent with either
transistors or diodes.

THE BASIC SWITCH

Any device which has, or can be made to have, two distinct states may be con-
sidered for possible application in digital equipment. This property need not always
resemble amechanical switch in being open or closed. For example, adevice which
can be made to oscillate on one of two distinct frequencies, or adevice which operates
as an oscillator on a single frequency but which can be made to have one of two
distinct phases, or even adevice that can be made to oscillate or not oscillate could be
used. Frequently switches are made of two components such as alight-emitting diode
and a photo-diode where the photo-diode is necessary to detect the presence of
absence of alight from the light emitter. In short, there are many ways of producing
an analog of the simple mechanical switch.
The most common usage for transistors and diodes is as a direct analog of the
mechanical switch. That is, the diode and transistor are made to have ahigh resistance
(open) state and alow resistance (closed) state.

THE BASIC DIODE SWITCH

A diode can be changed from alow resistance state to ahigh resistance state by
the simple expedient of altering the bias conditions across the diode junction. Figure
8.1 gives the voltage-current characteristic for aPN junction and from this it can be
seen that a very small voltage in the forward direction can cause an appreciable
current flow (low resistance) while avoltage in the reverse direction (but to the right
of the avalanche region) will produce only asmall leakage current (high resistance).
This figure is somewhat misleading in that it is not drawn to scale. A typical value
for leakage current for the 1N3805 at room temperature is 15 nano-amperes at a
reverse voltage of 50 volts which corresponds to an "open" circuit resistance of more
than 3000 megohms. On the other hand, a forward bias of 0.8 volts will typically
produce acurrent of 80 milliamperes at room temperature which corresponds to 10
ohms for the "closed" circuit resistance. Thus a diode can be a very good switch.

THE BASIC TRANSISTOR SWITCH

A generalized volt-current characteristic for an NPN transistor is shown in Figure
8.2. That portion of the load line between point A and point B lies in what is com-
monly referred to as the active-region of the transistor. This region is bounded on the

139
6 SWITCHING CHARACTERISTICS

CURRENT

FORWARD BIAS
(ON)

LOW RESISTANCE

— BREAKDOWN

LEAKAGE CURRENT

e VOLTAGE
'\'• HIGH
RESISTANCE

AVALANCHE CURRENT
(LOW DYNAMIC RESISTANCE)

REVERSE BIAS
(O FF )

GENERAL VOLT-CURRENT CHARACTERISTIC

OF A DIODE
Figure 6.1

MAXIMUM +E
RATED
7
1 - DISSIPATION

Io•6A
/c
Io.5à

4t, IVCE

IC Io. OA
/CS

SLOPE Io. 2A
_
SAT v LOAD LINE
/ LOPE -L IB .

A,'
OFF . CONDITION
LB. 0
Io

Vs
VcE

GENERALIZED VOLT-CURRENT CHARACTERISTICS

FOR AN NPN TRANSISTOR
Figure 6.2

left by the line formed by the superposition of the base current lines with a slope of
1/1..1, and on the bottons by the In = O base current line. Thus point A is on one
boundary of the active region and point B is on the other.

140
 SWITCHING CHARACTERISTICS 6
Point A occurs at alow current, I0, and arelatively high voltage implying ahigh
resistance or "open" condition. In a properly designed circuit, 10 will approach lc°.
This current can be extremely small in amodern transistor of the silicon planar type.
The 2N914, for example, has a guaranteed maximum of 25 nano-amperes at 20V at
room temperature which implies a resistance of about 800 megohms. Typically the
value is about four times this or 3200 megohms. Germanium devices, however, have
appreciably higher leakage currents. The 2N404, for example, has aguaranteed maxi-
mum leakage of 5micro-amperes at 12 volts at room temperature implying aresistance
of only 2.4 megohms. In this one respect silicon is abetter choice for aswitch. It will
be seen, however, that other factors are important also.
Point B occurs at a relatively low voltage and high current point implying low
resistance. The ratio of V. to Ics in Figure 6.2 is often called the saturation resistance.
The 2N914, with 1c = 10 IB, has atypical value of V. = 0.35 volts at Ic = 200 ma
which is equivalent to about 1.75 ohms for rsAt. Actually rBAT is asomewhat mislead-
ing parameter as will be shown.
The high value of "off" resistance and low value of "on" resistance associated
with atransistor make the device valuable for switching applications on apar with the
diode. The transistor has one very important advantage over the diode in that its
state is easily controllable from the base lead. This is because a relatively small cur-
rent in the base can control alarge current in the collector. The diode can only be
switched by altering its bias. This switching "gain" makes the transistor amore versa-
tile device. By analogy, amechanical switch is to adiode what arelay is to atransistor.

STATIC PARAMETERS
The parameters of interest may be separated into static and transient groupings.
This is, of course, somewhat arbitrary in that the same parameters may influence both
aspects of device behavior, but it is convenient for purposes of discussion.

POWER
Examination of the load line of Figure 6.2 reveals that a considerable portion of
the line is in an area where the power dissipation is excessive. This is a common
characteristic of many switching circuits. Since the device is operated either "on"
(point B) or "off" (point A), the device will not dwell for any appreciable time in
the region of excessive power and therefore the average power will not be influenced
appreciably at moderate switching rates by this transient excursion into normally
forbidden regions. At high switching rates, however, the average power will definitely
be influenced by this condition.
Consider Figure 6.3 where atypical waveform has been linearized. It is assumed
periodic in form and the transitions are assumed to be ramp functions. The power
dissipated in the collector circuit is

1foT el ut

Evaluating this integral we have as aresult

P = Is Vs (AV Is — Vs )(2 toff 2Ttr tf) AI (3 toff + -Ejl)
3T
where
= E — Jo R — Vs
= Is — Io
T = tr tort tr -I- ton
If V8 = 0 and Io = 0 are assumed, then the power dissipated in one cycle is due

141
6 SWITCHING CHARACTERISTICS

only to the transient during switching and not to the power dissipated when fully
on or fully off. Under these conditions the power becomes

P = E Is pr +tfl
6 L T
If the on-time and off-time are reduced to zero, then T = tr tr and this represents
a limiting case for a given voltage and current swing. The transistor simply cannot
operate at ahigher repetition rate than this and still maintain afull swing. Fortunately,
most transistors have sufficiently high power handling capabilities that this is not a
serious problem for many applications. For example, if E = 6volts and I s = 10 milli-
amperes, only 10 milliwatts will be dissipated at this ultimate rate.
It is interesting to note that the limiting repetition rate is determined only by the
rise-time, t, and fall-time tf, of the device and circuit itself.
tOFF.ti r
+E

+E
E-I,R
_ TIME

(b) COLLECTOR VOLTAGE AS A FUNCTION

OF TIME

BO BASIC CIRCUIT

-CURRENT FALL TIME

10,•CURRENT OFF TIME

'CURRENT RISE TIME

top, 'CURRENT ON TIME

(c) COLLECTOR CURRENT AS A FUNCTION
OF TIME
T TIME OF ONE PERIOD

LINEARIZED SWITCH WAVEFORM

FOR POWER CALCULATIONS
Figure 6.3

For cases where power is very critical, the dissipation in the base should be added
to that of the collector. Normally this is quite small compared to the collector power
but, especially in heavily saturating circuitry, this is not necessarily so. The base
power is given by
Ps = Is v. —[Av. I. +Y. àib ][2tor, 2Tt, +1 + AVs Mb[ 34 " t'
3T
where
VB = base voltage when transistor is on
IB = base current when transistor is on
AVb = "on" base voltage minus "off" base voltage or the total change in base
voltage from on to off
AL, = change in base current from on to off
Ps = power dissipated in the base
and the switching times are the same as for the collector. If the device is actually
reverse biased in the off condition, then AVs and AL, will be larger than Vs and Is. All
equations are taken for the NPN configuration.
The limiting factor in transistor (or diode) power dissipation is the temperature
of the junction. In asense, the power dissipated is immaterial as long as the junction
temperature does not exceed its maximum rated value. Figure 6.4 is a typical curve
of the maximum permissible power as a function of ambient temperature. At room
temperature (25°C) the maximum rated power is P. This implies that at atempera-
ture of 25°C and Pwatts, the junction temperature is at its maximum permissible value.

142
 SWITCHING CHARACTERISTICS 6
At an ambient temperature TJ, the maximum power that may be dissipated is zero
which also implies that the junction temperature is at its maximum permissible value.
As amatter of fact, at each point along the sloping portion of the curve the junction
temperature is at its maximum value.
POWER

EFFECT OF A
NEAT SINK
•
•
•
•
•
AMBIENT
TEMPERATURE
25° C TA Tj

TYPICAL POWER DERATING CURVE

Figure 6.4

Two problems arise in practice. In the first case, the power dissipated in the tran-
sistor, PT, is known and it is desired to know the maximum ambient temperature, TA,
which may be permitted. This may be determined graphically as indicated by the
dotted lines starting at PTand TAin Figure 6.4 or the ratio
PT P
T., — TA— T1 25
may be used. If the ratio is used, then obviously

TA= T,— —
P T (Tl — 25)

The second case is the problem of determining the maximum permissible operating
power if the maximum ambient temperature is known. Again this may be determined
graphically, or using the ratio method we have
rT, — TA]
PT= P
— 25
The use of aheat sink can increase the power capability of atransistor considerably for
ambient temperatures below T,. It cannot, however, enable operation above that im-
posed by the junction. The dashed curve in Figure 6.4 shows the effect of aheat sink
on the power capability.
It sometimes happens that the manufacturer will specify two power ratings at
two different ambient temperatures. Since the shape of the derating curve is known,
this is generally sufficient to reconstruct the curve. For example, suppose the two
points given are (Pi, T, )and (P., T.) with T. > T1, P1 > P.. The power along the
sloping portion of the curve is given by
p = T2 •—• P2 T1 ) PI P2 )
T
T. — T2 — I1
The maximum junction temperature occurs when P = 0and hence
= P, T2 — P2 T1

— P.
while the maximum rated power occurs when T = 25° C.Hence
p m.. = (PIT
T: T1 ) 25 — P2 \
T. — Ti
To reconstruct the graph, power remains at P.., for all temperatures below 25° C.
From the 25° C point to T., astraight line is drawn which starts at (P..., 25) and ends
at (0, TJ).

143
6 SWITCHING CHARACTERISTICS

LEAKAGE CURRENT, lop

This current, along with the current gain, determines to alarge extent the minimum
off current, Io, as indicated in Figure 6.3(c). The physical nature of lc() is discussed
elsewhere. In this section only the manner in which it influences the circuit designer
will be discussed.
WM 10

600
MO 4
6

200

00
2

LO
muummu
so o.
040 ,
c.j 0.0
NJ
N
'A 20 0.2
—1
4
01 MMMOMMUMM
CC

2
CC .06
.04
ilemmummumm
o
4

.oz VOMMIIMMMEM
1
11 1.0 14
9 01
MMMUMMUM
0.6
0.4
.006
0.04
'1111 mom mu
02 .002

0.1 MI
MMUMMMEMMM
. 2
WO 0 +50 +100 +MO •200 4 6 S 10 12 14 16 16 20 22

TEMPERATURE -CENTIGRADE VcE N VOLTS

BEHAVIOR OF
WITH TEMPERATURE
AND VOLTAGE
Figure 6.5

Ico is defined as the dc collector current when the collector junction is reverse
biased and the emitter is open-circuited. Its value is determined by the voltage applied
and the temperature at which it is measured as is indicated in Figure 6.5. As the
curves indicate, Ico essentially varies exponentially with temperature and above the
"knee" of the voltage curve tends to follow an exponential variation with voltage.
The use of normalized values for Ico is simply a convenience. For example, at
25°C and 20V the normalized value of Ico is unity. If the specification sheet reads
Ico = 5ga at 25°C and 20 volts then all values along the ordinate should be multi-
plied by 5 micro-amperes. Thus at 100°C where the normalized value reads 60, the
actual value would be 60 x 5microamperes or 300 microamperes.
In order to eliminate the need to take voltage variation into account each time a
circuit is designed, Ico is almost always specified at a voltage near the maximum
rating of the transistor. The circuit designer then assumes Ico constant for voltages
less than this value (in some cases this is nearly true). This means that the designer
is nearly always conservative; the actual I cois always less than he has assumed and

therefore the design is on the "safe" side. The temperature which determines Ico is the
junction temperature of the device, not the ambient. If the basic measuring circuit is
studied, however, it is seen that the power dissipated in the transistor is the product of
Ico and E. Since Ico is very small the power is very small and the junction temperature
is essentially that of the ambient temperature. Many manufacturers label the Ico versus
temperature curve with ambient rather than junction temperature.
To the designer of switching circuits, Ico is important in that it determines how
close he may approach to atrue open circuit condition. As has been shown, this cur-
rent can be very small indeed. Unfortunately, another phenomena enters into this
consideration. Consider the circuit of Figure 6.6 in which the base lead is open rather

144
 SWITCHING CHARACTERISTICS 6

than the emitter. Leakage current leo flows across the reverse biased collector-to-base
diode junction as before. Now, however, this current cannot return to the battery
source unless it flows across the base-to-emitter diode junction. Since polarities are
such that this junction tends to be forward biased, this leakage current is essentially
indistinguishable from a base current supplied externally. The transistor therefore
amplifies this current to produce an additional current, 14. leo, in the collector. The
net result is that atotal collector current of (1± he.) leo appears.

t IC0 hfe
COLLECTOR

'CO hfeICO

I BASE

1-- (11-4,)Ico
•
EMITTER

E B= E CO

EFFECT OF TRANSISTOR GAIN ON LEAKAGE CURRENT

Figure 6.6

If afinite resistance is placed between the base and the emitter, some of the leo
current can be shunted through this resistor. This shunted portion of the leakage cur-
rent would not be amplified and therefore acollector current, Io, will flow such that
leo < Io < (1± he.) leo. This is the Io shown in Figure 6.3 and used in the power
calculations.
By reverse-biasing the base to emitter by approximately 0.2 volts, L can be made
to approach leo quite closely for germanium transistors. Because of the higher thresh-
olding effect of silicon, L approaches Ieo quite closely at zero bias. It is not always
desirable, however, to return the base to zero bias in some circuits and frequently Io is
specified for some specific forward bias on silicon units. Thus the 2N914 is specified for
amaximum current of 10 microamperes at acollector-to-emitter voltage of 20V, an
ambient temperature of 25°C and aforward bias of 0.25 volts. Io under these condi-
tions is only 25 nanoamperes maximum. Because germanium has such low base-emitter
voltages and because leakage current is very much greater than in silicon, it is not very
practical to apply this type of specification to germanium transistors.
If the base to emitter of atransistor is reverse biased, there will be aleakage cur-
rent, him, similar in every way to 'co except that it flows from emitter to base. Thus
to reverse bias atransistor, it is necessary to allow for leo and IEBO to flow out of the
base lead. When I.Ro is not specified it is usually assumed to be equal to leo.

CURRENT GAIN, hrE

The current gain of greatest interest to the designer of switching circuits is the
direct-current gain. This is defined as

LiFE
= lc

where h and Ie is the absolute value of the base current and collector current respec-
tively. The more commonly used parameter, he., is essentially the ratio of achange in
collector current for asmall change in base current.
The value of hre is usually measured at avoltage between collector and emitter
which is rather close to the saturation voltage as this represents a minimum value.
Speaking loosely, h5 is not avery strong function of collector-emitter voltage outside
of saturation. It is, however, arather strong function of junction temperature and of

145
6 SWITCHING CHARACTERISTICS

Ic-COLLECTOR CURRENT MA)

VARIATION OF h, WITH
TEMPERATURE AND CURRENT
Figure 6.7

collector current. Figure 6.7 is aset of typical curves for hFE as a function of I c for

the 2N914. Each curve is associated with adifferent temperature.

The most important feature is that over most of the current range, the gain
decreases with decreasing temperature. Obviously, this rule cannot be applied indis-
criminately. The reverse begins to be true beyond 10 milliamperes and 100°C. A
second feature of interest is that the gain has a definite maximum which may be
quite broad (at room temperature for example) or rather sharp (at 125°C). The
collector current at which this maximum occurs is afunction of the junction tempera-
ture. It follows that the selection of operating (on) current to be used should take
into consideration the temperature range over which the circuit will be expected
to operate.
It sometimes happens that adecreasing gain with increasing temperature is desira-
ble. Magnetic cores, for example, often require less drive at high temperatures than
at low. Generally, however, this characteristic cannot be controlled sufficiently well
to be useful.
hFE should not be confused with forced current gain. Consider Figure 6.2. When
Ic = E/R, VCE = 0 and therefore all collector bias is removed from the transistor.
Actually this cannot quite happen. As shown by point B, further transistor action
ceases at avoltage V. (which is quite small). Hence the collector current is actually
limited to I cs = (E — V. ) /R. It is, however, quite possible to force more base current
than necessary for Ic = Ics. This, of course, cannot change I c appreciably. The ratio

of Ics to Is when Is > ICS/hFE is called the forced current gain and it is always less
than the natural gain hFE. The forced current gain is sometimes referred to simply as
the circuit current ratio.

COLLECTOR SATURATION VOLTAGE, VCE (SAT)

The collector saturation voltage, VCE (SAT), which has been abbreviated to V. in
Figure 6.2 and in the equations for power, is the parameter that effectively limits how
closely the transistor may approximate aclosed switch. Figure 6.8 contains two curves
which show how this parameter varies with the circuit current ratio, collector current,
and temperature.

146
 SWITCHING CHARACTERISTICS 6

I./

100 MA
)6 I
BASE COLLECTOR SATURATION VOLTAGE
VERSUS CIRCUIT CURRENT RATIO
2N914
TA • 25*C
1.5

50 MA
k4

20 MA ,
10 MA

1.3

e lMA

1.2
---"'"----e..-----........-

DI

n
10 20 30 40 50
1c/1,3-CIRCUIT CURRENT RATIO (A)

0.5 I 7

VcE I(SAT ) VS TA

IC -IOIB
2N9I 4
0.4 lc .100MA

..--

-o
° 0.3
Ic.50MA

1
lc =20MA
60.2 lc 10MA

Ic .1MA

0.1

-55 -15 +25 +65 +105 +145 +185

TA -* C

VARIATIONS IN V' %T WITH TEMPERATURE,

COLLECTOR CURRENT, AND FORCED GAIN
Figure 6.8

In the first set of curves the temperature is held constant while the circuit current
ratio is increased (or In decreased )and the saturation voltage changes linearly. The fact
that the saturation voltage changes with the circuit current ratio makes the concept
of r(SAT) as the reciprocal of the slope of the characteristic curve below V. in Figure 6.2

147
6 SWITCHING CHARACTERISTICS

rather awkward. This is probably the reason r(SAT) has never been widely accepted.
The two curves of Figure 6.8 represent the best method yet devised to describe satura-
tion voltage over awide range of operating conditions.
The second of the two sets of curves indicate that temperature is not aparticularly
strong influence and that the saturation voltage increases with increasing temperature.
This depends very much on the device being used. In some devices the saturation
voltage is almost completely independent of temperature while in others the tempera-
ture coefficient can be negative over all or part of the temperature range.

BASE EMITTER SATURATION VOLTAGE

VERSUS CIRCUIT CURRENT RATIO
2N9I4
T.25.0

tî 0.90
100 MA

50 MA
0.80
UI 20MA
(/)
4
10MA

0.70
Ic.I MA

0.60
o 10 20 50 40 50
I,/ CIRCUIT CURRENT RATIO (A)

s. a
......,„_ VBE (SAT VS T
A
.1 ...........................____ I
e cn,
2N9I4

3 I,•100MA
3
1' )
o
0
h
7 7.c .50PAA

1
06 s i.c.20MA
PA A
o5
I
I,- 1MA
o4

-55 -15 +25 + 65 + 105 +145 +185

(6)

VARIATIONS IN Vni.(1, WITH OPERATING CONDITIONS

Figure 6.9

148
 SWITCHING CHARACTERISTICS 6
BASE- EMITTER SATURATION VOLTAGE,VR E (SAT)

A set of curves similar to the curves for collector saturation are shown in Figure
6.9 for the 2N914. The most characteristic feature is that the slopes of these curves are
opposite to those shown in Figure 6.8. The temperature coefficient is negative and
varies little over the entire range. A common rule of thumb is to allow 2 millivolts
change per degree centigrade in the base-emitter voltage. This rule is surprisingly
good, even for germanium at moderate current levels. At higher current levels this
value tends to be too large.

TRANSIENT RESPONSE CHARACTERISTICS

The factors which influence the transient response of the transistor are basically
associated with the diffusion time of the carriers across the base region, the effect of
capacitances due to the collector-base and base-emitter junctions, the associated para-
sitic capacitances between leads and from case to leads and, just as important, the
operating conditions of the circuit. In predicting transient response it is convenient to
think of the turn-on delay time, td, the current rise time, t,, the storage or turn-off
delay time, t., and the current fall time, t,, as dependent variables whose value depends
upon the operating conditions of the device as well as the capacitances and diffusion
parameters. These latter are also affected by the operating conditions of the circuit.
It follows that the calculations of the time intervals (td, t t., and t, )can be very
complex.

DEFINITION OF TIME INTERVALS AND CURRENTS

The time intervals are defined in Figure 6.10. This set of definitions has become
almost universally accepted for measurements and therefore requires no further expla-
nation beyond pointing out that the 10% and 90% points of the collector waveform
are taken as the points at which measurements are to be made. The collector wave-
form is, of course, the voltage from collector to emitter. For most calculations we
shall use collector current rather than collector voltage as the reference thereby
avoiding some difficulty with what is meant by rise-time, t,. In Figure 6.10(c), the
voltage is falling during t, but, of course, this is due to the fact that the current is
increasing (or rising )during this interval.

TURN-ON DELAY, t
a

Consider the circuit of Figure 6.10(a) with the switch in its open position. Under
static conditions there exists only a —10V source connected to the base, B, through
the 100 ohm resistor in series with RR. Thus the base must be reverse biased at —10V,
plus avery slight voltage drop due to leakage currents, and the transistor is off. The
collector, C, must, therefore, be at +10V minus avery small voltage due to collector
leakage, Io, and the total voltage between collector and base is +20 volts. Any capaci-
tance between base and collector is, therefore, charged to 20 volts, and any capacitance
between base and emitter must be charged to 10 volts as shown in Figure 6.11(a).
Since the transistor is off, it is effectively not in the circuit.
At the instant of switch closure, the voltage at the base cannot change immedi-
ately because of the capacitances associated with the base. This means that effectively
20 volts has been placed across Rn thus making Is = 1 ma as indicated in Figure
6.11( b). Until the base-emitter voltage vanishes, there is no way the transistor can
turn-on. As current continues to flow, the transistor base-to-emitter becomes forward
biased and the transistor begins to turn-on. This occurs when VBE approaches about
+0.1 volt for germanium and +0.5 volts for silicon. Beyond this point the base-emitter
diode acts as aclamp so that the voltage cannot continue to rise at the base. Since
0.5 volts is very small compared to 10 volts, the final base-current will be about 0.5

149
6 SWITCHING CHARACTERISTICS

+10V (A) TYPICAL CIRCUIT

I9 102 0.5 mo
Ic. 10 ma
Ici < hFE
491

o
j-
E1 +10V (B) WAVEFORM GENERATED
AT A BY SWITCH

E2.-10V

(C) WAVEFORM AT B
SHOWING FORWARD BIAS
ON BASE DURING
SATURATION

+10V
—-10% (D)COLLECTOR WAVEFORM
SHOWING STANDARD
—etch DEFINITIONS OF
--90%
- RESPONSE TIMES
—Wt. 44
1—•1 1/ 14-
--. TIME

TRANSIENT RESPONSE
Figure 6.10

ma as indicated in Figure 6.11(c ).

The time required to reach the threshold of transistor turn-on may be calculated,
assuming CEand Cc are simple capacitances whose value is known. This time interval
is not td since the collector current has not reached its ten percent point at this time.
Calling this time interval td' and realizing that td is the sum of td' plus asmall portion
of the rise time, At„ we have, for this particular circuit
td = td' + At,
Due to the fact that the circuit of Figure 6.11 gives rise to two time constants, it
is not a simple matter to solve explicitly for td'. For this reason it is customary to
make some reasonable approximation for ta'. The change in voltage at the base is
AVb = 10V. Assuming that the collector voltage does not change, the change in
charge, QcE, on Cc is QCE = CC àV b and the change in charge on QEis CEàVb. The
total charge which has flowed into both capacitors is thus (Cc + CE) AVb. Since this
occurred in atime td', then the average current must have been

Ig(.,.) = (CC -I- CE)

ta'
The average current is very nearly given by the arithmetic mean of the initial current
and final current.
IB(avg ) [IE(o) ±19 (te')]
2
This gives 0.75 ma for 1E (,‘„, )although in this example the true value would be closer
to 0.7 ma. Using this value (0.75 ma) for we have

td' (Cc + CE)[. AVb = 13.3 (Cc + CE) X 103

1B (av g.)

150
 SWITCHING CHARACTERISTICS 6
If 0.7 ma (obtained by assuming an exponential decay from 1 to 0.5 ma and aver-
aging) had been used, td' would have been 14.3 (Cc -I- CR) xlie
and the error would
be about seven percent.

+10V

VOLTAGE TO GROUND

A: -10V
13: -10V
C: +10V

-I0V

(a) STEADY-STATE 'OFF' CONDITION WITH ALL CURRENTS

DECAYED TO ZERO.
+IOV

VOLTAGE TO GROUND
RL
1K
A: +10V

20 V B: -10V
C: +10V
A

+ Re2OK • VA -Ve 10-(-10). IMA

+ 10V Re 20K
2004, loon
MA -
-10V

(b) CURRENT FLOW AT THE INSTANT OF SWITCH CLOSURE.

+10V

VOLTAGE TO GROUND

+ 10V
13: OV
C: +10V

ie - 181. Yê •A •0.5 MA
Re 20

(c) CURRENT FLOW AT THE THRESHOLD 'TURN-ON'

PHYSICAL REASONS FOR td

Figure 6.11

COLLECTOR AND EMITTER TRANSITION CAPACITANCES

Although these calculations are quite simple and give reasonably good results,
there is asignificant drawback inherent in this method. This has to do with the nature
of the capacitances involved. Consider Figure 6.12 where the capacitances Cc and CE
are depicted as functions of voltage. A swing of ten volts, for example, causes Cc to
change from approximately 4picofarads at 10 volts to 6 picofarads at 0.1 volts. It is
thus rather difficult to state precisely what value of Cc to use in calculating td'.
It is frequently mentioned in the literature that Cc is afunction of voltage. If this
function is known, then the total change in charge on the capacitor for a change in
voltage from V, to V2 is

QcD =f Cc (V) dV
V,

151
6 SWITCHING CHARACTERISTICS

This value for the change in charge for achange in voltage V. — V, = AV may then
be used to calculate an equivalent linear capacitance, Cc. Thus

Ec — = CCD
eiV
and this value may then be used. Unfortunately, this evaluation requires aknowledge
of the proper analytical expression for Ce as a function of Ve.

5
CAPACITANCE (PF)

4
Cc let:»

3 Ce (lc 0)

COLLECTOR OUTPUT CAPACITANCE VS COLLECTOR —BASE VOLTAGE

2— EMITTER TRANSITION CAPACITANCE VS EMITTER —BASE VOLTAGE —
2N914
TA .25°C
f.350kc

1
O
0.1 10 100
REVERSE BIAS VOLTAGE (VOLTS)

Figure 6.12

It is generally easier and simpler to use the graph of Figure 6.12 directly. Initially
VCBwas at 20V as indicated in Figure 6.11. Using the graph of Figure 6.12, it can
be seen that Cc is about 3.6 picofarads at this voltage. This implies that the charge,
Qr = C VCR is 72 picocoulombs. At the edge of turn-on, VeE is 10 volts (Figure
6.11(c) )and Cc is 4 picofarads (Figure 6.12) giving Qr = 40 picocoulombs. Since
-
1Qc = QCD = 72 — 40 = 32 picocoulombs, we have

CCD = e= àQc — 32 = 3.2 picofarads

10
and the effective linear capacitance is actually less than the capacitance at each point.
Using the minimum capacitance (at 20V )in this case would be somewhat conservative.
The same process may be used for CEexcept that in this case the voltage across
CE is reduced to zero (or even slightly reversed) as indicated in Figure 6.11(c).
Thus the total charge to be removed is determined only by the charge at the 10 volt
point. The net result is that the time interval, td', is modified as

ta' = (Cc EE) W 1, = (cep + "

vb
.v.
.. 114 (,v g
Supposing that CEis 2 picofarads at 10 volts for some particular transistor (not
a 2N914), then .1(2. will be 20 picocoulombs for a 10-volt change from 10 volts to
zero volts. Hence the effective capacity, CE, is 2 pf. Using the previous estimate td' =
14.3 CCC
- X me we have td' = 14.3 (5.2) x 10 = 74.4 nanoseconds.

FORWARD BASE CURRENT, 1E1

When the circuit of Figure 6.10(a) reaches the edge of transistor turn-on, as indi-
cated in Figure 6.11(c), the base-emitter diode acts as a clamp to hold the base volt-

152
 SWITCHING CHARACTERISTICS 6

age near ground. Under these conditions the value of I Rremains constant throughout
the rise time and "on" time of the device. This constant current is denoted as IRI and
in applications where In is not constant it is usually understood that IRl is some sort
of average or effective value in the formulas. It is frequently referred to as the forward
base current.

GAIN BANDWIDTH PRODUCT

The common base current gain, generally denoted as a, is afunction of frequency.
One of the better approximations, obtained by solving the diffusion equation (with
some simplifying assumptions regarding boundary conditions) is

a= Sech [a VI-I- jeir]

where a= W/L << 1, W= base width, L = diffusion length of carriers in the base,
and T is the carrier life time. Such aformula is rather awkward to use and an approxi-
mation occasionally suggested is

a =
1 j

where a,, is the low frequency gain, co,, is the 'alpha cutoff' frequency in radians per
second and determined as that frequency where the magnitude of ais —3 db, or 0.707,
of its low frequency value, and kis an empirically determined constant (about 0.2 -0.4)
for aparticular device. Even this formula, however, is somewhat awkward to use and
thus the most common approximation is simply

a= a.
1+

This final approximation has the same magnitude at all frequencies as the previous
estimate but the predicted phase can be in considerable error.
As ca/co,, becomes large compared to 1, the magnitude of a becomes a°
(cualw ), or, rearranging, we have
culal a. co« = tor = 2w fT
That is, the product of the frequency w and the magnitude of the gain at this fre-
quency is approximately equal to the product of the low frequency gain and the
alpha cutoff frequency, both of which are constants of the device. The product is
termed the gain-bandwidth product and may be given in terms of radians/second
(an) or cycles/second (fT) and is widely used as a figure-of-merit for transistors.
The small-signal common-emitter gain, /3, is defined as

= a P.
(1 — a) 1-I- L)
T

where 130 = ao/( 1— ). The frequency at which the magnitude of pis —3 db down
(or 0.707 of) from go occurs when w = wT/{3, and is usually referred to as the "beta
cutoff frequency." It can be seen that the beta cutoff frequency is considerably lower
than the alpha cutoff frequency. As w becomes larger than cuT/13., the magnitude of
{3 rapidly approaches

1131 P. (13%) —
or

153
6 SWITCHING CHARACTERISTICS

Thus the gain-bandwidth product is the same in the common-emitter configuration as

it is in the common-base configuration.
For switching applications it is usually assumed that 13 is approximately hFE. This
is due to the fact that p (as a small-signal parameter) changes at different operating
points and hFE is a sort of average value over the entire switching range. Thus the
frequency dependent relation for IRand Ir becomes
hFE Is
le =
1 jhFE
or, rewriting,
WT T
WIC-I- = 0,1* I
R
hFE

Examining this last statement, it can be seen that this corresponds to the sinusoidal
solution of the differential equation
d • oil, •
—
dt (le) (lc) = coTie
hFE

I= iR+ lc )

. V _ CV q
=i
RR
R•= CR T

q CV T. RC I = CONSTANT

0dvt _
C—
d c (CV).
d
d t (iRR) _ c
cl
It e
ddqt

(a) BASIC CIRCUIT AND FUNDAMENTAL RELATIONS

DIFFERENTIAL SOLUTION

CURRENT: r.r°18-+i R
dt
= I (1 -E -1/7 )

dv v
VOLTAG E: I =C + v.IR (I- ertil)

dq q
CHARGE: q

(b) TIME SOLUTION FOR BASIC CONCEPTS OF

CHARGE ,VOLTAGE , AND CURRENT

DEVELOPMENT OF EQUIVALENT CONCEPTS

Figure 6.13

154
 SWITCHING CHARACTERISTICS 6
The solution for i„ if ih = I
III (a constant), is very simply
( —coTt )
i, = hEE hi 1 — E hFE

which is awell known form given by simple RC circuits. Indeed, if the very simple
circuit of Figure 6.13 is considered, we have several possible forms for expressing the
basic differential equation. Provided
hVE
= -COT •

= hFE 1111 = Ic

the circuit of Figure 6.13 exactly represents the equivalent circuit for the approximate
transistor relation
hp': In
Ic = co
1± j E

RC.fi

(a) SIMPLE EQUIVALENT CIRCUIT WITH

CHARGE IN COLLECTOR

IB

(b) SIMPLE EQUIVALENT CIRCUIT WITH

CHARGE REFERRED TO BASE

SIMPLE EQUIVALENT CIRCUIT WITH

CHARGE REFERRED TO BASE
Figure 6.14

If acircuit is desired which will distinguish I. and hrs this can be done by using a
current generator as shown in Figure 6.14.
The current solution of Figure 6.13 indicates that in is directly equivalent to the
collector current, Ic. The voltage and the charge are related to the collector current
by constants. Thus

V — IR or Ic —

Q= I
c T or Ic =

It is immaterial at this point from what viewpoint (current, voltage, or charge)

the device is viewed, as the viewpoints can be shown to be equivalent. Thus the
transistor may be considered as: acurrent-controlled device, in which the current in

155
6 SWITCHING CHARACTERISTICS

the base controls the collector current; avoltage-controlled device in which the junc-
tion voltages are considered the controlling factors; or a charge-controlled device in
which the charge within the transistor controls the device (and base current is needed
only to replenish charge which has leaked' away) —just as one may consider the simple
circuit of Figure 6.13 as having ix controlled by the input current I, or controlled by
the voltage across the capacitor, or controlled by the charge in the capacitor. As devel-
oped, however, the charge concept appears to offer some slight advantage in reducing
the number of required parameters needed to describe switching behavior, as well
as providing amental concept of the device which can aid intuition.

CHARGE CONTROL CONCEPTS

The emitter and collector junctions of a transistor when in the cutoff condition
are reversed biased; in this condition only leakage currents flow across the junctions,
the base charge is negligible, and the junction depletion layers are wide because of
the reverse bias applied as shown in Figure 6.15( a). In Figure 6.10 (a), this condition
exists in the transistor when the switch is open; VBE is equal to —10 volts and VCB is
equal to 20 volts. Immediately after the switch is closed, no collector current flows
since the emitter junction is reverse biased, thus the initial base current which flows
supplies charge to the emitter and collector junction depletion layers and soon causes
the emitter junction to become forward biased and begin emitting as shown in Figure
6.15( b). The quantity of charge which has been supplied to the emitter junction
depletion region is called QE and is afunction of the reverse bias voltage which was
applied to the junction prior to the application of the turn-on signal. The charge
supplied to the collector depletion region during this time is denoted QED and is a
function of the reverse bias on the emitter, and the collector supply voltage being
sweched. Looking again at Figure 6.10( a), the condition illustrated in Figure 6.15(b)
exists when VBE equals about 0.3 volts and VCB equals about 10 volts.
With the emitter junction now forward biased, the transistor enters the active
region. Collector current begins to flow and the voltage at the collector begins to drop
because of the presence of the collector load resistor, RL, shown in Figure 6.10(a).
During this time a gradient of charge is established in the base region of the tran-
sistor. The slope of this charge gradient is proportional to the collector current which
is flowing. If the base current supplied is greater than the rate of recombination of
charge in the base region, the gradient will continue to rise until an equilibrium
condition is reached. If equilibrium is reached before the collector junction is for-
ward biased, the transistor will not saturate. Since the recombination rate of charge
in the base is IE/hEE (or Is.), the collector current will rise to hFE In if the device
does not saturate. If, on the other hand, the collector current causes the collector-base
junction to become forward biased before equilibrium is reached, the device will
saturate. The existing condition within the transistor at the edge of saturation is
depicted in Figure 6.15(c). The time required to move from the edge of cutoff to the
edge of saturation is the rise time. Charge quantities involved are the base gradient of
charge Q.., which is afunction of collector current flowing, and Q E, which is afunction
of VCB. Qc is the charge required to cause the collector junction to narrow and becomes
forward biased. Since measurement of QD and QE is frequently accomplished by
measuring the two quantities together and then separating them as shown in Chapter
18, the sum of QDand Qc is frequently used and is called Qx*. At the edge of satura-
tion the Vim.; is about 0.3 volt and VED is 0volts if the bulk resistance of the collector
body is neglected. Since equilibrium is not established with respect to the base current,
charge in excess of that required to saturate the transistor is introduced into the base
region. The base gradient of charge remains constant since the collector current is at a
maximum for the circuit; the excess charge, Qxx, is afunction of the current which is

156
 SWITCHING CHARACTERISTICS 6
permitted to flow into the base in excess of that required to saturate the transistor.
This current is called IBx. Distribution of QBx in the transistor is shown in Figure
6.15(d).
In the alloy type transistor, essentially all of the stored charge is in the base region.
In devices where the collector bulk region has high minority carrier lifetime, excess
carriers can also be stored in the collector. These carriers reach the collector from the
base since the collector junction is now forward biased and base majority carriers are
free to flow into the collector region during saturation. These stored carriers have no
effect during turn-on time. Storage time, however, is the time required to remove these
stored carriers as well as those stored in the base. Both the mesa and planar devices

EMITTER I COLLECTOR
JUNCTION JUNCTION

1
.EMITTER
BASE
„,, COLLECTOR
.

DEPLETION REGIONS I
(A) TRANSISTOR CUTOFF-WIDE DEPLETION REGIONS

!OE SUPPLIED

SUPPL ED

, NARROW DEPLET I
ON REG I
ONS I

(B) EDGE OF CUTOFF CONDITION

CI , SUPPLIED

'NARROW DEPLETION REGIONS I

(C) EDGE OF SATURATION CONDITION

(D) TRANSISTOR SATURATED

CHARGE DISTRIBUTION IN TRANSISTOR DURING SWITCHING

Figure 6.15

157
6 SWITCHING CHARACTERISTICS

exhibit collector minority carrier storage. The epitaxial process used in General Electric
transistors 2N781, 2N914, 2N994 and the 2N2193 minimizes collector storage while
not adversely effecting collector breakdown voltage or other desirable characteristics
of the transistor. Incidentally, it may be possible to meet the electrical specification of
a given registration without using epitaxial techniques. Component manufacturer's
data should be consulted for process information.
From the various charge quantities introduced, anumber of time constants can be
described that relate the charge quantities to the currents flowing; these time constants
are defined in the following equations
T 7913
— IRS

Te 911
— I
CS

Db
IBX
T. is called the active region lifetime, r, is called the collector time constant, and
Tb is the effective lifetime in the saturated region. In some literature Tb has been called
r.. Where collector minority carrier storage exists the measurement method for Tb
shown in Chapter 18 does not only measure QBx/IBx but includes much of the collec-
tor stored charge; as such, this parameter is still avaluable tool in rating the storage
characteristics of various transistors since alow Tb value indicates alow storage time.
The time constants defined are constant over large regions of device usage and are
normally specified as device constants.
To determine the transient response using the charge approach, the required charge
for the time in question is divided by the current available to supply that charge; thus,
the basic equations are

t, -
QB Qc Te I
C Qc
I
B,
t. = — Tb -1112`- and
IR. — IR2
QB± QC re Iv Qc
— ¡DI —

The simplicity of these equations is readily seen. Their accuracy is dependent upon
the assumption made in the equations that hi and I B2 truly are constant. Refinements
in these equations arise from the fact that some of the charge in the base recombines
on its own and must he accounted for in determining transient speed.

APPLICATION OF STORED CHARGE CONCEPTS

In calculating that portion of the delay time before the current begins to rise td', it
was found necessary to employ the approximation

QE
T QC
AB (avg. ) D
ta =

in order to obtain a reasonably simple solution. Qi.; is essentially the total charge
which must be removed from the base emitter junction to turn on the device. QC»,
however, is but a portion of the total charge stored at the base collector junction.
During actual rise time, the remaining portion of this charge must be removed. Letting
QTC be the total charge due to this capacitive effect, it is wise to separate QTe into
two components, Q8D and Qc. QC!) is then the charge removed during td' and Qc is

158
 SWITCHING CHARACTERISTICS 6
the charge removed during the rise time. It is rather obvious that the calculation for
ta' lends itself nicely to charge concepts.

RISE- TIME,t,
Basically, only one mathematical relationship is involved in the remaining discus-
sion. This will be briefly examined before dealing with the full solutions.
The equation,

fo in dt =f t dr) dt + Jo
o dt o Ts
dt,

which may also be written in differential form as

41:9L1± 91.3
dt T.'
is the fundamental governing equation in most practical approaches for determining
the switching time intervals. This equation represents afirst order approximation and
should never be regarded as more than this.
The first term on the right hand side is simply the rate of change of OBwith time
(coulombs per second )and essentially represents the capacitive element in the equiva-
lent circuit. The second term (often called the recombination term) is associated with
resistance in the equivalent circuit and accounts for loss (leakage) of charge with
time through the shunt resistance. T. is the RC time constant of the equivalent circuit
and is often referred to as the recombination time constant. Initially, QBand the collec-
tor current are zero. At the end of the rise-time, QBand the collector current are at
their final value. Two cases immediately present themselves. In the first case, the tran-
sistor does not enter saturation and the collector current stabilizes at Ic =
while in the second case the transistor enters saturation and the collector current is
'Cs <h5 I B1 where the sin the subscript merely indicates saturation. Ins, defined as
Ics/hFE, is merely that base current which is just sufficient to bring the transistor to the
edge of saturation. Thus I B, = In. + lux where lux is the excess base drive above that
necessary to saturate the device.
As indicated in Figure 6.14 ( b), QBis related to Ic by the constant (ÚT. Thus the
final value of QBin the unsaturated case is QB= Ic/WT = I cT e while in the saturating

case the final value for OBis given by OR= I CS/COT = ICS re. Since lc = hFE In, and
les = hFE I BA, then QBis related to In or Inn as well. Thus QB= hFle re = I BI T.,.
For In = where In is aconstant, the solution to the basic equation is
t
OB= As " B
where A and B are arbitrary constants determined by the boundary conditions. For
example, at t= 0we expect QBto be zero if the device is off and ready to be turned
on. The above equations immediately reduce to A ± B = 0at t= O. At t= oo, the
exponentional term has vanished and hence QBmust be at its final value, Qr. This
makes B = QFand we have
—t —t \
QB= —QF€ QF= QF(1 — e
Naturally, if the device does not saturate, Qs. = TaIBI and we then have

OB = T. hi (i -

This equation may be solved for tas follows,

t
r r. ln T. I
BI
I
B1 QB( t
To find the rise time it is necessary to determine t., the time at which OSreaches 0.1

159
6 SWITCHING CHARACTERISTICS

T. hiand th, the time at which QB reaches 0.9 T. Igt. The rise time from the 10 to 90
percent points is simply th — t, and we have
T. LI T. Ii
t= r,, ln T. ln = In 9= 2.2 ra
r. In, — 0.9 T. T. Igl 0.1 T. hi
The rise time from zero to 90 percent is simply t, = r. In 10 2.3 r,.. Thus the
turn-on time is

To.; = Qe° 2.3 T.

ia
and the total turn on delay is given by

ta = Q: Qe"-
I-0.1 T.
Ig (aV g
For the saturating case amore complicated situation arises. Qn is limited to QBB, the
charge required to just reach the edge of saturation. QBB, of course, is simply equal to
T. IBS and hence if the 10 to 90 percent points of r. Ins are taken, the solution becomes
t, = r. In — 0.1 IBS
Igl — 0.9 I'm
Frequently approximations are made in solving for tin order to simplify the mathe-
matics. For example, for t«r,, dQB/dt is the only factor of importance and we have
¡in dQ B AQB
dt àt
or
àt = .1Q
r
B— Ogg
1r
_ IRS
Igt BI — 1.* ¡Bi
where At is simply the time interval of interest and AQ the total change in charge.
For At = t,, QB must go from zero to QBB and hence AQ0 = QBS and t, QBB/IBI.
As can be seen from Figure 6.16, for tappreciably less than Tn, it is necessary that
QBS be appreciably less than r. In,. This occurs, of course, in the saturating case.

Tr„
OB . e

T -
/1
8S EXPONENTIAL CURVE
FE

hFEI -"7" 51

OB e BS i 08 IB ( E.- " ,1 )

- -
h FE I BS _
hFEIB
1,

r,„
TIME

APPROXIMATE SOLUTION FOR RISE -

TIME
Figure 6.16

A second approximation, which attempts to correct somewhat for the recombina-

tion term is sometimes used. Essentially, the original differential equation is written as

— —
dt r.
The final value of QB is Qgg = IBS t,. Assuming that QB is roughly linear with

160
 SWITCHING CHARACTERISTICS 6
time, we have Qs = I
BS tfor 0< t< tr. It follows that
ORS
dt =f d QB = QBS = I
BI tr hs =[ — 1:211s 1 tr
f t,
dt o 2r. 2r,
or
tr =
OBS OHS T. IRS
I
BI
O RS
2r.
IBI 0.5 I
I»; I
B 0.5 'FIR

Although the logarithmetic solution is the exact solution for the basic equation while
these last two are only approximate solutions, it should be kept in mind that the basic
equation itself is only an approximation.
The three solutions obtained for t, should be compared.

t, (0to 100% ) (6a)

tr r. (0 to 100% ) (6b)
IB— 0.5 Is

T. ln [ Ins (10% to 90% ) (6c)

To alter (6a and 6b) to read from 10% to 90% we need only multiply by the factor
0.8. Thus

0.8 T. I
IB.S
B
(6d)

tr 0.8 r,, (6e)

Is — 0.5 I
BS
Figure 6.17 gives a comparison of the predicted rise-time for each of the three
approximations. The steepness of the curve below Is/Iss= 3 indicates that none of the
equations will be in good agreement, whereas above Is/Is,; = 3 all the curves tend to
converge.

26

2.4

2.2 I
r -o ,
115
=n ,
1 1131

I 1-0.9 ±13 -
2.0 1 131

18

1.6

=0.8
1.4
r /I
t

1.2
COMPARISON
RATIO

OF CALCULATED
SWITCHING TIME 0.8 - 18 1
FOR SEVERAL 0.8[
Ie;
APPROXIMATIONS 0 6-

Figure 6.17 a4

02-

0 1 2 3 4 5 6 7 5 9 10

RATIO IBI /IB s

161
6 SWITCHING CHARACTERISTICS

COMPLETE SOLUTIONS
The simple solutions obtained for rise time in the previous section are not really
adequate in that two very important factors have been ignored. The most important
of these two remaining factors is the effect of Ce on the rise and fall times. During
either of these two intervals, the device is passing through the active region and Cc
acts as afeedback capacitor from output to input. Hence the effects produced by this
parameter are much greater than one would assume from its capacitive value alone.
To modify the basic charge equation, it is only necessary to realize that at satura-
tion all charge is effectively removed from Cc due to the fact that the collector voltage
approaches very closely that of the base. Thus acharge Qc = Cc dV must be removed
during the rise-time. (Note that Ce is no longer the sanie as CeB, as the base voltage
is not changing very much during this interval.) Thus the modified charge equation
becomes
dQl! QB dQ.
dt + — dt

IB

(a) Qc 24 -CcVc

hFEQB dQc hFEQ5

b) To df =
d08
C-
te,
„ dOc d E, hFE QB _ CRLhFE
"
—dt —
dt RL 7a
dt

EFFECT OF C ON SWITCHING WITH

SIMPLIFYING ASSUMPTIONS
Figure 6.18

An equivalent circuit is given in Figure 6.18. A word of caution is in order here.

The base voltage is not changing appreciably during the rise-time and this circuit
indicates that it should. Any derivations, therefore, should assume that only Ve is
effectively present across Cc while still permitting Ce to rob base current.
By using the relationships shown in Figure 6.18, the equation may be rearranged
as follows:
_ dQB Qn
_1
1± [h" Tat R1,1 dt hFE R..

The solution to this equation is, after applying the necessary boundary values,

— Ta 11FE Ec Rt.)
QB I
B1 Ta (1 — E
which indicates that the effective time constant has been increased from Ta to
T. hFE cRL. The effect of chas been multiplied by hFE. Thus the simple formulas

162
 SWITCHING CHARACTERISTICS 6
previously given are still valid provided the time constant is replaced with the new
value.
We now consider the last effect, namely the effect of a shunt capacitance across
the load. Figure 6.19 is an equivalent circuit of this condition. The basic charge
equation is simply enlarged to include the charge Qr., which must be removed from
CI, during the switching interval.

çe e9-12
dt r, dt dt
By inspection, it is evident that Qr. will increase the effective time constant in amanner
analogous to the increase in the effective time-constant with Qc. There will, however,
be some interaction between C -. and CI, and it is obvious that an exact solution to this

equation will involve several time constants and, indeed, be transcendental in nature.
It is best, therefore, to make some approximations in order to achieve asolution which
will be solvable for time.
The component of current flowing through cis very much less effective in the
collector circuit than it is in the base circuit where it robs some of the driving current
available for turning on the device. From the previous discussion where Cc alone was
considered, it was found that the current taken by Ue was
d(h eR,.hrE d
dt T. dt

18 hFE

• 11 — • Vc

TCL
tdQL
dt d01 f
dt »co hFE.B =—
C
Yo =RC 9 QB yo
0 T CLRL
r
(a) EQUIVALENT CIRCUIT INCLUDING Cc AND CL

IB

c)

-
-CL
dQ, d
dO
1B j.
RLhrE

I
dt C
QLRL
L

dt GB hFEOB

RC

(b) REDUCED EQUIVALENT CIRCUIT

IB

OLRLd
A i tI FE CG R I.d1 dQB RL

To dt 9 To dt e dt * Q8 hFE Q8
r
o

•
(c) APPROXIMATION FOR OBTAINING A USEFUL SOLUTION

APPROXIMATE SOLUTION TO THE

COMPLETE SWITCH PROBLEM
Figure 6.19

163
6 SWITCHING CHARACTERISTICS

Figure 6.19( b)is asimplification of Figure 6.19(a) in that chas been removed
and an equivalent capacitance placed in the base circuit to account for this effect.
The collector circuit contains two components of current which are related by
hrs.: QB_ dQL 4. Q1,
T. dt CL
After steady state conditions are achieved, the capacitive current disappears and we
obtain
hFF: 1Olt Of.
T. — C1. Rr.
Or

hFF CIRI
AOL = -
1Q8

where AQL is the change in the charge on CLand 1OB is the change in the charge on
C in the base circuit. Since these changes are essentially complete in a time interval
At, an average or equivalent steady current, ici., must have been supplied which may
be written
= 111,1, CIRI —
= AQL
r. At At
and must correspond to a component of the base current, im.. With in,. = iEL/hFE,
we have
CIRI 10µ 1 1OI.
At hrE At
This base current must act to rob some of the drive current available for driving the
load during the switching interval only. If the approximations
AQR dOK
1t dt
AQL cl Oc
Lt = dt
are used, then one may write
Cr FIL dQB
iBL (ti
r. dt
Thus the equivalent circuit of Figure 6.19( b) may be further reduced to that of
Figure 6.19(c). It is now possible to write the expanded charge equation as

= ddt
Qi! Olt OFE T RL) dOR CLRI. ) 49,3
7" . dt r. dt
which has as the general solution

On = 'RI T.( 1— ;+i RL+ CLRL)

in which it is immediately seen that the time constant is r0 hFE è
-E CLRL and
the time solution from the 10 to 90 percent points would be
I
RI — 1Li
tr = rR ln [— —
— 0.9 IDS
where
TR = T. ± hFE éC
. RL CL R.

= hFE [ 1 CLRL] — II FL THL

_
IdT nFE
if T./hFE = 1/WT. The constant TRE insert is called the rise-time constant by J. A.
Ekiss and C. D. Simmons."> The development here, while not quite identical to the

164
 SWITCHING CHARACTERISTICS 6
work of Simmons and Ekiss, nevertheless has the same result.
Although the time constant r, has been treated as a constant, in general T. does
vary somewhat with operating conditions. Since r, is taken as hrs/ter and both 1150
and ter are functions of operating point, this is only reasonable. The assumption of
constancy is frequently justified in that the variation of r. is less than either hss or ter
alone, the variation with operating point is frequently less than the variation from unit
to unit in many types, and the variation is frequently masked to some extent by hsE Cc
which can have an appreciable influence on rise-time.

Storage-Ti me, t.
Of all the switching time intervals, storage-time has generally been the most
difficult to predict. No one has, as yet, determined asufficiently general approach for
calculating storage-time with reasonable accuracy, and with a reasonably (useful)
simple solution that will apply to any junction transistor regardless of type or geometry.
The stored charge approach has a simple solution but is reasonably accurate for a
limited number of transistor processes.

Reverse Drive, I BS
During the storage interval of the transistor, the base voltage remains virtually at
the same value as during the "on" interval. Examination of Figure 6.10( c), for exam-
ple, indicates that immediately after the switch is opened, the base to emitter remains
slightly forward biased. Since point A is no longer held at +10V, this implies acurrent
flow from base, through RB and the 100n resistor, to the —10V supply. This current,
whose magnitude is about 0.5 milliamperes, must flow from the base of the transistor
and is usually referred to as Ins. It represents areverse current from the base to shut
the device off. The symbol In represents magnitude only and IB = —Ins during this
interval.

Circuit Conditions and Initial Conditions

During storage-time, the collector voltage and current and the base to emitter
voltage remain constant. Since this is so, the capacitances Cc and CBare not effective
since no voltage change implies no capacitive current. Thus the only parameters of
interest for the basic charge equation are the active region charge QB and the excess
stored charge QBX. The basic equation becomes
dQ. , ,d00,1 - ,Qnx
r
= —
dt r. dt Tb
Before turn-off, the base current was I B = IB1. At the point where Ic =

the base current necessary to maintain Ics is Ins = Ics/hrs = QB/r.. The difference
loi — I BS is I
BX, an excess base drive which forces the device into saturation. At this
time QB has reached its final value and hence d Q0/dt = 0. Thus initially we have
hi _ 1. +--+
d L_t_ 9j_is
dt Tb
or

IBI — IBS = d Q" = lox

dt lb
which has the simple solution
—t \
Qgx = IBX (1 — rb) (6f)
Obviously, the value of QB X is a function of the length of time the device is in
saturation. Assuming the device has been in saturation for a time interval t., then
the accumulated stored charge at the instant of turn-off will be some value QBX (t.).
For convenience, the storage-time is treated in two parts very similar to the treat-
ment of the delay interval. That is, we have t. = t.' + Att in order to account for the

165
6 SWITCHING CHARACTERISTICS

fact that t. is actually measured to the point at which the collector current has fallen
to its ten percent point. Thus t.' is simply that interval before the collector current has
begun to fall. The point at which QSX has been reduced to zero is the end of t.'. It is
furthermore assumed that QSdoes not change during t.' and therefore d QB/dt = 0.
During t.' the basic equation becomes

—I
B. — IB. = (1--Q4
-
11 9L3x--
dt
which has the solution
QBX = [QBX (tx) + Tb (IB2 'Bs)] e —Tb (
IB. I
B.) (6g)

Since QBX = 0 when t= ts, equation (6g) may be set equal to zero and solved for
t.' to give
t.
= Tb ln [Q" (t‘_)+_rb (IS2 I
RS)] (6h)
Tb (IS2 IBS)

For t. > 3re equation (6h) reduces to the more familiar form

t.' = rb ln [ + (6i)
IR. -
FIs.

since QBX approaches IBX Th as t. becomes large.

As with the rise time solutions, various approximations are frequently used. The
simplest being t.' = QBx/In.. Naturally if QM( = Tb IBx, this simply becomes t.' =
Tb IBX/IB2.

LIMITATIONS
The above approach has been most successful in describing the alloy type tran-
sistor, but far less successful in mesa and planar devices where minority charge can be
stored not only in the base material but also in the bulk material of the rather high
resistivity collector. Epitaxial construction essentially minimizes this by minimizing
the amount of high resistivity material in the collector. It follows that some devices will
follow very closely the solution for t.' as given above, while other devices will only
approximate this solution and still others will be wildly different.
To some extent the validity of the solution can be extended by considering Tb as
strictly afunction of lc.. Thus at different current levels there will be different values
for Tb, Figure 6.20 is an example of Tb as afunction of collector current for aplanar
device. From the Tb curve, it is very obvious that Tb is reasonably constant only at
very low or very high currents. In the middle range, where the device is used most
widely, Tb is far from constant. If a curve of t, and a curve of hrs as functions of
collector current are given, Tb may be calculated for any collector current. If Tb is
given directly as afunction of collector current, no calculations need be made and the
proper value to use may be taken directly from the graph.
By using the corrected values of Tb for the proper collector current level, changes
in the drive conditions (IBi, Is.) act as small perturbations which alter the predicted
result in roughly the proper direction to account for the observed change in storage
time. The simple model, if used with care, can therefore be an effective tool in circuit
analysis despite its weaknesses.

T. SPECIFICATION
A time constant Tto is frequently used on specification sheets. This is ameasurement
of storage time, t., under the condition that lc. = I B, = IB2. Assuming that IB. << I C.

166
 SWITCHING CHARACTERISTICS 6
under these conditions (hrE > > 1), then
T. = Tb In 2
or
Tb = 1.44 T.
Tb is essentially the same as C. D. Simmons' Hole Storage Factor K's" ) used to describe
the behavior of alloy devices.

100
80
60 rbIN n SEC 7—

ts IN n SEC
40

hFE
20

10
8
11111 BBC
6

2 4 6810 20 40 60 80 100 200 400 1000

COLLECTOR CURRENT Ics IN MA

VARIATION OF Th, t,', AND WITH I,

Figure 6.20

Method of Grinich and Noyce (")

Because of the generally unsatisfactory nature of the simple approximation used
above for storage time, asecond approach has been suggested for diffused base struc-
tures in which minority carrier lifetime in the collector region is quite large.
In saturation, the collector-base diode becomes forward biased. Figure 6.21 is a
simple sketch of an NPN transistor with adiode connected between base and collector
to represent this forward biased collector-base diode. Thus the transistor is conceived
as essentially unsaturated and the diode accounts for the saturation effect. In trying
to turn off the device, it is necessary that the charge stored in the diode be removed
before turn off can properly start. The recovery time of the diode is essentially the
storage time interval of the transistor.
The standard diode reverse recovery formula as used in this analysie is

erf t
.' = If
-77' If+ I,
where t.' is the storage time or the time required by the diode to become reverse
biased, It is the current (I D)in the diode just prior to turn-off, I, is the current (—I
D)
in the diode during turn-off, and r is the minority carrier lifetime in the collector.
Solving for t.' there is obtained

t,,' = r [erf -'(I, I'I)] 2

+

167
6 SWITCHING CHARACTERISTICS

Prior to turn-off If = +In and IB= Ian. It follows that

hss IR, — I
CS
If = In =
1 -I- hFE

After turn-off commences, In = I, and I. = Therefore

= —I
D= I
B. I
CS
1 - I- }ICE

CB' -
Making the proper substitutions the solution for t.' becomes
t. ,= [ed . I
R.)] 2
= [erf-i I
Bx )]
+ 1,32 IBI
While theoretically r should be the lifetime of minority carriers in the collector,
the picture is somewhat confused by the available tables for the error function (erf).
The error functions differ to the extent of a multiplying constant and thus it would
appear that, in effect, r= kr' where kis determined by the particular table being used
and r is the lifetime of minority carriers in the collector.
'

Essentially this approach assumes that the major portion of the storage time lies
in clearing minority carriers from the high resistivity collector material and the excess
base charge is quite insignificant.

TRANSISTOR

hFE IB - 'Cs
Ics hFE (1 B- / D)
I hFE

SIMPLE EQUIVALENT CIRCUIT FOR ESTIMATING STORAGE TIME

WHEN APPRECIABLE CHARGE IS LOCATED IN COLLECTOR
Figure 6.21

CALCULATION OF FALL-TIME, t,
For devices where collector body storage is not an important factor, the parameters
which affect fall-time are the same, or nearly the same, as those affecting the rise-time.
The effect of Cc, CL, r., and RL are all present during the turn-off interval. The basic
charge equation is
dQB QB d42 dQT.
I
B= dt Ta — dt dt
which can be referred to QBonly, as with rise-time, to obtain
= lcQm ,hrE Cc RL , CLRL] 9j_3
dt r. T. Ta

or

= ,1 + -
9
Ta T.

168
 SWITCHING CHARACTERISTICS 6
where
TF = Ta hFE CCRL CLRL
which has the simple solution
QB= T. (182 + '
B.)e—t/TB — Ta 1132
At the point where QB= 0.9 T. ha the collector current has decreased 10 percent
while at QB= 0.1 Ta IB$ the collector current has decreased 90 percent. The difference
in time is tf and given by

ti = 7-F In
r ± 0.9 Insi
LI
B. -I- 0.1 I» J
If there is any collector storage, or any other factor implied by saturation, the effec-
tive fall time-constant will be greater than the TF calculated. It is frequently the
practice, therefore, to make separate measurements of the effective rise and fall time-
constants.
In cases where collector storage is a very important phenomenon, the fall time-
constant must be measured in order to use the above results. For this reason Simmons"'
uses hFE TEE as the rise time-constant and hFE TFE as the fall time-constant.

SUMMARY OF RESULTS
Of great importance to aproper appreciation of the problem involved in the pre-
diction of transition times is an understanding that there is no exact solution which
is applicable to every device. Furthermore, solutions obtained from asolution of the
diffusion equation are usually based on an assumed geometry with simple boundary
conditions which are not necessarily the same as the actual device. At any rate, the
need to assume ageometry necessarily implies that the solution may not be valid for
all geometries.
A solution which cannot be solved explicitly for time is of limited use to most
design engineers and certainly even more limited in usefulness to hobbyists, experi-
menters, etc., most of whom do not have large scale digital computers available to
solve any problem numerically. It is necessary to have available techniques for approxi-
mating the answers needed despite the fact that the approximations are limited in
scope and do not always work very well.
Any transistor is a temperature dependent device. This means that any and all
of the parameters involved are affected by temperature. In general, both the turn-on
and turn-off intervals tend to increase with temperature. Turn-off, essentially that
portion due to saturation, is generally affected more than the turn-on time.

Table 6.1 summarizes the most frequently encountered solutions. Obviously

expressions other than those shown may be derived if one chooses a more elaborate
model than the very simple RC circuit.

ANTI-SATURATION TECHNIQUES
Saturation implies the presence of turn-off delay or storage-time, t.. The storage
time is every bit as important as the rise or fall times, which are influenced primarily
by T. = hFE/COT and parasitic capacities. Unfortunately, storage-time is not directly
related to r,. That is, asmall value of r, does not necessarily imply asmall value for
Tb. The relationship of :I, to the time constant developed by Moll' 43 becomes quite
remote when appreciable minority carrier storage begins to occur in the collector.
Indeed, it is not incorrect to state that the gain-bandwidth product of adevice is not
a measure of its storage-time capabilities. Attempts are frequently made to operate
the transistor in such a manner as to avoid saturation entirely. In pulsed systems,

169
 6
.TIME INTERVAL FIRST APPROXIMATION SECOND APPROXIMATION THIRD APPROXIMATION FOURTH APPROXIMATION

SWITCHING CIIARACTERISTICS
, *
OW +OE +0.1 mg OCD -1- OE OB * OCD +OE ' BI
0%
43 1( AVG1 =+
., B1 'BI (AVG1+0.1 'BI (AvG1 +TR LN 'BI -0.1 Isis
/B1 -0 .
51 E15
td r T ON
OCD +OE ,
.B90* OCD+OE 08 *
0 +1/9 +1/9
IBHAVG1 /I31 /B11AVG) 'BI - 0.518s

08 Q8 44 OB * ' BI 1 [/131 -01 'BS]

90% 0.8 rR LN [IF,' -18s TR LN
'BI 'BI -0 5I8s Is! - 0.918s

tr r TON n *
0 B90 *
0% 8/9 , 0
8/9 „.
1.81 +131 -115 IBS

* *
IBX 08 T b I BX QB / BX
90% -I- 0.1 r LERF -1 (
b Tb LN 1B2 +1 BS 1
1 B2 4- CH 1 132 182+0.5IB )( IB2+0.5IBS 412+ 'BI )12
[/132 + /131
T

Is =TOFF
IBX , ,, ,, °B90* *I, IBx °B90* /B2+ IBS
+TR LN [ IB2+IBS
00% r - e
IB2+05-1-1/9
±FF
* LN [
Tb 1 B2 li 1 B2 IBx 182 +0.51 8 s 1 B2 +0.91851 182 + 0 9I gs ]

OR * OB * LIB2 + 1.8s 1 1
TF LN [I B2 +0.9I BB
0% 0.8 0.8 rF LN
1 82 4 32 +0.54s 182 182 +0.1 Iss _1
tf = TOFF
Q B90 * 0 E190 *
90% 8/9 8/9
18 2 +0.51 8 s
1 132

Qs* =QB+ Qc TR r Ta -1-1.1FEC + R L = RISE TIME CONSTANT

0890* =THAT PORTION OF QB +Q c REQUIRED TO REACH -1- bFEC RL +CL RL = FALL TIME CONSTANT
THE 90%'ON' LEVEL
rF NORMALLY SOMEWHAT GREATER THAN rR
T = TIME CONSTANT OR EFFECTIVE LIFETIME OF
MINORITY CARRIERS IN COLLECTOR - BASE DIODE

SUMMARY OF APPROXIMATE SOLUTIONS

TO SWITCHING TIME INTERVALS
Table 6.1
 SWITCHING CHARACTERISTICS 6
where the pulse width is very short compared to ri,, the device may be permitted to
reach saturation without incurring the penalty of long storage-time simply because
the narrowness of the pulse does not permit sufficient time to build up appreciable
storage charge. The forward recovery characteristics of the base to collector diode
governs the rate at which charge is accumulated.
By and large, however, most approaches to the elimination of storage-time are
simply techniques to eliminate the possibility of saturating the transistor. Some of
the approaches will be discussed in the following paragraphs.
In general, the advantages of saturated switch design are: (a) simplicity of circuit
design, (b) well defined voltage levels, (c) fewer parts required than in non-saturating
circuits, (d) low transistor dissipation when conducting, and (e) immunity to short
stray voltage signals. Against this must be weighed the probable reduction in circuit
speed since higher trigger power is required to turn off asaturated transistor than one
unsaturated.

h F

ED E CC VCE

DIODE COLLECTOR COLLECTOR CHARACTERISTICS

CLAMPING CIRCUIT TO SHOWING LOAD LINE AND OPERATING
AVOID SATURATION POINTS

COLLECTOR VOLTAGE CLAMP

Figure 6.22

A number of techniques are used to avoid saturation. The simplest is shown in

Figure 6.22. The diode clamps the collector voltage so that it cannot fall below the
base voltage to forward bias the collector junction. Response time is not improved
appreciably over the saturated case since Ic is not clamped but rises to hFEIB. Typical
variations of IB and hrE with temperature and life, for astandard transistor, may vary
Ic by as much as 10:1. Care should be taken to ensure that the diode prevents satura-
tion with the highest Ic. When the transistor is turned off I c must fall below the value

given by (Ecc — ED)/RL before any change in collector voltage is observed. The time
required can be determined from the fall-time equations in the section on transient
response. The diode can also have along recovery time from the high currents it has
to handle. This can further increase the delay in turning off. Diodes such as the 1N3604
or 1N3606 have recovery times compatible with high speed planar epitaxial transistors.
It is not always obvious in design work that power will be an important considera-
tion. During the on-time the power dissipated in the device is very close to being
hFc Ia ED. Although I Band ED may be quite fixed in value, hFE is not.
A much better way of avoiding saturation is to control I D in such away that Ic is

just short of the saturation level. This can be achieved with the circuit of Figure
6.23(a). The diode is connected between a tap on the base drive resistor and the
collector. When the collector falls below the voltage at the tap, the diode conducts
diverting base current into the collector and preventing any further increase in Ic. The

171
6 SWITCHING CHARACTERISTICS

voltage drop across R2 is approximately IcR2/11212 since the current in R2 is I B. Since

the voltage drop across the diode is approximately the same as the input voltage to
the transistor, VcE is approximately IcR2/hrE. It is seen that if the load decreases (Ic
is reduced) or hFE becomes very high, WE decreases towards saturation. Where the
change in hFE is known and the load is relatively fixed, this circuit prevents saturation.

COLLECTOR
CURRENT CLAMP R2 ECC
RL hFE +R2
WITHOUT BIAS SUPPLY
ECC R2
Figure 6.23(a) RL hFE
IF VEE << ECC

Ecc

R2 ( Ecc +1 3 Ri hFc )
VCE
COLLECTOR CURRENT R L h FE + R2

USING BIAS SUPPLY E„

R2 2) IF Vcc <<E
RL hFE CC
Figure 6.23(b)

To avoid the dependence of VCE on Ic and hFE, 118 may be added as in Figure
6.23( b). By returning IL to abias voltage, an additional current is drawn through R2.
Now VCE is approximately (Ic/hrE L) R2. 13 can be chosen to give asuitable mini-
mum VCE.

COLLECTOR VCE 0.7V at 25 * C

CURRENT CLAMP
USING SILICON AND
GERMANIUM DIODES
Figure 6.23(c)

172
 SWITCHING CHARACTERISTICS 6
The power consumed by R. can be avoided by using the circuit of Figure 6.23( c),
provided a short lifetime transistor is used. Otherwise fall-times may be excessively
long. R. is chosen to reverse bias the emitter at the maximum Icc. The silicon diode
replaces R2. Since the silicon diode has a forward voltage drop of approximately 0.7
volt over aconsiderable range of current, it acts as aconstant voltage source making
VcE approximately 0.7 volt. If considerable base drive is used, it may be necessary to
use ahigh conductance germanium diode to avoid momentary saturation as the voltage
drop across the diode increases to handle the large base drive current.
In applying the same technique to silicon transistors with low saturation resistance,
it is possible to use asingle germanium diode between the collector and base. While
this permits VcE to fall below VBE, the collector diode remains essentially non-
conducting since the 0.7 volt forward voltage necessary for conduction cannot be
reached with the germanium diode in the circuit.
Diode requirements are not stringent. The silicon diode need never be back biased,
consequently, any diode will be satisfactory. The germanium diode will have to with-
stand the maximum circuit VcE, conduct the maximum base drive with alow forward
voltage, and switch rapidly under the conditions imposed by the circuit, but these
requirements are generally easily met.
Care should be taken to include the diode leakage currents in designing these
circuits for high temperatures. All the circuits of Figure 6.23 permit large base drive
currents to enhance switching speed, yet they limit both Is and Ic just before saturation
is reached. In this way, the transistor dissipation is made low and uniform among
transistors of differing characteristics.
It is quite possible to design flip-flops which will be non-saturating without the
use of clamping diodes by proper choice of components. The resulting flip-flop is
simpler than that using diodes but it does not permit as large aload variation before
malfunction occurs. Design procedure for an undamped non-saturating flip-flop can be
found in Transistor Circuit Engineering by R. F. Shea, et al (John Wiley & Sons, Inc).

STORED CHARGE
NEUTRALIZATION
BY CAPACITOR
Figure 6.24

Another circuit which is successful in minimizing storage-time is shown in Figure

6.24. If the input is driven from avoltage source, it is seen that if the input voltage
and capacitor are appropriately chosen, the capacitor charge can be used to neutralize
the stored charge, in this way avoiding the storage-time delay. In practical circuits,
the RC time constant in the base necessary for this action limits the maximum pulse
repetition rate.

REFERENCES
( 1)Ekiss, J. A., Simmons, C. D., "Junction Transistor Transient Response Characterization, Parts I
and II," The Solid State Journal, January and February, 1961.
(2) Simmons, C. D., "Hole, Storage Delay Time and its Prediction," Semiconductor Products, May/
June 1958.
(5) Grinich, V., and Noyce, R., "Switching Time Calculations for Diffused Base Transistors," pre-
sented at IRE — Wescon, August 22, 1958.
(.0 Chen, C. H., "Predicting Reverse Recovery Time of High Speed Semiconductor Diodes," General
Electric Application Note 90.36.

173
6 SWITCHING CHARACTERISTICS

NOTES

174
 cc

DIGITAL CIRCUITRY o_

C-)

INTRODUCTION
In adigital computer the numerical values change in discrete steps. An example of
adigital computer is the ordinary desk calculator or adding machine. In an electronic
digital computer numerical values involved in the calculation are represented by the
discrete states of flip-flops and other switching circuits in the computer. Numerical
calculations are carried out in digital computers according to the standard rules of
addition, subtraction, multiplication and division. Digital computers are used primarily
in cases where high accuracy is required such as in standard accounting work. For
example, most desk calculators are capable of giving answers correct to one part in
one million, but aslide rule (analog computer) would have to be about Ya of amile
long to be read to the same accuracy.
The transistor's small size, low power requirements and inherent reliability have
resulted in its extensive use in digital computers. Special characteristics of the transistor
such as low saturation resistance, low input impedance, and complementary NPN and
PNP types, have permitted new types of digital circuits which are simple, efficient and
fast. Computers operating at speeds of 5 megacycles are a commercial reality, and
digital circuits have been proved feasible at 160 megacycles.
This chapter offers the design engineer practical basic circuits and design proce-
dures based on proven techniques and components. Flip-flops are discussed in detail
because of their extensive use in digital circuits as memory elements.

BASIC CIRCUITS
Methods for using transistors in gate circuits are illustrated in Figure 7.1. The base
of each transistor can be connected through aresistor either to ground or a positive
voltage by operating aswitch. In Figure 7.1(A) if both switches are open, both tran-
sistors will be non-conducting except for asmall leakage current. If either switch A or
switch B is closed, current will flow through RL. If we define closing aswitch as being
synonymous with applying an input then we have an "OR" gate. When either switch is
closed, the base of the transistor sees apositive voltage, therefore, in an "OR" gate the
output should be apositive voltage also. In this circuit it is negative, or "NOT OR".
The circuit is an "OR" gate with phase inversion. It has been named a"NOR" circuit.
Note that if we define opening aswitch as being synonymous with applying an input,
then we have an "AND" circuit with phase inversion since both switch A and switch B
must be open before the current through RLceases. We see that the same circuit can
be an "AND" or an "OR" gate depending on the polarity of the input.
The circuit in Figure 7.1(B) has identically the same input and output levels but
uses PNP rather than NPN transistors. If we define closing aswitch as being an input,
we find that both switches must be closed before the current through RLceases. There-
fore, the inputs which made the NPN circuit an "OR" gate make the PNP circuit an
"AND" gate. Because of this, the phase inversion inherent in transistor gates does not
complicate the overall circuitry.
Figure 7.2(A) and (B)are very similar to Figure 7.1(A) and (B) except that the
transistors are in series rather than in parallel. This change converts "OR" gates into
"AND" gates and vice versa.
Looking at the logic of Figure 7.2, let us define an input as apositive voltage; a
lack of an input as zero voltage. By using the circuit of Figure 7.1(A) with three

175
7 DIGITAL CIRCUITRY

+10V

(A) GATE USING NPN TRANSISTORS

IF CLOSING A SWITCH IS AN INPUT, THIS IS AN "OR" GATE
IF OPENING A SWITCH IS AN INPUT, THIS IS AN "AND GATE
NOTE: PHASE INVERSION OF INPUT

+10V

(B) GATE USING PNP TRANSISTORS

IF CLOSING A SWITCH IS AN INPUT THIS IS AN"AND" GATE
IF OPENING A SWITCH IS AN INPUT THIS IS AN "OR" GATE
NOTE: PHASE INVERSION OF INPUT

BASIC LOGIC CIRCUITS USING PARALLEL TRANSISTORS

Figure 7.1

+10V

+10V

(A) GATE USING NPN TRANSISTORS - (B) GATE USING PNP TRANSISTORS
IF CLOSING A SWITCH IS AN INPUT THIS IS AN "AND" GATE IF CLOSING A SWITCH IS AN INPUT THIS IS AN "OR" GATE
IF OPENING A SWITCH IS AN INPUT THIS IS AN "OR"GATE IF OPENING A SWITCH IS AN INPUT THIS IS AN"AND"GATE
NOTE: PHASE INVERSION OF INPUT NOTE PHASE INVERSION OF INPUT

BASIC LOGIC CIRCUITS USING SERIES TRANSISTORS

Figure 7.2

transistors in parallel, we can perform the "OR" operation but we also get phase
inversion. We can apply the output to an inverter stage which is connected to an
"AND" gate of three series transistors of the configuration shown in Figure 7.2(A).

176
 DIGITAL CIRCUITRY 7

_1(OR) (I+M+L)

I(I+m+L) -4> (AND) (I+M +L).(I+M+LHI+M+L)

C
M + I

TYPICAL LOGIC DIAGRAM

Figure 7.3

An output inverter stage would also be required. This is shown in Figure 7.4( A ).
By recognizing that the circuit in Figure 7.1(A) becomes an "AND" gate if the
input signal is inverted, the inverters can be eliminated as shown in Figure 7.4( B).

+10V

ALL TRANSISTORS - 2N2 95 „

'NOR'GATE INVERTER NOT "AND GATE IN

(A) INVERTERS COMPENSATE FOR PHASE INVERSION OF GATES

+10V

OUTPUT

10K

10K

'NOR' GATE TO OTHER NOT "AND"

"NOR" GATES GATE

10K

(B) PHASE INVERSION UTILIZED TO ACHIEVE "AND " AND "OR" FUNCTIONS FROM THE SAME CIRCUIT

CIRCUITS REPRESENTING (I + M+ L) (I + M + I:) (Ï + M + L) =

Figure 7.4

177
7 DIGITAL CIRCUITRY

If the transistors are made by processes yielding low saturation voltages and high
base resistance, the series base resistors may be eliminated. Without these resistors the
logic would be called direct-coupled transistor logic DCTL. While DCTL offers ex-
treme circuit simplicity, it places severe requirements on transistor parameters and
does not offer the economy, speed or stability offered by other logical circuitry.
The base resistors of Figure 7.4 relax the saturation voltage and base input voltage
requirements. Adding another resistor from each base to a negative bias potential
would enhance temperature stability.
Note that the inputs include both "on" and "off" values of all variables e.g., both
Iand iappear. In order that the gates function properly, Iand Icannot both be posi-
tive simultaneously but they must be identical and oppositely phased, i.e. when Iis
positive Imust be zero and vice versa. This can be accomplished by using a phase
inverter to generate Ifrom I. Another approach, more commonly used, is to take I
and Ifrom opposite sides of asymmetrical flip-flop.

IF A OR B OR C IS RAISED FROM ZERO TO

12 VOLTS THE TRANSISTOR WILL CONDUCT.

BASIC NOR CIRCUIT

Figure 7.5

"NOR" logic is anatural extension of the use of resistors in the base circuit. In the
circuit of Figure 7.5, if any of the inputs is made positive, sufficient base current
results to cause the transistor to conduct heavily. The "OR" gating is performed by
the resistors; the transistor amplifying and inverting the signal. The logic of Figure
7.3 can now be accomplished by combining the "NOR" circuit of Figure 7.5 with
the "AND" circuit of Figure 7.2(A). The result is shown in Figure 7.5. In comparing
the circuits in Figures 7.4(A) and 7.6, we see that the "NOR" circuit uses one-fourth
as many transistors and one-half as many resistors as the brute force approach. In fact if
we recall that the equation we are dealing with gives R rather than R, we see that
we can get R by removing the output phase inverter and making use of the inherent
inversion in the "NOR" circuit. In the circuit of Figure 7.5 two supply voltages of
+20 and —10 volts are used. The —10 volt supply is to insure that the transistor is
held off when L. increases at elevated temperatures. If silicon transistors (such as the
2N708, 2N914, or 2N2193A) are used in NOR logic circuits the hold off supply may
not be necessary. Since VBE is larger for silicon devices and L. is very low aresistor
returned to the emitter reference may result in sufficient circuit stability.
Because of the fact that ageneralized Boolean equation can be written as aseries
of "OR" gates followed by an "AND" gate as was shown, it follows that such equations
can be written as aseries of "NOR" gates followed by a"NOR" gate. The low cost
of the resistors used to perform the logic and the few transistors required make "NOR"
logic attractive.

178
 DIGITAL CIRCUITRY 7

ALL TRANSISTORS
2N708

41K

IN

47K

- 10V

(A) NOR LOGIC USING SERIES TRANSISTORS FOR "AND" GATE

+20V

4.7K

(B) NOR LOGIC USING INVERSION FOR "AND" GATE

Figure 7.6

A detailed "NOR" building block is shown in Figure 7.7. The figure defines the
basic quantities. The circuit can readily be designed with the aid of three basic
equations. The first derives the current I. under the worst loading conditions at the
collector of astage.
Vcc — VHF I
COM RC
• R. NRc (7a)

where Icom is the maximum ko that is expected at the maximum junction temperature.
The second equation indicates the manner in which I. is split up at the base of the
transistor.
IR 1B
y
M WCFM
-
VCF ,; VBE — VE11) (VHF; — VCRs)
ICOM
T
(7b)
RE

179
7 DIGITAL CIRCUITRY

DEFINITIONS
IK •MINIMUM CURRENT THROUGH RK FOR
TURNING TRANSISTOR ON
IB 'MINIMUM BASE CURRENT FOR
TURNING TRANSISTOR ON
IT 'BIAS CURRENT TO KEEP TRANSISTOR
OFF AT HIGH TEMPERATURES
M • MAX. NUMBER OF INPUTS PERMITTED
N •MAX. NUMBER OF OUTPUTS PERMITTED
VBE• MA X. BASE TO EMITTER VOLTAGE WHEN
THE TRANSISTOR IS ON.
VcE • MAX. COLLECTOR TO EMITTER VOLTAGE WHEN
THE TRANSISTOR IS ON.

CIRCUIT USED FOR DESIGN OF NOR CIRCUITRY

Figure 7.7

where VEEN is the minimum expected saturation voltage, Vc.. is the maximum expected
saturation voltage and VER is the reverse bias required to reduce the collector current
to ICO. VER is anegative voltage. The third equation ensures that VER will be reached
to turn off the transistor.
(
VCRS! VEB) NI
I
T= I
COM (7c)
RK
Knowing I T and choosing a convenient bias potential permits calculation of RT. In
using these equations, first select a transistor type. Assume the maximum possible
supply voltage and collector current consistent with the rating of the transistor and the
maximum anticipated ambient temperature. This will ensure optimization of N and
M. From the transistor specifications, values of 103., VB., VC.., and Ili (min) can be
calculated. In (min) is the minimum base current required to cause saturation. Re is
calculated from the assumed collector current. In equation (7a) solve for I Kusing the
desired value of N and an arbitrary value for R.. Substitute the value for I Kin equa-
tion (7b) along with achosen value for M and solve for IB. While superficially I Bneed
only be large enough to bring the transistor into saturation, increasing I. will improve
the rise time.
Circuit speed can be enhanced by using a diode as shown in Figure 7.8(A) to
prevent severe saturation. Excess base current is diverted by the diode into the tran-
sistor collector. By controlling the maximum base current the diode clamps the collector
close to saturation. The voltage across RBraises the effective clamping voltage. Since
RBcarries I Tplus the base current required to barely saturate the transistor, the voltage

180
 DIGITAL CIRCUITRY 7

OUTPUT

CLAMPING DIODE REDUCES STORAGE

TIME TO INCREASE SPEED
(A)

INPUTS

CAPACITORS REDUCE STORAGE

TIME TO INCREASE SPEED

(8)

METHODS TO INCREASE CIRCUIT SPEED

Figure 7.8

across RBwill vary with transistor beta. Best results are obtained with narrow beta
range transistors and I Tlarge compared to the base current.
If asilicon transistor is used, agermanium diode will generally clamp well enough
with R = O. Since the diode carries only excess base current its recovery time is gen-
erally short compared to the transistor's storage time.
The speed-up capacitor in Figure 7.8(B) helps clean out stored base charge. The
capacitors may cause malfunction unless the stored charge during saturation is care-
fully controlled. The capacitors permit high frequency input transients to appear at
the base of the transistor. If the transistor's stored charge is too small, the transients
will generate aspurious output. If the stored charge is too large the capacitors cannot
sweep it all out with resulting slower speed. In general, it is impractical to exceed two
inputs to acommon base. The capacitors also aggravate crosstalk between collectors.
For this reason it is preferable to use higher frequency transistors without capacitors
when additional speed is required.
Table 7.1 lists the characteristics of common logic systems employing transistors.

181
7 DIGITAL CIRCUITRY

TYPICAL CIRCUIT DESCRIPTION

NAME
(Positive signals are defined as 1)

Logic is performed by re-

sistors. Any positive input
RTL produces an inverted out-
put irrespective of the
Resistor other inputs. Resistor Rs
transistor gives temperature stability.
logic (See Fig. 7.7)
(NOR)

Same as RTL except that

capacitors are used to en-
RCTL hance switching speed.
a+b The capacitors increase the
Resistor
base current for fast col-
capacitor lector current turn on and
transistor minimize storage time by
logic supplying a charge equal
to the stored base charge.

Logic is performed by
transistors. Ven and VBE,
DCTL ab a+b
measured with the tran-
sistor in saturation, define
Direct
the two logic levels. Vex
coupled must be much less than
transistor VBE to ensure stability and
logic circuit flexibility. (See
Fig 7.4 )

Logic is performed by
diodes. The output is not
o+b+c inverted. Amplifiers are re-
DL quired to maintain the cor-
rect logic levels through
Diode several gates in series.
logic

Logic is performed by
diodes. The output is in-
a+b+c verted. The diode D iso-
LLL lates the transistor from
the gate permitting R to
Low turn on the collector cur-
level rent. By proper choice of
logic voltage changes occur.
This method is also called
current switching diode
logic.

COMMON LOGIC SYSTEMS

182
 DIGITAL CIRCUITRY 7

SUITABLE TRANSISTORSSUITABLE
DIODES
FEATURES GERMANIUM SILICON SILICON
Low Speed High Speed Low Speed High Speed
(fa<15mcs.) (fa>15mcs.) (fa<15mcs.) (fa>15mcs.) High Speed

The circuit design is 2N78. 2N335* 2N706*

straightforward. All logical 2N167* 2N656A* 2N708
operations can be per- 2N169A 2N914
formed with only this cir- 2N396A* 2N1613*
cuit. Many transistors2N2.1932 N5 2 5
2N526*
readily meet the steady
2N1305*
state requirements. 2N1924

Faster than RTL at the ex- 2N396A* 2N1613•

pense of additional compo- 2N404 2N2193
nents and stringent stored
charge requirements.

Very low supply voltages 2N7O8

may be used to achieve 2N914
high power efficiency and
miniaturization. Relatively
fast switching speeds are
practical.

Several gates may be used 2N78* 2N333* 2N706* DHD

between amplifiers. High 2N167* 2N337* 2N708 1N4150
speeds can be attained. 2N396A• 21•1658A* 2N914 1N4151
2N526 *
Non -inversion simplifies1N4152 2N1613 *
circuit design problems.1N4153 2N2193
Relatively inexpensive
DO-7
components are used.
1N3604
1N3605
1N3606

The number of inputs to 2N396A• 2N335* 2N914

the diode gate does not 2N525 2N338* 2N1711*
affect the transistor base 2N526* 2N2192
current thus giving pre- 2N1305*
dictable performance. The
small voltage excursions
minimize the effects of
stray capacitance and en-
hance switching speed.

Table 7.1

183
7 DIGITAL CIRCUITRY

TYPICAL CIRCUIT DESCRIPTION

NAME (Positive signals are defined as 1)

Logic is performed by
transistors which are biased
CML from constant current
SOuturb Lu keep them far
Current out of saturation. Both in-
mode verted and non-inverted
outputs are available.
logic

Logic is performed by
diodes. The output is in-
DTL oab.c
verted. The transistor acts
as an amplifier. This is
Diode essentially an extension of
transistor the diode logic discussed
logic above.

Logic is performed by
cores and transmitted by
CDL diodes. Transistors act as
drivers to shift informa-
Core tion. Each transistor can
diode drive many cores but not
successive cores in the
logic
logic line.

Logic is performed by
131.1,•e silicon controlled switches
which are triggered on at
4 Layer the gate lead. The gates
can be actuated by pulse
Device or DC levels. The gates
logic have a built in memory
and must be reset.

Logic is performed by
tunnel diode switching
from low voltage to high
TDL voltage state. Whether
circuit represents AND or
Tunnel OR gate depends on bias
diode current through resistor R.
Tunnel diode biased near
logic
peak current for OR gate,
and close to ground for
AND.

COMMON LOGIC SYSTEMS

184
 DIGITAL CIRCUITRY 7

SUITABLE TRANSISTORS SUITABLE

DIODES
FEATURES GERMANIUM SILICON SILICON
Low Speed High Speed Low Speed High Speed
(fa< 15 mcs. ) (fa > 15 mcs .) (f
a < 15 mcs. ) (fa > 15-
mcs. ) High Speed

Very high switching speeds

2N337* 2N708
are possible because the 2N338* 2N914
transistors are operated at
optimum operating condi-
tions. Although the volt-
age excursion is small the
circuitry is relatively un-
affected by noise.

High speeds can be at- 2N78* 2N333* 2N706* DHD

tamed. The impedance 2N167* 2N337* 2N708 1N4150
and voltage levels from 2N396A* 2N914 1N4151
stage to stage are well 2N526* .2N1613* 1N4152
defined. 2N1305* 1N4153

These core modules can 2N697* DO-7

be made very small. Speed 2N1613* 1N3604*
is limited by core switch- 2N1893 1N3605
ing speeds. 2N2193 1N3606
2N2243

SUITABLE DEVICES
These gates are pulse or
dc actuated and the input
need not be maintained.
High output power capa-
bility is available. In gen- 3N58
eral, in the presence of 3N59 Silicon Controlled
radiation, units will turnSwitches 3N81
on permitting fail-safe de- 3N82
sign in this atmosphere.

Current flowing through

input resistors determines
logic. Circuit is basically 1N3713
simple and very high 1N3715 Germanium
speed is obtainable. 1N3717 Tunnel Diodes
TD-401

NOTE: Other peak current diodes are listed in Chapter 19.

*Military types
Table 7.1 (Continued)

185
7 DIGITAL CIRCUITRY

FLIP-FLOP DESIGN PROCEDURES

SAT URATED FLI P-F LOPS
For standard transistor types the flip-flop circuit in Figure 7.9(A) is preferable at
moderate temperatures. We shall refer to the conducting and non-conducting transistors
as the on and off transistors respectively. For stability, the circuit depends on the low
collector to emitter voltage of the saturated on transistor to reduce the base current of
the off transistor to a point where the circuit gain is too low for regeneration. The
2209 emitter resistor can be removed if emitter triggering is not used. By adding

2 2K

2N525

(A)

25V VCc

2N525

VE

220 OHMS
R4
(B)

25V

I.5K

• OUTPUT

2N3965

TRIGGER

750 OHMS

SATURATED FLIP-FLOPS
Figure 7.9

186
 DIGITAL CIRCUITRY 7
resistors from base to ground as in Figure 7.9(B), the off transistor has both junctions
reverse biased for greater stability. While the 33K resistors divert some of the formerly
available base current, operation no longer depends on a very low saturation voltage
consequently less base current may be used. Adding the two resistors permits stable
operation beyond 50°C ambient temperature.
The circuit in Figure 7.9(C) is stabilized to I00°C. The price that is paid for the
stability is: smaller voltage change at the collector, more battery power consumed,
more trigger power required, and a low ¡co transistor must be used. The capacitor
values depend on the trigger characteristics and the maximum trigger repetition rate
as well as on the flip-flop design.
By far, the fastest way to design saturating flip-flops is to define the collector and
emitter resistors by the current and voltage levels generally specified as load require-
ments. Then assume atentative cross-coupling network. With all components specified,
it is easy to calculate the on base-current and the off base-voltage. For example, the
circuit in Figure 7.9( B)can be analyzed as follows. Assume VBE = 0.3 volt and W E=
0.2 volt when the transistor is on. Also assume that VER = 0.2 volts will maintain the off
transistor reliably cut-off. Transistor specifications are used to validate the assumptions.

1. Check for the maximum temperature of stability.

R4 Vcc 220
VE= RI 4- R4 - 2200 -I- 220 (25) - 2.3 volts
Vc.. = VE+ Vceon = 2.3 + 0.2 = 2.5 volts
Assuming no leo, the base of the off transistor can be considered connected to
apotential,
R3 R2 R3
VB'= VC.. through aresistor RR'
R2 4- R3 R2 ± R3
(2.5) (33K)
VB' -- 1.1 volts
(42K + 33K)
(33K) (42K)
RB'= 75K = 18.5K

The ¡co of the off transistor will flow through RB' reducing the base to emitter
potential. If the Icois high enough, it can forward bias the emitter to base junction

causing the off transistor to conduct. In our example, VE= 2.3 volts and VEB = 0.2 volts
will maintain off conditions. Therefore, the base potential can rise from 1.1 volts to
2.1 volts (2.3 - 0.2) without circuit malfunction. This potential is developed across

RB' by ¡co 2.1 - 1.1= 54 ga. A germanium transistor with ¡co = 10 #4a at 25°C
18.5K
will not exceed 54 1.2a at 50°C. If a higher operating temperature is required, R2 and
R3 may be decreased and/or R4 may be increased.

2. Check for sufficient base current to saturate the on transistor.

VB.. = VE VBE.. = 2.3 + 0.3 = 2.6 volts
2.6v
The current through R3 = = 33K - .079 ma
VCC VBon 25 - 2.6
The current through RI and R2 in series is 12 =
RI + R2 = 42K ± 2.2K
= 0.506 ma
The available base current is I
B= 12 - Is = 0.43 ma

The collector current is I

c=
Vcc - Vo OD 25 - 2.5 10.25 ma
RI 2.2K

187
7 DIGITAL CIRCUITRY

The transistor will be in saturation if hcs at 10 ma is greater than

Ic 10.25
= 24
Is 0.43
If this circuit were required to operate to —55°C, allowance must be made for
the reduction of liss at low temperatures. The minimum allowable room temperature
hss should be 50% higher or hss mt = 36.
Generally it is not necessary to include the effect of Ico flowing through RI when
calculating I. since at temperatures where Ico subtracts from the base drive it simulta-
neously increases hcc. If more base drive is required, R2 and R3 may be decreased.
If their ratio is kept constant, the off condition will not deteriorate, and so need not be
rechecked.

3. Check transistor dissipation to determine the maximum junction temperature.

The dissipation in the on transistor is
(0.3) (0.43) (0.2) (10.25)
VBE on LI VCE = = 2.18 mw
1000 1000
Ti ,I.ssipation in the off transistor resulting from the maximum Ico is
" (25) (55)
‘itS I
CO = 1.4 mw
— 10°
Generally the dissipation during the switching transient can be ignored at speeds
justifying saturated circuitry. In both transistors the junction temperature is within 1°C
of the ambient temperature if transistors in the 2N394-97 or 2N524-27 series are used.
NON-SATURATED FLIP-FLOP DESIGN
The abundance of techniques to prevent saturation makes a general design pro-
cedure impractical if not impossible. While it is asimple matter to design aflip-flop
as shown above, it becomes quite tedious to check all the worst possible combinations
of component change to ensure manufacturability and long term reliability. Often the
job is assigned to a computer which calculates the optimum component values and
tolerances. While anumber of flip-flop design procedures have been published, they
generally make simplifying assumptions concerning leakage currents and the voltages
developed across the conducting transistors.

CIRCUIT CONFIGURATION FOR

NON-SATURATING
FLIP-FLOP DESIGN PROCEDURE

Characteristics:
Trigger input at points E
Trigger steering by D2 and R5
Collector clamping by DI and R3
RS Connect points A, B, C, D, E as shown in
Figure 7.11 to get counter or shift regis-
ter operation
Cl and C2 chosen on basis of speed re-
quirements

Figure 7.10 (A)

188
 DIGITAL CIRCUITRY 7
The design procedure described here is for the configuration in Figure 7.10( A). No
simplifying assumptions are made but all the leakage currents and all the potentials
are considered. The design makes full allowance for component tolerances, voltage
fluctuations, and collector output loading. The anti-saturation scheme using one resistor
(R3) and one diode (D1) was chosen because of its effectiveness, low cost and
simplicity. The trigger gating resistors (R5) may be returned to different collectors to
get different circuit functions as shown in Figure 7.11. This method of triggering offers
the trigger sensitivity of base triggering and the wide range of trigger amplitude
permissible in collector triggering. The derivation of the design procedure would
require much space, therefore for conciseness, the procedure is shown without any
substantiation. The procedure involves defining the circuit requirements explicitly then
determining the transistor and diode characteristics at the anticipated operating points.
A few astute guesses of key parameters yield a fast solution. However, since the
procedure deals with only one section of the circuit at a time, a solution is readily
reached by cut and try methods without recourse to good fortune. A checking pro-
cedure permits verification of the calculations. The symbols used refer to Figure
7.11(A) or in some cases are used only to simplify calculations. A bar over asymbol
denotes its maximum value; a bar under it, its minimum. The example is based on
polarities associated with NPN transistors for clarity. The result is that only E2 is
negative. While the procedure is lengthly, its straightforward steps lend themselves
to computation by technically unskilled personnel and the freedom from restricting
assumptions guarantees aworking circuit when asolution is reached. A circuit designed
by this procedure is shown in Figure 7.11( B).

ALL DIODES
1N4152

620n 620n

LOAD-3.16 VOLTS I2O,f LOAD-316 VOLTS

220,.f +16v 220,.f

NON-SATURATED FLIP-FLOP
Figure 7.10 (B)

The same procedure can be used to analyze existing flip-flops of this configuration
by using the design check steps.

189
7 DIGITAL CIRCUITRY

10V

2N396A 111 j 2N396A

9.1 K

2.2 K250 pf 250 pf 2.2K

E
(A) FLIP—FLOP

uCE DI- u EDB1-

C

INPUT 0 (!)
(B) INTERCONNECTION AS COUNTER

B --0.,......,...„:: A B LA B
CE D -0- CED CED -0-
TRIGGER
(C) INTERCONNECTION AS SHIFT REGISTER

500 KC COUNTER-SHIFT REGISTER FLIP-FLOP

Figure 7.11

190
 NON-SATURATING FLIP-FLOP DESIGN PROCEDURE

STEP I DEFINITION OF OPERATION SYMBOL I SAMPLE DESIGN FOR 2N396 TRANSISTOR

(A) Circuit Requirements and Device Characteristics

1 Assume maximum voltage design tolerance ae Let Ae = :17 5%

2 Assume maximum resistor design tolerance eir Let Air = ± 7% (assuming -±- 5% resistors)

3 Assume maximum ambient temperature TA Let TA= 40°C

4 Assume maximum load current out of the off side Io Let Io = 1ma

5 Assume maximum load current into the on side I, Let Ii = 0.2 ma

6 Estimate the maximum required collector current in the on L Let L < 17.5 ma
transistor

7 Assume maximum design Ico at 25°C From spec sheet Ico < 6pa

8 Estimate the maximum junction temperature Ta Let TA= 60°C

9 Calculate Ico at T.1 assuming Ico doubles every 10°C or L 12 = 6e.°71.3 = 71 pa; Let I2 = 100 /la
IcoTi = ICO25 e"°"j -25)

10 Assume the maximum base leakage current is equal to the I, Let L = 100 pa
maximum Ico

Z MIIIIIDIED IVII9ICI
11 Calculate the allowable transistor dissipation 2N396 is derated at 3.3 mw/°C. The junction temperature
rise is estimated at 20°C therefore 67 mw can be allowed.
Let Pc = 67 mw

12 Estimate hrE minimum taking into account low temperature pm in Let am,. = 0.94 or f3n, in = 15.67
degradation and specific assumed operating point
_
13 Estimate the maximum design base to emitter voltage of Vi Let V, = 0.35 volts
the "on" transistor
14 Assume voltage logic levels for the outputs Let the level separation be >. 7volts,
 NON-SATURATING FLIP-FLOP DESIGN PROCEDURE (CONTINUED)

STEP DEFINITI O N O F O PER A TI ON SYMB O L SAMPLE DE SI

GN FOR 2N 396 TRAN SI
STO R

15 Choose the maximum collector voltage permissible for the V. Let V. < 2.0 volts
"on" transistor

AILLII1DIIID
16 Choose suitable diode types Let all diodes be 1N4152
17 Estimate the maximum leakage current of any diode L Maximum leakage estimated as < 0.25 Aa. Let L = 40 eta at
end of life
18 Cakulate I. = L + L LS 40 + 100 = 140 µa
19a Choose the minimum collector voltage for the "off" transistor V8 Let V. > 9.0 volts
keeping in mind 14 and 15 above

19b Choose the maximum collector voltage for the "off" tran- V. Let V. < 13.0 volts
sistor

20 Choose the minimum design base to emitter reverse bias to V. Let V. = 0.5 volt
assure off conditions

21a Estimate the maximum forward voltage across the diodes V. Let V. = 0.8 volt
21b Estimate the minimum forward voltage V7 Let V7 = 0.2 volt
22 Estimate the worst saturation conditions that can be tol-
erated.
22a Estimate the minimum collector voltage that can be tolerated V. Let V. = 0.1 volt

22b Estimate the maximum base to collector forward bias volt- V. Let V. = 0.1 volt
age that can be tolerated

23a Calculate V. ± V7 V70 2+ 0.2 = 2.2 volts

23b Calculate V, + V. V77 2+ 0.8 = 2.8 volts

24a Calculate V8 + V7 V7g 0.1 + 0.2 = 0.3 volt

STEP DEFINITION OF OPERATION
SYMBOLI SAMPLE DESIGN FOR 2N396 TRANSISTOR
24b Calculate V. ± V0 V18 0.1 ± 0.8 = 0.9 volt
25 Calculate V. ± V14 0.1 ± 0.1 = 0.2 volt
(B) Cut and Try Circuit Design
Assume E2 E2 Let E2 = -16 volts -±: 5%; E. = -15.2 v; E. = -16.8 v
(1 + AO 1.07
2 Calculate Ki = 1.15
(1 - e.r) 0.93

2b Calculate (1 ± AO 1.05
(1 - AO K2 = 1.105
0.95

2c Calculate 2 1
17.5
= 1.117 ma
pmln 15.67
2d Calculate 12 ± 1
0 + 21.
1C4 0.1 + 1.0 + 0.08 = 1.18 ma
Ve - V9 0.8 - 0.1
2 Calculate
V. + V9 --. E2 - 0.0454 volts
0.1 + 0.1 + 15.2

3 Calculate iT4 < 10 - V1

KiK.
K1 (V1 - E2) j
1
r 2.2 - 0.35
1.117 L(1.15) (0.0454) - 1.15 (0.35 + 16.8) j = 14.03 K

4 Choose R4 R4 Let R4 = 13 K -±- 7%; iii = 13.91 K; R4 = 12.09 K

rivnoia
5 Calculate R3 > K5 Fa (0.0454) (13.91K) = 0.632 K

6 Choose R3 R3 Let R3 = 0.68 K ± 7%; FT3 = 0.7276 K; R3 = 0.6324 K

Z AILLIflallID
R4 (V10 - V1) (12.09 K) (2.2 - 0.35)
7 Check R3 by calculatingrt3 < = 0.730 K; choice of
Vi-- E2 ± K. R4 0.35 + 16.8 ± (1.117) (12.09)
R3 satisfactory
R4 13.91 K
8 Calculate K. -- 1.091 K/V
-V. - E - L R4 -0.5 -I- 15.2 - (0.14) (13.91)
 NON-SATURATING FLIP-FLOP DESIGN PROCEDURE (CONTINUED)

XIIIIf1DIED 'IVIMICI
STEP DEFINITION OF OPERATION SYMBOL SAMPLE DESIGN FOR 2N396 TRANSISTOR

Ko (V. -I- V.) - R3 (1.091) (2.0 + 0.5) K - 0.632 K

9 = 2.19 K
Calculate R2 > 1- K.1. 1- (1.091) (0.04)

10 Choose R2 - If there are difficulties at this point, assume a iv,

Let R2 = 2.7 K ÷ 7%; R2 = 2.889 K; R2 = 2.511 K
different Et.

Ki 2 [V3 - V12 ± K. R2] (1.15) 2[9.0 - 0.3 -I- (1.18) (2.511)]

11 Calculate K2 _ 1.51
V. - V118 110 - 2.

< KN. - VII (1.51) (13.0) - 9.0

12 Calculate E, = 17.63
K. - 1/K2 1.51 - 1/1.105
--
13 Choose E1 E1 Let E1 = 16 volts ± 5%; E = 16.8 volts; E, = 15.2 volts

(Ei - V,,) R2 (15.2 - 9.0) (2.511)

14 Calculate Ki < - 1.335 K
V3 - V, 2 -I- K., R2 9.0 - 0.3 + (1.18) (2.511)
_

(E - V.) (R2) (16.8 - 13.0) (2.889)

15 Calculate RI > ‘, , - 1.077 K
- 13.0 - 2.8

16 Choose RI RI Let RI = 1.2 K -±- 7%; Ill = 1.284 K; RI = 1.116 K

(C) Design Checks

1 Check "off" stability. Reverse bias voltage is given by:

R4 13.91
VER <E+ [v., É-4I,R2+I.(R2-1-R3)]VEB VER - 15.2 ±
R4-FR3A-R2 17.05
[2 ± 15.2 + ( 0.04 )(
2.511 )± (
0.14 )(
3.14 )] =_- -0 .
7 volts
The design value of V. was 0.5 volts. Therefore, the "off"
Circuit stable if VER <
condition is stable.
STEP DEFINITION OF OPERATION SYMBOL SAMPLE DESIGN FOR 2N396 TRANSISTOR
2 Check for non-saturation under the worst conditions.
R4 (VIA -r2) 13.91 (0.9 ± 15.2)
Vim < E + vi ,. - 15.2 ± _ 0.19 volts
IT4 ± R3 14.54
Circuit non-saturated if VBE < VI, The design maximum of V,. was 0.2 volts.
3 Check for stability. Calculate:
3a RA=T11 - I
-TI2 RA 1.284 + 2.889 = 4.173 K
3b RB= TII ± TI2 + TI3 + R4 RB 1.284 ± 2.889 ± 0.728 -I- 12.09 = 16.99 K

3c Re = 1
1
75+ R4
- Rc 0.728 -I- 12.09 = 12.82 K
3d E.' = E, - K. TII E.' 15.2 - (1.18) (1.284) = 13.68 volts
3e RD= RI ± R2 ± R3 + R4 RD 1.116 ± 2.889 -I- 0.728 + 13.91 = 18.643 K

,- V2) - RI [E - E2 - L El
RD(E. - L (R3 + R4)] 18.64 (16.8 - 2) - 1.116 [16.8 + 16.8 - (0.14) (13.91)
3f L, = I
A
RI (RD- RI) 1.116 (18.64 - 1.116)
- (.04) (0.728 ± 13.91)] 12.34
= ma
B 16.99 (13.68 + 16.8)
3g I
T= (E,' - V») - 1 (E,' - E2) 17 (13.68 - 2.2) = 1.266 ma
K.Anc Rc (4.173) (12.82) 12.82
L ± L± 1 7 0.2 ± 12.34 ± 1.266
3h L=

XIIIIfIDIII3 IVIIDICI
ame ± R4/ Rc L 15 .67 ± 12 .09/12 .82 = 0.831 ma

16.8 12.09 t1 . 4.173

_ + 16.99 ‘ 1- 12.818 ) (13.683 + 16.8)

R4 / RA \ / 12.09 2
3i VBE' = E2 + R, 1 R-c
+ --) E1'- ) - 683 22) - 0' 831 1209
-- --
12.818 (13 ' - ' -16.99

_ M (El' -V10) - 1,, 111 ( RAR4 _ RA- TI3 (4.1713

2)8(18
12.09) __. . =
VBE' 4.173 07276) 0.55V
Rc RB \ Re
0.55V is greater than V, = 0.35V, therefore the design is
satisfactory.

Z
7 DIGITAL CIRCUITRY

TRIGGERING
Flip-flops are the basic building blocks for many computer and switching circuit
applications. In all cases it is necessary to be able to trigger one side or the other into
conduction. For counter applications, it is necessary to have pulses at asingle input
make the two sides of the flip-flop conduct alternately. Outputs from the flip-flop must
have characteristics suitable for triggering other similar flip-flops. When the counting
period is finished, it is generally necessary to reset the counter by a trigger pulse to
one side of all flip-flops simultaneously. Shift registers and ring counters have similar
triggering requirements.
In applying atrigger to one side of aflip-flop, it is preferable to have the trigger
turn a transistor off rather than on. The off transistor usually has a reverse-biased
emitter junction. This bias potential must be overcome by the trigger before switching
can start. Furthermore, some transistors have slow turn on characteristics resulting in
adelay between the application of the trigger pulse and the actual switching. On the
other hand, since no bias has to be overcome, there is less delay in turning off a
transistor. As turn-off begins, the flip-flop itself turns the other side on.
A lower limit on trigger power requirements can be determined by calculating
the base charge required to maintain the collector current in the on transistor. The
trigger source must be capable of neutralizing this charge in order to turn off the
transistor. It has been determined that the base charge for anon-saturated transistor is
approximately QB= 1.22 Ir/274 using the equivalent circuit approach, or r. Ic using
charge parameters. The turn-off time constant is approximately heid2rf or r«. This
indicates that circuits utilizing high speed transistors at low collector currents will
require the least trigger power. Consequently, it may be advantageous to use high
speed transistors in slow circuitry if trigger power is critical. If the on transistor was in
saturation, the trigger power must also include the stored charge. The stored charge is
given approximately by Q. rb IBX, where the symbols are defined in the section on
transient response time.
Generally, the trigger pulse is capacitively coupled. Small capacitors permit more
frequent triggering but alower limit of capacitance is imposed by base charge con-
siderations. When atrigger voltage is applied, the resulting trigger current causes the
charge on the capacitor to change. When the change is equal to the base charge just

+6V

2N708 2KI708

FO
PULSE
2K CT INPUT

MAXIMUM TRIGGER RATE EXCEEDS 2MC WITH TRIGGER

AMPLITUDE FROM 4V TO I2V.
EMITTER TRIGGERING
Figure 7.12

196
 DIGITAL CIRCUITRY 7
calculated, the transistor is turned off. If the trigger voltage or the capacitor are too
small, the capacitor charge may be less than the base charge resulting in incomplete
turn-off. In the limiting case C= Q./VT. The speed with which the trigger turns off a
transistor depends on the speed in which Q. is delivered to the base. This is determined
by the trigger source impedance and 11'.
In designing counters, shift registers or ring counters, it is necessary to make
alternate sides of a flip-flop conduct on alternate trigger pulses. There are so-called
steering circuits which accomplish this. At low speeds, the trigger may be applied at
the emitters as shown in Figure 7.12. It is important that the trigger pulse be shorter
than the cross coupling time constant for reliable operation. The circuit features few
parts and a low trigger voltage requirement. Its limitations lie in the high trigger
current required.
At this point, the effect of trigger pulse repetition rate can be analyzed. In order
that each trigger pulse produce reliable triggering, it must find the circuit in exactly
the same state as the previous pulse found it. This means that all the capacitors in the
circuit must stop charging before atrigger pulse is applied. If they do not, the result
is equivalent to reducing the trigger pulse amplitude. The transistor being turned off
presents a low impedance permitting the trigger capacitor to charge rapidly. The
capacitor must then recover its initial charge through another impedance which is
generally much higher. The recovery time constant can limit the maximum pulse rate.

CT
(-0 - trir

900 PULSE
INPUT

MAXIMUM TRIGGER RATE EXCEEDS 5MC

MAXIMUM TRIGGER RATE EXCEEDS 5MC WITH TRIGGER WITH TRIGGER AMPLITUDE FROM 4175 TO
AMPLITUDE FROM 9V TO I2V. 2 VOLTS .

COLLECTOR TRIGGERING BASE TRIGGERING

Figure 7.13 Figure 7.14

Steering circuits using diodes are shown in Figures 7.13 and 7.14. The collectors
are triggered in 7.13 by applying anegative pulse. As adiode conducts during trigger-
ing, the trigger pulse is loaded by the collector load resistance. When triggering
is accomplished, the capacitor recovers through the biasing resistor RT. To minimize
trigger loading, RTshould be large; to aid recovery, it should be small. To avoid the
recovery problem mentioned above, RTcan be replaced by adiode as shown in 7.15.
The diode's low forward impedance ensures fast recovery while its high back im-
pedance avoids shunting the trigger pulse during the triggering period.
Collector triggering requires arelatively large amplitude low impedance pulse but
has the advantage that the trigger pulse adds to the switching collector waveform to

197
7 DIGITAL CIRCUITRY
enhance the speed. Large variations in trigger pulse amplitude are also permitted.
In designing acounter, it may be advantageous to design all stages identically the
same to permit the economies of automatic assembly. Should it prove necessary to
increase the speed of the early stages, this can be done by adding a trigger amplifier
as shown in Figure 7.16 without any change to the basic stage.

DIODE TO SUPPLY VOLTAGE REDUCES

TRIGGER POWER AND EXTENDS MAXIMUM
TRIGGER RATE .

COLLECTOR TRIGGERING
Figure 7.15

36pf

CT
PULSE
INPUT

FOR IMC TR I
GGER RATE LESS THAN I VOLT TR I
GGER
AMPLITUDE REQUIRED .

COLLECTOR TRIGGERING WITH

TRIGGER AMPLIFIER
Figure 7.16

198
 DIGITAL CIRCUITRY 7
Base triggering shown in Figure 7.14 produces steering in the same manner as
collector triggering. The differences are quantitative with base triggering requiring
less trigger energy but a more accurately controlled trigger amplitude. A diode can
replace the bias resistor to shorten the recovery time.

10K 1N4152 OR 162K

1N3605
CT
220 pf ) 2u2T0 pf

BASE TRIGGERING WITH HYBRID GATE

Figure 7.17

Hybrid triggering illustrated in Figure 7.17 combines the sensitivity of base

triggering and the trigger amplitude variation of collector triggering. In all the other
steering circuits the bias potential was fixed, in this one the bias potential varies in
order to more effectively direct the trigger pulse. By returning the bias resistor to the
collector the bias voltage is VeB. For the conducting transistor, Vc5 is much less than
for the off transistor, consequently, the trigger pulse is directed to the conducting
transistor. This steering scheme is particularly attractive if VeB for the conducting
transistor is very small as it is in certain non-saturating circuits such as shown in
Figure 6.23.
Care should be taken that the time constant CTRT does not limit the maximum
counting rate. Generally RTcan be made approximately equal to RK, the cross-coupling
resistor.

SPECIAL PURPOSE CIRCUITS

SCHMITT TRIGGER
A Schmitt trigger is a regenerative bistable circuit whose state depends on the
amplitude of the input voltage. For this reason, it is useful for waveform restoration,
signal level shifting, squaring sinusoidal or non-rectangular inputs, and for de level
detection. Practical circuits are shown in Figure 7.18.
Circuit operation is readily described using Figure 7.18(B). Assuming Q1is non-
conducting, the base of Q2 is biased at approximately +6.8 volts by the voltage
divider consisting of resistors 3.3K, 1.8K and 6.8K. The emitters of both transistors are
then at 6.6 volts due to the forward bias voltage required by Q2. If the input voltage

199
 DIGITAL CIRCUITRY 7

FREQUENCY RANGE 0- 500KC

OUTPUT AT COLLECTOR HAS 8V
MINIMUM LEVEL CHANGE
QI ALWAYS CONDUCTS IF INPUT
IS MORE NEGATIVE THAN -5V

02 ALWAYS CONDUCTS IF INPUT

IS MORE POSITIVE THAN -2V
AMBIENT TEMPERATURE -55•C
TO 71°C

+12V

2.2 K

FREQUENCY RANGE 0 TO IMC

OUTPUT OUTPUT AT COLLECTOR HAS 2V
MINIMUM LEVEL CHANGE
QI ALWAYS CONDUCTS IF INPUT
EXCEEDS 6.8V
1K 02 ALWAYS CONDUCTS IF INPUT
IS BELOW 5.2V
AMBIENT TEMPERATURE 0•C
TO 71.0

(3)

SCHMITT TRIGGERS
Figure 7.18

is less than 6.6 volts, QI is off as was assumed. As the input approaches 6.6 volts, a
critical voltage is reached where QI begins to conduct and regeneratively turns off Q2.
If the input voltage is now lowered below another critical value, Q2 will again conduct.
ASTABLE MU LT I VI BRATOR
The term multivibrator refers to atwo stage amplifier with positive feedback. Thus
a flip-flop is a bistable multivibrator; a "one-shot" switching circuit is a monostable
multivibrator and a free-running oscillator is an astable multivibrator. The astable
multivibrator is used for generating square waves and timing frequencies and for
frequency division. A practical circuit is shown in Figure 7.19. The circuit is sym-
metrical with the transistors dc biased so that both can conduct simultaneously. The
cross-coupling capacitors prevent this, however, forcing the transistors to conduct
alternately. The period is approximately T = CT 100/28.8 microseconds where CTis
measured in pf WM. A synchronizing pulse may be used to lock the multivibrator to an
external oscillator's frequency or subharmonic.

MONOSTAB LE MU LT I
VI BRATOR
On being triggered amonostable multivibrator switches to its unstable state where
it remains for apredetermined time before returning to its original stable state. This
makes the monostable multivibrator useful in standardizing pulses of random widths
or in generating time delayed pulses. The circuit is similar to that of aflip-flop except
that one cross-coupling network permits ac coupling only. Therefore, the flip-flop can

200
 DIGITAL CIRCUITRY 7

I2V

FREQUENCY RANGE ICPS TO 250KCPS BY

CHANGING CT

OUTPUT AT COLLECTOR HAS 8 VOLT

MINIMUM LEVEL CHANGE

AMBIENT TEMPERATURE -55.0 TO 71.0

SYNCHRONIZING PULSES PERMIT
GENERATING SUBHARMONICS

SYNC PULSE AMPLITUDE MUST EXCEED

I.5V POSITIVE; RISETIME MUST BE LESS
THAN 1.0µ SEC.

ASTABLE MULTIVIBRATOR
Figure 7.19

only remain in its unstable state until the circuit reactive components discharge. Two
circuits are shown in Figure 7.20 to illustrate timing with a capacitor and with an
inductor. The inductor gives much better pulse width stability at high temperatures.

-I2V

I.8K

OUTPUT AT COLLECTORS HAS 8 VOLT

OUT PUT LEVEL CHANGE

OUTPUT PULSE DURATION 2µSEC TO ISEC

MAXIMUM INPUT FREQUENCY 250KC

MAXIMUM REQUIRED INPUT PULSE IS

2N396A
5 VOLTS

DUTY CYCLE EXCEEDS 60%

AMBIENT TEMPERATURE -55 .0 TO 71.0

(A)

OUTPUT AT COLLECTOR HAS

5 VOLT LEVEL CHANGE

OUTPUT PULSE DURATION APPROX

600 MICROSECONDS

MAXIMUM INPUT PULSE REQUIRED

3 VOLTS

AMBIENT TEMPERATURE -55 .0

TO 71.0

MONOSTABLE MULTIVIBRATOR
Figure 7.20

201
7 DIGITAL CIRCUITRY

INDICATOR LAMP DRIVER

The control panel of acomputer frequently has indicator lamps to permit monitor-
ing the computer's operation. The circuit in Figure 7.21 shows a bistable circuit
which permits controlling the lamp by short trigger pulses.
A negative pulse at point A turns on the lamp, which remains on due to regenera-
tive feedback in the circuit. A positive pulse at A will turn off the lamp. The use of
complementary type transistors minimizes the standby power while the lamp is off.

24V+ 20%

NOTE:
I. TRIGGER PULSE REQUIREMENT 2 VOLTS NEGATIVE
WITH RESPECT TO 24 V MAXIMUM.
2.AMBIENT TEMPERATURE -55 °C TO 71 °C.
3. RESISTOR TOLERANCE ± 10% AT END OF LIFE.

BISTABLE INDICATOR LAMP DRIVER

Figure 7.21

PERFORMANCE
AMPLITUDE 25V RISE TIME 25 ns
IMPEDANCE 5on WIDTH 200 ns
REP RATE 100kc FALLTIME 30 ns

PULSE GENERATOR WITH 0.5 AMPS. IN 25 NSEC.

Figure 7.22

202
 DIGITAL CIRCUITRY 7
PULSE GENERATOR
Frequently, in computer circuits a clock pulse is required to set the timing in an
array of circuits. A pulse generator is shown in Figure 7.22 which delivers a very
fast rise time (25 nsec. )pulse of high power. The circuit is basically composed of two
parts. A multivibrator is formed by Q1 and Q2 and their associated circuitry and
triggers the pulse generator formed by Q3 and Q4.

RING COUNTER
The circuit of Figure 7.23 forms a digital counter or shift register with visual
readout. The circuit operates from a 12 volt source and uses six components per stage.
The counter and indicator functions are combined to insure low battery drain. The
.22 ihfd capacitor ensures that the first stage turns on after the reset button is released.
No current is drawn by the stages except when alamp is on. As many stages as desired
may be included in aring.

RESET N.C.

+12V0-0 T

IN4009

1144009
IN4009
RECTIFIERS
PROVIDE BIAS
VOLTAGES FOR
TEMPERATURE
STABILITY.

INPUT

154009
OUTPUT
IN4009 H o TO NEXT
COUNTER
0.1/ad RING

FIRST STAGE SECOND STAGE LAST STAGE

OF RING COUNTER

RING COUNTER WITH VISUAL READOUT

Figure 7.23
DCTL
Some circuits have been designed making specific use of saturation. The direct
coupled transistor logic (DCTL) flip-flop shown in Figure 7.24 utilizes saturation.
In saturation VCE (SAT) can be so low that if this voltage is applied between the base
and emitter of another transistor, as in this flip-flop, there is insufficient forward bias
to cause this transistor to conduct appreciably. The extreme simplicity of the circuit
is self evident and is responsible for its popularity. However, special requirements are
placed on the transistors. The following are among the circuit characteristics:
First, the emitter junction is never reverse biased permitting excessive current to
flow in the off transistor at temperatures above 40°C in germanium. In silicon, how-
ever, operation to 150°C has proved feasible.
Second, saturation is responsible for astorage time delay slowing up circuit speed.

203
7 DIGITAL CIRCUITRY

0.2V

vcE (sat)

DIRECT COUPLED TRANSISTOR LOGIC (DCTL) FLIP-FLOP

Figure 7.24

In the section on transient response we see the importance of drawing current out of
the base region to increase speed. In DCTL this current results from the difference
between VCE (SAT) and VBE of aconducting transistor. To increase the current, VeE (SAT)
should be small and n,' should be small. However, if one collector is to drive more
than one base, n,' should be relatively large to permit uniform current sharing between
bases since large base current unbalance will cause large variations in transient response
resulting in circuit design complexity. High base recombination rates and epitaxial
collectors to minimize collector storage result in short storage times in spite of ri,'.
Third, since VCE (SAT) and VBE differ by less than 0.3 volt in germanium, stray voltage
signals of this amplitude can cause faulty performance. While stray signals can be
minimized by careful circuit layout, this leads to equipment design complexity. Silicon
transistors with a0.6 volt difference between VeE (SAT) and VBE are less prone to being
turned on by stray voltages but are still susceptible to turn-off signals. This is some-
what compensated for in transistors with long storage time delay since they will remain
on by virtue of the stored charge during short turn-off stray signals. This leads to
conflicting transistor requirements — long storage time for freedom from noise, short
storage time for circuit speed.

NOTES
 cc

o_
OSCILLATORS
C-1

OSCILLATOR THEORY
The study of oscillators forms one of the most interesting fields available to the
electronic circuits designer. The anonymous wag quoted as saying "an oscillator ampli-
fies and an amplifier oscillates" underlines the capricious nature of the amplifier which
furnishes its own input signal from its own output signal. Vital and fundamental to
all oscillators is an amplifier. The process of oscillation simply involves a connection
of output to input so that certain conditions are fulfilled. These conditions are called
stability criteria; and different types of oscillators are classed primarily by the means
employed to obey the basic stability criteria.
Although one hears about transistor oscillators, or vacuum tube oscillators, or
tunnel diode oscillators, etc., these various classes are as many as the active devices
furnishing the gain necessary for oscillation, but do not really reveal much about the
nature of the oscillator. Figure 8.1 shows an amplifier having avoltage gain A, whose
output is connected to asecond amplifier having avoltage gain B. Further, the input
of amplifier A is connected to the output of B.
e. = ei ± Be. (8a)
e. = Ae. (8b )
e. A
ei 1± AB (8c)

INPUT OUTPUT
es
AMPLIFIER e.
GAINA

Be o zer

AMPLIFIER
GAIN=B
OUTPUT INPUT

STABILITY CRITERIA
Figure 8.1

Nothing is said about the amount of voltage, current or power gains of either
amplifier (whether it is greater or lesser than unity), or how the outputs are added.
Figure 8.1 writes three simple equations. Equation (8e) is called a transfer function
and describes how the output voltage/input voltage ratio behaves in terms of the
gains of the amplifiers. In an oscillator we might expect that a small input signal
would be amplified regeneratively until infinite, or until some limit is imposed. This
condition, from equation (8e) is possible if the product of AB = —1. This, in turn,
would require us to choose the positive sign in equation (8a). Returning to the
block diagram, this positive sign stipulates that ef = Be. "add" to el or be in phase
with el. The ratio of eje, need not be infinite for oscillation to occur, nor must the
product of A and B exactly = 1. Exact specification, in general terms, of the condi-
tions for oscillation is most simply stated as AB > 1. In some cases the gain considered
in writing the transfer function is most conveniently expressed as power or current

205
8 OSCILLATORS

gain. If power gain is considered, then the loop gain (net gain) must be greater than
unity. This criteria is called the Barkhausen criteria.
Four other common approaches are used for analytical determination of the stability
of the system. These approaches are, from direct examination of the system differen-
tial equation solutions: Routh's criterion, Nyquist's criterion, Bode's attenuation and
phase shift method, or combinations of all. In nearly all oscillators the amplifier we
have labeled A has avoltage gain and current gain greater than unity (in addition
to apower gain greater than unity), and the amplifier labeled B has gain less than
unity. An active device, such as atransistor, furnishes the gain; resistors, capacitors,
and inductors provide the loss and phase shift to insure the proper polarity of output
to input feedback.

PHASE SHIFT OSCILLATORS

Figure 8.2(A) depicts a simple, versatile transistor amplifier. (Chapter 4, Figure
4.3 and accompanying text as well as Chapter 2 give detailed design of this type of
amplifier.) Its current gain is stabilized against transistor variation. The means used
to stabilize both operating point and small signal current gain also allow it to be
used over acollector voltage range of 2to 24 volts.

+Vcc 047 047 047 47K

33K
470K
eOUT
'OUT 47K >47K
eIN
'IN 2N2924

(A) (B)

10 TO 20V
3.3K

oOUTPUT
470K .047 .047
II I
4.7K
4.7K — .047
5.0K

(C)

AMPLIFIER TO OSCILLATOR
Figure 8.2

When this simple amplifier is combined with the phase shift network in Figure
8.2(B) oscillation will occur at afrequency where there is a360° total phase shift;
180° of this 360° total is furnished by the grounded emitter amplifier, and 180° is
furnished by the high pass network. Figure 8.2(C) connects both together and pro-
vides a 5K pot for frequency adjust. This pot adjusts frequency from about 200 to
400 cps. Both hi., and hob enter as terms in the expression for frequency, but the
unusually low impedances chosen provide excellent temperature and voltage stability.

206
 OSCILLATORS 8
Output is derived across the collector and is approximately equal to Vcc. Frequency
of oscillation is
1
(8d)
2w V6R2 Cz + 4R RI, C2
(This equation assumes R > 10111. and 1/11.. > 10 RL)
The hi. for sustained oscillation is

hr. 22 + 30 R + 4RL (8e)

RL R
Figure 8.3 details yet another RC phase shift oscillator using abridged-T network.
In this case the simple amplifier is supplemented by an emitter follower to eliminate
111. loading variations. Exceptional frequency stability (.2%) is possible over the
temperature range of —55°C to +80°C. In both phase shift oscillators the affect of
h.. variations is swamped by the low (3.3K) collector load.

HIGH STABILITY BRIDGED-T OSCILLATOR

Figure 8.3

RESONANT FEEDBACK OSCILLATORS

Among the most prevalent, useful oscillators is a class termed resonant-feedback
circuits. These use either inductance-capacitance combinations or their equivalent
(electro-mechanical resonators). They are characterized by having circuit simplicity,
good power efficiency, and good frequency stability. Figure 8.4(A) demonstrates how
ac coupling between input and output of a transistor amplifier is accomplished. This
circuit is classed as a tuned collector oscillator. L, and C in the collector of transistor
Q, form a parallel resonant circuit. Further, the mutual coupling between L. and L2
(called atickler winding) provides an input signal current whose direction and mag-
nitude are set by the physical arrangement of L, relative to L., and by the direction
and magnitude of the current through L.
The dots shown on the coils indicate winding start and infer phase coincidence,
so that an increase in collector current causes an increase in base current which pro-
vides the regenerative, or positive, feedback required to initiate oscillation. The core
placed in the transformer is shown to indicate unity coupling between Li and L2
which simplifies the analytical design procedure, but is not necessary for oscillator
operation. The collector current and base current waveforms of Figure 8.4(B) both
show an offset which comes about from a bias current not shown in this simple ac
circuit. This offset, or bias, current insures that the oscillator will start. Reversal of the
increasing, or decreasing, base current is limit cycle in nature and comes about because
the current gain of atransistor falls at both very high and very low currents. The exact
points in Ic where reversal occurs are determined by loop gain and loss, and will

207
8 OSCILLATORS

BIAS
CURRENT
TIME —6.

(A)

(C)

RESONANT FEEDBACK OSCILLATOR

Figure 8.4

always lie between transistor cutoff and saturation. The period of oscillation is very
nearly set by the familiar relation between L. and C
1
f= • (8f)
2.3- VL. C
This presupposes that the core coupling Li and L. is operated over a reasonably
linear portion of its B-H characteristic. A more nearly exact expression, including the
mutual inductance M is
1
fr= (8g)
22r VC (L2 + 1,1 ± 2M) — (L2 1 1 Mr hObillib
, —

In Figure 8.4( C), the ac circuit, an auto transformer can be substituted for the two
winding transformer, and the emitter rather than the base may be allowed to float.
This preserves the proper feedback polarity, and is the basic circuit of the Hartley
oscillator. Further, it is a grounded-base oscillator and stability criteria are appropri-
ately expressed in terms of grounded base hybrid parameters. Analysis of this type of
oscillator most frequently concerns itself with limit conditions. First, and fundamental,
is the ability of the oscillator to start and continue oscillation. For this purpose small
signal hybrid parameters may be used to establish the power gain of the circuit or the
equivalent current or voltage gains. The Barkhausen criteria for loop unity gain forms
the most convenient analytical approach. In terms of the mutual inductance M and the
inductances L1 -I- L2 oscillation requires
L2+ M
hn, — +M (8h)
In power applications, device ratings become important limit parameters to
examine. The first point to consider is the power dissipation of the device compared
to the power needed in an attached load. In most cases oscillator efficiency will be
somewhat greater than the theoretical class "A" efficiency of 50%. This follows
because of the bias needed to guarantee starting and proceeds from the stability
criteria. A figure of 50% is pessimistic; it may later be refined by actual circuit

208
 OSCILLATORS 8
performance measurement. Supposing we desire to furnish 1 watt of power into a
stipulated load; and further, that we may, by an additional winding or other means,
provide acorrect reflected load to the collector of the transistor related to the desired
power output as follows
VC1.2
RL — (8i)
— 2Po
h Po Po
(neglecting circuit loss ) (80
100 — PI— -F PE
RL = required load
Vcc = collector supply voltage
Po = output power
PI = input power
PE = power dissipated in the transistor
h = efficiency as apercent
In our example, at aworse case efficiency of 50%, .5 = 1/1 -I- PEwhere
PD= 1— . 5= .5 watts.
A device must be chosen which has ahalf watt capability at the highest environ-
mental temperature to be encountered. The 2N2192 series of silicon devices, described
in Chapter 19, will provide ample margin up to their f« at approximately 100 mega-
cycles.
The next concern is that of collector voltage swing. Having selected a supply
voltage, Vcc, the maximum swing will be determined by the value of the load resistor
RL. If RL= co then the worst case occurs and the oscillator tank voltage swing is
the largest. The peak voltage appearing across the tank circuit is
vis Vcc QwL (8k)
RL
coL
Q = RL (assuming an unloaded Q > 10 ) (81)

then
Vcc co' L2
VP (8m)
RL 2
the peak stress across the transistor then becomes
w 2
VCE VCC 1± (8n)
RL2
The peak stress across the emitter base junction is related to VcE through the
transformer turns ratio. So,
Vcc co' L2N
VEB = where N = turns ratio (8o)
RL 2

If the capacitor used to resonate the collector tuned circuit is split and used to
form the feedback divider network aColpitts oscillator results. A simplified ac circuit
for this configuration is shown in Figure 8.5(A). Both Ci and C. together, set the
effective capacity against which L resonates.
Figure 8.5(B) is identical to 8.5(A) except that the emitter rather than the base
is shown at ground. At higher frequencies one may relate nearly any oscillator to the
Hartley or Colpitts types even though part of the capacitive voltage divider is hidden
as transistor capacity. In this figure, C,, connected between collector and emitter of
the transistor, is termed the feedback capacity ofte n s
een in high f re quenc y gro un ded

base oscillators.
Figure 8.5(C) illustrates apractical 10 Kc Colpitts oscillator having atemperature

209
8 OSCILLATORS

(A) (8)

+10v

SIGNAL
OUTPUT

(C)

COLPITTS OSCILLATOR
Figure 8.5

drift rate of .035% CC. This is the total drift rate and is determined by the tempera-
ture rate of incremental permeability of the coil core material. For the purpose of
stability analysis, the Thevanin equivalent of the emitter resistor and the bias divider,
together with transistor hil, and the loaded voltage divider, are lumped to form the
lossy feedback loop.
If very high frequency-stability is desired, the frequency determining network
should be buffered from the amplifier, furnishing its losses, as well as possible. This
provision cushions the frequency determining network from the inevitable changes
induced from electrical environmental variation, but demands higher losses in coupling
networks and a higher amplifier gain to satisfy stability criteria. The alternative to
this is a lower loss frequency determining network. The lower loss network is an
alternative way of saying that high Q is required; where Q is defined as the energy
stored per radian of angular period divided by the energy lost per radian of angular
period. This Q definition is the usual figure of merit associated with resonant circuits,
but is equally applicable to many other networks having a transcendental solution.

CRYSTAL OSCILLATOR
The quartz crystal is an example of avery low loss resonator which will furnish
exceptionally good frequency stability. In Figure 8.6( A,B) the equivalent circuit and
impedance vs. frequency characteristic indicate that two modes of operation exist. The
lower mode is called the series resonant mode, the upper mode the parallel resonant
mode. The series resistance, Rs, of the crystal is a factor of prime importance since
it sets, together with the equivalent inductance, the impedance at mode resonance.
This impedance in turn sets the design of the feedback loop and the frequency stability
of the oscillator. In general, the higher the value of Rs, the tighter the coupling to
produce sustained oscillation and the poorer the frequency as set by changes in elec-
trical environment. The analysis of oscillator starting criteria directly involves both
Rs and L and these should be recognized in writing the expression for loop current gain.
In much of the citizen's band equipment, cost is aconstant challenge and higher
Rs units must be accommodated. Figure 8.6(C) typifies an oscillator designed to

210
 OSCILLATORS 8

IZ1

1
f1 f2
(A) -.' (B)

+22V (OR 12V)

01
Ho OUTPUT

L1-16 TURNS #24 WOUND

ON CTC SPI1C -4L FORM
TAPPED AS SHOWN

(C)

CRYSTAL OSCILLATOR
Figure 8.6

accept higher Rs crystals (to 300) ;and provide adequate output to satisfy most MOPA
applications. The output tap is arranged to match directly a companion grounded
base amplifier (2N2195 — see Experimenter's Chapter). The crystal used is the 3rd
overtone type. Operation at lower power is possible, at 12 volts.

REFERENCES
Glasgow, R. S., "Principles of Radio Engineering," McGraw-Hill Book Company, Inc., New York,
New York (1936)•
Ware, W. A., Reed, H. R., "Communication Circuits," John Wiley & Sons, Inc., New York, New
York (1948).
Shea, R. F., et al, "Transistor Circuit Engineering," John Wiley & Sons, Inc., New York, New York
(1957).

211
8 OSCILLATORS

NOTES

212
 cc
FEEDBACK AND SERVO
o_
AMPLIFIERS

USE OF FEEDBACK IN TRANSISTOR AMPLIFIERS

NEGATIVE FEEDBACK
Negative feedback is used in transistor amplifiers to fix the amplifier gain, increase
the bandwidth (if the number of transistors is less than three),") reduce distortion, and
change the amplifier input and output impedances. Feedback is used in servo ampli-
fiers to obtain one or more of these characteristics.
Gain is reduced at the midband frequencies as the feedback is increased, and the
predictability of the midband gain increases with increasing feedback. Thus, the greater
the feedback, the less sensitive will be the amplifier to the gain changes of its transistors
with operating point and temperature, and to the replacement of transistors.
The output and input impedances of the amplifier are dependent upon the type of
feedback. If the output voltage is fed back, the output impedance is lowered. In con-
trast, feedback of the output current raises the output impedance. If the feedback
remains avoltage, the input impedance is increased, while if it is acurrent, the input
impedance is decreased.

C _ G _ IGH
I+GH H I+GH)
E R-B

B HC
C GE

OUTPUT

SERVO-TYPE FEEDBACK SYSTEM

Figure 9.1

A convenient method for evaluating the external gain of an amplifier with feedback
is the single loop servo-type system as shown in Figure 9.1. (The internal feedback
of transistors can be neglected in most cases.) The forward loop gain of the amplifier
without feedback is given by G and it includes the loading effects of the feedback
network and the load. H is the feedback function, and is usually a passive network.
In using this technique, it is assumed that the error current or voltage does not affect
the magnitude of the feedback function. The closed loop gain is then

_lf CH
R 1+ GH H \ 1 GH

where C is the output function and R is the input. If CH is made much larger than
one, the closed loop response approaches 1/H and becomes independent of the ampli-
fier gain. Thus, CH determines the sensitivity of the closed loop gain to changes in
amplifier gain.
Since CH is a complex quantity whose magnitude and phase are a function of
frequency, it also determines the stability of the amplifier. The phase shift of CH for

213
9 FEEDBACK AND SERVO AMPLIFIERS
all frequencies must be less than 180° for aloop gain equal to or greater than one or
the amplifier will become unstable and oscillate. Therefore, if the number of transistors
in the amplifier is greater than two, the phase shift of CH can exceed 180° at some
frequency, and stabilization networks must be added to bring the loop gain to one
before the phase shift becomes 180°.

ZF

GAIN AND IMPEDANCE

RELATIONSHIPS

YA i Zr
1+AiTZ L ZL

Zr

eL ZL (I L ZF

eg Zg Ig Zg

Z1
(A )BLOCK DIAGRAM Zinee 14-6H I+ A, yZL

Z1 + y ZL

Z0»
zo
I+ A, Z. n

Z r

A, yZL
GH
Z t+ TZL

Y-
I-I- ZL

Zon
CONDITIONS: Z1

Z1
(B)SIMPLIFIED EQUIVALENT CIRCUIT << GH +I
Zr

VOLTAGE FEEDBACK AMPLIFIER

Figure 9.2

Figure 9.2 shows avoltage feedback amplifier where both the input and output
impedances are lowered. A simplified diagram of the amplifier is shown in Figure
9.2( B), which is useful in calculating the various gains and impedances. Z. is the input
impedance of the first stage without feedback, and Z,,,, is the output impedance of the
last stage without feedback. Ai is the short circuit current gain of the amplifier without
feedback (the current in the load branch with 111, = 0for aunit current into the base
of the first transistor). Any external resistors such as the collector resistor, which are
not part of the load, can be combined with Z00. The gain and impedance equations
shown are made assuming that the error voltage (617.) is zero which is nearly correct
in most cases. If this assumption is not made, the loop gain of the amplifier can be
derived by breaking the loop at y-y' and terminating the point y with Zi.'" The loop
gain is then if/ib, with the generator voltage set equal to zero. Since the loop is a

214
 FEEDBACK AND SERVO AMPLIFIERS 9
numeric, the voltage and current loop gains are identical. The loop gain is then
Ai(Zi? ( Z,
(9a)
Zr Z,') Z,
where
ZLZon
ZL = = ZL7, and
Z..

Z,' = Z Z'
Z, Z,
Notice that if Z, > > Z, and ZF> > Z,, then the loop gain is very nearly equal to CH
as given in Figure 9.2.
The input impedance of the amplifier is reduced by 1 CH, while the output im-
pedance is also decreased.
Figure 9.3 shows acurrent amplifier where both the output and input impedances
are increased. The loop is obtained by breaking the circuit at y-y' and terminating
points y-a with Z,. The loop gain is and is approximately equal to
yAiFZ
(9b)
Zg -F Z,

GAIN AND IMPEDANCE

RELATIONSHIPS

A, yZ,

IL ZgT Zi
is - I+A iyZ F

Zi+2,3

e t_ A i Z L
(A) BLOCK DIAGRAM eg + Ai yZ F

Zi+Z 9

Z .2 1 (4-A i YZ F

Zo =Z 0«,(+A, ZF

Zi+Zg

Ai YZE
GH
2,1-Z 9

-
I+ ZL

Zo„

I
9 Zg

CONDITIONS:

(B) SIMPLIFIED EQUIVALENT CIRCUIT Z F«Z I;Z F<<Z I_

CURRENT FEEDBACK AMPLIFIER

Figure 9.3

POSITIVE FEEDBACK
Positive feedback can be used without stability considerations if the loop gain is
less than unity. (It can also be used with a loop gain greater than unity if it is used
in conjunction with negative feedback, and stability is properly considered. )"• 5) If
positive feedback is applied as acurrent to the transistor base, the input impedance is

215
9 FEEDBACK AND SERVO AMPLIFIERS

increased, while if it is applied as avoltage in series with the emitter, the input imped-
ance is decreased.
A common example of positive feedback with less than unity loop gain is the boot-
strapping of the biasing resistors in a transistor amplifier. This is done to minimize
the shunting effect these resistors have on the input impedance of the circuit. Figure
9.4( A) shows atransistor amplifier biased in aconventional manner. The transistor's
input impedance ( Zin t)seen at the base is

Zifl t hf. REre ± r. (9e)

h.. (RE- I
-RL) ± re
where it is assumed RE> > r, and re > > RT.

INPUT
INPUT
ein

BOOTSTRAPPING THE
BASIC CIRCUIT
BIASING RESISTORS

(A) (B)

BOOTSTRAPPING THE BIASING

RESISTORS AND COLLECTOR
(C)

BOOTSTRAPPING
Figure 9.4

Thus, to increase the transistor's input impedance, it is necessary to increase RE;

however, an upper limit of value re is reached when hr. RE>> re. While this may be
in the order of several megohms, the impedance seen at the input terminals is Zin t in
parallel with the parallel combination of RI and R2. The value of these resistors are
determined by the biasing requirements of the circuit, and consequently they reduce
the input impedance of the circuit.

216
 FEEDBACK AND SERVO AMPLIFIERS 9
Figure 9.4 shows how the bias resistors are bootstrapped in order to reduce their
shunting effect on the transistor input impedance. The circuit input impedance (Zin c )
becomee
Zin c = R3' REhr. (9d)
R3' + REhr.
where R3' = R3/I — A; where it is assumed that the reactance of the capacitor
is negligible at the frequencies of interest; and where hf. RI << re and Hr. << re/ht..
A is the voltage gain between the base and the emitter or e2/ein. It is given by
Rp
A — (9e)
n, (1— a) -I- r, -I- RP
where
1_ 1 ± 1 ± 1
and r" M26
Rp — TI E R4 RI IE
Since the voltage gain can be made near unity, R4' can become very large. For exam-
ple if Rp is selected to be 3.6K and the transistor is a2N1711 (biased at 1ma and 10
volts) with an hr. of 100 and an, of 1000 ohms, then A 0.99. R3' becomes 100 R3.

+28V

2NI613 OR
2N2049

e2

SHIELD GUARD

BOOTSTRAPPED EMITTER FOLLOWER

Figure 9.5

In some applications the input bootstrapping becomes so effective (through a

judicious choice of bias conditions and transistors) that the amplifier input impedance
is again limited by re. This situation can be remedied by bootstrapping the collector as
shown in Figure 9.4(C). Another stage of current gain is provided by Q2, and the
voltage en2 is coupled back to the collector of QI by C2. Bootstrapping the collector
also reduces the effect of the collector to base capacitance, C.1,, on the input imped-
ance. Figure 9.5 shows a bootstrapped emitter follower with an input impedance of
about 20 megohms and with a band width of 1cps to 5 kc. The upper frequency is
limited by the hf. cutoff frequencies of QI and Q2, since they are respectively biased
at 10 and 100 pamperes.

SERVO AMPLIFIER FOR TWO-PHASE SERVO MOTORS

PREAMPLIFIERS
Figure 9.6 shows a two stage preamplifier which has a low input impedance, and
which is quite stable in bias point and gain over wide temperature ranges. In addition,
no selection of transistors is required.

217
9 FEEDBACK AND SERVO AMPLIFIERS

Because only two stages are involved, the amplifier is stable, and frequency stabili-
zation networks are not required. The current gain io/iin is approximately RE/RF if the
generator impedance and RE are much larger than the grounded emitter input imped-
ance of Ql. RF should not exceed afew hundred ohms because it contributes to the
loss of gain in the interstage coupling network. The loss of gain in the interstage
coupling is
K= - — Z1 ' — (9f)
Z„,' ni.2 nfe2 nE
where Z.,1' is the parallel combination of R2 and the output impedance of Ql. The loop
gain then is approximately
K RF
(hr., hf.
R: heI+R5
lR5 ) (9g)

22K

01 =Q2 rG E. 2N335,4C30,
4C3I, OR 2N336

'o RE RL ,
— — Fvrt
ii n RF R4

400 CYCLE PREAMPLIFIER FOR OPERATION IN

AMBIENTS OF —55°C TO 125°C
Figure 9.6

Because the feedback remains acurrent, the input impedance of this circuit is quite
low; less than 100 ohms in most cases. This preamplifier will work well where current
addition of signals is desired and "cross-talk" is to be kept to aminimum.
Bias Design Procedure for Stage Pair
(Reference Figure 9.7 )
1. The values of EBB, IEly 1E2, VCEI, and VcE2 are selected by the designer to be com-
patible with the constraints imposed by the circuit and component specifications.
Thus, IE2 and EBB must be large enough to prevent clipping at the output under
conditions of maximum input. For designs which must operate in wide tempera-
ture environment, the bias currents and voltages ( IEand VcE) of QI and Q2
should be approximately equal to those used by the manufacturer for specifying
the "h" parameters. (For the 2N335, IEi = 'El = 1ma and VCE = 5to 10 volts.)

218
 FEEDBACK AND SERVO AMPLIFIERS 9

IN

Figure 9.7

2. For good bias stability, L; Rl should be five to ten times VEB,, i.e., 3 to 5 volts;
thus, knowing LEI, RI can be found. L should also be five to ten times larger
than

3. R2 = Ebb — VEEI ¡El RI

(9h)
IFI ¡in
where
y I
Fl y
/no — - ,1(1102, IIt I ICROI (9i)
n E2 W JSI

and where hrE, and hFE2 are the typical dc current gains at the particular bias
conditions. Ic80 is the collector-base leakage current at the temperature and
collector-base voltage being used.

4. R5 = I
F, 111 VEgi
I5 (9i)

where L is selected to be 5to 10 times larger than 1Ri.

5. RE= WEI VERI VER2

15 181 (9k)

6. R3 = IF, RI -I- WEI — \TER:

(91)
1E2 — (I5 IB1 )

7. R4 = EBB — IF:2 R3
2IE2 (9m)

8. RF= RF
(9n)

where G, is the desired closed loop ac current gain. (The emitter by-pass
capacitors are selected to present essentially a short circuit impedance at the
lowest frequency of interest.)
Figure 9.8 shows a three-stage 400 cycle direct-coupled preamplifier with good
bias stability from —55°C to 125°C. The de biasing of the circuit is discussed in Chap-
ter 4, with the collector bias voltage of Q3 being given by equations (411) and (4mm).

219
9 FEEDBACK AND SERVO AMPLIFIERS

The various ac gains and impedances can be calculated from the equations of Figure
9.1 with the exception that the ac feedback is now approximately
RI? \ (R10\ (9o)
R8 ) R9
where 1/Rn' = 1/R. 1/Ro. + 1/R7 and Ro3 is the output impedance of Q3. This
assumes that the input impedance of QI is much less than RI and R9. The value of
R10 determines the closed loop gain, while the values of C31, C.., R4, and R6 are used
to bring the magnitude of the loop gain to unity before the phase shift reaches 180°.
The values required for these capacitors and resistors are dependent upon the maxi-
mum expected loop gain.

39K

01.02=03.GE 2N335,4C30

THREE -
STAGE 400 CYCLE DIRECT -
COUPLED PREAMPLIFIER

Figure 9.8

DRIVER STAGE •
Because the output stages of servo amplifiers are usually operated either Class B
or amodified Class B, the driver must provide phase inversion of the signal. In most
cases, this is accomplished by transformer coupling the driver to the output stage. The
phase shift of the carrier signal in passing through the transformer must be kept small.
However, since the output impedance of the transistor can be quite large, the phase
shift can be large if the transformer shunt inductance is small, or if the load resistance
is large as shown in Figure 9.9. The inductance of most small transformers decreases
very rapidly if adc current flows in the transformer. Therefore in transformer coupling,
the phase shift of the carrier is reduced to aminimum if the de current through the
coupling transformer is zero, or feedback is used to lower the output impedance of
the driver.

220
 FEEDBACK AND SERVO AMPLIFIERS 9

h fe

TS
IL = I y1 0

yR,2

Ro
I =L- II
Y -
I TRANSISTOR LOW FREQ. II TRANSFORMER Ro ÷ RI!
I EQUIV. CIRCUIT ii 8 REFLECTED
S = LAPLACE
I Ii LOAD TRANSFORM.
I
.- — — — —' 1---- — — — — i Lp = PRIMARY SHUNT L

= LOAD REFLECTED
- TO PRIMARY

CARRIER PHASE SHIFT

DUE TO TRANSFORMER COUPLING
Figure 9.9

Figure 9.10 shows amodified "long tail pair" driver. In this case QI and Q2 oper-
ate Class A, and the quiescent collector current of QI and Q2 cancel magnetically in
the transformer. Transistor QI operates grounded emitter, while Q2 operates grounded
base. Separate emitter resistors Ri and Ri are used rather than a common emitter re-
sistor in order to improve the bias stability. The collector current of QI is approximately
ha.' ibl, while the emitter current of Q2 is (hr. 1) iba. Since Q2 operates grounded
base, the collector current of Q2 is —hfb2/(hiel + I) ibl or —hr. Iba if the current gain
of QI and Q2 are equal. Thus push-pull operation is obtained.
In order to stabilize the driver gain for variations in temperature and interchange-
ability of transistors, another transistor can be added to form a stage pair with QI as

EBB

C3 = TRANSFORMER
TUNING CAPACITOR

01 = 02 = G. E 2N656A
2N2017
2N2 108

TWO-STAGE CLASS "A"

PUSH-PULL DRIVER
Figure 9.10

221
9 FEEDBACK AND SERVO AMPLIFIERS 11111MIIIMIIIMMIIMIIIIIIIMMII

TO
OUTPUT
TRANSISTORS

30V

9.IK QI =02 G.E. 2N656A, 2N2017, OR 2N2I08

03 G.E. 2N335A, 2N760
15K =1C2 clONA.
C4 =ADJUST TO TUNE T

"STABLE" 400 CYCLE DRIVER

Figure 9.11

shown in Figure 9.11. The gain of the driver is then very stable and is given approxi-
mately by
¡el iC2
(9p)
—

is — is
OUTPUT STAGE
The output stages for servo amplifiers can be grounded emitter, grounded collector
or grounded base. Output transformers are generally not required because most servo
motors can be supplied with split control phase windings. Feedback of the motor con-
trol phase voltage to the driver or preamplifier is difficult if transformer coupling
is used between the driver and output stages. If ahigh loop gain is desired, the motor
and transformer phase shifts make stabilization of the amplifier very difficult. One
technique which can be used to stabilize the output stage gain is to use a grounded
emitter configuration where small resistors are added in series with the emitter
and the feedback is derived from these resistors. The motor time constants are thus
eliminated and stabilization of the amplifier becomes more practical.
A second technique which results in astable output stage gain and does not require
matched transistor characteristics is the emitter follower (common collector) push-pull
amplifier as shown in Figure 9.12. Also it offers the advantage of a low impedance
drive to the motor. A forward bias voltage of about 1.4 volts is developed across DI
and D2, and this bias on the output transistors gives approximately 20 ma of no signal
current. At lower levels of current the cross-over distortion increases and the current
gain of the 2N2202 decreases. D3 and D4 protect the 2N2202's from the inductive

222
 FEEDBACK AND SERVO AMPLIFIERS 9
load generated voltages that exceed the emitter-base breakdown. The efficiency of this
circuit exceeds 60% with a filtered de voltage supply and can be increased further

0[

03

VOLTAGE
600 fl SUPPLY
INPUT Q I. 02 G.E. 2N2202
2N2203
2N2204
2N2I96
2N2197
(TUNED
7F2
CONTROL
OR 7F4
04 PHASE OF
SERVO
MOTOR)
02

TRANSFORMER-NI: N2: N3 .1
D I, D2, D3, 04 - IN1692S

SERVO MOTOR DRIVE CIRCUIT

(1 TO 4 WATTS)

Figure 9.12

by using an unfiltered rectified ac supply. This unfiltered supply results in lower

operating junction temperatures for the 2N2202's, and in turn permits operation at a
higher ambient temperature. The maximum ambient operating temperature varies
with the power requirements of the servo motor and the type of heat radiator used
with the 2N2202. It is practical to attain operation in ambients to 125°C.
Another technique which results in a stable output amplifier gain over wide am-
bient temperature extremes and which is compatible with low gain transistors is shown
in Figure 9.13. In this case, a grounded base configuration and a split control phase
motor winding are used. The driver is coupled to the output stage by means of astep-
down transformer, and the current gain occurs in the transformer since the current
gain of the transistors is less than one. The current gain is 2aNpi/Nsi if the drivers
are operated Class A such as shown in Figures 9.10 or 9.11. The negative unfiltered dc
supply and diode DI are used to operate the transistor Class AB and eliminate cross-
over distortion. As the signal increases, the diode DI becomes conductive and shunts
the bias supply. The operation of the output stage thus goes from Class A to Class B.
An unfiltered de is used for the collector supply to reduce transistor dissipation.
If saturation resistance and leakage currents are neglected, 100% efficiency is possible
under full load conditions with an unfiltered supply. The transistor dissipation is
given by
EcNi 2 [ a az + Rs )] ±
p
(9q)
4RL RL

where PL is the dissipation due to leakage current during the half-cycle when the
transistor is turned off, a is the fraction of maximum signal present and varies from
0to 1, Rs is the saturation resistance, RLis the load resistance, and Ecm is the peak
value of the unfiltered collector supply voltage. If PL is negligible and Rs/RL << 1,

223
9 FEEDBACK ANI) SERVO AMPLIFIERS

02

TI
CONTROL
PHASE
Np,
TO
DRIV ER 4
TRANSISTORS Np2

4 MOTOR

Cll. 02. GE 2N2203 OR

7F3
DI .GE IN676
TO •
Np
LINE
Ns
C IS ADJUSTED FOR MAXIMUM QI
STALLED TORQUE

—' /\7—E-L
F3A1

EB

GROUNDED BASE
SERVO OUTPUT STAGE
Figure 9.13

then maximum dissipation occurs at a= 1/2 or when the signal is at 50% of its maxi-
mum. Thus for amplifiers which are used for position servos, the signal under steady-
state conditions is either zero or maximum which are the points of least dissipation.
The peak current which each transistor must supply in Figure 9.13 is given by
2W
= (9r)
nem

where W is the required control phase power. The transistor dissipation can then be
written in terms of the control phase power

P= —
W [ a— a2 (1 )] + PT (9s)
2
The driver must be capable of supplying apeak current of

(9t)
a Nri
where ais the grounded base current gain of the output transistor.
Figure 9.14 shows a complete servo amplifier capable of driving a 3 watt servo
motor in an ambient of —55°C to 125°C (if capacitors capable of operation to 125°C
are used). The gain can be adjusted from 20,000 to 80,000 amperes/ampere by adjust-
ing RFin the driver circuit. The variation of gain for typical servo amplifiers of this
design is less than 10% from —55°C to 25°C, and the variation in gain from 25°C to
125°C is within measurement error. The variation in gain at low temperature can be
reduced if solid tantalum capacitors are used instead of wet tantalum capacitors. The
reason is that the effective series resistance of wet tantalum capacitors increases quite
rapidly at low temperatures thus changing the amount of preamplifier and driver feed-
back. The effective series resistance of solid tantalum capacitors is quite constant with
temperature. Many 85°C solid tantalum capacitors can be operated at 125°C if they
are derated in voltage.

224
 PREAMPLIFIER DRIVER OUTPUT
07

+60V

TO
+50 V PEAK
UNFILTERED
FULL WAVE
RECTIFIED 400 CYCLES

INPUT OH

20p.f TO -50V PEAK

UNFILTERED FULL
WAVE 400v

71,-12.5 ,1STEP DOWN (TURNS RATIO)

24K
- GEIN676

NOTES , I. ADJUST RF FOR DESIRED GAIN.

2. C9 ADJUSTED TO TUNE MOTOR FOR
01,02,03, -GE 2N335 OR GE 2N336
MAXIMUM STALLED TORQUE.
04,05,-GE 2N656A OR 2N2017 3. C6 ADJUSTED TO TUNE Ti

06 ,07 ,-GE 2N2202, 2N2203, OR 7F3

3 WATT 400 CYCLE SERVO AMPLIFIER FOR -55°C TO 125° OPERATION

Figure 9.14
9 FEEDBACK AND SERVO AMPLIFIERS

REFERENCES
a> Hurley, Richard B., "Designing Transistor Circuits — Negative Feedback for Transistor Amplifiers,"
Electronic Equipment Engineering, February 1958.
(2> Hellerman. H., "Some Stability Considerations in the Design of Large Feedback Junction Transistor
Amplifiers," Conference Paper #CP58-87, presented at the 1958 AIEE Winter General Meeting.
(a) Blecher, F.H., "Transistor Circuits for Analog and Digital Systems," Bell System Technical
Journal, Vol. 35, March, 1956.
(4) Looney, James C., "How to Analyze Feedback in Transistor Amplifiers," Electronic Industries,
September 1961.
Middlebroud, R.D., and Mead, C.A., "Transistor AC and DC Amplifiers with High Input Imped-
dance," Semiconductor Products, Vol. 2, No. 3, March 1959.
(
6)Bernstein — Bervery, Sergio, "Designing High Input Impedance Amplifiers," Electronic Equipment
Engineering, August-September, 1961.

NOTES

226
REGULATED DC SUPPLY AND eL. 1 o
INVERTER CIRCUITS

REGULATED DC SUPPLIES
The regulated supply of Figure 10.1 is a conventional circuit using a series regu-
lating element. With QI mounted on a21 2 "xPk" x%2 " aluminum fin the circuit can
/
operate in an ambient temperature up to 55°C. The 2N2108 can be mounted with a
washer as shown in Chapter 11.

IR AD
F-92A 01
2N2I97
OR
2N2106

REGULATED DC VOLTAGE SUPPLY

Figure 10.1

Q1 requires a VeER capability equal to the unregulated output voltage of the

bridge. The voltage rating for Q2 must be equal to the difference between the regu-
lated output and the Zener voltage.
Figure 10.2 shows equal regulating ability for all load currents to 350 ma, and 2%
voltage regulation at 400 ma. Peak-to-peak output ripple of this circuit is less than 0.3
volt at 400 ma load current, and 0.01 volt at no load; output impedance is less than
2 ohms from dc to 20 cycles and then decreases to less than 1 ohm at 200 ma load
current. The output voltage has very little overshoot with step load functions.

50

49
I-
0 48
a. a
ao 47-J
>

46
o (00 200 300 400 500

LOAD CURRENT (MILLIAMPERES)

OUTPUT VOLTAGE VS. LOAD CURRENT

Figure 10.2

Improved regulation is obtained by using a Darlington connection for the series

regulating element (Q1 and Q2) as in Figure 10.3. This regulated de supply also fea-

227
10 REGULATED DC SUPPLY AND INVERTER CIRCUITS

tures higher current capability. The supply is designed for output currents up to
2amps average, or 3.5 amps peak. Output voltage can be adjusted from 45 to 65 volts
with R7, but for operation below 60 volts output, the total resistance of R2 and R3
should be increased by apercentage equal to the decrease in output voltage. This will
maintain the 22 volt Zener dissipation within its rating.
TRIAD
N-471A
2:1
01
84V(NO LOAD) 2N I970 (DELCO)
72V RI

LOAD CURRENT (D.C.) REGULATION

1/2 AMP 0.50 %

1AMP 0.72%

2 AMP 2.1%

REGULATED DC VOLTAGE SUPPLY

Figure 10.3

Transistors Q2 and Q3 should each be mounted on a heat dissipator capable of

dissipating approximately 2 watts; such as an IERC #LP5A1B (135 West Magnolia
Blvd., Burbank, California), or a Thermolloy Company #2210 (4417 North Central
Expressway, Dallas, Texas). QI should be mounted on aheatsink that has a thermal
resistance of less than 2.5°C per watt; such as the Delco Radio heatsink #7270725. The
1N3570's can be mounted with insulating hardware to a metal surface of 10 square
inches or more.
Output ripple is less than 1millivolt rms at no load and increases to 60 millivolts
peak-to-peak at 2amps dc load current; output impedance at 0.5 amp dc load current
is less than 0.5 ohm clown to dc. There is negligible shift in output voltage with step
load current from 0 to 1amp. The output overshoots approximately 5% (decaying in
0.10 sec. )with step load change from 1amp to zero.
The 6.2 volt Zener diode together with RI limits the peak output current to
approximately 5.5 amps. At higher currents the emitter-base of QI will have less than
0.66 volt drive, thus the output voltage will decrease. If 5.5 amps is sustained for about
100 milliseconds, the 3amp fuse will open.

PRECISION POWER SUPPLIES USING REFERENCE AMPLIFIERm

The General Electric types RA-1, RA-2 and RA-3 are Reference Amplifiers (see
C.E. Pub. 35.35) designed for applications in regulated voltage or current sup-
plies where they can serve the dual function of a voltage reference element and an
error voltage amplier. They are integrated devices comprised of a Zener diode and
NPN transistor in a single pellet. Cancellation of temperature coefficients between the
Zener diode and the transistor result in atransfer characteristic having a very low net

228
 REGULATED DC SUPPLY AND INVERTER CIRCUITS 10

temperature coefficient. Temperature differentials between the Zener diode and the
transistor are minimized owing to the integrated structure with aconsequent reduction
in the transient variation and long term drift of the reference voltage. Reference Ampli-
fiers offer significant advantages in performance, circuit simplicity, and overall cost.
The temperature coefficient of the Reference Amplifier is determined by

% per .c Vref Ti —Vref e 25°C X 100% (10a )

(Vref 250c) (Ti — 25°C)

where V„f T ,is the reference voltage at temperature Ti and V„fe 25°C is the ref-
erence voltage at 25°C. The temperature coefficient of the Reference Amplifier as
defined above shall not exceed the specified maximum value at any temperature over
the entire operating temperature range. This definition is illustrated in Figure 10.4
together with a curve of versus temperature for a typical unit. Note that the
curve must lie entirely within the triangular areas to satisfy the specifications for the
type RA-2B.
In contrast, the common method of specifying the temperature coefficient of acom-
pensated Zener diode is to determine the voltage variation at each temperature extreme
equivalent to the specified temperature coefficient and to guarantee only that this volt-
age variation will not be exceeded at temperateres between 25°C and the tempera-
ture extreme. This definition is illustrated in Figure 10.4(B) together with acurve of
W. versus temperature for a typical unit. Note that although the temperature range
and maximum temperature coefficient is the same as for the Reference Amplifier, the
voltage variation is considerably higher for the Zener, particularly for temperatures in
the vicinity of 25°C.
The temperature coefficient specification applies only when the biasing conditions
are identical to those given in the specification. Increasing the collector current or the
bias current will tend to make the temperature coefficient more positive.

+I7.5W

+II.2W

U ref
150C -55C 150C
-55

-11.2W -11.2MV

".-17.5MV i 17.5W
(A) (13)

TEMPERATURE COEFFICIENT
Figure 10.4

A base source resistance, RR, is included in the specification of the reference volt-
age temperature coefficient to duplicate the effect of the resistance divider which is
used in most power supplies to set the output voltage. It is desirable to choose the
resistance of the divider as low as possible to maximize the gain of the Reference Ampli-
fier and to reduce the effects of In, and 11FE on the reference voltage. However, consid-
erations such as power dissipation in the divider and current drain will set a lower
limit on the resistance which can be used. In consideration of these requirements a
compromise value of 1000 ohms has been chosen for RB.
The transfer characteristic of the Reference Amplifier as shown in Figure 10.5 is of
importance in the design of a regulated power supply since it determines the change
in collector current resulting from asmall change in the reference voltage at the base.

229
10 REGULATED DC SUPPLY AND INVERTER CIRCUITS

The circuit transconductance, defined as the ratio of collector current change to refer-
ence voltage change, is equivalent to the slope of the curve in Figure 10.5.

gm =V c,Iz constant ) (10b )

dV,of

7.10

Iz.5MA

6.80

0.03 0.05 0.07 0.1 02 03 05 0.7 I 2 3

COLLECTOR CURRENT-Ic-MILLIAMPERES

TRANSFER CHARACTERISTICS OF REFERENCE AMPLIFIER

Figure 10.5

The circuit transconductance includes the effects of the base source resistance and
the dynamic Zener impedance and hence is lower than the transconductance of a
transistor common emitter amplifier stage (1/111b). The circuit transconductance is
approximately

(10e)

where rz is the dynamic resistance of the Zener diode and all parameters are measured
at the specified bias conditions.
The dynamic resistance of the Zener diode in the Reference Amplifier is relatively
low as indicated by Figure 10.6 from which it is seen that at low current levels rz is
lower than the dynamic resistance of a forward biased silicon diode. The low value
of rz permits the Reference Amplifier to be operated at values of collector current as
low as 0.5 ma without additional biasing current for the Zener diode, thus permitting
asimplification in the design of regulated power supplies without requiring acompro-
mise in performance.
The simplest version of aregulated power supply using the Reference Amplifier is
shown in Figure 10.7. This supply is designed for an output of 12 volts at currents
up to 100 ma. The 180 ohm resistor provides short circuit protection, limiting the
output current to less than 200 ma. The 100 gfd capacitor and the 4.7K resistors
provide an effective filter for the base current to the 2N2108 transistor, reducing the

230
 REGULATED DC SUPPLY AND INVERTER CIRCUITS 10

‘.4.,
N
N
70 \
N
‘ TYPICAL FORWARD
50
\ BIASED DIODE

\
\
ZENER DYNAMIC RESISTANCE-rz-OHMS

30 \
\
\
20
\
\
ZENER \ ZENER
10 PERCENTILE \\ 90 PERCENTILE

10 \
7 "...

\ ....,.
3

I
0.3 05 0.7 1 2 3 5 7 10 20 30
TOTAL ZENER CURRENT-MILLIAMPERES

REFERENCE AMPLIFIER ZENER DYNAMIC RESISTANCE

Figure 10.6

G.E. 7A32
OR
2N2I08+
DELTA 207
1800 HEAT SINK
IOW
• +12

500µf + 1000 T 25µ1

50V 50V
L. 25V

25V
1
A 4 4

1
- •
INI69; (4)
• • • - O..-

REGULATED DC VOLTAGE SUPPLY

Figure 10.7

output ripple to less than 80 microvolts under full load conditions. Output impedance
of the supply is approximately 0.65 ohms. For line voltage variations of ±10% the
output voltage regulation is better than ±-0.3%.
The variable 8 to 25 volts supply in Figure 10.8 limits the current to 100 ma for
protection against output shorting. Limiting occurs when the voltage drop across R2
exceeds 6.8 volts and cuts off the current flow in the 2N1924, which is the bias current

231
10 REGULATED DC SUPPLY AND INVERTER CIRCUITS

2N2I97
(GE.)
ON HEAT SINK
24 XL67.
R2
•
GEM
RI
2W
azy 2.7
84 e2.5K
VOLTAGE
IN4009
ADJUST

2NI9
20 ±-13-25V
IK
500
50V
RAI
25V
IA REFERENCE
4.7K - IK

.
005 T "PLIFIER

51692

GENERAL PURPOSE POWER SUPPLY WITH CURRENT LIMITING

Figure 10.8

source for the 2N2197. In operation the 2N1924 functions as aconstant current source
and improves regulation with input voltage variations to the regulator circuit. The
circuit of Figure 10.8 has 0.02% regulation for line voltages from 105 to 130 volts.
The output impedance is 1.0 ohm and the ripple is 200 itv at 20 volts, 100 ma.
Output currents up to 300 ma can be obtained by reducing R1 and R2 and using
asuitable heatsink for the 2N2197. The heatsink should be large enough to keep the
case temperature below 100°C at minimum output voltage, maximum output current,
and maximum line voltage.

PRECISION REGULATED VOLTAGE SUPPLY

Use of the Reference Amplifier in a precision 12 volt, 200 ma regulated voltage
supply is shown in Figure 10.9. In this supply the 2N1131 PNP silicon transistor is
used to regulate the collector current of the Reference Amplifier. The output current
of the 2N1131 will vary with line voltage due to the finite output resistance of the
transistor and the voltage divider action between R2 and the dynamic resistance of
DI and D2. Resistor R3, added to compensate for these effects, makes the output
current of the 2N1131 almost completely independent of changes in line voltage. For
a-± -10% change in line voltage, the variation in output voltage is typically less than

±0.001% and by adjustment of R3 can be reduced to less than 1-.-0.0001%. Diode

-

D2 provides temperature compensation for the base-emitter diode of the 2N1131.

RI
2211 220 2N2I97
2W 2W
0+12V

10V

117
VAC 25µf
2NI131 25V
(GE)

T
- 005 RAS
25V
R2
IA 2.2K
4,7K 23
R .2 14

• • • • • 0
IN3639(4)

PRECISION REGULATED VOLTAGE SUPPLY

Figure 10.9

232
 REGULATED DC SUPPLY AND INVERTER CIRCUITS 10

This compensation is not critical since, owing to the gain of the Reference Amplifier, a
1% change in the collector current of the 2N1131 has only the effect of a 0.01%
change in the reference voltage.
A Darlington transistor connection is used for the series regulator. The current
gain of the Darlington is typically 10,000 at 100 ma so the normal variation of collec-
tor current of the Reference Amplifier over the full range of output current will be
10 microamperes, or only 2% of the nominal collector current.
In a constant-voltage power supply, regulation of the collector current in the
Reference Amplifier allows the collector-to-base voltage to be adjusted to the 3 volt
nominal operating value by adding resistor R5 between the base of the series regu-
lator and the collector of the Reference Amplifier. R4 limits any surge current via the
base-collector path in the 2NI131.
Sharp current limiting is provided in this circuit at 300 ma by RI and D3. When
the IR drop across RI exceeds 6 volts, diode D3 will conduct decreasing the emitter
current to the 2N1131 and thus reducing the base current to the 2N1711. The output
impedance of the power supply is approximately .012 ohm; output ripple and noise
at full load is less than 300 microvolts peak-to-peak. Voltage regulation for 100 ma
load change is 0.01%. Temperature stability of the supply is mainly dependent on
the temperature coefficient of the reference amplifier. An overall temperature coeffi-
cient of -
±0.002%/°C can easily be achieved using the RA-2B.

PRECISION CONSTANT CURRENT SUPPLY

In many applications requiring precise measurements of dc parameters, it is more
convenient to use acurrent reference rather than a voltage reference. However, there
is apopular misconception that precision current sources are more difficult to achieve
than precision voltage sources.

-20V 03 RAIS

PRECISION CONSTANT CURRENT SUPPLY

Figure 10.10

It will be noted that the current reference supply is similar to the voltage reference
supply shown in Figure 10.9, but is somewhat simpler. The Reference Amplifier in
Figure 10.10 acts together with transistor Q2 to maintain the voltage constant across
R4 at V,.r. The current through R4 equals the current through the load except for
the relatively small base currents of Q2 and Q3.
V f
ILOAD = — 1112 1113 (10d)
R4
where I B2 is the base current to Q2 and IB3 is the base current to Q3. Since these cur-
rents have opposite signs in the above expression, they can be made to compensate for

233
10 REGULATED DC SUPPLY AND INVERTER CIRCUITS

each other for changes in ambient temperature by proper selection of transistors and bias
points. However, since the base currents have only a second order effect on the tem-
perature coefficient of the output current, it is generally more practical to include the
base current changes in the overall temperature compensation.
Transistors with typical values of hr0 and h. were used to evaluate the circuit.
The Reference Amplifier had a temperature coefficient of +0.002%1°C. Resistor R4
is a Precision Resistor Corporation wire wound type having specified temperature
coefficient of ±-20 ppm per °C. All other resistors, being much less critical than R4,
are standard composition types. During performance evaluation, output current was
measured across aprecision resistor, in place of load, using a Keithley 660 differential
voltmeter; output impedance was measured by inserting a resistor in series with the
load with a value chosen to give a 10 volt drop and noting the resultant change in
voltage across the load. The entire circuit was inserted in a temperature chamber.

TEST CONDITION NO. 1: Io = 10 ma (R4 = 700 ohms)

Change in current for 10 volts change in V,
aIo < 100 na (0.001% or 1ppm per volt)

Output impedance
> 100 megohms
Change in current with temperature (25°C to 55°C )
iI o = +5.0 a (+0.0013% per °C)

TEST CONDITION NO. 2: Io = 1.0 ma (R4 = 7K)

Output impedance
> 1300 megohms

Change in current with temperature (25°C to 55°C)

àIo = —0.2 ita (—0.0008% per °C)

Drift (15 hours)

<0.01% (limited by measuring resistor)

No attempt was made to minimize the temperature coefficient by trimming the

circuit values. This could easily be done by adjusting the bias current to the collector
of the Reference Amplifier by changing the value of RI. The specification sheet for
RA-1 shows change in reference voltage vs. temperature for different collector currents.

PARALLEL INVERTERS
The parallel inverter configuration shown in Figure 10.11 provides an output that
is essentially asquare wave. An ac input can be rectified to provide the primary power
for the inverter, in which case it will function as afrequency changer. A square wave
drive to this inverter causes QI to conduct half the time while Q2 is blocking, and
vice-versa. In this manner, the current from the supply will flow alternately through
the two sides of the transformer primary and produce an ac voltage at the load.
It may be desirable to incorporate the feedback diodes DI and D2 if the circuit is
to be lightly loaded or operated under open circuit conditions. For reactive loads these
diodes can conduct to supply the out-of-phase portion of the load current. When the
inverter switches from QI to Q2 an inductive load prevents the main load current
from reversing instantaneously, so transformed load current must flow through D2 and
back into the de supply until the load current reverses. The feedback diodes prevent
the voltage across either half of the primary winding from exceeding the supply volt.
age. These diodes not only maintain a square wave output under all load conditions,
but also decrease the voltage requirements for QI and Q2.

234
 REGULATED DC SUPPLY AND INVERTER CIRCUITS 10

500,11
LOAD

T3

01 02
DC TO AC 2N2I97 pI D2' 2N2 97
(SQUARE WAVE)
INVERTER
Figure 10.11
TI OF F10.10.12 TI OF FIG.10.12

The de source should have a low transient impedance, and a capacitor on the
output of the de supply is usually required so it can accept power as well as supply
power. It is often important to have this capacitor (Cl) right at the inverter itself as
shown in Figure 10.11 since the inductance of the supply leads of afew feet in length
represents an undesirable impedance during the gsec switching intervals.
For a driven transistor inverter, it is desirable to select a transformer and core
with a volt-second saturation capability that is at least two times the actual circuit
requirements. The leakage inductance should be held to a minimum since the trans-
former will be subjected to rapidly changing currents during the switching interval.
Bifilar transformer winding is usually used to obtain tight coupling between the two
primary windings. Since the inverter output transformer (T3) cannot be allowed to
saturate, its design must either incorporate an air gap, have a high ratio of saturation
to residual flux density, or be used with predictable reset circuitry.
The inverter circuit of Figure 10.11 was operated using two stacked AJ-H12
(Arnold) C-cores (4mil), in transformer T3. The core gap spacing was .02 inch. This
gives about a2:1 volt-second capability at 400 cycles.
The square wave inverter drive is easily obtained with a transistor multivibrator
that uses a unijunction transistor to stabilize and control the frequency as in Figure
10.12. This circuit provides a symmetrical square wave drive which avoids second
harmonics in the output and also a de component in the inverter, tending to saturate
the transformer. With this drive circuit, the inverter output voltage waveform across
the load is shown in Figure 10.13. The efficiency of the square wave inverter (Figure
10.11) is 80 to 85% in the 400 to 3200 cycle frequency range at 16 watts output.
General Electric transistor type 11C10B1 can be used for Q1 and Q2 of Figure 10.11
with both improved efficiency and waveform at 3200 cycles. The efficiency is 92% at
20 watts output. Type IICIOB1 has lower saturation voltage because of epitaxial
construction and also higher switching speeds. Q1 and Q2 should each be mounted
on aheatsink capable of dissipating 1.75 watts.
The circuit of Figure 10.12 is aslightly modified "hybrid-multivibrator," described
in more detail in Chapter 13. The unijunction transistor provides a source of short,
precisely timed negative pulses with the period between pulses depending on the
C1R2 time constant. These pulses are coupled to the common emitter resistor of acon-
ventional transistor flip-flop (Q3 and Q4). Each pulse from the unijunction transistor
will turn off the transistor which is on in the flip-flop and the resulting square wave
of voltage at the collectors is coupled to the inverter by a small transformer. D3 and
D4 are used to prevent the emitter-base voltage of Q3 and Q4 from exceeding ratings
when atransistor is turned off.
The multivibrator free-runs at about 100 cps, but is synchronized and controlled

235
10 REGULATED DC SUPPLY AND INVERTER CIRCUITS

0I-GE 2N167IA OR USAF 2N490

03 04-GE 2N526 OR JAN 2N526
03 D4 -GE IN4009
71 -GE 9793YI338

SQUARE WAVE INVERTER

DRIVE CIRCUIT 1357
5 7
Figure 10.12

amimun

400 cycles

1.0.A

3200 cycles

INVERTER OUTPUT VOLTAGE

(VERTICAL SCALE 50 VOLTS/CM)

Figure 10.13

236
 REGULATED DC SUPPLY AND INVERTER CIRCUITS 10

by the unijunction at the higher operating frequencies at which it is designed to

operate. This circuit has good frequency stability with variations in supply voltage and
ambient temperature, due to the inherent stability of the unijunction. The circuit has
an operating frequency range of 400 to 3200 cps in an ambient temperature up to
70°C. The output impedance of this square wave generator is about 8 ohms and the
open circuit voltage is about 4 volts peak.

DC TO DC CONVERTERS
A simple and efficient saturating core inverter is shown in Figure 10.14. The load
can be shorted without any harm to the circuit and operation automatically resumes
after removal of the short. The operating frequency is approximately 8.5 kc with an
efficiency of 80% at 10 watts output. Each transistor should be mounted on aheatsink
that can dissipate about 1.5 watts; such as IERC #LP5AIB (135 West Magnolia
Blvd., Burbank, California), or Thermolloy Company, #2210 (4417 North Central
Expressway, Dallas, Texas ).

+ I62V

LOAD
250041

5T e
56
,••••••,.... •
9T #20

•
9T #20
56
5T

32 32
0+12V
O
200kat 02

it 01 12N2868
2N2868 I OR
OR 10536 OIICI 536
(GE) (GE.)
• •

T1 —TWO #3C3 E CORE # 206F440 iFERROXCUBE

BOBBIN # 595F425 SAUGERTIES,N.Y.

FREQUENCY% 8.6 KC

DC TO DC CONVERTER
(12 VOLT SUPPLY)

Figure 10.14

The 560 ohm resistor assures start-up with QI conduction initially. The 56 ohm
resistor in series with the base, limits the drive and hence the transistor current during
the switching interval at core saturation. The operating frequency is determined by

ti 2N (10e )
Vs
where
ti = 1/2 the operating period
N = 9turns in Figure 10.14
= total flux = BA
B = flux density
A = core cross sectional area
Vs = about 11.5 volts in Figure 10.14

237
10 REGULATED DC SUPPLY AND INVERTER CIRCUITS

The higher power de to de converter in Figure 10.15 has the following characteristics:
Output — 125 watts
Input voltage — 28 volts
Input current — 5.1 amps
Operating frequency — 10 ke
Output voltage — 420 volts
Output current - 0.3 amps
Output voltage ripple — 0.7 volts P-P
Efficiency — 87%
Ambient temperature range - —50°C to -1-12&C

1N646
N FERROXOUBE
5000
3W zw IN646 CORE

470pF MYLAR,500V
2NI618 3T,

22µF,I5V TANTALUM
100»F,50V TANTALUM
al I7T,
28V 5A •
+ INPUT -
2NI618 17T,

22µF,I5V TANTALUM

3T2
50,2W
500V
IN646 OUTPUT
A 420V •I25W

NOTE :EACH TRANSISTOR IS MOUNTED ON A COPPER

HEATSINK WITH DIMENSIONS -5" X e X 3/ 32"

NOMENCLATURE

TRANSFORMER T

1/2 SECONDARY A MAGNETIC CIRCUIT

FERROXCUBE {U CORE PT * IF2
WINDING
136 TURNS CASING (SAUGERTIES, NY)IF2B1 I CORE PT*
MAINTAIN 1/2 MM GAP

B WINDING DIMENSIONS (SEE FIGURE AT LEFT) ALL

WINDINGS WOUND IN SAME DIRECTION.
371-3 TURNS ENAMEL COPPER WIRE, *23
17Ti -17 TURNS ENAMEL COPPER WIRE, *18
17T, - 3T2 1772 -17 TURNS ENAMEL COPPER WIRE, *18
3T, - 177, 3T2- 3 TURNS ENAMEL COPPER WIRE, It 23
SECONDARY WINDING 136 + 136 TURNS ENAMEL
COPPER WIRE, *26
C STACKING OF THE WINDINGS ON THE CORE
THE WINDINGS ARE STACKED ON THE CORE AS
SHOWN. THIS WILL MINIMIZE CORE LOSSES AND
DECREASE THE HIGH VOLTAGES THAT WILL
CORE OCCUR AS A RESULT OF THE SWITCHING OF THE
2 SECONDARY TRANSISTORS
WINDING D. INSULATION
136 TURNS APPLY PAPER INSULATION BETWEEN LAYERS
APPLY DOUBLE PAPER INSULATION BETWEEN
WINDINGS.

125 WATT DC TO DC CONVERTER

Figure 10.15

Additional information on circuit performance is shown in Figures 10.16 and 10.17.

The power transistors can be mounted on a common heatsink.

238
111.111M REGULATED DC SUPPLY AND INVERTER CIRCUITS 10

EFFICIENCY AT 25°C AMBIENT TEMPERATURE

EFFICIENCY AT I25°C AMBIENT TEMPERATURE

100

90

BO

:1 70

60
e
50

40 0 10 20 30 40 50 60 70 BO 90 100 110 120 130 140

OUTPUT POWER (WATTS)

EFFICIENCY VS. OUTPUT POWER

(VARIABLE LOAD BETWEEN A AND B)

Figure 10.16

(AMBIENT TEMPERATURE 25°C)

gbll

450

440
/
430 G , v

420
I

410

Ann
15 .2 25 3 35

lolil

OUTPUT VOLTAGE VS. OUTPUT CURRENT FOR

CONSTANT INPUT VOLTAGE
Figure 10.17
REFERENCES
III Sylvan, T. P., "An Integrated Reference Amplifier for Precision Power Supplies," General Electric
Application Note 90.15, Semiconductor Products Department, Syracuse, New York.

239
10 REGULATED DC SUPPLY AND INVERTER CIRCUITS

NOTES

210
AUDIO AND HIGH FIDELITY
AMPLIFIER CIRCUITS

Part I— Audio Amplifier Circuits

BASIC AMPLIFIERS
In this chapter on audio amplifiers afew basic circuit concepts are given in a sim-
plified approach. Approximate circuit design techniques are used, but in most cases
the accuracy attained is practical because of the production variation in a given tran-
sistor parameter for aparticular transistor type. Chapter 2 discusses some of the more
exact formulas.

SINGLE STAGE AUDIO AMPLIFIER

Figure 11.1 shows a typical single stage audio amplifier using a 2N1414 PNP
transistor. With the resistance values shown, the bias conditions on the transistor are
1 ma of collector current and six volts from collector to emitter. At frequencies at
which C2 provides good by-passing, the input resistance is given by the formula
Rin = (1 + hr.) hit,
For the 2N1414, at a design center of 1ma, the input resistance would be 45 x 29,
or about 1300 ohms.

Figure 11.1 SINGLE STAGE AUDIO AMPLIFIER

The ac voltage gain eo.lein is approximately equal to RL/hib. For the circuit
shown, this would be 5000/29, or approximately 172 (44 db). The low frequency
gain will drop 3 db when the reactance of Cl equals RI. -F r
g.This assumes the bias

network, R1 and R2, are high impedance compared to Ran. Also, the low frequency
gain will drop 3 db when the reactance of C2 equals the parallel impedance of R3
and RE. Where
RE R. + hib
hre 1
and RG is the parallel impedance of the bias network and generator, r g.Where the

low frequency gain loss is mostly circuit dependant, the high frequency gain loss can
be due to transistor characteristics (see Chapter 2).

TWO STAGE RC COUPLED AUDIO AMPLIFIER

The circuit of a two stage RC coupled amplifier is shown by Figure 11.2. The
input impedance is the same as the single stage amplifier and would be approxi-
mately 1300 ohms.

241
11 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS

TWO STAGE RC COUPLED AUDIO AMPLIFIER

Figure 11.2

The load resistance for the first stage is now the input impedance of the second
stage. The voltage gain for the two stage circuit is given approximately by the formula

A. h .R— i
.

hb
CLASS B PUSH-PULL OUTPUT STAGES
In the majority of applications the output power is specified so adesign will usually
begin at this point. The circuit of a typical push-pull Class B output stage is shown
in Figure 11.3.

FROM
DRIVER
STAGE

CLASS B PUSH-PULL OUTPUT STAGE

Figure 11.3

242
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

The voltage divider consisting of RI and R2 gives aslight forward bias of about
0.14 volts on the transistors to prevent cross-over distortion. The 10 ohm resistors in
the emitter leads stabilize the transistors so they will not go into thermal runaway
when the ambient temperature is less than 55°C. Typical collector characteristics
with aload line are shown below.

I MAX

COLLECTOR CURRENT

NO SIGNAL
OPERATING
POINT

ECC
COLLECTOR VOLTAGE

TYPICAL COLLECTOR CHARACTERISTICS AND LOAD LINE

Figure 11.4

It can be shown that the maximum oc output power without clipping using a push-
pull stage is given by the formula

Pont
I max VCE
— 2
where VcE = collector to emitter voltage at no signal. Since the load resistance is
equal to
VCE
RL=

and the collector-to-collector impedance is four times the load resistance per collector,
the output power is given by the formula

= 2Ves°
(11a)
Re-e

Thus, for aspecified output power and collector voltage the collector to collector load
resistance can be determined. For output powers in the order of 50 mw to 850 mw
the load impedance is so low that it is essentially ashort circuit compared to the out-
put impedance of the transistors. Thus, unlike small signal amplifiers, no attempt is
made to match the output impedance of transistors in power output stages. The power
gain is given by the formula

Power Gain = P "ut =

Since I./Ii. is equal to the current gain, beta, for small load resistance, the power gain
formula can be written as

P. G. = (32 (11b)
R5-5

where
is the collector-to-collector load resistance,
Rb -b is the base to base input resistance, and
pis the grounded emitter current gain.
Since the load resistance is determined by the required maximum undistorted output
power, the power gain can be written in terms of the maximum output power by com-

243
11 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS

bining equations (Ila )and (1lb )to give

2fe W E'
P. G. =
RO -b Pout
CLASS A OUTPUT STAGES
The Class A output stage is biased as shown on the collector characteristics below

I MAX.

COLLECTOR CURRENT DC OPERATING POINT

IC

VCE 2 VCE

COLLECTOR VOLTAGE

DC OPERATING POINT OF CLASS A AUDIO AMPLIFIER

Figure 11.5

The de operating point is chosen so that the output signal can swing equally in the
positive and negative direction. The maximum output power without clipping is
equal to
VCE Ir
PoU t = —
2
The load resistance is then given by

RL =

Combining these two equations, the load resistance can be expressed in terms of the
collector voltage and power output by
VCE 2
RL = (11d)
2P„
For output powers of 20 mw and above the load resistance is very small compared to
the transistor output impedance and the current gain of the transistor is essentially the
short circuit current gain beta. Thus for aClass A output stage the power gain is given
by the formula
Vcé (11e)
RI. 2Ri. P„

CLASS A DRIVER STAGES

For a required output power of 500 mw the typical gain for a 12 volt push-pull
output stage would be in the order of 27 db. Thus the input power to the output stage
would be about 1to 2mw. The load resistance of aClass A driver stage is then deter-
mined by the power that must be furnished to the output stage and this load resistance
is given by equation (11d). For output powers in the order of a few milliwatts, the
load resistance is not negligible in comparison to the output impedance of the tran-
sistors, therefore, more exact equations must be used to determine the power gain of
a Class A driver stage. From four-terminal network theory, after making appropriate
approximations, it can be shown that the voltage gain is given by

Av= RL (11f)
ha, -I- Z.

244
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

where
hib is the grounded base input impedance, and
Z. is the external circuit impedance in series with the emitter.
The current gain is given by
a
At= (11g)
1— a+ Rt. ho.
where
h.b is the grounded base output conductance
The power gain is the product of the current gain and the voltage gain. Unlike the
formula for high power output stages, there is no simple relationship between required
output power and power gain for aClass A driver amplifier. Thus the following design
charts simplify acircuit design.

DESIGN CHARTS
Figures 11.7 through 11.16 are design charts for determination of transformer
impedances and typical power gains for Class A driver stages, Class A output stages,
and Class B push-pull stages. The transformer power output charts take into account
atransformer efficiency of 75% and therefore may be read directly in terms of power
delivered to the loudspeaker. Power gain charts show the ratio of output power in the
collector circuit to input power in the base circuit and therefore do not include trans-
former losses. Since the output transformer loss is included in the one chart, and the
design procedure that follows includes the driver transformer loss, it can be seen that
the major losses are accounted for.
The charts can best be understood by working through a typical example. Assume
a500 mw output is desired from a 12 volt amplifier consisting of a driver and push-
pull output pair. To obtain 500 mw in the loudspeaker, the output pair must develop
500 mw plus the transformer loss.

Pont 500 mw
Prollector—to—rollertor = = 666 mw
transformer eff. .75
From Figure 11.11, apair of 2N1415's in Class B push-pull produce a power gain
of approximately 27 db at 666 mw. This is anumerical gain of 500, so the input power
required by the output stage is

Pont 666 mw
P,. = — = 1.33 mw
Gain 500
If the driver transformer is 75% efficient, the driver must produce
Pdriver = P into output stage 1.33 mw 1.8mw
75% .75

From Figure 11.16 the 2N322 has apower gain of 42 db at apower output of 1.8 mw.
The output transformer primary impedance is obtained from Figure 11.12 on the
12 volt supply line at 666 mw output, and is 340 ohms maximum collector to collector
load resistance. Therefore, a more standard 300 ohm center tap (CT) output trans-
former may be used with secondary impedance to match the load. From Figure 11.13
the driver transformer primary impedance is 20,000 ohms. The secondary must be
center tapped with a total impedance of 800 to 5000 ohms. When this procedure is
used for commercial designs, it must be remembered that it represents full battery
voltage, typical power gain and input impedance, and therefore does not account for
end-limit points. Figure 11.6 is a circuit that uses the above design calculations.
The input sensitivity is between 10 and 20 millivolts for 1
/ watt output.
2

245
11 AUDIO AND IIIGH FIDELITY AMPLIFIER CIRCUITS

INPUT
TO LOUDSPEAKER

GAI
I2V

RI
C

190K

500
I2V I2V

PERFORMANCE
RI-VOLUME CONTROL TI -DRIVER TRANSFORMER
1MEG AUDIO TAPER PRI. 20K/SEC 2K CT MAX. POWER
OUT @ 10% 500MW
R2-TONE CONTROL T2-OUTPUT TRANSFORMER
HARM DIST
25K UNEAR TAPER PRI. 3000 CT/SEC V.C.

12 VOLT AUDIO AMPLIFIER Figure 11.6

400
MAX PRACTICAL POWER
r. 300

e,
7. 2
0 200
2NI413
2
- crx
0
100 2N1175
25 80
- 60 2NI414
o
— 40
2NI415
W 30
j. 11/
o l0 12 14 16 18 20 22 24 26 28 30 32 34
POWER GAIN-DECIBELS

TYPICAL POWER GAIN FOR CLASS B

PUSH-PULL AMPLIFIERS, 3.0 VOLT SUPPLY
Figure 11.7

1000 MAX RATED POWER

850
600
cn
- 400
2NI413
Z. 300
-o
g
0
200
I- I- 2NI414

2NI415

o 40
a. 30 2NI175

10 12 14 16 18 20 22 24 26 28 30 32 34

POWER GAIN-DECIBELS

TYPICAL POWER GAIN FOR CLASS B

PUSH-PULL AMPLIFIERS, 4.5 VOLT SUPPLY
Figure 11.8

246
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

1000 MAX RATED POWER

850
600

.
1 400
300 2NI413

2N1414

2NI415
40
30
2NI175
o
12 14 16 18 20 22 24 26 28 30 32 34 36

POWER GAIN- DECIBELS

TYPICAL POWER GAIN FOR CLASS B

PUSH-PULL AMPLIFIERS, 6 VOLT SUPPLY
Figure 11.9

IQ8 MAX RATED POWER

.E„ 600 1
2NI413
400
-1Q
É 300
IS 2NI414
200
D (I)
d-

2NI415

2NI175
40
30

0
14 16 18 20 22 24 26 28 30 32 34

POWER GAIN -DECIBELS

TYPICAL POWER GAIN FOR CLASS 13

PUSH-PULL AMPLIFIERS, 9 VOLT SUPPLY
Figure 11.10

1000 MAX RATED POWER

850
600

400
32
3F_
o 300 1
2NI413
200

26 2NI414
-
D 100
(=> e 80
cr 60
2NI415

40

2NI175

018 20 22 24 26 28 30 32 34 36

POWER GAIN-DECIBELS

TYPICAL POWER GAIN FOR CLASS B

PUSH-PULL AMPLIFIERS, 12 VOLT SUPPLY
Figure 11.11

247
11 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS

I
000
1 I III
BOO DESIGN CHART FOR
OUTPUT TRANSFORMER
600

POWER OUTPUT- MILLIV/ATTS (<10% DISTORTION )

IN CLASS B PUSH PULL
AUDIO AMPLIFIERS

400

200

°4 4
6 ...
0<
loo N
srs5.
80

&
60
(y

T
40
MAXIMUM

20
\\\.

1
0
100 200 500 IK 2K 5K 10K

COLLECTOR TO COLLECTOR LOAD —OHMS

DESIGN CHART FOR OUTPUT TRANSFORMER

IN CLASS B PUSH-PULL AUDIO AMPLIFIERS
Figure 11.12
100
80

60

40

1.0
0.8

200 400 600 800 IK 2K 4K 6K BK 10K 20K 50K

COLLECTOR LOAD RESISTANCE-OHMS

DESIGN CHART FOR OUTPUT TRANSFORMER

IN CLASS A SINGLE-ENDED AMPLIFIER
Figure 11.13

248
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

MAX RATED POWER

I MAX RATED POWER

2NI175

2N322

2NI413

....-2N323

1
.
I

1
--- 2NI414

r
2N324

2N1415

1.0 2N508
0.8
0.6
II I
0.4_

26 28 30 32 34 36 38 40 42 44

POWER GAIN-DECIBELS

TYPICAL POWER GAIN FOR CLASS A

SINGLE-ENDED AMPLIFIERS, 6 VOLT SUPPLY
Figure 11.14

MAX RATED POWER

100
MAX RATED POWER
_

40

2N1175

2N322

2NI413

2N323

2NI414

2N324

2N1415

2N508
1.0
08
0.6

0.4

26 28 30 32 34 36 38 40 42 44 46
POWER GAIN-DECIBELS

TYPICAL POWER GAIN FOR CLASS A

SINGLE-ENDED AMPLIFIERS, 9 VOLT SUPPLY
Figure 11.15

249
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

100 MAX RATED POWER

MA X
-RATED POWER
_

2N1 175
cn 40
2N322
•
3F.. 20 2NI 413
àg 2N323
,17,
e 2N1414
F- at 6 2N324
an
cc — 4 2NI415
ta
2N508
2 2

0.8
0.6
OA-
o
28 30 32 34 36 38 40 42 44 46 48
POWER GAIN-DECIBELS

TYPICAL POWER GAIN FOR CLASS A

SINGLE-ENDED AMPLIFIERS, 12 VOLT SUPPLY
Figure 11.16

TRANSISTORS LISTED IN THE TOP ROW ARE PREFERRED TYPES. THEY CAN BE
SUBSTITUTED FOR TYPES LISTED BELOW THEM IN THE SAME COLUMN.
BRACKETED TYPES ARE NOT RECOMMENDED FOR NEW DESIGNS.
* * * *
2N322 2N323 2N324 2N508 2NI413 2NI414 2N1415 2N1175
(2N190) (2NI91)
(2N192) (2N265) (2N187A) (2N1888) (2N24IA) (2N192)
(2N189) (2N190) (2NI91) 2N324
2N319 2N320 2N321
2N322 2N323
*THESE TYPES CAN NOT BE SUBSTITUTED IF APPLICATION REQUIRES
V >16 VOLTS
cER

PREFERRED TYPES AND SUBSTITUTION CHART

Figure 11.17

Part 2— High Fidelity Circuits

INTRODUCTION
Transistors are ideally suited for high fidelity amplifiers since there is no problem
with microphonics or hum pick-up from filaments as there is with tubes. Transistors
are inherently low impedance devices and thus offer better matching to magnetic
pick-ups and loudspeakers for more efficient power transfer.
Transistor circuits with negative feedback can give the wide frequency response and
low distortion required for high fidelity equipment. In general, the distortion reduction
is about equal to the gain reduction for the circuit to which negative feedback is
applied. The input and output impedances of amplifiers with feedback are either
increased or decreased, depending on the form of feedback used. Voltage feedback

250
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

from the collector, over one or several transistor stages, decreases the output imped-
ance of that stage; whereas current feedback from the emitter increases the output
impedance of the stage. If either of these networks are fed back to the base of a
transistor the input impedance is decreased, but if the feedback is to the emitter then
the impedance is increased. The feedback can be applied to the emitter for effective
operation with a low generator impedance, whereas the feedback to the base is
effective with ahigh impedance (constant current) source. If the source impedance
is low in the latter case then most of the feedback current would flow into the source
and not into the feedback amplifier. The feedback connections must be chosen to
give a feedback signal that is out-of-phase with the input signal if applied to the
base, or in-phase if it is applied to the emitter of acommon-emitter stage.
Care must be used in applying feedback around more than two transistor stages to
prevent high frequency instability. This instability results when the phase shift through
the transistor amplifiers is sufficient to change the feedback from negative to positive.
The frequency response of the feedback loop is sometimes limited to stabilize the cir-
cuit. At the present time the amount of feedback that can be applied to some audio
power transistors is limited because of the poor frequency response in the common-
emitter and common-collector connections. The common-collector connection offers
the advantage of local voltage feedback that is inherent with this connection. Local
feedback (one stage only) can be used on high phase shift amplifiers to increase the
frequency response and decrease distortion.

PREAMPLIFIERS

Preamplifiers have two major functions: increasing the signal level from a pickup
device to about 1volt rms; and providing compensation, if required, to equalize the
input signal for aconstant output with frequency.
The circuit of Figure 11.18 meets these requirements when the pickup device is a
magnetic microphone, phono cartridge (monaural or stereo), or a tape head. The
total harmonic or IM (intermodulation) distortion of the preamp is less than 0.3%
at reference level output (1volt).
This preamp will accommodate most magnetic pickup impedances. Input imped-
ance to the preamp increases with frequency (except in switch pos. #4) because of
the frequency selective negative feedback to the emitter of Ql. The impedance of the
magnetic pickups will also increase with frequency but are below that of the preamp.
The first two stages of this circuit have a feedback bias arrangement with RI
feeding bias current to the base of QI that is directly proportional to the emitter
current of Q2. This stabilizes the voltage and current bias points in the circuit for
variations in both hFE of the 2N508 and ambient temperatures up to 55°C (I31°F).
The output stage is well stabilized with a5K emitter resistance.
The ac negative feedback from the collector of Q2 to the emitter of QI is fre-
quency selective to compensate for the standard NAB recording characteristic for
tape or the standard RIAA for phonograph records. The flat response from astandard
NAB recorded tape occurs with the treble control (R9) near mid-position (see Figure
11.19). There is about 5db of treble boost with the control at 25K and approximately
12 db of treble cut with R9 = 0. Mid-position of the treble control also gives flat
response from a 33 / "/second tape. This treble equalization permits adjustment for
4

variations in program material, tap heads, and loudspeakers.

The 0.36 henry tape head gives an equalized response within - ±1 db variation
from 50 cycles to 15 kc (see Figure 11.19). Noise level is 66 db below reference level
output with a weighted measurement. The unweighted noise level is 57 db below
reference. Measurement of unweighted noise even in the audio range (16 cps to 20 kc)

251
 SWITCH POSITIONS
C5 I I PHONO (R1A A EQUALIZATION)
C4 .0082
110% T C6 2 TAPE - 7 1/2" /SEC. (NAB)
RIO .0047 3 TAPE -3 3/4"/ SEC
C8
18 K ±10% T .027 • 4 MICROPHONE(MAGNETIC) OR TUNER
TREBLE I10%
R8 EQUALI- C7 NOTE. ALL RESISTORS 1/2 WATT,
330K ZAT ION R11
R9 .0068 25% TOLERANCE -40 TO
25K 210% IIK
ALL CAPACITOR VALUES -µf -46V

-22V 4.25 ma —* 4•
25 ".2ND STEREO
- CHANNEL
R5 G.E.
C3 RI3 Z4XL228
R6 .1 20K
56K 10K
03
TUNER OR I0.7V 2N508 OR
FM DECODER

î
2N322 4_±1

BASS
CI 2N508 500
BOOST
INPUT 20 QI 25V
LEVEL I5V 2N508A

HL OR
2N508
.7 HENRY
50n
MAX. DC

R16
5K 1- 1 -
220K LEVEL CIO
200
I5V
OUTPUT

R4
I.5K
o o
MAGNETIC TAPE HEAD OR
PHONO MICROPHONE
CARTRIDGE

PHONO, TAPE, MICROPHONE PREAMPLIFIER

Figure 11.18
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

+10

0
1I
REFERENCE LEVEL (1 VOLT) -.0
250— R9.25K

-10
1
----
R9 IIK
(db)

-20
TAPE PREAMPLIFIER OUTPUT

R9 -0

30
TAPE HEAD -NORTRONICS ASO7K (#1101)
OR CSO7K (#1001)
VIKING TAPE DECK
40 TAPE SPEED 7 I/2" /SEC

50
PNP

-60

r
NOISE LEVEL (WEIGHTED) .'""• 66db BELOW REFERENCE (TAPE STOPPED)
--.
-70

50-- 100 500 1C 5 10 I5KC

FREQUENCY

TAPE PREAMPLIFIER RESPONSE FROM NAB RECORDING

Figure 11.19

does not give results that correlate with the low level audible noise as heard from a
speaker. For measurement of low level noise, a filter can be used with a response
that follows the Fletcher-Munson curve of equal loudness at a level of 40 db above
the threshold of hearing at 1 kc. This response falls within the ASA standard "A"
weighting curve." )
A good signal-to-noise ratio (S/N) can be realized with a tape head inductance
between 0.2 and 0.5 henry. One has to be careful of the physical position of the tape
head or the noise output will increase considerably due to pick-up of stray fields.
For good S/N it is important that the tape head have good shielding and hum bucking.
The S/N and dynamic range is improved by R14 in the emitter of Q2 which reflects
ahigher input impedance for this stage and thus increases the gain of Ql. The preamp
performance with a Nortronics B2Q7K, or F, head will be similar to Figure 11.19
with the preamp output level increased about 2 db.
The preamp in the #2 (Tape 7½ "/sec.) position requires about 1.5 mv input
signal at 1 kc for 1 volt output. Therefore a tape head with a 1 kc reference level
output of 1.2 to 2 mv is desirable. Maximum output of the preamp before clipping
is over 14 db above the 1volt reference output level.
In switch position #3 (Tape 33 / "/sec.) with R9 ± R10 = 30K, the equalized
4

response is within -±-1 db from 50 cycles to 71/ kc with Ampex Standard Alignment
2

Tape #6000-A4 and Nortronics ASQ7K tape head. The preamp reference level output
is 0.55 volts and the noise (weighted) is 56 db below this level.
The voltage feedback from the collector of Q2 decreases at lower frequencies
because of the increasing reactance of the feedback capacitor in series with the treble
control. In switch position #4 the capacitor C4 is large enough with R8 to make the
voltage feedback, and thus the gain, constant across the audio spectrum. This flat

253
11 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS

preamp response can be used with a tuner, FM decoder or microphone. The input
impedance to the preamp in #4 switch position is about 4.5K ohms, and 350 micro-
volts input level gives 1 volt output (69 db gain). This sensitivity and input im-
pedance gives excellent performance with low and medium impedance magnetic
microphones. The noise (weighted) is 64 db below the 1volt output level. A magnetic
pickup should be left connected at the preamp input while using the tuner or FM
decoder. This tuner input has asensitivity down to 250 millivolts.
The RIAA feedback network (switch position #1) has a capacitor C7 for
decreasing the amplifier gain at the higher frequencies. This eliminates the need to
load a magnetic cartridge with the proper resistance for high frequency compensa-
tion. An input level of 8millivolts gives 1volt output, and the preamp output noise
(unweighted) is 78 db below this level. The equalized output is within ±1 db varia-
tion from 40 cycles to 12 kc using the London PS-131 stereophonic frequency test
record and aShure M77 Stereo Dynetic pickup cartridge.
Generally, the manufacturer of a piezoelectric pickup often has a recommended
network for converting his pickup to avelocity device, so that it may be fed into an
input jack intended for amagnetic pickup.
The emitter-follower output stage of the preamp gives a low impedance output
for acable run to apower amplifier (transistor or tube), and acts as abuffer so that
any loading on the preamp will not affect the equalization characteristic. The preamp
output should not be loaded with less than 3K ohms and preferably about 10K or
greater.
Since this is a high gain circuit care should be used in the physical layout to
prevent regenerative feedback to the input. Also, aswitching circuit at the input will
increase the possibilities for hum pickup and thus decrease the S/N. All connections
to the base of QI should be very short, or shielded. A 22 1
/ volt battery can be used
2

to power this preamp circuit with good battery life since total load current is only
4.25 ma. The treble control should have alinear taper and the level control an audio
taper.

BASS BOOST OR LOUDNESS CONTROL CIRCUIT

The bass boost circuit of Figure 11.20 operates on the output of the preamp
(Figures 11.18, 11.22). With this addition, the operator has the necessary treble and
bass control to compensate for listening levels, or deficiencies in program material,
pickup, speakers, etc. This bass boost circuit gives the operator independent control
of the level, or amount of bass boost desired, or the level control can be used as a
loudness control.
TRANSISTOR

BASS BOOST

INPUT

0.7 HENRY
500 oc
MAXIMUM

20µI
OUTPUT
I5V

BASS BOOST OR LOUDNESS CONTROL CIRCUIT

Figure 11.20

It is usually desirable to have some method of boosting the level of the lower
portion of the audio spectrum as the overall sound level is decreased. This is to com-
pensate for the non-linear response of the human ear as shown in the Fletcher-Munson

254
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

curves that are often referred to in the audio industry. The ear requires ahigher level
for the low frequency sound to be audible as the frequency is decreased and also as
the overall spectrum level is decreased.
Figure 11.21 shows the frequency characteristics of this bass boost circuit. With the
level control set for zero attenuation at the output there is no bass boost available, but
as the output level is attenuated the available bass boost increases.
woo
(db)
OUTPUT VOLTAGE
INPUT VOLTAGE

R17.0

RI7.50K

R17.0

R17 .50K

-so

60
30", 50 [00 500 IKC 5 10 I5KC
FREQUENCY

FREQUENCY RESPONSE OF BASS BOOST CIRCUIT

Figure 11.21

Figure 11.21 shows the frequency response (lower dashed curve) when the output
is attenuated 40 db and the bass boost control is set for minimum (50K ohms). The
solid curve immediately above represents the frequency response when the bass boost
control is set at maximum (zero ohms). Thus, a frequency of 30 cycles can have
anything from zero to 27 db of boost with respect to 1kc, depending on the adjust-
ment of the bass boost control.
The Fletcher-Munson contours of equal loudness level show most of the contour
changes involve a considerable boost of the bass frequencies at the lower levels of
intensity. Therefore, this circuit combination fulfills the requirements of level control,
bass boost, and loudness control.
When using R17 as aloudness control, set it at 50K and adjust the level control,
R16, so that the program material sounds as loud as the original and adjust the treble
equalization (Figure 11.18 and 11.22) for proper tone balance. Now the program
level can be reduced to the desired listening level and R17 adjusted for the same
acoustical bass response. With R17 set for maximum bass boost and the level control
at —40 db output, the frequency response as shown in Figure 11.21 is within about
2db of the 55 phon curve of equal loudness as given by Fletcher and Munson below
1kc. Forty decibals higher intensity level at 1kc would be at the 95 phon curve of
equal loudness. This is near the maximum level of very loud music peaks while a
55 phon level is representative of background music level.
The bass boost control may be astandard 50K potentiometer with alinear taper.
The desired inductance may be obtained by using the green and yellow leads on the
secondary of an Argonne transistor transformer #AR-128 (Lafayette Radio Catalog).

NPN-TAPE AND MICROPHONE PREAMPLIFIER

The basic preamplifier of Figure 11.22 is similar to that of Figure 11.18 except
silicon planar NPN transistors are used and thus the first stage does not require a
temperature compensating resistor in the emitter circuit. Since Q1 is aplanar passi-
vated transistor which has very low leakage current (Icso), the bias current can be

255
 11 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS

reduced. Approximately 0.35 ma of collector current for QI gives the best signal-to-
noise ratio (S/N). R4 and C2 provide ripple reduction in the supply to the first stage.
This preamp has higher open loop gain than the preamp in Figure 11.18 and thus R5
is required for NAB equalization at 50 cycles.

C4 RS
.1 330K

R5 TREBLE R7 3
SWITCH POSITIONS 560K EQUALIZATION I2K 2
TAPE-7 I/2"/SEC (NAB)
2 TAPE-3 3/4/SEC C3 R6

3 MICROPHONE(MAGNETIC) OR TUNER
.0056 310%
NOTE ALL RESISTORS 1/2 WATT, 35% TOL.
ALL CAPACITOR VALUES -µf
e +22V
@3.5mcs

100K 03
TUNER OR 2N2925,2N2924
FM DECODER OR 2923
INPUT
BASS
CI BOOST
30
6V

50K
RI?
0.7 HENRY
son
MAX. DC
LEVEL
5K e«— H I+
IV RIA 20
I5V
CIO
R2

T
OUTPUT
47 RI I
100 1
IK
3V

TAPE HEAD OR
MICROPHONE

TAPE-MICROPHONE PREAMPLIFIER
Figure 11.22

The 0.4 henry tape head gives an equalized response within -

-t1 db variation from

50 cycles to 15 kc (see Figure 11.23). Noise level is approximately 66 db below

reference level output with a weighted measurement, and 57 db unweighted. The
equalized response is equally good with a Nortronics B2Q7K or ASQ7K tape head.
The preamp in switch position #1 (Tape 71k"/sec.) requires 1.8 mv input signal
at 1kc for 1.1 volts output. This level is about 14 db below maximum output. The
IM distortion is less than 0.25% at 1.1 volts output (reference level). The input
impedance at 1 kc is over 100K and approximately 43K at 15 kc. This high input
impedance along with the treble equalization adjustment accommodates tape head
impedances to 0.8 henry. The optimum output level of the tape head for best dynamic
range and S/N is a1kc reference level of 1.8 mv ±3 db.
In switch position #2 (Tape 33/ 4"/sec.) with R6 + R7 = 22K, the equalized

response is within ±-1.25 db from 50 cycles to 71

/ kc with Ampex standard alignment
2

tape #6000-A4 and Nortronics B2Q7F tape head. The preamp reference level output
is 1.18 volts which is 57 db above the weighted noise level.
In switch position #3, the flat preamp response can be used with a tuner, FM
decoder, or magnetic microphone. The microphone preamp input impedance is 43K,
and a400 microvolts input signal gives 1.2 volts output (70 db gain). This output
level is 14 db below maximum, and is 62 db above the weighted noise level. The

256
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

+10

O REFERENCE LEVEL (.1 VOLT)

R6 20K

R6.6 8K
-10

• 20
R6.0

ce
w 30
TAPE HEAD-NORTRONICS B2Q7F
3 VIK NG TAPE DECK
rà. TAPE SPEED -7 1/2" /SEC
-40
(A.1
a.
w 50

o-
z
• 60
DI _
NOISE LEVEL (WEIGHTED) '
e
- 66db BELOW REFERENCE s(TAPE
ToppE

70

80 _I_
30-, 50 100 500 KC 5 10 I5KC
FREQUENCY

TAPE PREAMPLIFIER RESPONSE FROM NAB RECORDING

Figure 11.23

frequency response is flat within 0.25 db from 30 cycles to 15 kc and the total harmonic
distortion is 0.01% at 1.2 volts output. The tape head or a 200 ohm resistor should
be connected at the preamp input while using the tuner or FM decoder. This tuner
input has asensitivity down to 260 millivolts.
A large capacitor value for Cl is desirable to keep the impedance low at the base
of Q1 for best S/N performance. All connections to the base of QI should be very
short, or shielded. Since this basic preamp is quite similar to the circuit in Figure
11.18, the previous detailed discussion applies also to this NPN preamp.

03
2N3397,2N2924
OR 2N2925
QI
20 2N2925
I5V
- 4-

MAGNETIC
CARTRIDGE

PHONO (RIM) PREAMPLIFIER

Figure 11.24

257
11 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS
NPN-PHONO PREAMPLIFIERS
The circuit of Figure 11.24 is designed for a magnetic phono cartridge and is
quite similar to the basic circuit of Figure 11.22. An input signal of 6 millivolts at
1 kc gives 1 volt output which is 15 db below the clipping level and 72 db above
the unweighted noise level. The RIAA equalized output is within ±1 db variation
from 40 cycles to 12 kc using the London PS 131 stereophonic frequency test record
and a Shure M77 Stereo Dynetic cartridge. The input impedance at 1 kc is 43K.
The total harmonic distortion at 1kc is 0.15% at 1volt output.
The circuit of Figure 11.25 gives an RIAA equalized output when used with
ceramic cartridges that have 5,000 to 10,000 pf capacitance. The input impedance is
approximately 620K at 50 cycles. With the Astatic Model 137 cartridge the output
reference level of 1 volt is 13 db below maximum output and 69 db above the
unweighted noise level. The total harmonic distortion is less than 0.6% at the 1 volt
output level. R3 and R4 with the .01 capacitor give the 500 and 2,122 cycle turnover
points for RIAA equalization.
The circuit of Figure 11.26 gives an RIAA equalized output when used with
ceramic cartridges that have 1,000 to 10,000 pf capacitance. Here the feedback

CARTRIDGE
CAPACITANCE le-
5,000 TO OUTPUT
01
10,000 pf
1'10%

PHONO PREAMPLIFIER FOR CERAMIC CARTRIDGE

(AMPLITUDE RESPONSE — RIAA EQUALIZATION)

Figure 11.25

1200 pf 5'10% 120K

CARTRIDGE
CAPACITANCE
1,000 TO oe-
10,000 pf

PHONO PREAMPLIFIER FOR CERAMIC CARTRIDGE

(VELOCITY RESPONSE — RIAA EQUALIZATION)

Figure 11.26

258
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

equalization is from collector to base which lowers the input impedance. This has
the advantage of accepting a wide range of cartridge capacitance. It is also less
susceptible to cable capacitance and noise pickup. The input impedance, which is
about 30K at 40 cycles, decreases with increasing frequency. This results in avelocity
response from the cartridge and thus the preamp frequency response is like that
required for amagnetic cartridge.
Using the Astatic 137 cartridge (7,800 pf) and the London PS 131 stereophonic
frequency test record the output is equalized within ±-1.6 db from 40 cycles to 12 kc.
The output reference level is 11
/ volts which is 14 db below clipping, and 70 db above
4

the unweighted noise level. The 1kc total harmonic distortion is less than 0.1% at
11
/ volts output.
4

Using the Astatic 17 cartridge (1,000 pf), the preamp output is equalized within
±-1.6 db also, but at about 10 db lower level.

POWER AMPLIFIERS
It is difficult to attain faithful reproduction of asquare wave signal with atrans-
former amplifier. A high quality transformer is required and it must be physically
large to have agood response at the low frequencies. Thus, a great deal of effort has
gone into developing transformerless push-pull amplifiers using vacuum tubes. Prac-
tical circuits, however, use many power tubes in parallel to provide the high currents
necessary for direct-coupling to alow impedance load such as loudspeakers.
The advent of power transistors has sparked new interest in the development of
transformerless circuits since the transistors are basically low voltage, high current
devices. The emitter-follower stage, in particular, offers the most interesting possibili-
ties since it has low inherent distortion and low output impedance.
Figure 11.27 is a direct-coupled power amplifier with excellent low frequency
response, and also has the advantage of de feedback for temperature stabilization of
all stages. This feedback system stabilizes the voltage division across the power output
transistors Q4 and Q5 which operate in a single-ended Class B push-pull arrange-
ment. Q2 and Q3 also operate Class B in the Darlington connection to increase the
current gain. Using an NPN for Q3 gives the required phase inversion for driving
Q5 and also has the advaptage of push-pull emitter-follower operation from the out-
put of Q1to the load. Emitter-follower operation has lower inherent distortion and
low output impedance because of the 100% voltage feedback.
Q4 and Q5 have a small forward bias of 10 to 20 ma to minimize cross-over
distortion and it also operates the output transistors in amore favorable beta range.
This bias is set by the voltage drop across the 390 ohm resistors that shunt the input to
Q4 and Q5. Q2 and Q3 -are biased at about 1ma (to minimize cross-over distortion)
with the voltage drop across the silicon diode (DI ). Junction diodes have atempera-
ture characteristic similar to the emitter-base junction of a transistor. Therefore, this
diode also gives compensation for the temperature variation of the emitter-base
resistance of Q2, Q4 and Q3. These resistances decrease with increasing temperature,
thus the decrease in forward voltage drop of approximately 2 millivolts/degree
centigrade of the diode provides some temperature compensation.
QI is aClass A driver with an emitter current of about 3 ma. Negative feedback
to tle base of Q1lowers the input impedance of this stage and thus requires asource
impedance that is higher so the feedback current will flow into the amplifier rather
than into the source. Resistor RI limits the minimum value of source impedance.
The value of R3 permits about one-half the supply voltage across QS.
About 11 db of positive feedback is applied by way of C3 across RS. This boot-
strapping action helps to compensate for the unsymmetrical output circuit and permits
the positive peak signal swing to approach the amplitude of the negative peak. This

259
Il AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS

0 46V

04
2N553
OR
C3 _ 2N297A
(DELCO)
20µI
25V
1/2 AlTYPE
AGC OR 340)

0 8 OR 1611
SPEAKER
1500F f
50V

24i RI 05
25V 2700
2N553
OR OUTPUT
2N2976
(DELCO) 22

INPUT "I/2A
(TYPE AGC
OR 3AG)

10 WATT AMPLIFIER
Figure 11.27

positive feedback is offset by about the same magnitude of negative feedback via R3
to the base of Ql. The net amount of negative feedback is approximately 14 db result-
ing from R12 connecting the output to the input. In addition, there is the local feed-
back inherent in the emitter-follower stages. The value for the C2 feedback capacitor
was chosen for optimum square wave response (i.e., maximum rise-time and minimum
overshoot ).
A 1/ ampere fuse is used in the emitter of each output transistor for protective
2

fusing of Q4 and QS, and also to provide local feedback since the 1 / ampere type
2

AGC or 3AG fuse has about 1ohm de resistance. This local feedback increases the
bias stability of the circuit and also improves the declining frequency response of Q4
and Q5 at the upper end of the audio spectrum. Because of the lower transistor effi-
ciency above 10 kc, care should be used when checking the amplifier for maximum
continuous sinewave output at these frequencies. If continuous power is applied for
more than ashort duration, sufficient heating may result to raise the transistor current
enough to blow the 1 / ampere fuses. Since there is not sufficient sustained high
2

frequency power in regular program material to raise the current to this level, actual
performance of the amplifier does not suffer since the power level in music and speech
declines as the frequency increases beyond about 1to 2kc. •
The speaker system is shunted by 22 ohms in series with 0.22 pfd to prevent the
continued rise of the amplifier load impedance and its accompanying phase shift
beyond the audio spectrum.
The overall result, from using direct-coupling, no transformers, and ample degen-
eration, is an amplifier with output impedance of about 1 ohm for good speaker
damping, low distortion, and good bandwidth. The power response at 1watt is flat

260
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS Il

from 30 cycles to 15 kc and is down 3 db at 50 kc. At this level the total harmonic
and 1M distortion are both less than 1%. At 7 watts the 1M distortion is less than
21
/ % and the total harmonic distortion is less than 1% measured at 50 cycles, 1 kc,
2

and 10 kc. The performance of the amplifier of Figure 11.27 is about equal for both 8
and 16 ohm loads.
This amplifier is capable of about 8 watts of continuous output power with 1 volt
rms input, or 10 watts of music power into 8 or 16 ohms when used with the power
supply of Figure 11.28. This power supply has diode decoupling which provides
excellent separation (80 db) between the two stereo amplifier channels.

STANCOR
IA RT- 201

AMPLIFIER 2

II 7vAC

CI ,C2, a C3 -1500/1f, 50V.

POWER SUPPLY FOR STEREO SYSTEM

Figure 11.28

The power transistors Q4 and Q5 should each be mounted on an adequate heat

radiator such as used for transistor output in an automobile radio, or mounted on a
3" x 3" x3 4 9" aluminum plate that is insulated from the chassis.
/

SILICON POWER AMPLIFIERS

Some of the transistor power amplifiers to date have been lacking in their high
frequency performance and their temperature stability. The diffused silicon transistors
permit good circuit performance at high frequency. Silicon transistors are desirable
for power output stages because of their ability to perform at much higher junction
temperatures than germanium. This means smaller heat radiating fins can be used
for the same power dissipation. On the negative side, silicon often has higher satura-
tion resistance which gives decreased operating efficiency that becomes appreciable
when operating from low voltage supplies.
The power handling capability of a transistor is limited by both its electrical and
thermal ratings. The electrical rating limit is a function of the transistor's voltage
capability, and its maximum current at which the current gain is still usable. The
thermal rating is limited by the transistor's maximum junction temperature. Therefore,
it is desirable to provide the lowest thermal impedance path that is practical from
junction to air. The thermal impedance from junction to case is fixed by the design

261
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

of the transistor; thus it is advantageous to achieve a low thermal impedance from

case to the ambient air.
The GE 7A31, 2N2I07, and 2N2I96 are NPN diffused silicon transistors. They will
be limited in their maximum power handling ability by the thermal considerations
for many applications unless an efficient thermal path is provided from case to air.
These transistors are constructed with the silicon pellet mounted directly on the
metal header, and it is therefore more efficient to have an external heat radiator in
direct contact with this header than to make contact with the cap of the transistor
package.

WAS { APPROX. 3/4" 0.0

HER
1.11 •.3475+ .0125

ALUMINUM FIN
1/8" (OR I/16"COPPER)

:4
2 1/2" , 64
:1-13/

•--21/2'=.
MOUNTING THREE 3/32"
HARDWARE DIA HOLES

2N2I07
OR 7A3I
- FIN ONLY

TRANSISTOR HEAT RADIATOR

Figure 11.29

Figure 11.29 shows apractical method for achieving amaximum area of direct con-
tact between the metal header and an aluminum fin for efficient heat transfer to the
surrounding air. A plain washer with two holes drilled for the mounting hardware is
simple but quite adequate for securing the transistor header to the fin. Since air is a
relatively poor thermal conductor, the thermal transfer can be improved by applying
a thin layer of GE Silicone Dielectric Grease #SS-4005 or equivalent between the
transistor and the radiating fin before assembly. The fin may be anodized or fiat paint
may be used to cover all the surface except for the area of direct contact with the
transistor header. An anodized finish would provide the insulation needed between
the base and emitter leads and the sides of the feed-through holes in the aluminum
fin. Figure 11.30 shows a thermal rating for the 2N2107 and 7A31 as assembled on
the radiating fin. An efficient commercial version of the heat radiator shown in Figure
11.30 is available in the IERC #LP5C1B (IERC, 135 W. Magnolia Blvd., Burbank,
California ).

8 Watt Transformerless Amplifier

The circuit of Figure 11.31 is very much like that described for Figure 11.27.
Opposite polarity is used for transistors, capacitors, and supply voltage. The 1N91
in the emitter circuit of Q4 stabilizes the push-pull output stage for variations in
transistor beta and temperature. The fuse, FI, in the emitter circuit of Q4 gives
protective fusing for Q4 and Q5, and also its 1 ohm de resistance gives increased
circuit stability. The voltage drop across forward biased diodes, DI and D2, sets the
quiescent current level for the circuit and also adds to the temperature stability as
mentioned for Figure 11.27.

262
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

THERMAL RESISTANCE
RT 25* C /WATT

20 40 60 80 100 120 140 160

AMBIENT TE MPERATURE -

THERMAL CHARACTERISTIC
Figure 11.30

The silicon power amplifier of Figure 11.31 has an output impedance of 0.5 ohm
for good speaker damping. There is about 20 db of overall negative feedback with
R12 connecting the output to the input. The rise-time and fall-time for asquare pulse
is less than 2 microseconds. The square wave response shown in Figure 11.32 is
indicative of an amplifier with good transient response as well as good bandwidth.
The bandwidth is confirmed by the response curve of Figure 11.33 where it is —3 db
at 86 kc. Power response at 6watts output is fiat within 1/
3 db from 30 cycles to 15 kc.

The amplifier exhibits good recovery from overload, and the square wave peak power
output without distorting the waveform is 12 watts.

R5
1500
+50V

C3 04
20µ f 2N2196, 2N2107
50V - OR 7A3I (G.E.)

FI
FI -1/24 (TYPE 3AG) STANDARD
FUSE
ALL RESISTORS 1/2 WATT IN91
I6R
° LOAD

STEREO
BALANCE RI
CI 2N2I96 122
10K 2.7K
2N2I07
OR 7431 OUTPUT
20µf OR 2N3364
12V (GE) .22
I5V
INPUT

8 WATT AMPLIFIER
Figure 11.31

263
11 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS

2 KC SQUARE WAVE RESPONSE

Figure 11.32

Odb •1/2 WATT

20 100 1KC IOKC 100KC

FREQUENCY RESPONSE
Figure 11..33

The output transistors, Q4 and Q5, were mounted on heat dissipating fins as
shown in Figure 11.29 and the amplifier operated successfully delivering 1 watt rms
400 cycles continuous power to the load with no increase in total harmonic distortion
from room ambient of 75°F to 175°F (approx. 80°C). At 175°F the de voltage across
Q5 had decreased less than 15% from its room ambient value. Operation at higher
temperatures was not attempted because of Q3 being a germanium transistor which
has a maximum operating junction temperature of 85°C.
When operated with the heat radiator assembly, this amplifier can safely deliver
up to 10 watts rms of continuous power to the load at room temperature. When
driving aloudspeaker with program material at a level where peak power may reach
10 watts, the rms power would generally be less than 1 watt. This amplifier, when
operated with 2N2196's in the outputs, cart be mounted on a smaller 2" x 2" fin be-
cause of its increased power capabilities. The 2N2196 has acase that simplifies mount-
ing on aheat radiator and has electrical characteristics that equal or excel the 2N2107
or 7A31 for this application.
IM and total harmonic distortion is less than /
2 % at power levels under 31
1 2 watts.
/
The total harmonic distortion measured at 50 cycles, 400 cycles, and 10 kc is still

264
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

under 1% at 6 watts output, and the IM distortion under 2%. An rms input signal
of PA volts is required for 8watts continuous output with asupply furnishing 350 ma
at 48 volts. The amplifier operates with an efficiency of 47% to 60%, and has a
signal-to-noise ratio of better than 98 db.
The performance tests were made with a 16 ohm resistive load. Performance near
maximum power output will vary slightly with transistors of different beta values.
Also, varying values of saturation resistance for the output transistors Q4 and Q5
affect the maximum power output.

2 8 'ins
8
P
o VS RL 3
6 z

2 0
5WATT DISTORTION VS RL cc

0 10 20 30 40 51
0 1 61
0 70 80 90 1CO
e
LOAD (R L IN OHMS)

AMPLIFIER PERFORMANCE VS. LOAD

Figure 11.34

Figure 11.34 shows the load range for maximum performance. It indicates that
for avarying load impedance, such as aloudspeaker, the most desirable range is 16 to
40 ohms. A 16 ohm speaker system is in this range. A 20 to 600 ohm auto-transformer
should be used for driving a600 ohm line.
This amplifier can be used with either the power supply shown in Figure 11.35 or
Figure 10.1 of Chapter 10.
TRIAD
IA F-92A

117VAC

CI, C2, 8 C3 - 1500µI, 50v

POWER SUPPLY FOR STEREO SYSTEM

Figure 11.35

21/
2 Watt Transformerless Amplifier

Figure 11.36 is alower power version of the circuit shown in Figure 11.31. This
21
/
2 watt amplifier uses economical semiconductors, and the output transistors, Q4

265
 11 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS

and Q5, can be fastened with their strap directly to the printed circuit board for
adequate heat dissipation. This circuit requires about 330 millivolts input for 21/ 2

watts power output. At this power level the total harmonic distortion at 1 kc is less
than 1% and the IM distortion less than 2%.

+24V
@150ma

1000
ALL RESISTORS I/2W

Q2
3900 2N3414

04
C) 2N 3402
20 » f-IL--
25V -7-- SILICON
DIODES 470
1N4154 OR IN9 1y 500f
S0974 (GE) I2V + — 1612
Q3 ° LOAD
2N320 I5V

130K
05
122
15V 2700 5 01 2N3402

- w. 2N3392
OUTPUT
15µf
85V
.22
INPUT I8K
470
390

100K
'VVs.

21
/
2 WATT AMPLIFIER
Figure 11.36

12 Watt Transformerless Amplifier

The amplifier shown in Figure 11.31 is limited in maximum power output by
supply voltage and the increasing saturation resistance of the output transistors, Q4
and Q5, as the current increases. The supply voltage can not be increased much
beyond 50 volts at maximum amplifier signal swing without making the VCE rating
for Q1 marginal. Under these conditions the saturation resistance becomes the limit-
ing factor for obtaining increased power output.
The circuit of Figure 11.37 uses two transistors in parallel for each of the outputs.
This enables the saturation resistance to be reduced in half and gives 12 watts output.
The 0.47 ohm resistor used in the emitter of the paralleled transistors gives a more
uniform input characteristic for sharing of the input currents. These emitter resistors,
in addition, aid the bias stabilization. R9 in the emitter of Q3 improves the perform-
ance of this germanium transistor stage through local feedback. The rest of the circuit
is the same as in Figure 11.31.
Performance of the 12 watt circuit is like that given previously for the circuit of
Figure 11.31 except for the distortion vs. power output. Figure 11.39 indicates the
increased power output and also the lower distortion which is a second advantage of
parallel operation of the outputs. Lower distortion results from parallel operation since
the signal current swing in each transistor is approximately halved and thus confined
to the more linear portion of the transfer characteristic.

266
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

1/2 A
(TYPE AGC
OR 3AG) +50V
a360mo
e
I
R5
1500

ALL RESISTORS 1/2 WATT 2N34I6

t R6
7432 (GE) 04 9 06
j6800 OR 2N2108
25207'S
OR 7A3I'S
C3 •
200
50v yDI
1N4154 OR
ID S
2 D974
R8
1K e
R13
.47
Rt4
-47
e5
1500 f
25V 50V 160
.11- • ° LOAD
R9
47

R2
03
C2 2NI924
— 220

RI Rit
01 05 a 07 22
CI 2.79
9-1 11 - WI.. 25336A 2N2107S OUTPJT
OR 263416 OR 7931S
20µf

INPUT
15V
R4
y I5K
R7 <
390.,
I. C4
_.,150µf
Ri. R.,
.470
eR16
.470
_C6
I .22
3V

RI2
33K

12 WATT AMPLIFIER
Figure 11.37

12 WATT AMPLIFIER
Figure 11.38

267
 11 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS

The 12 watt amplifier operates at maximum power output with an efficiency of

67%. This circuit can be packaged with minimum volume and weight without com-
ponent crowding (see Figure 11.38). One of the paralleled output transistors uses
the technique described in Figure 11.29 and the other makes for simplified mounting
using the 2N2196 as previously discussed. All four of the output transistors could be
7A31's, 2N2107's, or all 2N2196's. Each mounting fin is %." x 11
2 "x41
/ 2 "aluminum.
/
If the amplifier is powered by the supply of Figure 11.35. It will provide 10 watts
of continuous power output or 12 watts at Music Power Rating.

HARMONIC
INTERMODULATION - - -
{6KC
AND
60.••_
10 KC

ae 0.5
50^.
.••••••
1KC -

o
1 2 3 4 5 6 7 8 9 10 11 12
POWER OUTPUT (WATTS)

DISTORTION VS. POWER OUTPUT FOR

12 WATT AMPLIFIER
Figure 11.39

15 Watt Transformerless Amplifier

The amplifier in Figure 11.40 has an input stage added to increase the input
impedance from about 3K ohms, as in the previous power amplifiers, to over 200K
ohms. This stage also increases the amplifier sensitivity so that slightly less than 1volt
rins signal is required for full output.
The power frequency response is flat within 1 2 db from 20 cycles to 20 kc. Output
/
impedance is less than 0.3 ohm for good speaker damping. At 15 watts the total
harmonic distortion is less than 1
4 % across the band, 20 cycles to 20 kc. IM distortion
/
(60 and 6000 cps mixed 4:1) is about 1% at 15 watts.
The output transistors should be mounted on aheat dissipator such as IERC #LP
5C3B (IERC, 135 W. Magnolia Blvd., Burbank, California).
Diode D3 has a leakage current which increases with temperature in a manner
similar to the I CO of Q3. D3 can thus shunt this temperature sensitive current to
ground, whereas, if it were to flow into the base of Q5 and Q7, it would be amplified
in the output stages. The standard 1 / ampere fuse (Littlefuse type 3AG) has a de
2

resistance of about 1ohm and is used in the emitter circuit of each output transistor
for bias stabilization, equalization of the input characteristic for parallel operation,
and protective fusing of the transistors. Bias adjust, R2, is set for one-half the supply
voltage across Q5 and Q7. The power supply in Figure 10.3 is more than adequate
to power two of these 15 watt amplifiers for 30 watts of continuous stereo power.
This will give superb performance in a stereo system when used to drive 16 ohm
speakers that have at least moderate sensitivity.

268
 o +60V
FUSES - F4, F5, F6,F7 1500 @400MA
I/2A (TYPE 3AG) STANDARD R5
ALL RESISTORS
1/2 WATT 6800 02
R6 2N2I08

C3 +
200 04 a
06
50V - 2N2107 .5
DI
IN 4154'S
C5
D2 R8 F4 F6 1500» f
+60V IK 50V
30V
BIAS +I h- o
22K ADJ
100K R9 160
R2 47 LOAD

35V 39µ0
C1 2N1614
22K — C2
50/4f 03
-± 50V
•,¡ 4.7 100K 22
20V
MEG. R3 R11
IIV 01A
.220
'
11 2N2I08
05 El 07
2N2107'S
OUTPUT
QI
2N27I2

I-
2V OR I8K 1.2000
390 RIO ingi — .22
INPUT 2N3393 R4 3V F5 i F7
1.8(< R7 1K D3 C6
C4

RI2
33K

15 WATT AMPLIFIER
Figure 11.40
11 AUDIO AND IIIGII FIDELITY AMPLIFIER CIRCUITS

STEREOPHONIC SYSTEMS
Complete semiconductor, stereophonic playback systems may be assembled by
using combinations of previous circuits as indicated in the block diagrams that follow.

20 WATT STEREO WITH 8 OR 16 OHM SPEAKERS

10 WATT
CHANNEL PREAMP POWER
AMP 8 OR 16.Q.
FIG. 11.18
FIG. 11.27 SPEAKER
MICROPHONES,
FM TUNER,
TAPE POWER
DECK, SUPPLY
OR FIG 1128
PHONO
PLAYER
10 WATT
CHANNEL PREAMP POWER
8 OR 16S2
2 FIG. 11.18 AMP
SPEAKER
FIG. 11.27

BLOCK DIAGRAM OF 20 WATT STEREOPHONIC SYSTEM

Figure 11.41

STEREOPHONIC SYSTEMS USING SILICON TRANSISTORS

PREAMPLIFIER 2 1/2 WATT

CHANNEL
FIG I1.22 ,FIG. 11.24 POWER AMP
160
SPEAKER
FIG 11.25 OR FIG. 11.26 FIG. 11.36

PREAMPLIFIER

-EC
CHANNEL 2 1/2 WATT
160
FIG. 11.22,FIG. 11.24 POWER AMP
2 SPEAKER
FIG. 11.25 OR FIG 11.26 FIG. 11.36

5 WATT STEREOPHONIC SYSTEM

Figure 11.42

PREAMPLIFIER 8 WATT

E(
CHANNEL
FIG 11.22,FIG. 11.24 POWER AMP 160
SPEAKER
FIG 11.25 OR FIG. 11.26 FIG. 1.31

POWER SUPPLY
FIG. 11.35 OR
FIG. 10.1

PREAMPLIFIER 8 WATT
* CHANNEL r el 16D.
FIG. 11.22,FIG. 11.24 POWER AMP
2 44
1 SPEAKER
FIG. 11.25 OR FIG. 11.26 FIG. 11.31

16 WATT STEREOPHONIC SYSTEM

Figure 11.43

270
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

EC
PREAMPLIFIER 12 WATT
CHANNEL
FIG 11.22 ,FIG. 11.24 POWER AMP ISO
SPEAKER
FIG 11.25 OR FIG. 11.26 FIG. 1.37

POWER SUPPLY
FIG II 35 OR
FIG 10 I

PREAMPLIFIER 12 WATT

E(
* CHANNEL
FIG. 11.22,FIG. 11.24 POWER AMP 1611
2 SPEAKER
FIG. 11.25 OR FIG. 11.26 FIG 11 37

24 WATT STEREOPHONIC SYSTEM

Figure 11.44

PREAMPLIFIER 15 WATT
CHANNEL 1611
FIG 11.22,FIG. 11.24 b. POWER AMP
-1„. SPEAKER
1
FIG 11.25 OR FIG. 11.26 FIG II 40

POWER
SUPPLY
FIG. 10.3

PREAMPLIFIER 15 WATT
CHANNEL 160
FIG. 11.22,FIG. 11.24 POWER AMP
2 SPEAKER
FIG. 11.25 OR FIG. 11.26 FIG. 11.40

30 WATT STEREOPHONIC SYSTEM

Figure 11.45

STEREO HEADPHONE AMPLIFIER

The stereo headphone amplifier shown in Figure 11.46 will drive dynamic head-
phones of 75 to 400 ohms impedance to apower level of 45 to 60 milliwatts. Program
source may be from atuner or from records using a ceramic cartridge. This amplifier
may also be used as alow level 600 ohm line driver.
Typical performance of the amplifier with a 200 ohm load, such as the AKG
Model K50 dynamic headphones, has less than 1% 1M distortion for 10 milliwatts
output. At 1milliwatt level or less (usual listening level with the K50) the distortion
level is below the measuring capability of most test equipment. Frequency response
is flat within -± 1
/ db from 20 cycles to 20 kc. The input impedance is 1 megohm
2

from 30 cycles to 2.5 kc and gradually decreases to 400K ohms at 15 kc. An input
signal level of 110 millivolts will give 10 milliwatts output, and 250 millivolts input
gives the maximum output of 60 milliwatts into a200 ohm load.
The high input impedance is attained by using a "bootstrapped" bias network for
Q1 and also with the negative feedback via C4 and R6. This high impedance will not
load the output of atuner and can be readily adapted to many of the standard ceramic
cartridges. Figure 11.47 shows a practical equalization and level control circuit for a
cartridge capacitance of 1000 pf.

271
11 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS

+I8V

TIOV IW IW TIOV
RI R2 I, 1
CI
00 R103 10101 R1
102 R
ig
18K IK 2O
R03.1 5% , CI,2
25 100 8104
84
220K 220K

02 0102
2NI415 65V 6.5V 2N 415 R1051
47K 47K C102
C2
01 .05
05 0101
2N3393 1i—o IN
INDHI 2N3393
C4
C3 86 10 8106 C103
4.7K 3V C5 • • C105 C104
10 3V
3V , 4.7K Lev
65 V 100 — — 100 -1 •
•%.•
I5V I5V

47K 5
5

e 89 RIO RII0 3V 8108

4.7K
8107
47K

GNDe 'AND
GNDOUT OUT AND

NOTE. SELECT 84 AND 8104 TO GIVE 13 VOLTS AT EMITTER OF 02 AND 0102.

03 AND 0103-2N2868 OR IIC1536(G.E.)
ALL RESISTORS 1/2 WATT, UNLESS NOTED.
ALL CAPACITORS IN ,,fd

Figure 11.46 STEREO HEADPHONE AMPLIFIER

240K I STEREO
• HEADPHONE

3MEG I AMPLIFIER
ASTATIC 170 AKG
1000pf si 1
STEREO K50
CARTRIDGE DYNAMIC
1000pf FIG. 11.46
HEADPHONES

3 MEG
240K

DUAL 3MEG POTENTIOMETER

Figure 11.47 PHONO -HEADPHONE STEREO SYSTEM

A printed circuit board is shown in actual size in Figure 11.49. The component
assembly of the Figure 11.46 circuit is shown in Figure 11.48.

\-PRINTED BOARD

Figure 11.48 STEREO AMPLIFIER COMPONENT ASSEMBLY

272
AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

PRINTED CIRCUIT BOARD

CI

bl)

- IN
NJ
(

273
11 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS

TAPE RECORDING AMPLIFIER WITH BIAS

AND ERASE OSCILLATOR
The design of amagnetic recording amplifier will be discussed with equalization
to produce a flat final system response with a Nortronics low impedance recording
head when the playback preamplifier is adjusted for NAB equalization at 71 2 "/second
/
tape speed. This design has sufficient input impedance to permit the use of amedium
high impedance magnetic microphone and the circuit is capable of providing audio
current at least 15 db above reference recording level at 1kc.
The recording amplifier must perform several functions to properly impress a
magnetic recording on tape. The microphone, or high level, signal must be amplified,
pre-equalized, and presented as arecording current signal to the head. At the same
time an oscillator, operating in this case between 70 kc and 80 kc, provides abias cur-
rent which is electrically added to the audio current supplied to the head. Figure 11.50
illustrates ablock diagram for one channel only of the amplifier that will be described.

HI— LEVEL INPUT I

-2N508A

POWER
SUPPLY

MIC. INPUT BIAS

2-2N 508A'S -I -
2N5o8A TRAP

'EQUAL- I
IIZER 4 I

2— 7A3IS (GE) BIAS ADJ.

BIAS 84 ERASE
OSCILLATOR REC.
ERASE rà
HEAD HEAD

_t
B2Q4R
SEQ 4
(NORTRONICS)

DIAGRAM OF RECORDING SYSTEM

(ONE CHANNEL)

Figure 11.50

RECORDING AMPLIFIER*
Record equalization for 7.5 ips is arrived at by extrapolating back to the NAB
playback curve, the basic Nortronics constant current head response curve, and assum-
ing that flat system response from 50 to 20 kc is desired. The NAB playback curve is
shown in Figure 11.51. It represents what the output voltage of the amplifier will
look like when the input is energized with aconstant voltage signal in series with the
playback head impedance over the audible range.
*Courtesy of Nortronics Co., 8101 West 10th Avenue, N., Minneapolis 27, Minn. Customer Engi-
neering Bulletin No. 8.

274
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

20

° is
1
-
2
D 10
a.
D 5
o
cr 0

-5

10

50-- 100 500 IKC 5 10 20KC

FREQUENCY

PLAYBACK AMPLIFIER RESPONSE WITH CONSTANT VOLTAGE

INPUT SIGNAL IN SERIES WITH HEAD IMPEDANCE
Figure 11.51

20

15

50", 100 500 IKC 5 10 20KC

FREQUENCY

TYPICAL PLAYBACK HEAD RESPONSE FROM A TAPE

RECORDED WITH CONSTANT CURRENT AT PEAK BIAS AT 7.5 IPS •
Figure 11.52

Figure 11.52 is aplot of the constant current characteristic of a typical Nortronics

head. This curve would result when taking the unequalized, open circuit voltage from
the terminals of a playback head, where the recorded signal was with a constant
recording current and bias current adjusted to peak at 1kc response. When the curve
in Figure 11.52 is subtracted from the curve in Figure 11.51 the resultant curve is
shown by A in Figure 11.53. It is the inverse of this curve that is required during
the recording process to give an overall flat system response. The inverted curve
represents the desired audio current for the recording head.

15

10

o 0

10

15

••••• 100 500 IKC 5 10 20KC

FREQUENCY

RECORD EQUALIZATION CHARACTERISTICS AT 71/

2"/SEC.

Figure 11.53

275
TI -BURNSTE1N APPLEBEE 18 B 506
R3-50K, AUDIO TAPER 117 VAC
R8-10K,LINEAR
RESISTORS 1/2 WATT UNLESS NOTED Q4
2N508A ON

30 VAC R22 100 IW

C5 I/25V i\AA/
MONITOR

RI2 Ç RIO CI3 —C14

68K a2K INI69aS + 1000
5001- -
50V 25V

HIGH LEVEL INPUT

RI4 2.2K
-I9VDC -27 VDC
0X
220K
REC. I
R4 ADJ. C7 - RIS
Re 200 TO BIAS AND
I5K R7 10K 25v + 330K ERASE OSC
R2 120K RII
-4VDC -I4V
IK 22K
01 DC
02 6
2N508A 2N508A 1/25V
C2 1/25 CI
MIC INPUT 00022
03 330 pf RECORD
HEAD-8204R
2N508A
1/25V CII
R28
Wv
100K ±1%
R5
R20

H
R3 100
50K 07.5
ee°
LEVEL C2I 0.0047
L2 11
330 R29
IOMH
Pf 150K MILLER
+1% 7OF 102 AI

Figure 11.54 RECORDING AMPLIFIER

 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

The first two stages of the recording amplifier in Figure 11.54 have asmall amount
of negative feedback through R7 to stabilize gain, increase input impedance, and
generally provide amplification with low distortion.
The equalizing components in the amplifier include R11, C6, R13, C9, C11, C12,
and L2. With frequencies between 200 cycles and 1500 cycles, RI 1and R13 act as a
straight voltage divider between the output of the Record Current Adjust and the
base input of the last stage. At frequencies below 200 cycles the capacitive reactance
of C9 becomes increasingly higher as the frequency goes down. This produces the
slightly rising characteristic which is called for in Figure 11.53 at the low end.
At frequencies above 1500 cycles capacitor C6 begins to shunt resistor R11 pro-
ducing an increasing amplitude of signal at the base of the driver transistor as the
frequency goes up. The series resonant action of C11 and L2 provides a further assist
to the high end boost, up to apeak of approximately 20 kc. This LC peaking circuit
offers a further advantage of suppressing noise above 20 kc. The resulting curve is
shown in Figure 11.55. Note that this curve is nearly the same as is called for in
Figure 11.53. 0db is 0VU at 1kc with ahead current of 0.05 ma (50 microamperes).
Note that the amplifier overload point is above tape saturation at 1kc. With aquality
playback system such as Figure 11.18 or Figure 11.22 aflat system response between
50 cycles and 15 kc is easily attained at 7.5 ips. It must be remembered that full
frequency response at 7.5 ips must be checked at least 15 db below reference record-
ing level, and at least —20 db at 375 ips.

*-
25 3.75
cr E
Ir in 20
a••••
o •
0o 15 AMPLIFIER OVERLOAD

ta -
Cà 10 SATURATION
7.5

c.) z
_
cr O

50 ^- 100 500 IKC 5 lO 20 30KC

FREQUENCY

Figure 11.55 RECORD AMPLIFIER WITH B2Q4R

Record equalization for 3.75 ips is shown also in Figure 11.55 and is obtained by
simply switching the additional capacitor (C12) into the circuit.
A bias trap consisting of Li and CI provides a high impedance to the bias fre-
quency and thus reduces bias intermodulation at the collector of the driver stage.
Adjust Li for minimum bias signal at the collector of Q3. C21 is abypass filter for the
bias or higher rf frequencies.
The use of the gain control before the first stage will not be a source of noise
if agood quality control is used. There are several good reasons for placing the control
in this position, they include: the amplifier cannot be over-loaded under any condi-
tions; and feedback can be applied between the first and second stage which will help
to make the gain independent of transistor beta variations. The philosophy of design
in this amplifier tends to promote operation at the highest signal-to-noise ratios under
all conditions. The standard VU-meter which is driven by the emitter-follower is,
in turn, directly connected to the output of the first two stages. Therefore, when a
recording is being made sufficiently high in level to give proper reading on the VU-
meter (peaks from 0to +2) the operator is making full and proper use of signal level
in the first two stages.
Construction of the amplifier should follow good standard practice and excessive
heat should be avoided when soldering transistors and components. The power trans-

277
11 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS

former should be located away from the input transistor and, if possible, it should
be shielded with an external steel case. For stereo recording all of the Figure 11.54
circuit would be duplicated for the second channel except for the power supply. R22
can be reduced to maintain a27 volt supply for astereo system.

TAPE ERASE AND BIAS OSCILLATOR

As previously mentioned it is necessary to add a supersonic "bias current" to the
audio current during the recording process; the amplitude (or magnitude) of this
current is approximately ten times the amplitude of the average audio current. If it
is too high it will result in unwanted degeneration of the higher audio frequencies,
and if it is too low, recording stability, distortion, and dynamic range will all be
adversely affected. At the so called "peak bias" operating mode, the 1 kc signal
recorded on the tape will be at its maximum value; in practice this is a good point
to operate arecording system.
In this application diffused silicon transistors are used since they offer the advan-
tage of efficient operation with no external heat sink required. This silicon transistor
is the 2N2106 or 7A30, and it has the standard TO-5 package.
The circuit of Figure 11.56 provides ample power to give a minimum of 60 db
erasure of saturated tape (at 400 cycles) with a stereo erase head. This is accom-
plished with at least 10 ma of 70 to 80 kc signal in the Nortronics SEQ4 erase head.
The total power output of this circuit is approximately 11 / watts with an efficiency
2

of 60%. This erase signal increases the noise level only about 1 db on bulk erased
tape. The balanced push-pull oscillator circuit of Figure 11.56 has negligible dc or
even harmonic distortion in the output waveform which is arequirement for minimum
increase in tape noise during playback. Total harmonic distortion is less than 1 / %.
2

SI

RECORDING 3
BIAS ADJUST
R2I
470 500K
Df LINEAR pf
TO RECORDING. I
2ND CHANNEL
HEAD

BROWN YELLOW WHITE 12mo

NORTRONICS ERASE HEAD

760-T2 NORTRONICS SEO 4

BLUE BLUE
SWITCH SI
1 UPPER TRACK ONLY
2 STEREO
3 LOWER TRACK ONLY

05 06
2N2I06 2N2I06
OR OR
7A30 7A30 (G.E.)

NO. 47
27 30 a LAMP
RECORD
S2 IW
5jaf -27V
25V + IW PLAYBACK

Figure 11.56 TAPE ERASE AND BIAS OSCILLATOR

278
 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS 11

C16 in the resonant tank circuit determines the frequency of the oscillator. Since
the efficiency of the erase head decreases above approximately 76 kc, this was chosen
as the operating frequency for the oscillator. Also, higher frequencies will be more
difficult to handle in equipment with cable capacitance losses, circuit switching, etc.
The 27 ohm resistors provide negative feedback which help to compensate for
component variations in the circuit. The transistor interchangeability vs circuit per-
formance is very good.
This circuit is a cross-coupled multivibrator with a tuned load. The erase head
winding is coupled to the transformer tap with 560 pf which series resonates with
the erase head winding. Thus, the load appears largely resistive on the transformer
secondary winding. This permits switching a2.7K resistor in place of the series tuned
erase head load without changing the loading or the frequency of the oscillator. This
permits erasing and recording on only one channel of the tape. The series resonant
circuit of the erase head winding and the 560 pf capacitor has alow Q of about 11 /;
2

variations in either the L or the C, therefore, will not alter appreciably the value of
erase current in the head.
The 76 kc bias current for the recording head is adjusted with R21. Bias current
can be measured by measuring the voltage across the 100 ohm resistor in series with
the record head in Figure 11.54. A VTVM, such as a Ballantine 310A, is used for
this measurement. The audio signal record current can also be measured at R20, but
switch S2 in Figure 11.56 must be in the playback position to stop the oscillator bias
current. The approximate reference level 1kc record signal current for the Nortronics
B2Q4R is 0.05 ma and the bias current is 0.70 ma. Accurate determination of bias
and record currents can best be achieved by using a deck with an independent play-
back head and amplifier. Under these conditions the bias current is adjusted until the
1 kc response is maximum and the record current is adjusted until "0—VU" on the
meter is one-fourth (—12 db )of saturation level.

REFERENCES
("McKnight, J.C., "Signal-to-Noise Problems and a New Equalization For Magnetic Recording of
Music." Audio Engineering Society Preprint #58, presented October 1958.
Jones, D.V., "Class B Power Amplifier Performance with Silicon Transistors," Audio Engineering
(2)

Society Convention Paper, presented October 1960.

(3>Geiser, D.T., "Using Diodes as Power Supply Filter Elements," Electronic Design, June 10, 1959.

("Jones, D.V., "All Transistor Stereo Tape System," Electronics World, July 1959.

NOTES

279
11 AUDIO AND HIGH FIDELITY AMPLIFIER CIRCUITS

NOTES

2S0
RADIO RECEIVER CIRCUITS 12

Transistorized radio receiver circuits are of two main categories; portable and line
operated. The transistors used may be germanium or silicon or a combination of the
two. Practical working circuits representing some of the more popular radios are
offered at the end of this Chapter.

SILICON TRANSISTORS
Silicon transistors in low cost epoxy housings have recently been introduced by
General Electric for use in FM, AM, and TV receivers. Figure 12.1 shows the size and
shape of the new transistor as compared to the conventional TO-18 and TO-5 pack-
ages. Figure 12.2 presents an internal view of the construction.

SIZE COMPARISON OF LOW COST EPDXY

HOUSING TO TO-18 AND TO-5
Figure 12.1

The transistors are manufactured by the planar passivated process, which is the
very latest technique employed on high reliability military transistors. Low costs are
achieved by an entirely new concept of highly mechanized manufacture, the use of
the epoxy package, and high speed automatic testing.
When designing radio circuits with silicon transistors there is very little difference
in technique as compared to germanium transistors, with the major exception of the
dc biasing circuits. Silicon transistors will exhibit alarger change in quiescent collec-
tor current when the supply voltage is varied than will germanium transistors if con-
ventional biasing circuits are used. In portable radios, where operation is required at
half the original battery voltage, aspecial biasing technique is required. This has been
discussed on page 101 of Chapter 4. Other more obvious methods would be the use
of aZener diode to regulate the supply voltage at avalue below the original battery
voltage, or the use of asingle, separate battery to supply only the base circuits. Since
current drain would be very low, the life of the battery would be essentially its shelf life.
ADVANTAGES
Some of the advantages to be gained by the use of silicon transistors are
1. Low leo permits simpler circuit design and improved high temperature
operation.
2. Stable characteristics are guaranteed by the passivated surface.
3. Consistent characteristics are inherently produced by the planar process

281
12 RADIO RECEIVER CIRCUITS
,'-------- "-- '•
• ,i

I1
4-- EPDXY
1
KO VAR

PELLET

PHENOLIC
HEADER
INTERNAL VIEW
OF 2N2711 AND
2N2921 SERIES
Figure 12.2

E c B

which simplifies bias circuits, makes possible fixed neutralization of col-

lector feedback capacity, and assures constant power gain.
4. Small solid package is practically immune to shock and vibration.
5. High cut-off frequency in excess of 100 Mc assures aconstant, high power
gain across the frequency band.
6. High betas of 500 and higher are perfectly practical and useable with
silicon transistors. This permits high gain AVC systems and high gain
audio systems.

LINE OPERATED RECEIVERS

Subsequent sections are devoted to astage by stage discussion of portable receivers
and with few exceptions they are applicable to line operated receivers. The main
differences to consider are the derivation of a suitable supply voltage from the line
voltage, the higher audio output generally required, and the feasibility of using Class A
output stages since power consumption is not very important.
The most economical design, the Four Transistor Line Set, is shown in Figure
12.21. Incorporation of aClass A output stage, with its constant current drain, permits
the use of a simple half wave rectifier and dropping res:stance. The resistance may
consist of alight bulb, ahigh resistance line cord, or an actual resistor. Even with an
inefficient power supply of this nature, power consumption of the transistor set is only
one third that of atube set. Sensitivity, selectivity, and audio output of the transistor
receiver are all equal or superior to an equivalent 5tube AC-DC radio.
A more deluxe radio for those who prefer push-pull output is the Six Transistor
Line Set shown in Figure 12.22. The varying load current drawn by the output
necessitates alow impedance power supply in order to maintain the B+ voltage nearly
constant as the load power is increased. A "filament" step down transformer and
half-wave rectifier is sufficient to allow close to one watt audio output power.

RADIO FREQUENCY CIRCUITS

A tuned RF stage at the input of a radio receiver will greatly enhance perform-
ance in several important respects. Improved signal to noise ratio, sensitivity, selec-
tivity, and AVC are all benefits to be expected from the use of atuned RF stage.
In establishing the maximum useable sensitivity of a receiver (or the minimum
signal that can be satisfactorily received) the predominating factor is the noise con-

282
 RADIO RECEIVER CIRCUITS 12

TO
CONVERTER

0+ 9 VOLTS

AVC

TUNED RF STAGE
Figure 12.3

tribution of the first stage. If the first stage has a high equivalent noise input, then
alarge signal will be required to overcome the noise and produce an intelligible out-
put. Once the signal and noise have been inter-mixed, it is practically impossible to
separate them. The effect of noise added by succeeding stages is of secondary impor-
tance because it is reduced by the gain of the first stage according to the relation
NF-
NF = NFi - --
C,
where
NF is the overall receiver noise figure
NF, is the RF stage noise figure
NF2 is the converter stage noise figure, and
Gi is the RF stage gain.
A transistor used as a linear RF amplifier will inherently be several db quieter
than the same transistor used as a converter because the mixing action of a converter
produces additional noise components not present in the RF stage. For the ultimate
in sensitivity therefore, an RF stage is required.
An alternative method to describe noise performance, which in practice is simpler
to measure, is signal to noise ratio, S/N. The end result, however, is identical; afigure
of merit which describes areceiver's ability to perform on weak signals. ENSI ratio or
equivalent noise sideband input is still another method. For a complete description of
these procedures see the Radiotron Designer's Handbook by Langford-Smith, or appro-
priate IEEE standards.
Improved selectivity results directly from the extra tuned circuit in the collector
of the RF stage. By narrowing the bandwidth, unwanted signals close to the desired
signal will be rejected. Image frequencies (desired RF signal frequency plus twice the
intermediate frequency, IF) will also be greatly attenuated.
Automatic volume control, AVC, is improved by an RF stage for several reasons.
In the ordinary converter input radio, AVC power is taken from the detector and
applied to the first IF stage. There is only one stage of gain between the controlled
stage and the detector, which is the second IF. In a receiver with an RF stage there
will be at least two stages of gain between the controlled stage and the detector, the
converter and IF. There will therefore be more loop gain within the AVC closure, and
better AVC action. A small amount of AVC may also be placed on the IF for addi-
tional control.
A converter is not usually AVC'd, as the bias change would cause an appreciable

283
12 RADIO RECEIVER CIRCUITS

shift in oscillator frequency. When the converter is the input stage it must be operated
at maximum gain for best performance on weak signals. Under strong signal condi-
tions, it still will be high gain and will deliver alarge signal to the IF, tending to cause
overload. With an RF stage, control is applied to the very first amplifier, which is the
most effective place. Blocking of the converter on strong signals is greatly reduced by
AVC on the RF stage, as the signal to the converter can be less than the incoming
signal.
However, there are afew disadvantages in using an RF stage: athree-gang tuning
condenser is required which occupies more space and is more expensive; and, due to
the extra tuned circuit the receiver is more difficult to align and track.

AUTODYNE CONVERTER CIRCUITS

The converter stage of a transistor radio is a combination of a local oscillator, a
mixer, and an IF amplifier. A typical circuit for this stage is shown in Figure 12.4.

I5K:500C/
AUTOMATIC 725
A
AC 190.6 AA&
TO FIRST
IF STAGE

_J

AUTODYNE
CONVERTER
Figure 12.4

FOR ADDITIONAL INFORMATION SEE PAGE 299

Redrawing the circuit to illustrate the oscillator and mixer sections separately, we
obtain Figures 12.5 and 12.6.
The operation of the oscillator section in Figure 12.5 is as follows: random noise
produces aslight variation in base current which is subsequently amplified to alarger
variation of collector current. This ac signal in the primary of L. induces an ac current
into the secondary of L. tuned by CBto the desired oscillator frequency. C2 then couples
the resonant frequency signal back into the emitter circuit. If the feedback (tickler)
winding of L2 is properly phased the feedback will be positive (regenerative) and of
proper magnitude to cause sustained oscillations. The secondary of L2 is an auto-
transformer to achieve proper impedance match between the high impedance tank
circuit of L2 and the relatively low impedance of the emitter circuit.

2NI087 CB

OSCILLATOR
SECTION
Figure 12.5

+ 9V

284
 RADIO RECEIVER CIRCUITS 12
LI TI

MIXER
SECTION
Figure 12.6

0I9V

C, effectively bypasses the biasing resistors R3 and R3 to ground, thus the base is
ac grounded. In other words, the oscillator section operates essentially in the grounded
base configuration.
The operation of the mixer section in Figure 12.6 is as follows: the ferrite rod an-
tenna La exposed to the radiation field of the entire frequency spectrum is tuned by CA
to the desired frequency (broadcast station).
The transistor is biased in a relatively low current region, thus exhibiting quite
non-linear characteristics. This enables the incoming signal to mix with the oscillator
signal present, creating signals of the following four frequencies
1. Local oscillator signal
2. Received incoming signal
3. Sum of the above two
4. Difference between the above two.
The IF load impedance Ti is tuned here to the difference between the oscillator
and incoming signal frequencies. This frequency is called the intermediate frequency
(IF) and is conventionally 455 KC. This frequency will be maintained fixed since CA
and CBare mechanically geared (ganged) together. 11, and C3 make up afilter to pre-
vent undesirable currents flowing through the collector circuit. C3 essentially bypasses
the biasing and stabilizing resistor 11, to ground. Since the emitter is grounded and
the incoming signal injected into the base, the mixer section operates in the grounded
emitter configuration.

IF AMPLIFIERS AND AVC SYSTEMS

A typical circuit for atransistor IF amplifier is shown by Figure 12.7.

AUTOMATIC 725
AUTOMATIC 725
(EXO -3926)
2N293

500.a
I OUTPUT

Figure 12.7 IF AMPLIFIER

285
12 RADIO RECEIVER CIRCUITS

The collector current is determined by avoltage divider on the base and a large
resistance in the emitter. The input and output are coupled by means of tuned IF
transformers. The .05 capacitors are used to prevent degeneration by the resistance
in the emitter. The collector of the transistor is connected to a tap on the output
transformer to provide proper matching for the transistor and also to make the per-
formance of the stage relatively independent of variations between transistors of the
same type. With a rate-grown NPN transistor such as the 2N293, it is unnecessary
to use neutralization to obtain a stable IF amplifier. With PNP alloy transistors, it
is necessary to use neutralization to obtain a stable amplifier and the neutralization
capacitor depends on the collector capacitance of the transistor. The gain of a tran-
sistor IF amplifier will decrease if the emitter current is decreased. This property
of the transistor can be used to control the gain of the IF amplifier so that weak
stations and strong stations will produce the same audio output from aradio. Typical
circuits for changing the gain of an IF amplifier in accordance with the strength
of the received signal are explained in the AVC section of this chapter.
AVC is a system which automatically varies the total amplification of the signal
in a radio receiver with changing strength of the received signal carrier wave. From
the definition given, it would be correctly inferred that amore exact term to describe
the system would be automatic gain control (ACC).
Since broadcast stations are at different distances from a receiver and there is a
great deal of variation in transmitted power from station-to-station, the field strength
around areceiver can vary by several orders of magnitude. Thus, without some sort
of automatic control circuit, the output power of the receiver would vary considerably
when tuning through the frequency band. It is the purpose of the AVC, or AGC,
circuit to maintain the output power of the receiver constant for large variations of
signal strengths.
Another important purpose of this circuit is its so-called "anti-fading" properties.
The received signal strength from adistant station depends on the phase and amplitude
relationship of the ground wave and the sky wave. With atmospheric changes this
relationship can change, yielding anet variation in signal strength. Since these changes
may be of periodic and/or temporary nature, the AVC system will maintain the
average output power constant without constantly adjusting the volume control.
The AVC system consists of taking, at the detector, avoltage proportional to the
incoming carrier amplitude and applying it as anegative bias to the controlled amplifier
thereby reducing its gain.
In tube circuits the control voltage is a negative going dc grid voltage creating
aloss in transconductance (Gm).
In transistor circuits various types of AVC schemes can be used.

EMITTER CURRENT CONTROL

As the emitter current of atransistor is reduced (from 1.0 ma to .1 ma for instance)
various parameters change considerably (see Figure 12.8).
The effect of these changes will be twofold
1. A change in maximum available gain, and
2. A change in impedance matching since it can be seen that both hob
and hib vary radically.
Therefore, a considerable change in power gain can be obtained as shown by
Figure 12.9.
On the other hand, as aresult of leo (collector leakage current) some current always
flows, thus atransistor can be controlled only up to a point and cannot be "cut-off"
completely. This system yields generally fair control and is, therefore, used more than
others. For performance data see Figure 12.10.

286
 RADIO RECEIVER CIRCUITS 12

10

Vc 5v
hob

hro

hf
•hfb

GND.
EMITTER —

hib

.2 .5 2 5 10
EMITTER BIAS,MA.

CHARACTERISTICS VS. EMITTER CURRENT

h PARAMETERS VS. EMITTER BIAS CURRENT

Figure 12.8

db
34
Vo. •9v
32

30
VCE •---
5i
-7 \

28

26

24

22
GE 2NI087
AGC CURVE
20
poviE8 GAIN VS EMITTER CURRENT
INPUT MeCHED AT I. • Imo
OUTPUT TUNED AT 455 KC
rc 2LOAD • 15Kn; Vo. • 5 VOLTS
16
o

12

10

2 .4 .6 B 2 4 6 8
EMITTER CURRENT -

POWER GAIN VS. EMITTER CURRENT

Figure 12.9

287
 12 RADIO RECEIVER CIRCUITS

EMITTER CURRENT
PLUS AUXILIARY A.V.0 DIODE
+6

+4

/*
+2
IDEAL CURVE ./'

EMITTER CURRENT
CONTROL ONLY
POWER OUTPUT IN DB

N (OVERLOAD
OBTAINABLE
\ ABOVE .1 V/ m
CURVE
\ YIELDS DISTORTION)

—9

—10

/l/
—12
vEAK
—14 iSIGNAl
joSD STRONG
SI GNALS
—16

—18
0.0001 0.001 0.01 01 1.0

SIGNAL STRENGTH IN VOLTS /METER

Figure 12.10 IDEAL VS. TYPICAL AVC PERFORMANCE

AUXILIARY AVC SYSTEMS

Since most AVC systems are somewhat limited in performance, to obtain im-
proved control, auxiliary diode AVC is sometimes used. The technique used is to
shunt some of the signal to ground when operating at high signal levels, as shown by
Figure 12.11.

CR1

T2

TO
2nd
CONVERTER
•
TRI

R2

bb AVC
FROM DETECTOR

I C

Figure 12.11 AUXILIARY DIODE AVC SYSTEM

288
 RADIO RECEIVER CIRCUITS 12
In the circuit of Figure 12.11, diode CR, is back-biased by the voltage drops across
R4 and R2 and represents ahigh impedance across Ti at low signal levels. As the signal
strength increases, the conventional emitter current control AVC system creates a
bias change reducing the emitter current of the controlled stage. This current reduction
coupled with the ensuing impedance mismatch creates apower gain loss in the stage.
As the current is further reduced, the voltage drop across R2 becomes smaller thus
changing the bias across CR,. At apredetermined level CR, becomes forward biased,
constituting alow impedance shunt across Ti and creating a great deal of additional
AVC action. This system will generally handle high signal strengths as can be seen
from Figure 12.10. Hence, almost all radio circuit diagrams in the circuit section of this
chapter use this system in addition to the conventional emitter current control.

DETECTOR STAGE
In this stage (see Figure 12.12), use is made of aslightly forward biased diode in
order to operate out of the square law detection portion of the I-V characteristics. This
stage is also used as source of AGC potential derived from the filtered portion of the
signal as seen across the volume control R.. This potential, proportional to the signal
level, is then applied through the ACC filter network C4, Ri and C. to the base of the
1st IF transistor in amanner to decrease collector current at increasing signal levels.
R. is abias resistor used to fix the quiescent operating points of both the 1st IF and the
detector stage, while Co couples the detected signal to the audio amplifier. (See
Chapter 11 on Audio Amplifiers. )
IF OUTPUT TRANSFORMER
r

FROM 2nd IF I IN64G

COLLECTOR ' OR
EQUIV.

C6
°

AVC R9 TO AUDIO
TO COLD SIDE OF 1st IF AMPLIFIER
TRANSFORMER TC5
BPLUS
DETECTOR STAGE

Figure 12.12

REFLEX CIRCUITS
"A reflex amplifier is one which is used to amplify at two frequencies — usually
intermediate and audio frequencies."'
The system consists of using an IF amplifier stage and after detection to return.the
audio portion to the same stage where it is then amplified again. Since in Figure 12.13,
two signals of widely different frequencies are amplified, this does not constitute a
"regenerative effect" and the input and output of these stages can have split audio/IF
loads. In Figure 12.14, the IF signal (455 KC) is fed through T2 to the detector circuit
CR1, C. and R.. The detected audio appears across the volume control R. and is re-
turned through C4 to the cold side of the secondary of Ti.
*F. Langford-Smith, Radiotron Designers Handbook, Australia, 1953, p. 1140

289
12 RADIO RECEIVER CIRCUITS

1 AUXILIARY

A.V.C.

IN1140 AUDIO

AUTODYNE FIRST IF 2nd IF • DIODE AUDIO

DETECTOR + POWER
CONVERTER AMPLIFIER AUDIO DRIVER
A.V.C. OUTPUT

2NI097 2N292 2NI69 2NI414

AUD

•.VC

Figure 12.13 REFLEX RECEIVER SYSTEM

AUDIO
OUTPUT

B PLUS

REFLEX IF-DETECTOR CIRCUIT

Figure 12.14

Since the secondary consists of only afew turns of wire, it is essentially a short
circuit at audio frequencies. C, bypasses the IF signal otherwise appearing across
the parallel combination of R, and 112. The emitter resistor Ra is bypassed for both
audio and IF by the electrolytic condenser C2. After amplification, the audio signal
appears across R. from where it is then fed to the audio output stage. C. bypasses R.
for IF frequencies and the primary of T2 is essentially ashort circuit for the audio signal.
The advantage of reflex circuits is that one stage produces gain otherwise
requiring two stages with the resulting savings in cost, space, and battery drain. The
disadvantages of such circuits are that the design is considerably more difficult,
although once a satisfactory receiver has been designed, no outstanding production
difficulties should be encountered. Other disadvantages are asomewhat higher amount
of "playthrough" (i.e. signal output with volume control at zero setting), and amini-
mum volume effect. The latter is the occurrence of minimum volume at a volume
control setting slightly higher than zero. At this point, the signal is distorted due to the
balancing out of the fundamentals from the normal signal and the out-of-phase play-
through component. Schematics of complete receivers will be found at the end of this
chapter and in Chapter 15.

290
 T2 T3

COMPLETE RADIO RECEIVER CIRCUIT DIAGRAMS

RADIO 1NCUSTR£S RADIO INDUSTRIES RADIO INDUSTRIES
4,B222 OR IN648 re8222 OR W8223 OR BECAUSE OF THE SPECIAL
AUTOMATIC C A NATURE OF MANY OF THE
AUTOMATIC AUTOMATIC COMPONENTS USED IN THIS
85.7258
BS-729G BS-6140 CIRCUIT HOME CONSTRUC •
DETECTOR ION IS NOT RECOMMENDED
111164G 14

HL t I
CRI lc A 950D,/ VC

. 4-
I
T 1
J
CR2

R12

C13;11-
--

/CONVERTER
TRI 1ST IF TR3
TR2
REEL X
C6 PI
S
CI

4
I 142 R6 R9
RI RI C9
C3
1
L•
9 VOLTS

MM R0 R14

- C5
147

RADIO RECEIVER CIRCUITS

RI, RI4, 1500 OHM CI, CI I, .02,AL Id LI, 435,01810%
Fr2 , 6800 OHM C2,C3,C7, 0414 L2, 250ph±10%
R3, . 27,000 OHM C4,C6,C9,C13- 05pfd CRI C17', IN646 OR EQUIV.
R4, R11, — 470 OHM C5, 15pf d 12V ACI
145, 82,000 OHM CB , 50pfd, 3V AC2 —89.5 P/C MODEL 242
R6, 330 OHM CO , 6pfd, I2V
PERFORMANCE
R7,R8,— 3300 OHM C12, 50pf d, I2V
NOMINAL SENSITIVITY 200 MICROVOLTS/METER
R9, 10,000 OHM CI4, 100pfd, 12V
(MEASURED WITH 5 MILLIWATTS REFERENCE POWER OUTPUT )
RIO, 91,000 OHM TRI, GE 2N1086,2N10864 MAXIMUM POWER OUTPUT ' 75 MILLIV/ATTS
RIO, VOLUME CONTROL OR 291087 CONVERTOR SELECTIVITY AT -6db 8.0 KC /S
10.000 OHM AUDIO TAPER TR2, 29290 1ST IF SELECTIVITY AT -60db 60.0 KC/S
1413, 100 OHM TR3, GE 29169 OR 2N1121 REFLEX TOTAL BATTERY DRAIN 17.0 MILLIAMPS
185,— 120 OHM TR9, 291415 AUDIO
*FOR FURTHER COMPONENT INFORMATION SEE PAGE 299

FOUR TRANSISTOR - 9 VOLT REFLEX RECEIVER

Figure 12.15
 12
RADIO INDUSTRIES RADIO INDUSTRIES RADIO INDUSTRIES
* 8222 OR *8222 OR .8223 OR PUSH-PULL
AUTOMATIC AUTOMATIC AUTOMATIC AUDIO OUTPUT

RADIO RECEIVER CIRCUITS

BS-725G BS-725G BS-614G BECAUSE OF THE SPECIAL
NATURE OF MANY OF THE
TI CRI T2 T3 COMPONENTS USED IN THIS EARPHONE
CIRCUIT, HOME CONSTRUC. JACK
TION IS NOT RECOMMENDED.
r--- ‘_f c p
t2 14
± ca2
54.5.1M • AUDIO
DRIVER
3T F o
\
L3
CONVERTER

TRI

R2
6V

11
111: —
13
RII

RI,R8, 10,000 OHM CI 02 mfd

R2, 15.000 OHM C2,C3,C5,C6,C7,C8, — Olmfd. PERFORMANCE
133, 1500 OHM C4,C10, 6mfd -6V
R4 270 OHM C9,.ODpfd. NOMINAL SENSITIVITY: 200 MICRO VOLTS/METER
R5, 47,000 OHM CII.C12,C13, 50mfd -12V (MEASURED WITH 50 MILLIVATTS REFERENCE POWER)
R6, 220 OHM CI4, .2mfd. MAXIMUM POWER OUTPUT: 200 MW
R7, R9, 2200 OHM CRI ,CR2, IN64G OR EOU1V SELECTIVITY AT -6 db 8.0 Kc /S
RIO, 1000 OHM TRI, GE 2NI087 SELECTIVITY AT-60 db : 60.0 Kc/S
RII,R14, 4700 OHM TR2, G 2N293 ZERO SIGNAL BATTERY DRAIN. 8 MILLIAMPS

RI2, VOLUME CONTROL TR3, eE.2N169 OR 2NI121

mow OHM I/2W AUDIO TAPER TR4, G. E.2 N324
RI3, 68,000 OHM IRS ,TR6, G. E. 2111415
RIS, 470 OHM *T4 =3600 0/200011 CT
R16, 100 OHM *T5 .360D CT/VC
R17,R18 8.2 OHM
RIS, 330FIM * FOR FURTHUR INFORMATION SEE PAGE 299

SIX TRANSISTOR — 6 VOLT BROADCAST RECEIVER

Figure 12.16
 RADIO INDUSTRIES PuSH PULL
*8223 OR BECAUSE OF THE SPECIAL AuDIO OUTPUT
AUTOMATIC AUTOMATIC AUTOMATIC NATURE OF MANY OF THE *T2
CRI
EXO 5460 EXO 5460 1X0-3015 OR COMPONENTS USED IN THIS
CIRCUIT, HOME CONSTRUC
BS614G
T1ONIS HOT RECOMMENDED
r
I CR2
t 14. * TI

LI Ac ,
AUDIO
R 2 DRIVER

L'_ _
-
-"M
' 12V

+T c
R9 SW

RI, RII, 6800 OHM CI, .02pf d 1* TI, 2000/2600 CT

RADIO RECEIVER CIRCUITS

R2, 33,000 OHM C2, C3, .0Ipfd * 72, 2000 CT/VC
63, 1500 OHM LI, 435pbt IO%
R4, RIO,RI5,— 470 OHM C5, 61d, I2V L2, 250ph±10%
R5, ece,000 OHM C9, .05p1d Ad I—190.6}
R6, 330 OHM CIO, 6pfd, 6V LiC2,— 89.3 R/C MODEL 242
R7, RI3,— 4700 OHM CII, .003pld CRI,CR2,— IN64 OR IN295 OR EQUIV.
1313, 2200 OHM C12,C13,C14,-50pfd, I2V
R9, 2,700 OHM CI5, 2pfd PERFORMANCE
RI2, VOLUME CONTROL TRI, GE 2141087
NOMINAL SENSITIVITY .150 MICROVOLTS/METER
10,000 OHM I/2W AUDIO TAPER CONVERTER
(MEASURED WITH 50 MILLIWATTS REFERENCE
RI4, 15,000 OHM TR2, — G.E 2N293 1ST IF
POWER OUTPUT)
RIG, 220 OHM TR3, GE 2N169 OR 2NI121 2,01.F. MAXIMUM POWER OUTPUT :IWATT
617, 2700 OHM TR4, GE 2N324 DRIVER SELECTIVITY Al -6db 8.0 KC/S
RI8, RI9,— 10 OHM TR5,TR6,—G.E.2N1415 AUDIO SELECTIVITY AT -60db .38.0 KC/S
R20, 33 OHM WITH CLIP-ON HEAT SINK ZERO SIGNAL BATTERY DRAIN •10 M1LLIAMPS
IBIRCHER 3AL635-2R OR EOU1V.)
*FOR FURTHER COMPONENT INFORMATION SEE PAGE 299

SIX TRANSISTOR - 12 VOLT 1 WATT RECEIVER

12
Figure 12.17
 100S/

12
RADIO RECEIVER CIRCUITS
—+ 100µfd 100p,fd
330K.12 56KS1 120Kfl
33012 22011
D2

-= 3.0

"I
• pf *
240K11

Ol 120011 02 180011
o
2r _=3.0

•4
1
loO
180011
TURNS
II
- II— 5

.01 .05
6pfd
150012 330f/

15K12

*USE 1.0 pf WITH 2N2926 AND 2N339I SERIES TRANSISTOR, 0.5 pf WITH 2N27I5 SERIES

GENERAL ELECTRIC CO. RADIO INDUSTRIES, INC. PERFORMANCE

01, 03 2N2926 (RED) OR 2N27I5 OR 2N3394 TI 13964-RI NOMINAL SENSITIVITY 75 p.v/m
02, 04 2N2926 (ORANGE) OR 2N27I6 OR 2N3393 T2, T3 13964 RATED OUTPUT POWER 280 MW
05, 06 2N32I
LI 16413 BATTERY DRAIN 10.5 MA
DI IN4009 (SILICON)
02 1N60 (GERMANIUM) L2 16411
OTHER COMPONENTS
MODEL 42-2A T4 7K13K C. T.

SIX TRANSISTOR — 6 VOLT RECEIVER

Figure 12.18
 RADIO RECEIVER CIRCUITS
GENERAL ELECTRIC CO. RADIO INDUSTRIES, INC. PERFORMANCE

QI ,Q3 2N2926 (RED) OR 2N27I5 OR 2N3394 TI -13964-R 1

NOMINAL SENSITIVITY 20µv/m
02,04 2N2926 (ORANGE) OR 2N27I6 OR 2N3393 T2,T3-13964 RATED OUTPUT POWER 500 MW
Q5,Q6 2N27I4 (WITH HEAT SINK) LI 16413
BATTERY DRAIN 10MA
DI INGO (GERMANIUM ) L2 16411
D2 ,D3 IN4009 (SILICON) AC MODEL 42-2A OTHER COMPONENTS
T4-5K/2K CT
T5-2501.
2 CT/VC
RUSE 1.0 pf WITH 2N2926 AND 2N339I SERIES TRANSISTORS, 0.5pf WITH 2N27I5 SERIES.

SIX TRANSISTOR - 9 VOLT RECEIVER

12
Figure 12.19
 + 1501

zi,
100

Sin-01HD llgAI3D3/1 OICIVII

220
+ \2.
- 9V

05

01

4700

GENERAL ELECTRIC CO. RADIO INDUSTRIES, INC. PERFORMANCE

01 2N2715 TI 16412
NOMINAL SENSITIVITY 30µ v/m
02, 03 2N27I6 T2 16414
RATED OUTPUT POWER 500 MW
04 2N2924 OR 2N3392 T3 13964
BATTERY DRAIN 12.5 MA
05, 06 2N27 I
4 (WITH HEAT SINK) LI 16413
DI ,D2 IN4009 L2 16411 OTHER COMPONENTS

RADIO CONDENSER CORP. T4 5K/2K CT

TUNING CONDENSER T5 250 CT/VC

MODEL 42- 3A (CN 909991)

SIX TRANSISTOR - 9 VOLT RECEIVER WITH TUNED RF STAGE

Figure 12.20
 03 BI

IlaA133311 OICIVII
GENERAL ELECTRIC CO RADIO INDUSTRIES, INC. PERFORMANCE

01 2N2926 (RED) OR 2N27I5 OR 2N3394 TI 16414 NOMINAL SENSITIVITY 40p.v/m

02,03 2N2926 (ORANGE) OR 2N27I6 OR 2N3393 12 13964 RATED OUTPUT POWER 750 MW
04 2N2I96 OR 2N2I07 (ATTACH TO HEAT SINK) LI 16413
TOTAL POWER DRAIN 0
1 W
DI IN4009 (SILICON) L2 16411
D2 IN60 (GERMANIUM) C MODEL 42-2A OTHER COMPONENTS

zi. SIIIIDIIID
03 INI692
T3 35K/10011
* USE 1.0pf WITH 2N2926 AND 2N339I SERIES TR ANSISTORS, 0.5 pf WITH 14 250/VC
2N27I5 SERIES.
BI 110V, 25W LIGHT BULB

FOUR TRANSISTOR LINE SET

Figure 12.21
 II7V AC

zi.
110ac

SIla:MID IlaAIUDUll ()KIVU

03 T6
7.5V 1500 I9.8V

5820K

2700
QI pf

.01
180

06
_771
05 .05 SPK
L2
270
1500 10 I
25
_t I5K
w.

GENERAL ELECTRIC CO. RADIO INDUSTRIES, INC.

PERFORMANCE
01, Q3 2N2926 (RED) OR 2N27I5 OR 2N3394 TI 13964—RI
NOMINAL SENSITIVITY 30/..v/m
02, 04 2N2926 (ORANGE) OR 2N27I6 OR 2N3393 T2, T3 13964
05, 06 2N2714 (WITH HEAT SINK) OR 4JX I1C1536 RATED OUTPUT POWER 940 MW
LI 16413
DI IN4009 (SILICON) TOTAL POWER DRAIN 4W
L2 16411
D2 IN60 (GERMANIUM)
03 IN1692 AC MODEL42-2A OTHER COMPONENTS
T4 4K/2.5K CT
*USE 1.0pf WITH 2N2926 AND 2N339I SERIES
15 450 CT/VC
TRANSISTOR, 0.5 pf WITH 2N27I5 SERIES
TE I2.6V FILAMENT TRANSFORMER

SIX TRANSISTOR LINE SET

Figure 12.22
 RADIO RECEIVER CIRCUITS 12
Heatsinks for the 2N2714 transistor may be constructed by epoxy glueing, or
clamping the "flat side" of the transistor to a2" x2" piece of copper or aluminum. Both
transistors may be mounted on the same heatsink, as the case is electrically insulated
from the transistor.
The 2N2196 and 2N2107 may be bolted or clamped to a2" x2" copper or alumi-
num heatsink. Observe proper isolation of the heatsink, as the collector of the tran-
sistor is connected to the case. See Chapter 11 for further details.

ADDITIONAL COMPONENT INFORMATION

ANTENNA, IF TRANSFORMERS, OSCILLATOR COIL,

TUNING CONDENSER
Original equipment manufacture (OEM) should contact Radio Indus-
tries Inc., 666 Garland Place, Des Plaines, Illinois for further information.

NOTES

299
 SILICON UNIJUNCTION TRANSISTORS
Rau n Ir (Max) 11:o (Max) Volt,
Interbose Intrinsic Peak Point Emitter (Min)
Resistance Standoff Emitter Reverse Base One
Van = 3V Ratio Current Current Peak Pulse Comments
Type Ig = 0 Viin = 10V Vii = 25V 'Li = 25 °C Voltage
Type
TO-18 TO-5 Kilohms - Po /to volts
21N2417 2N489( 1) 4.7-6.8 .51-.62 12 2.0 -
2N2417A 2N489A 12 2.0 3
2N241711 2N48913 '1" 6 0.2 3
2N2418 2N490( 0 6.2 19.1 12 2.0 -
2N2418A 2N490A 12 2.0 3 A versions are guaranteed in recom-

2N241813 2N490B 1' 6 0.2 3 mended circuit to trigger G.E. SCR's

2N2419 2N491( 1> 4.7 6.8 .56-.68 12 2.0 - over range TA = - 55 °C to 125 °C.

2N2419A 2N491A 12 2.0 :I Industr i

al

2N241911 2N491E 1 / 6 0.2 3 and

Military
2N2420 2N492(I) 6.2 9.1 .56 .68 12 2.0 - Types
2N2420A 2N492A 12 2.0
3
2N242013 2N49211 / "i" 6 0.2
2N2421 2N493(1) 4.7 6.8 .62 .75 12 2.0 -
2N2421A 2N493A 12 2.0 3 II versions in addition to SCR trig-
2N242113 2N49313 / 6 0.2 3 goring, guarantees lower Inn and Ir
2N2422 24N94(l) 6.2 9.1 12 2.0 - for long timing periods with a smaller
2N2422A 2N494A 12 2.0 3 capacitor.
2N2422I3 2N49411 6 0.2 11
3
- 2N494C / 2 0.02
- 2N1671 4.7 9.1 .47-.62 25 2.0 -
- 2N1671A 25 2.0 3 Industrial
Types
- 2N167113 `I" l' 6.0 0.2 3
- 2N2160 4.0-12.0 .47-.80 25 2.0 3
Low Cost UJT (SCR Trigger)
2N2646 - 4.7-9.1 .56-.75 5 2.0 3
2N2647 - 4.7-9.1 .68-.82 2 0.2 6 For long timing periods & trigger high current SCR's
VP
2\2810 - 4.7-9.1(2) 1.31.5(0 10(2) 1 - Low Voltage Applications
NOTES ( Available as USAF TYPES (MIL-T-19500/75) (2) Vaa = 1.5 volts
UNIJUNCTION TRANSISTOR
CIRCUITS

The unijunction transistor (UJT) is athree-terminal semiconductor device which

has electrical characteristics quite different from those of aconventional two-junction
transistor. Its most important features are: (1) astable triggering voltage (V, )which
is a fixed fraction of the applied interbase voltage, (2) a very low value of firing
current (I,), (3) a negative resistance characteristic which is uniform from unit to
unit and stable with temperature and life, (4) a high pulse current capability, and
(5) alow cost. These characteristics make the unijunction transistor advantageous in
oscillators, timing circuits, voltage and current sensing circuits, SCR trigger circuits
and bistable circuits.
The unijunction transistor is available in 47 distinct types to meet the needs of a
wide range of applications. The chart on the opposite page shows 45 of these types as
to package size, main parameter differences, and some general comments as to the
circuit application for which they are characterized. Types 5E35 and 5E36 are not
shown since they are characterized in a specific multivibrator circuit and are dis-
cussed later.

THEORY OF OPERATION
The symbol of the unijunction, Figure 13.1, and a simplified equivalent circuit,
Figure 13.2, show aresemblance. RBI plus RBI represents the interbase resistance, RBB,

1„

1 82

V55
v,

SYMBOL FOR UNIJUNCTION TRAN- SIMPLIFIED EQUIVALENT CIRCUIT

SISTOR WITH IDENTIFICATION OF OF THE UNIJUNCTION TRANSISTOR
PRINCIPLE VOLTAGES AND CUR- Figure 13.2
RENTS
Figure 13.1

and is between 5K and 10K ohms. This is the resistance of an n-type silicon bar with
ohmic contacts, called base-one (B1) and base-two (B2), at opposite ends. A single
rectifying contact, called the emitter (E), is made between base-one and base-two.
The diode in the simplified equivalent circuit of Figure 13.2 represents the unijunc-
tion's emitter diode. In normal circuit operation base-one is grounded and a positive

301
 13 UNIJUNCTION TRANSISTOR CIRCUITS

bias voltage, VEE, is applied at base-two. With no emitter current flowing, the silicon
bar acts like asimple voltage divider (Figure 13.2) and acertain fraction, n, of VEE
will appear at the emitter. If the emitter voltage, VE, is less than nVEE, the emitter
will be reverse biased and only asmall emitter leakage current will flow. If VE becomes
greater than nVita, the emitter will be forward biased and emitter current will flow.
This emitter current consists primarily of holes injected into the silicon bar. These
holes move down the bar from the emitter to base-one and result in an equal increase
in the number of electrons in the emitter base-one region. The net result is a
decrease in the resistance between emitter and base-one so that as the emitter current
increases the emitter voltage decreases, and a negative resistance characteristic is
obtained (Figure 13.3 ).
EMITTER
VOLTAGE
VE
NEGATIVE
--CUTOFF RESISTANCE t.4-SATURATION---
REGION I REGION REGION
Vp PEAK POINT

EMITTER TO BASE-
VBB.I0V ONE DIODE
CHARACTERISTIC

ALLEY POINT \,
VE (SAT )- --

1EMITTER
1CURRENT
Ip Iv 50MAIE

IE 0

STATIC EMITTER CHARACTERISTIC CURVE

SHOWING IMPORTANT PARAMETERS

Figure 13.3

On the emitter characteristic shown in Figure 13.3 curve there are two points of
interest, the peak point and the valley point. The region to the left of the peak point
is called the cut-off region; here the emitter is reverse biased and only asmall leakage
current flows. The region between the peak point and the valley point is the negative
resistance region. The region to the right of the valley point is the saturation region;
here the dynamic resistance is positive.
VBB

.50MA

' B2

BASE-TWO CURRENT STATIC INTERBASE

CHARACTERISTICS CURVES
Figure 13.4

302
 UNIJUNCTION TRANSISTOR CIRCUITS 13
The electric field that exists between the base-two and base-one contacts is such
that the majority of holes injected at the emitter will be swept toward the base-one
contact. RB., is also modulated but to alesser degree than RB, due to the direction of
the electric field in the pellet. This characteristic is specified by measuring the current
in base-two for aspecified value of emitter current and interbase voltage. This param-
eter is defined by the symbol Iru mom. The resultant static characteristic curve is
shown in Figure 13.4. It is important to note that in many applications alarge value
of peak power is developed between base-two and emitter and it is wise to use a
current limiting resistor in series with base-two.
The resistance RBI varies with the emitter current as indicated in Figure 13.5.

IE RB I

(MA) (OHMS)

O 4600
2000
2 900
5 240
10 150
20 90
50 40

VARIATION OF R,, WITH I , IN REPRESENTATIVE CIRCUIT

(TYPICAL 2N492)
Figure 13.5

PARAMETERS—DEFINITION AND MEASUREMENT

1. Interbase Resistance (RBB). The interbase resistance is the resistance measured
between base-one and base-two with the emitter open circuited. It may be measured
with any conventional ohmmeter or resistance bridge if the applied voltage is five
volts or less. The interbase resistance increases with temperature at about 0.8% /`C.
This temperature variation of R86 may be utilized for either temperature compensation
or in the design of temperature sensitive circuits.
2. Intrinsic Stand-off Ratio (n). This parameter is defined in terms of the peak
point voltage, V,,, by means of the equation: V„ = nVB B ± VD. A circuit which may
be used to measure nis shown in Figure 13.6. In this circuit RI, Cl and the unijunc-
tion transistor form arelaxation oscillator and the remainder of the circuit serves as a
peak voltage detector with the diode automatically. subtracting the voltage VD. To use
the circuit, the "cal" button is pushed and R3 adjusted to make the meter read full
scale. The "cal" button is then released and the value of n is read directly from the
meter (1.0 full scale). If the voltage V, is changed, the meter must be recalibrated.
Current limiting should be provided in the• power supply to protect the unijunction
transistor.
3. Peak Point Current (Ir). The peak point current corresponds to the emitter
current at the peak point. It represents the minimum current which is required to trigger
the unijunction transistor or required for oscillation in the relaxation oscillator circuit.
II. is inversely proportional to the interbase voltage. I,. may be measured in the circuit
of Figure 13.7. In this circuit the potentiometer setting is slowly increased until the
unijunction transistor fires as evidenced by asudden jump and oscillation of the meter
needle. The current reading just prior to when the jump takes place is the peak point
current.
4. Peak Point Emitter Voltage (Va). This voltage depends on the interbase voltage
as indicated in 2. V,. decreases with increasing temperature because of the change in
VI, and may be stabilized by asmall resistor in series with base-two.

303
13 UNIJUNCTION TRANSISTOR CIRCUITS

5. Emitter Saturation Voltage (VE (sat). This parameter indicates the forward
drop of the unijunction transistor from emitter to base-one in the saturation region.
It is measured at an emitter current of 50 ma and an interbase voltage of 10 volts.
6. Interbase Modulated Current (I B2 (mod). This parameter indicates the effective
current gain between emitter and base-two. It is measured as the base-two current
under the same condition used to measure VE (sat).
7. Emitter Reverse Current (IEE). The emitter reverse current is measured with
an applied voltage between base-two and emitter with base-one open circuit. This
.current varies with temperature in the same way as the ¡co of aconventional transistor.
8. Valley Voltage (Vr ). The valley voltage is the emitter voltage at the valley
point. The valley voltage increases as the interbase voltage increases, it decreases with
resistance in series with base-two and increases with resistance in series with base-one.
9. Valley Current (Iv). The valley current is the emitter current at the valley
point. The valley current increases as the interbase voltage increases and decreases
with resistance in series with base-one or base-two.
+10V

TEST CIRCUIT FOR INTRINSIC TEST CIRCUIT FOR PEAK POINT

STANDOFF RATIO (,7) EMITTER CURRENT (I,)
Figure 13.6 Figure 13.7

CONSTRUCTION
The unijunction types shown in the chart at the beginning of this chapter are from
two basic unijunction structures which we shall identify as bar and cube structures.
The 2N2646, 2N2647, and 2N2840 types are the cube structure (5E production line),
and all the remaining types are bar structure.
A cross-sectional view of the bar unijunction transistor structure is shown in
Figure 13.8(A). A ceramic disc having the same thermal expansion coefficient as
silicon is used as a mounting platform. The pellet is a single crystal of n-type silicon
with dimensions of 8 x 10 x60 mils. The pn emitter junction is formed by alloying a
3mil aluminum wire to the top of the pellet nearest the base-two ohmic contact. The
resultant device is then surface passivated and hermetically sealed. This design per-
mits TO-5 and TO-18 package sizes with all leads electrically isolated from the case.
A cross-sectional diagram of the cube unijunction transistor structure is shown in
Figure 13.8(B). The pellet consists of single crystal of n-type silicon having dimen-
sions of 13 x 17 x 17 mils. It is mounted directly to the top of a gold-plated kovar
header. Thus base-two is common to the header and case. The base-one ohmic con-
tact is formed by alloying awire, 2 mils in diameter, into the top surface of the pellet.
This alloy ohmic contact has a shape which is a section of a sphere giving rise to a
non-linear voltage gradient between base-one and base-two. The pn emitter junction
 UNIJUNCTION TRANSISTOR CIRCUITS 13
EMITTER (E)
N-TYPE SILICON BAR
PN EMITTER JUNCTION

BASE-ONE (BI) BASE -TWO (82)

OHMIC CONTACT OHMIC CONTACT

(A) BAR STRUCTURE

BASE- ONE (BI)

OHMIC CONTACT RN EMITTER JUNCTION

EMITTER (E)
N-TYPE SI LICON CUBE

BASE-TWO (82)
OHMIC CONTACT

(B) CUBE STRUCTURE

CROSS SECTIONAL VIEWS OF UNIJUNCTION STRUCTURES

Figure 13.8

is formed by alloying an aluminum wire, 3mils in diameter, into the side of the pellet.
The resultant unit is surface passivated and hermetically sealed in aTO-18 size pack-
age. Because of the geometry of the small area ohmic contact used for base-one, the
voltage gradient in the vicinity of base-one is higher than elsewhere in the silicon,
so it is possible to achieve ahigh standoff ratio with amuch smaller spacing between
emitter and base-one. This then permits the cube structure to have lower peak point
current, turn-on time, and lower emitter saturation voltage with a large base-one
peak pulse for triggering silicon controlled rectifiers (SCR). This design also makes
possible unijunction operation at low voltage. Cube structure unijunctions, in general,
have alower valley point and alarger value of negative resistance (see Figure 13.9).
This results in excellent switching action for this device with its low saturation voltage
and high negative resistance. Also, a larger voltage swing may be derived from the
cube structure in such applications as oscillators and pulse generators than for the
bar structure with a comparable intrinsic standoff ratio. At the same time one must
consider the lower valley current of the 2N2646 (cube) with regard to lock-up of a
circuit in the saturation region by allowing the emitter to supply asteady state current
in excess of the valley current.
The electric field gradient between base-one and base-two of the bar structure is
essentially linear in contrast to that of the cube. Even with this difference, however,

305
13 UNIJUNCTION TRANSISTOR CIRCUITS

18

16

14

STATIC EMITTER CHARACTERISTICS

TA • +25 •C

V„ •30V

VA , 20V

V. .10 V

VA , 5V

I82 .0

oo 2 4 6 e io 12 14 16 18 20 22
EMITTER CURRENT -I,- MILLIAMPERES

(A) BAR STRUCTURE

20

18

16

VA ,• 30V STATIC EM TIER CHARACTERISTICS

TA . -4-25* C

14

„ =20 V
là. 6
1-
„ .I
0V
i
I
w

VAA •5V

2 4 6 8 10 12 14 16 18 20 22
EMITTER CURRENT -I,- MILL '
AMPERES

(B) CUBE STRUCTURE

TYPICAL STATIC EMITTER CHARACTERISTIC CURVES

AT 25°C FOR BAR AND CUBE STRUCTURES
Figure 13.9

306
 UNIJUNCTION TRANSISTOR CIRCUITS 13
the interbase resistance characteristics (1100) of the two structures, for allowable
values of voltage and temperature, are essentially identical. The positive temperature
coefficient of RBB improves the thermal stability of the unijunction at junction tem-
peratures below 150°C. Of the two structures, the bar structure unijunction types
exhibit more stable characteristics at extreme junction temperatures (beyond —40°C
and +100°C).

IMPORTANT UNIJUNCTION CHARACTERISTICS

PEAK POINT
The most important characteristic of the unijunction is the peak point character-
istic since it determines the triggering voltage in bistable circuits, the threshold level
in sensing circuits, and the frequency of relaxation oscillators. Peak point voltage (Ve)
is proportional to the interbase bias voltage and is
Vi. =nV00+ Vn (13a)
where VDis the voltage drop across the emitter diode with aforward current equal to
the peak point current. Generally Vr is not measured directly but is obtained by
measurement of nin test circuits such as Figure 13.6. At 25°C the diode voltage for
the cube structure is typically 0.4 volt compared with 0.67 volt for the bar structure.
The peak point characteristic for a typical UJT (bar structure) is shown on an
expanded scale in Figure 13.10. The solid line in this figure indicates the V-I char-
acteristic calculated for asilicon diode in series with afixed value of negative resist-
ance. The value of the emitter current at the point where the peak point characteristic
has azero slope is defined as the peak point current (Ir).

Ci)
o
"

---
000 MEASURED VALUES
... CALCULATED VALUES ....-e-
.....f,
,...

Vc Vp0A+B LOG It IE RNp e

VE 0-04--AAA—* +nViN3 e- ,
a 0 ..-.'
IE
`1 0I
a.
3
5-0.2
V.I5V
T .25°C
A
s-03
........\\

0 -04

-0.5

001 01 10 100
EMITTER CURRENT- IE -MICROAMPERES

UNIJUNCTION TRANSISTOR STATIC EMITTER

CHARACTERISTICS AT PEAK POINT
Figure 13.10

PEAK POINT TEMPERATURE STABILIZATION

The principal variation of Vr with temperature is due to the variation of VDfor
the bar structure, since the nvariation is negligible. This effect may be compensated

307
 13 UNIJUNCTION TRANSISTOR CIRCUITS

+VI

RBI 4- R52 =RBB

RBI
yea RBI +RB2

TYPICAL UJT UJT EQUIVALENT CIRCUIT

BIAS CIRCUIT FOR PEAK POINT
Figure 13.11

by means of a smaller resistor (R2) as shown in Figure 13.11. As the ambient tem-
perature increases the interbase resistance (RDD) will increase and VDD will also
increase due to the voltage divider action of R2, RDD and RI.
If R2 is chosen correctly the increase in interbase voltage will compensate for the
decrease in VD. The approximate value of R2 is
R2 0'70 RBB (13b )
nV,
If R2 satisfies this equation the peak point voltage will be given by
VD = (13c )
In afollowing discussion on valley point it will be shown in Figure 13.16 that it
is generally desirable to keep the value of RI in Figure 13.11 less than 100 ohms.
This is the condition under which equation (13b )is valid. Figure 13.12 shows atypical
variation of relaxation oscillator frequency with temperature where the UJT was the
only component submitted to the varying ambient temperature. Frequency stability
could be improved if the other components had compensating temperature coefficients.
The value of the compensating resistor in series with base-two was selected using
equation (13b ).

Iv
+20V
IHL
PERCENT CHANGE IN FREOUENCY

e 20K 47011
E B,
6
Bi
0.1 211
4

___......--""''......'........7
0

-2

_.1
-60 -40 -20 20 40 60 80 00 120 140
TEMPERATURE "*C

UNIJUNCTION ONLY SUBMITTED TO TEMPERATURE

Figure 13.12

308
 UNIJUNCTION TRANSISTOR CIRCUITS 13
When circuit operation over the extreme temperature range (—60 to +140°C)
is not required better compensation can be achieved. The reason being that the tem-
perature coefficient of the UJT is not perfectly linear, and over a more limited range
the actual slope of the temperature coefficient can be compensated more accurately
with R2. For temperatures below 100°C more accurate compensation can be obtained
by using asmaller value for R2; this is given by equation (13d).

2N489 series
1, R2 _ 0.4 RIM (13d)
2N1671 series
2N2417 series nvi

-60 -40 -
?00 20 40 60 80 100 120 140

TEMPERATURE °C

TYPICAL FREQUENCY VS TEMPERATURE CURVE

Figure 13.13

The solid curve in Figure 13.13 is the same as Figure 13.12. If the value of 112
is decreased it causes the curve to rotate counter-clockwise with 25°C as the pivot
point (see dashed curve). Thus, if the temperature range of interest is from —45°C
to 100°C, then the value of R2 can be decreased to compromise between the 1 2 %
/
deviation at 100°C and the 31/ 2 % at —45°C, to give approximately 2% at each

temperature extreme as shown by the dashed curve of Figure 13.13.

Each individual unijunction has its own value of R2 that gives best compensation.
Therefore using one fixed value of R2 for a group of unijunctions, one would expect
the majority to follow a curve similar to that of Figure 13.13, with a scattering at
the more extreme temperature on each side. The best average value of resistance can
be determined for 112 by taking arandom sample of unijunctions, and then determin-
ing the average fixed resistance which compensates best over the desired temperature
range. With this general compensation method, one should be able to attain a fre-
quency stability of better than 2% for most all of the units over a temperature range
of 0°C to 100°C. Typically the stability should be better than 1 / %.
2

If the compensating resistor (R2) is adjusted or selected for each unit (by placing
the circuit in an oven and adjusting 112 of each circuit) the frequency change from
0°C to 100°C will generally be less than Y4% (all units under 1% ). It is easier and
often adequate to place a thermal probe on the UJT and adjust R2 for minimum
frequency change from room ambient conditions. This method gives very good results
when the values of the resistors and capacitors are quite stable with temperature.
If a stability of better than 0.05% is required over a wide ambient temperature
range, then the complete relaxation circuit can be operated in a small components
(crystal) oven.

309
13 UNIJUNCTION TRANSISTOR CIRCUITS

IG
20V •
R2
10
20K 270
FIT
8 B2 2N167IA
B1 4_
6 0.01
CT 27
4

0 e-----------"--..-

-4

-a
-60 -40 -20 20 40 60 100 120 140

TEMPERATURE °C

TYPICAL FREQUENCY VS TEMPERATURE

(
Un- ONLY SUBMITTED TO TEMPERATURE )
Figure 13.14

Stability at temperatures below 25°C can be improved by returning RTto base-two

of the UJT as shown in Figure 13.14. R2 may be tapped at an optimum point for best
temperature compensation for the particular supply voltage and temperature range.
The circuit mode used in Figure 13.14 offers another advantage in that the tem-
perature characteristic is more linear making compensation easier. In fact, the tempera-
ture characteristic of a mylar capacitor compliments the curve in Figure 13.14, and
is about the right compensation when used as CTfor a temperature range of —25°C
to +85°C.
In some applications a diode has been used in series with either base-two or the
emitter of the unijunction to improve the temperature stabilization or to reduce the
dependance on power supply variation.
The foregoing discussion on bar construction types applies in general to the cube
structure also, except that the 2N2646 and 2N2647 (5E production line) types have a
greater variation of II with temperature. Therefore, this has to be considered along with
the variation of VDand requires alarger value for R2 to temperature compensate these
types. R2 for the most usual ambient temperature requirements is given by

2N2646 } R2 = 10 '000 (13e)

2N2647 nV,

Figure 13.15 shows a temperature characteristic that is typical for the 2N2647 with
avalue for R2 as given in equation (13e). It is expected that afew units may depart
considerably from this curve. Such units would require a lower value resistor for R2
if they fall below the curve at 100°C and a larger value resistor for R2 if they fall
above the curve.
In the preceding discussion of UJT oscillator frequency stability vs. temperature,
although the primary consideration has been to stabilize the peak point, the valley
point also is involved in the total compensation.

VALLEY POINT
Both the valley point and the shape of the negative resistance characteristics are
circuit dependent and may be varied over a moderate range by choice of suitable

310
 UNIJUNCTION TRANSISTOR CIRCUITS 13
5 1 '+26V

r 4 39K 6800
E,
z
LU 3 2N2647 (5E LINE)
D
Cs
w
o 2 0.1 OUT
LL 270
z 1
w
o
z 0
a
x
o i
I-
z
w -2
E)
o
w
a. 3

-40 -20 0 20 40 60 80 100

TEMPERATURE- °C

2N2647 TEMPERATURE CHARACTERISTIC

Figure 13.15

circuitry. For example, valley voltage may be increased by increasing the interbase
voltage, by increasing the resistor in series with base-one, or by decreasing the resistor
in series with base-two. Similarly, valley current may be increased by increasing the
interbase voltage, by decreasing the resistance in series with base-one, or by decreas-
ing the resistance in series with base-two. Th emitter characteristics for different
values of base-one series resistance are shown in Figure 13.16. The emitter character-
istics for different values of base-two series resistance are shown in Figure 13.17. In

14
R1.3.3K

RI. LOA

RI. 4700

_ RI' 2200

RI.10011

RI. 0

0 2 4 6 8 10 12 14
EMITTER CURRENT — 1E — MILLIAMPERES

EMITTER CHARACTERISTIC CURVES FOR TYPE 2N492

UNIJUNCTION TRANSISTOR WITH BASE-ONE SERIES RESISTANCE
Figure 13.16

311
13 UNIJUNCTION TRANSISTOR CIRCUITS

14

12

R2 •0 (VIA • 20 V)

R2 5K

R2 •00 142 • 2.7 MA)

2 4 6 e lO ?
EMITTER CURRENT -L E - MILLIAMPERES

EMITTER CHARACTERISTIC CURVES FOR TYPE 2N492

UNIJUNCTION TRANSISTOR WITH BASE -
TWO SERIES RESISTANCE
Figure 13.17

taking the data for Figures 13.16 and 13.17, the bias voltage, VI, was adjusted to
give the same peak point voltage. In regard to Figure 13.17, the curves for all possible
values of base-two series resistor lie between the curve for constant interbase voltage
and the curve for constant interbase current. The range of valley voltage and valley
currents are determined by the valley points on these two curves.

POWER DISSIPATION RATINGS

The power rating of the UJT is given in terms of the total dissipation which is the
sum of the emitter dissipation and the interbase dissipation.
It is important or provide circuit stabilization in the interbase circuit when the
UJT is used in pulse type applications since the instantaneous temperature of the
silicon could rise to ahigh enough value to permit runaway if the interbase current
is not limited by R2.
Measurement of the thermal resistance of the UJT in aparticular socket or heat
sink is best accomplished by making use of RBB as the temperature sensitive parameter.

RELAXATION OSCILLATOR
CIRCUIT OPERATION
The relaxation oscillator circuit shown in Figure 13.18 is abasic circuit for many
applications. It is useful as a timing circuit, apulse generator, a trigger circuit, or a
sawtooth wave generator.
At the beginning of an operating cycle the emitter is reverse-biased and hence
non-conducting. As the capacitor CTis charged through the resistor RT the emitter
voltage rises exponentially towards the supply voltage Vi. When the emitter voltage

312
 UNIJUNCTION TRANSISTOR CIRCUITS 13
V
E

+ V,

VE(MIN)-

BASIC RELAXATION OSCILLATOR WITH TYPICAL

WAVEFORMS
Figure 13.18

reaches the peak point voltage Vp the emitter becomes forward biased and the dynamic
resistance between the emitter and base-one drops to a low value. Capacitor CT
then discharges through the emitter. When the emitter voltage reaches VBMIN), as
shown in Figure 13.18, the emitter ceases to conduct and the cycle is repeated.
Vie (MIN) is the minimum emitter voltage and is relatively independent of bias volt-
age, temperature, and capacitance if RI is zero. VIE (MIN) is approximately equal to
0.5 VEEsau. For small values of RI and R2 the frequency of oscillation is
1
f
(13f)
RI C ln ( 1 —1 n

and may be obtained conveniently from the nomogram of Figure 13.19.

e.
RESISTANCE - - N ILONAIS

e e e

MAXIMUM FREQUENCY TYPES 2N491 ,2N492

NOM INAL FREQUENCY TYPES 2N 489 ,
2N 490

FREQUENCY -I
-CYCLES PER SECOND .0.58

MINIMUM FREQUENCY TYPES 2N491 ,2N492

NOMINAL FREQUENCY TYPES 2N 493 ,
2N 494

1 1 1 1 1 1 I I

CAPAC1TANCE - C - M1CROFARADS

NOMOGRAM FOR CALCULATING FREQUENCY OF RELAXATION OSCILLATION

Figure 13.19

313
13 UNIJUNCTION TRANSISTOR CIRCUITS

OSCILLATION REQUIREMENTS AND COMPONENT LIMITS

The UJT relaxation oscillator is noteworthy for its ability to operate over awide
range of circuit parameters and ambient temperature. There are, however, several
important conditions which must be satisfied if this circuit is to operate satisfactorily:
1. The load line formed by the resistor RTand the supply voltage Vi must intersect
the emitter characteristic curve to the right of the peak point. This condition
ensures that the resistor RTcan supply sufficient current to the emitter to trigger
the UJT. This condition may be written
VI- Vp
> I
P ( 13g)
RT
IPis generally specified at an interbase voltage of 25 volts and is inversely
proportional to VBB. Equation (13g) sets a maximum limit on RT so that RT
must be chosen to satisfy the inequality under the worst conditions for each
of the other parameters. The worst conditions would include, (a) the maximum
value of Vp, (b) the minimum value of Va, and (c) the maximum value of Ip
at the minimum temperature of operation.
The limit value of RT can be greatly increased by supplying an externally
generated negative pulse at base-two. This will be discussed later under both
time delay and sensing circuits.
2. The second condition which must be satisfied is that the load line formed by
RTand the supply voltage Vi must intersect the emitter characteristic to the
left of the valley point.
V, — Vv (where Vv is circuit dependent and should
< Iv (13h)
RT be measured in the actual circuit)
If this condition is not satisfied the load line will intersect the emitter charac-
teristic curve in the saturation region and the UJT may not turn off after it
triggers on the first cycle. Note that the valley current given in equation (13h)
refers to the valley current of the UJT in the circuit together with the base-one
and base-two series resistors. If these external resistors are large the value of
Iv will be reduced as indicated in Figure 13.16 and 13.17.
In general the limitations imposed by condition 1and 2are not severe. A maxi-
mum value of Ip might be 2microamperes and aminimum value of Iv might be
8milliamperes so that the allowable range of RTshould be 1000 to 1 (approxi-
mately 3K to 3Meg).
3. A final condition for the operation of the UJT relaxation oscillator concerns
the allowable range of capacitance CT. As the size of CTis decreased below
about 0.01 ¿if d (0.001 effd for 2N2646 and other 5E production line types)
the amplitude of the emitter voltage waveform will decrease as indicated in
Figure 13.20. This decreases the frequency stability of the circuit and also
reduces the allowable range of RT.
The emitter peak current should not exceed two amperes for values of CTless than
10 pfd and peak point voltages less than 30 volts. For higher values of CT or VP,
resistance should be used in series with the capacitor to protect the emitter circuit.
This additional series resistance should be at least one ohm per microfarad of CT.

TRANSIENT WAVEFORM CHARACTERISTICS

In a UJT relaxation oscillator circuit the most important transient characteristic
is the emitter voltage fall-time (tf), or turn-on time. This is shown on unijunction
specification sheets as Emitter Voltage Fall-time (4) Microseconde vs. Capacitance
(C1) Microtarads, Ci being the emitter capacitor and sometimes referred to as CT.
The fall-time is found to be independent of the supply voltage and is determined

314
 UNIJUNCTION TRANSISTOR CIRCUITS 13

10

EMITTER
8

6
PEAK

OP
8LC:E°/1°N— ITS
4 /

°- 0
0.0003 0001 0.01 O
VALUE OF CAPACITOR C, I
cl

VARIATION OF PEAK TO PEAK EMITTER VOLTAGE WITH

CAPACITANCE IN UNIJUNCTION RELAXATION OSCILLATOR
Figure 13.20

primarily by the value of the capacitor C., and the ambient temperature, TA. For values
of RI other than zero the fall-time will be increased in proportion to the time constant
RI CT.

PULSE GENERATION
Each time the UJT in the relaxation oscillator circuit conducts, a current pulse
flows in the emitter, base-one, and base-two circuits. The relaxation oscillator can be
used as an efficient pulse generator which may be used to generate either positive or
negative pulses at various impedance levels. Various configurations of the pulse gen-
erator are shown in Figure 13.21. The first three configurations (A, B, C) use the
discharge current of the capacitor to generate the pulse and hence have a low output
impedance. The configuration shown in 13.21 ( )uses the base-two current to gen-
erate the pulse and has a higher output impedance although this configuration is
capable of generating higher voltages. In configuration 13.21(C) it is important to
note that the capacitor discharge current flows through the external supply so that a
low impedance power supply is required.

RI

(A) (B) (C) (DI

CONFIGURATIONS OF THE RELAXATION OSCILLATOR

FOR USE AS PULSE GENERATORS
Figure 13.21

The emitter current pulse width, measured between the 10% points, is approxi-
mately equal to 2 tr. For small values of RI the peak emitter current is given ap-

315

1
13 UNIJUNCTION TRANSISTOR CIRCUITS

proximately by
[V„ — 1/2 VE(sat)]CT
I
E(PEAK) = (13i) •
tf

and the corresponding base-two current is given approximately by

I
FI2 (MOD) T
1112 (PEAK) — V AE (PF:AK) (13j)
7
where the units are ma, volts, Ind, and scc.
The output pulse from a conventional UJT relaxation oscillator has a moderately
fast rise-time and a very slow fall-time. In applications where a well shaped pulse is
required with controlled width and fast rise and fall times the use of an inductance as
shown in the circuit of Figure 13.22 can yield asignificant improvement over the con-
ventional resistance coupled circuit. The inductance is given approximately by 0.4t 2/C
where tis the desired pulse width and C is the value of the emitter capacitor.

+10V

200S1

VouT

2N697

till PULSE SHAPING CIRCUIT

Figure 13.22

For the circuit shown the pulse width for various transistors fell between 11 and
12 microseconds and the rise and fall times were typically 0.3 microseconds. With a
47 ohm resistor substituted for the inductance the rise-time was typically 0.3 micro-
seconds, but the fall-time was typically 3 microseconds.

FREQUENCY STABILITY
Frequency variation of the relaxation oscillator with temperature is discussed in
a previous section on Peak Point Temperature Stabilization. The base-two circuit
resistor, R2, which is normally selected to stabilize the oscillator frequency with
temperature also is adequate for stabilizing the frequency for supply voltage variations.
Frequency change is usually less than - ±1% with supply variations up to ±25%.

SYNCHRONIZATION
The UJT relaxation oscillator can be synchronized by means of either positive
pulses at the emitter or negative pulses at base-two. Amplitude of the synchronizing
pulses must be large enough to reduce the peak point voltage below the instantaneous
emitter voltage according to equation (13a ). The effect of pulse width on the required
trigger amplitude is shown in Figure 13.23. For pulse widths greater than 1 micro-
second the required trigger amplitude approaches the dc conditions, for pulse widths
of less than 1 microsecond the required pulse amplitude is inversely proportional to
the pulse width. The equivalent electric charge required for triggering is approxi-
mately 10 -"coulombs for the bar structure and 10 -w coulombs for the cube structure.

316
 UNIJUNCTION TRANSISTOR CIRCUITS 13
4

V65 .25 VOLTS

n =0.68

PULSE AMPLITUDE -VOLTS 3

-TRIGGER AT BASE-TWO
2

+ TRIGGER AT EMITTER

O
02 04 06 08 10 12 14 16 18 20
TRIGGER PULSE WIDTH - MICROSECONDS

MINIMUM TRIGGER AMPLITUDE AS A FUNCTION OF TRIGGER

PULSE WIDTH FOR TURN ON OF UNIJUNCTION TRANSISTOR
Figure 13.23

SAWTOOTH WAVE GENERATORS

GENERAL CONSIDERATIONS
The voltage waveform at the emitter of the UJT in the basic relaxation oscillator
is afair approximation to asawtooth waveform. The most practical method to couple
this signal to a load is by the use of a direct-coupled emitter follower as shown in
Figure 13.24. It will be noted that simple direct coupling is made possible by the fact
that the minimum emitter voltage at the emitter of the UJT, VE (MIN), is 1.0 volt or
more. If VE(MINI is less than the normal base to emitter drop of the junction transistor,
then the waveform across the load, RI., will be clipped at the bottom.

UNIJUNCTION SAWTOOTH EQUIVALENT CIRCUIT FOR

GENERATOR WITH NPN EMITTER CALCULATION OF TEMPERATURE
FOLLOWER OUTPUT STAGE AND LOADING EFFECTS
Figure 13.24 Figure 13.25

The first order effects of the emitter follower output stage on the voltage wave-
form are indicated in the equivalent circuit of Figure 13.25. The loading effect of the
emitter follower stage is approximated by an equivalent circuit (hrE -I- 1) RLacross
the capacitor Cr. It is seen from this equivalent circuit that loading will change the
frequency of oscillation since the capacitor charging circuit will be changed by the

317
13 UNIJUNCTION TRANSISTOR CIRCUITS

presence of the resistor (hEE ± 1) RL. To minimize the effects of loading on the
frequency, the value of RLand hEE should be as large as possible. If the values of
hEE or RLare too small, the circuit will not oscillate. To ensure oscillation hEE and RI,
must satisfy the condition,
(hEE -I- 1) RL
> (MAX) 13k
RT (hEE ± 1) RL ( )

TEMPERATURE EFFECTS
Two important temperature effects are involved in the use of the emitter-follower
output stage. The variation in 11E'; with temperature will change the loading and
effect the frequency of oscillation; to minimize this temperature effect, (hEE ± 1) RL
should be much greater than the resistor RT. The second temperature effect results
from the collector leakage current, )6, of the junction transistor as indicated in Figure
13.25. It will be noted that this current adds to the emitter leakage current, 1E0, of
the UJT. Both of these leakage currents tend to increase the frequency as tempera-
ture increases. The effect of the leakage currents on the frequency can be minimized
by using alarge capacitor CT. If the NPN transistor is silicon, the effects of the two
leakage currents can generally be neglected at temperatures below 100°C.
Some improvement in circuit operation can be achieved by the use of an PNP
emitter follower output stage. For this circuit configuration the effective load resist-
ance, (hEE ± 1)RL, is in parallel with RTso that the possibility of nonoscillation due
to low values of hEE or RLis eliminated. Another advantage is that the Ico of the
transistor subtracts from 1E0 of the UJT so that some degree of temperature com-
pensation is obtained. This is particularly true if a silicon transistor is used as the
PNP output transistor.

IMPROVING LINEARITY
For many applications the linearity obtained with the basic UJT relaxation oscil-
lator is inadequate. To achieve the best linearity with the basic circuit, it is necessary
to use aUJT having the minimum value of n(types 2N489, 2N490). The best linearity
which can be obtained with these types is about 10%.
A number of simple circuit techniques can be used to improve the linearity of the
sawtooth waveform. The direct approach of using ahigher supply voltage for charg-
ing the timing capacitor is illustrated in Figure 13.26(A). This is an inexpensive
method of improving linearity if a high voltage supply is available in the system
under design. It suffers from the disadvantage that the frequency would not be as
stable as it would with asingle power supply.

VI

(
A)USE OF H GH VOLTAGE (3) USE OF COLLECTOR CHARACTERISTIC
SUPPLY FOR CHARGING FOR CONSTANT CURRENT SOURCE
OF TIMING CAPACITOR

TWO CIRCUITS FOR IMPROVING LINEARITY OF SAWTOOTH GENERATORS

Figure 13.26
Figure 13.26(B) illustrates the use of the high output impedance of a common-
base transistor to maintain aconstant charging current for the capacitor.

318
 UNIJUNCTION TRANSISTOR CIRCUITS 13

LINEAR SAWTOOTH WAVE GENERATORS

Two variations of a bootstrap charging circuit are shown in Figures 13.27 and
13.28. In 13.27 a constant voltage is maintained across the charging resistor by the
zener diode and the emitter follower transistor amplifier stage so that the capacitor
charging current is constant over the complete cycle. This circuit is quite economical
in that it makes double use of the transistor, both as the driver for the bootstrap
circuit and as an output amplifier stage. Note that the 3.9K load resistor is returned to a
negative voltage to prevent clipping at the bottom of the sawtooth waveform. Q3
maintains the zener current constant for improved linearity and also assists Q2 in
supplying current to the load. The circuit will generate alinear sawtooth up to 50 kc.

+24V
1N4154

03
2N525

680

5.6V

01
2N2646 J F
-0 OUTPUT

.001
3.9K

-10V

50 KC SAWTOOTH GENERATOR
Figure 13.27

The circuit shown in Figure 13.28 makes use of a capacitor in place of the zener
diode. This variation permits the negative supply to be eliminated. The NPN tran-
sistor serves as an output buffer amplifier with the capacitor C2 and resistor R2 serving
in abootstrap circuit to improve the linearity of the sawtooth. RI and Cl act as an
integrating network to provide second order compensation for the non-linearity of
the waveform. By varying the value of RI the output waveform can be made concave
upward, concave downward, or linear.

+20V

N\P
OUTPUT
6V P- P

OUTPUT
10 V P-P
IKC

SAWTOOTH GENERATOR WITH HIGH LINEARITY

Figure 13.28

319
13 UNIJUNCTION TRANSISTOR CIRCUITS

The feedback networks in Figure 13.28 are frequency sensitive. C2 will not be
effective at low frequencies and the effective emitter capacity can not be much less
than .01 gf without affecting the linearity and operation at the higher frequencies.
Cl could be reduced to about .001 1.4f by using the higher frequency type 2N2647.

PRECISION TIMING CIRCUITS

TIME DELAY RELAY
Figure 13.29 shows how the unijunction transistor can be used to obtain adelay
in the operation of arelay. When the switch SW1 is closed, capacitor CTis charged
to the peak point voltage at which time the unijunction triggers and the capacitor
discharges through the relay causing it to close. One set of relay contacts holds the
relay closed and the second set of contacts can be used for control functions. To be
used in this circuit, relays must have fast operating times, low coil resistance and
low operating power.

RELAY
CONTACTS

RT + V1
IMEG SW' (24-32V )

2NI6716
3300
2W

GE MICRO—
CT RELAY MINIATURE RELAY
I00µ fd 14613 3S2791G200A-6
25V DPDT
IN536

TIME DELAY CIRCUIT WITH RELAY

Figure 13.29

The time delay of this circuit is determined by RT, about one second of delay
for each 10K of resistance. The time delay is quite independent of temperature and
supply voltage.

PRECISION SOLID STATE TIME DELAY CIRCUITS

Figure 13.30 illustrates atypical time delay circuit ùsing the unijunction transistor
together with alow cost SCR. The timing interval is initiated by applying power to
the circuit. At the end of the timing interval, which is determined by the value of
RTCT, the unijunction triggers the SCR and the full supply voltage minus about one
volt is applied to the load. By suitable choice of RTand CTthis circuit will give time
delays from 0.4 milliseconds to 1minute. Load currents are limited only by the rating
of the SCR; up to 6 amperes for the C2OF (stud mounted). Use of aprecision cali-
brated resistor such as helipot in place of RTpermits the time delay to be set accurately
over awide range after one initial calibration.
The timing resistor in aconventional UJT time delay circuit must be small enough
to supply the minimum trigger current (I I.) of the UJT plus the leakage current of
the timing capacitor when the UJT emitter is biased at its peak point voltage. The
2N494C has amaximum h. requirement of 2ga. This places alimit of 3megohms on
RTand for CT= 4gf permits time delays to 12 seconds with a conventional circuit.
The circuit shown in Figure 13.31 reduces the effective trigger current by afactor

320
 UNIJUNCTION TRANSISTOR CIRCUITS 13

56on
+28V

EXTERNAL
LOAD

GN

SOLID STATE TIME DELAY CIRCUIT

Figure 13.30

27011
--0- +28V

22K R,
C35F
47011 1000 1500 CIOF
M.S1
C9F
CT
4µf d
YLHAR A • SSD708
N4009
10µf 2N494C
25V
SSD708
1.5n 47(7
)K
2711 LOAD

TIME ADJUST

ONE HOUR TIME DELAY CIRCUIT

Figure 13.31

of more than 1000 and allows time delays of up to 1hour to be achieved with alow
leakage 4 1.4.fd mylar capacitor. This is achieved by periodically sampling the voltage
on the timing capacitor. Between samples the timing capacitor is isolated from the
emitter of the UJT by ultra-low leakage planar silicon diodes (the SSD-708 has a
leakage current of less than 20 picoamperes at 25°C). The sampling pulse is gen-
erated by aUJT relaxation oscillator operating at approximately 2cps.
The 2N494C is biased continuously at the peak point by a 15 megohm resistor
to reduce the triggering energy required. Adjustment of the time intérval is obtained
by means of the 10K potentiometer which sets the initial voltage on the timing capaci-
tor. Extreme care must be taken in the choice of components and the layout to
minimize leakage. A high quality mylar capacitor must be used for CT. A glass sealed
resistor must be used for RT. Point A should be supported by the leads only or by a
single teflon standoff insulator.
The circuit in Figure 13.32 gives time delays from 0.3 milliseconds to 5 hours
without using atantalum or electrolytic capacitor. The timing interval is initiated by
applying power to the circuit. At the end of the timing interval, which is determined

321
13 UNIJUNCTION TRANSISTOR CIRCUITS

RI
2.2K TO
10.000
MEG

C9F, CI 2F
CI OR C4OF
0.1 TO 2,‘ f

FIVE HOUR TIME DELAY CIRCUIT

Figure 13.32

by the value of RI Cl, the 2N494C triggers the controlled rectifier. Load currents are
limited only by the rating of the controlled rectifier which is from 1ampere up to 25
amperes for the types specified in the circuit.
Charging resistor RI must be small enough to supply the minimum trigger cur-
rent (peak point current, Ip) of the 2N494C plus the leakage current of the capacitor
when the emitter of the unijunction is biased at its peak point voltage. This would
place alimit of 3megohms for RI and permit time delays to 6 seconds (Cl = 2 gf)
without using the additional 2N491 relaxation oscillator.
The circuit as shown effectively reduces the minimum It. requirement more than
1000 times by pulsing the upper base of the 2N494C with a 3/4 volt negative pulse.
This negative pulse rate is not critical but it should have a period that is less than
0.02 (R1 Cl). The negative pulse causes the peak point voltage to drop slightly and
if the voltage level at Cl is greater than this, the unijunction will trigger with the
necessary Ir supplied from Cl. The low leakage requirement for Cl is easily obtained
with amylar capacitor. R2 can be adjusted or selected for best stabilization over the
required temperature range. A pulse transformer can be used in place of the 27 ohm
resistor if it is necessary to have the timing circuit isolated from the power switching
(controlled rectifier) circuit which, for instance, might be connected to the ac line.
The input impedance of the 2N494C is greater than 1500 megohms before it is
triggered. The maximum time delay that can be achieved by this circuit is mainly
dependent upon the maximum values that can be obtained for RI and Cl consistent
I
N1694

3.9K
IW
START
SWITCH

200
100V
120V
60 CPS

SPRAGUE
312286
CIO OR C35

SOLID STATE AC TIME DELAY (ONE SECOND)

Figure 13.33

322
 UNIJUNCTION TRANSISTOR CIRCUITS 13
with the low leakage requirement. Without diode DI, R1 is limited to 15 megohms
for an accuracy of 0.5% at 25°C and 5% at 55°C, but with DI, RI can be increased
to 10,000 megohms.
An all solid state time delay circuit with ac output can be achieved with a single
UJT as shown in Figure 13.33. The timing sequence is started by closing the START
SWITCH and applying voltage to the UJT circuit. The time delay is determined by
the time constant (R1 ± R2) (Cl -I- C2). When the voltage at the emitter of the
UJT reaches the peak point voltage, capacitor Cl remains charged and the UJT
oscillates at ahigh frequency determined by the time constant (R1 ± R2) C2. The
pulses from the UJT are then coupled through the pulse transformer to the SCR's,
turning them on and applying voltage to the load. Since the UJT oscillates at a
frequency much higher than the line frequency the switching of the SCR's is prac-
tically from full on to full off. The 2N2647 is needed to obtain the high output pulse
required to fire two SCR's in parallel at ahigh repetition rate. When the start switch
is opened diode DI provides apath to discharge Cl. Larger values of time delay can
be obtained by increasing the value of Cl. The timing circuit and the load circuit
can be operated from acommon ac supply or aseperate ac supply as desired.

DELAYED DROPOUT RELAY TIMER

The circuit of Figure 13.34 provides a simple means for accurately delaying the
dropout of arelay after it is energized. In the quiescent state no power is applied to
the circuit. When SW1 is momentarily closed the transistor will turn on and the
relay will pull in. Voltage to the circuit is then maintained through the relay contact
so that the relay will remain energized when SW1 is opened. After a time interval
determined by the values of RI and Cl the UJT will trigger, and the discharge of Cl
will turn off the NPN transistor, allowing the relay to drop out. If SW1 is open the
voltage to the circuit will be removed and the circuit will revert to its quiescent state.

R3

DELAYED DROPOUT RELAY TIMER

Figure 13.34

An output voltage can be obtained from the relay contacts shown or extra sets
of contacts on the relay can be used as desired.
After deciding on the supply voltage and the relay to be used, R2 is then selected
to provide sufficient base current to the NPN transistor with regard to the resistance
of the relay coil and the minimum specified current gain of the transistor. The size of
the capacitor is then selected to provide sufficient off time for the NPN transistor to
allow the relay to drop out. Resistor RI is then chosen for the maximum time delay

323
13 UNIJUNCTION TRANSISTOR CIRCUITS

+30V

I
O

MOMENTARY
Ion
CONTACT
SWITCH
I
SCS 2µf 2p.f
IN536
3N61

2.5
4

35ma
IK 470
IWATT
RELAY ¡IN536

2N2647

10 SECOND TIMER
Figure 13.35

required and the maximum peak point current of the UJT. Finally, resistor R3 is
chosen for the required overall temperature compensation.
The circuit of Figure 13.35 provides for the relay to be energized for a preset
period of time up to 10 seconds. Closing Si triggers the silicon controlled switch
(SCS), and places most of the supply voltage across the relay which also starts the
unijunction timing interval. After a preset interval the unijunction will be triggered
and discharge the 4eif capacitance through the 10 ohm resistor. This discharge pulse
makes the anode negative with respect to the anode gate (connected to +30 volts)
and turns off the SCS which drops out the relay.

SENSING CIRCUITS
VOLTAGE SENSING CIRCUIT
The high sensitivity of the unijunction transistor and the extreme stability of VP
make it ideally suited for use in go no-go types of voltage sensing circuits such as
shown in Figure 13.36. This circuit includes a simple floating power supply with
zener diode regulation which operates from the 115 volt ac line. If the input signal
is negative the unijunction will not trigger and there will be no output. If the input
signal is slightly positive, the unijunction will trigger and pulses will occur at the
output as long as the input signal remains positive. The output pulses are of sufficient
magnitude to trigger a flip-flop, an SCR, or other pulse sensitive devices. Note that
the transformer coupled supply and output of this circuit give complete freedom of
choice in connecting the circuit to the signal source since there are no common grounds.
Most of the output pulse energy is supplied by capacitor C3. This capacitor is
charged rapidly through RI after each pulse and hence does not limit the response
time of the circuit. Diode D2 provides adischarge path for C3, and diodes DI and
D2 clamp the input voltage to enable C3 to charge to its steady state voltage when
very large voltages are present at the signal input. Capacitors Cl and C2 provide the
initial trigger energy for the unijunction transistor and also serve as afilter for tran-
sients appearing at the signal input and across the supply. In some cases asmall capaci-
tor will also be required across the primary of the pulse transformer to prevent false
triggering due to transients.
The circuit is initially adjusted by shorting the signal input and setting RI so that
the circuit is on the verge of triggering. If close temperature compensation is needed

324
 UNIJUNCTION TRANSISTOR CIRCUITS 13
330 A

SIGNAL
INPUT

3300
PUL SE
OUTPUT

VOLTAGE SENSING AND TRIGGER CIRCUIT

Figure 13.36

R2 is adjusted so that the triggering voltage does not change appreciably when the
unijunction is heated or cooled. It is normally possible to adjust the temperature com-
pensation so that the drift in trigger voltage is within ±-2millivolts from 0°C to 55°C.
After the temperature compensation is completed it will normally be necessary to reset
R1. The long term stability of this circuit is normally better than ±-10 millivolts and
the hysteresis is normally less than 1millivolt. The change in triggering voltage with a
change in the supply voltage (aV, )will be less than 0.7 AV1/V1. The voltage stability
can be improved by adding two silicon diodes in series with R2.

NANOAMPERE SENSING CIRCUIT WITH 100 MEGOHM INPUT IMPEDANCE

The circuit in Figure 13.37 may be used as a sensitive current detector or as a
voltage detector having high input impedance. R1 is set so that the voltage at point A
is 1/
2 to 3
4 volts below the level that triggers the 2N494C. A small input current (It.)
/
of only 40 nanoamperes will charge C2 and raise the voltage at the emitter to the
triggering level. When the 2N494C is triggered, both capacitors, Cl and C2 are dis-
charged through the 27 ohm resistor, which generates a positive pulse with sufficient
amplitude to trigger a silicon controlled rectifier (SCR), or other pulse sensitive cir-
cuitry. C2 is kept small for faster triggering response time and Cl is used to provide
the pulse output energy. Rapid recovery is obtained after the 2N494C triggers since
both capacitors are charged through Rl. This configuration has the advantage that
the leakage current of the silicon diode effectively subtracts from the leakage current
of the unijunction and thus provides some temperature compensation.
The input current available MO through the 100 megohm resistor will be much
lower than the minimum trigger requirement for the 2N494C (peak point current
(L.) = 2.0 sa). Use of a sampling technique described for Figure 13.31, however,
permits areduction in the external triggering current (II.) by as much as 1000 times
below h. By pulsing the upper base of the 2N494C with a 0.75 volt amplitude nega-
tive pulse the peak point voltage V, will drop slightly and if the voltage level at C2
is greater than this, the unijunction will trigger with the necessary Ir supplied from
C2. By use of this technique, the 2N494C has been triggered with external input cur-
rents MO as low as 1nanoampere with a2000 megohm resistor for R2.
The period of the 2N491 relaxation oscillation is not critical, but it should have a
time constant of 0.02, or less, than that of the 2N494C.
For this sensing circuit a floating power supply using a zener diode will permit

325
13 UNIJ
UNCTION TRANSISTOR CIRCUITS

SCR
(C9F, Cl2F,
OR C4OF

NANOAMPERE SENSING CIRCUIT WITH

100 MEGOHM INPUT IMPEDANCE
Figure 13.37

grounding one of the sensing input terminals if this is desirable. M. should be adjusted
so the circuit will not trigger at the maximum ambient temperature in the absence of
the current or voltage sensing signal. R3 can be adjusted or selected for best stabiliza-
tion of Vp over the required temperature range.

SCR TRIGGER CIRCUITS

SIMPLIFIED SCR TRIGGER CIRCUIT DESIGN PROCEDURES
SCR trigger circuits using the unijunction are simple and compact with low power
consumption yet the 2N2647 can easily trigger a235 amp rms SCR. An added advan-
tage is that triggering is assured over awide ambient temperature range even with
UJT and SCR limit units (due to production variations). This assurance is available
by using the tailored trigger circuits as outlined in Figures 13.38 and 13.39. These
circuits essentially marry the particular UJ T and SCR in a configuration that takes
into account the dynamic triggering requirement of the SCR. Whereas most SCR
specification sheets give consideration only to the static requirements. These design
curves give the condition for the required minimum trigger energy, and it is then
simple to double the value of CTor increase Vi for a guaranteed 2 to 1 above this
minimum which is often desirable to decrease the SCR turn-on time and switching
losses.
The value of R1 in the trigger circuits is kept low enough to prevent the de voltage
at the gate, due to interbase current, from exceeding the minimum gate triggering
voltage for the SCR.
The design of asuitable SCR triggering circuit can be achieved rapidly and easily
by using the design curves that are given. These curves give the minimum supply
voltage required to guarantee triggering of the various types of SCR's over the specific
temperature range as afunction of the UJT emitter capacitor, CT. The value of the
resistor RTis not important for the purposes of the design provided that it is within
the limits required for the UJT to oscillate. If R2 is significantly greater than 100 ohms
the minimum supply voltage which is assumed (Vi' )should be calculated from the
minimum supply voltage (Vi) given in the design curves using the equation (131).
Vi' (2200 ± R2 yi
(131)
2300
As an example of the practical design of an SCR triggering circuit, consider the
following:
Problem: A circuit is required to trigger ahigh current type 2N1913 SCR and the
trigger circuit supply is 22 volts. We choose the 2N2647 UJ T because of its guar-

326
 UNIJUNCTION TRANSISTOR CIRCUITS 13

UJT TYPE SCR TYPE CURVE RI V I(MAXI

I.. ..,

C60(2N202 3-30)
C55 AND C56 A 270 -± e% 35v
2N489A Et B C52(2N1792-98)
THROUGH C50(2N1909-16)
2N494A, B, AND C C46 s 470 ± e% 26V
(ALSO USAF TYPES) C45
C37
C36(2NI842 -50) c PULSE TRANS.
PE223I
35V

C40 D 270 ± 10% 35V

C38 0
2N24I7A 8 B C35(2N681-92) E 470 II0% 20V
THROUGH
C30 AND C32 **
2N2422A, El, AND C PULSE TRANS.
C20 AND C22 *. G 35V
C15 SPRAGUE 31Z204

C12
2N167IA 8 B CI 1(2N1770 -78, E 270 t 10% 32V
2N2619)
C10(2N1770A-77A)
C9 G 470 ± 10% 18 V
2N2646
C8(2N1929-35)
2N1595-99 PULSE TRANS.
r 35V
SPRAGUE 31Z204

C7(2N2344-48)
F ISO ±io% 35V
2N2647 C6 H 270 ± 10% 20V
C5 J _ SPRAGUE 31Z204 35V

NOTES: *LIMITED TO 27 VOLTS MAX ON "D" CURVE AND 15 ***MINIMUM TRIGGER PULSE IS TWICE THE AMP-
VOLTS ON "E" CURVE. L TUDE OF OTHER UJT'S, THIS ASSURES 2:1
**TRIGGER REQUIREMENTS LESS THAN OTHERS OVER MINIMUM SCR TRIGGER REQUIREMENTS.
IN THIS GROUP.
36

c ® v,
te\o
34
0
!. 32 OK - .„ LOAD
o é

oo
> 30

28 C
T
RI
t..) 26
0
0
1- 24
o 0
> 22

2 16

14

12
-.
10
—55° C TO+ I25° C
8 (NOTE: Temperature range may
be restricted by the SCR specification.)
6
001 0.1 10
CAPAC1TANCE-C T - MICROFARADS

SCR TRIGGER CIRCUIT DESIGN CURVES

(Assures minimum trigger requirement for IA rise <10A/gsec.)

Figure 13.38

anteed high trigger pulse, V.51. Assume that the value of capacitance, chosen on
the basis of operating frequency, is 0.2 uf and that the value of the base-two
resistor, calculated for temperature compensation, is 620 ohms.
Solution: From Figure 13.39 it is seen that curve B meets the above requirements
with a27 ohm resistor for RI. On curve B it is seen that the minimum voltage for
CT = 0.2 ,if is 11.7 volts. Correcting this value to take into account the value of
R2, equation (131) gives Vi' = (1.22) (11.7) = 14.3 volts. Triggering is therefore
assured for a supply voltage range of 14.3 to 35 volts. If the supply voltage is

327
13 UNIJUNCTION TRANSISTOR CIRCUITS

SCR TYPE CURVE RI

V IIMAX)

C80 A 27Ot 10% 20V

D PULSE 35V
TRANS.
PE223I
34 C60(2N202330) 27000% 35V
C55,C56 470110% 20V
32
C52(2N1792-98) PULSE 35V
30 C50(2N1909-16) TRANS.
C45 AND C46 PE2231
28 ZJ257
ZJ285
26
VOLTAGE -V 1 -VOLTS

24

22

20
SUPPLY

14
166

12
MINIMUM

10

O
6
4
2N2647
2 TA =-40•C TO 125•C
I I II
.01 .05 0I 05 10
CAPACITANCE -CT - MICROFARADS

HIGH CURRENT SCR TRIGGER CIRCUIT DESIGN

CURVES USING 2N2647
Figure 13.39

greater than 35 volts the SCR may be triggered by the de voltage across RI at an
elevated SCR junction temperature. Thus, asuitable design using the 2N2647 in
the triggering circuit would be CT= 0.2 pf, R2 = 620 ohms, RI = 27 ohms, and
V, = 22 volts, +60% or —35%.

TRIGGERING PARALLEL-
CONNECTED SCR'
S
If two or more SCR's in parallel are to be triggered by a single UJT the design
of the trigger circuit must take into consideration the possibility that an SCR with a
low gate resistance may be paralleled with an SCR having ahigh gate resistance, thus
loading down the output pulse sufficiently to prevent the second SCR from being
triggered. To reduce this possibility it is recommended that the trigger pulse be
coupled by means of aseparate capacitor to each SCR gate. These capacitors act to
equalize the charge coupled to each gate during the trigger pulse and thus tend to
reduce the effects of unequal loading. The optimum value of capacitor for this purpose
has been found to be 0.1 pf. In addition to this capacitor, aresistor having avalue of
220 ohms to IK should be connected between gate and cathode of each 'SCR. Using
this approach of equalizing capacitors, the design curves of Figures 13.38 and 13.39
can be used for parallel triggering of SCR's, provided that the minimum supply volt-
age is multiplied by afactor of 1.5 if two SCR's are to be triggered in parallel and
by afactor of 1.8 if three SCR's are to be triggered in parallel. Since the gates are
not direct coupled, the maximum supply voltage allowed is limited only by the 35
volt rating of the UJT.

328
 UNIJUNCTION TRANSISTOR CIRCUITS 13
Alternatively, a larger value of base-one resistance, R1, can be used to reduce
the otherwise required increase in value of supply voltage for parallel triggering. For
example, if RI . 100 ohms, and using equalizing capacitors, the curves for RI = 27
ohms apply for triggering two SCR's in parallel with no increase in supply voltage.
For triggering three SCR's in parallel under this condition the supply voltages given
by these curves should be increased by afactor of 1.25.

SIMPLIFIED SCR TRIGGER CIRCUITS FOR AC LINE OPERATION

A trigger circuit that is synchronized from the ac line is shown in Figure 13.40.

fYY1 rrn

R2

AC
01
FULL WAVE
RECT PIED

1
1
ZEN ER
DIODE
OUTPUT TO
SCR GATE

RI

LINE SYNCHRONIZED TRIGGER CIRCUIT

Figure 13.40

A full wave rectified signal obtained from a rectifier bridge or a similar source is
used to supply both power and a synchronizing signal to the trigger circuit. The
zener diode is used to clip and regulate the peaks of the ac as indicated in Figure
13.40. At the end of each half-cycle the voltage at base-two of the UJT will drop to
zero, and any charge on the capacitor will forward bias the emitter diode of UJT into
conduction. The capacitor is thus discharged at the beginning of each half cycle and
the trigger circuit synchronized with the line. A pulse is produced at the output at the
end of each half cycle which can cause the SCR to trigger and produce asmall current
in the load.
A simplified type of trigger circuit results if base-two and the emitter timing
circuit of the UJT are supplied directly from the line by way of dropping resistor RD
which keeps the peak voltage on the UJT within its specifications. (See Figure 13.41.)
The voltage across capacitor C will increase at arate determined by the time constant
of the circuit. When it reaches the peak point voltage the UJT will trigger and turn
on the SCR.

SIMPLIFIED UNIJUNCTION
TRANSISTOR TRIGGER
CIRCUIT
Figure 13.41

329
13 UNIJUNCTION TRANSISTOR CIRCUITS

LOAD
33K RD

RI WC 7
100K — 0.1
R
miN
120 01 SCR
VAC 2N2646 22K 500K Q. 02 CH/20
SCR CONTROL 2N2646
C11/20 RI
47 R
51 0.1 100K

33K
o
SIMPLIFIED FULL-WAVE UJT TRIGGER CIRCUIT
Figure 13.42

The half-wave circuit of Figure 13.41 can be extended to full-wave operation.

In Figure 13.42 two of the basic circuits of Figure 13.41 have been placed back-to-
back. The emitters of the two UJT's have been cross-coupled with a network that
exerts full cycle phase control over both SCR's.
The unijunction phase-control circuit in Figure 13.43 has a wide range of stable
control without hysteresis or dependence upon supply voltage. Automatic feedback
control systems can be designed with this UJT circuit since the UJT is essentially half
of a balanced bridge with built-in un-balance detection of high sensitivity and
stability. The dual diode is selenium and has alow peak reverse voltage requirement
in this circuit.

LOAD
RI R3 R2
33K 3-125K O. leaf 33K
120 VAC G.E.
60e. TI
TRI AC
• ZJ-257B
DUAL DIODE —OE
6RS5GDIBADf •
(T
o (G.E.)
TI -SPRAGUE TYPE 31Z204
WT/TRIAC PHASE CONTROL
Figure 13.43

SENSITIVE AC POWER SWITCH

The circuit Figure 13.44 switches load in response to agradually changing signal
such as light on acadmium sulfide photocell, temperature of athermistor and so on.
Switching is apositive snap action from full "off" to full "on" and vice versa. Differ-
ential in input between switching conditions may be adjusted over a wide range by
changing values of Cl and RI.

330
 UNIJUNCTION TRANSISTOR CIRCUITS 13

6.8K
2W

o
—r LOAD 1-40
4.7K
Z4XLI6

120V AC
GE
2N2646 8425
GE K GE
-
47 C2 PHOTO
A44B A44B CELL
SENSITIVE
AC POWER SWITCH
Figure 13.44 VOLTAGE PEAK POINT
ACROSS C2 — VOLTAGE OF UJT

•
OFF LON

The conventional unijunction transistor circuit has been modified so the voltage
waveshape across capacitor C2 has ahigher value at the beginning of each half-cycle
than at the end. This wave is the result of Cl and RI producing a higher charging
current to C2 at the beginning of the cycle. As the photocell resistance (in this case)
increases, the voltage on C2 rises until it reaches the peak-point voltage of the UJT.
Since this condition occurs first at the leading edge of the cycle, the UJT will only
trigger at that point, turning the SCR on early in each half cycle. Triggering the SCR
removes voltage from the UJT circuit, and capacitor Cl discharges. At the beginning
of the next half cycle, the discharged condition of Cl produces a higher charging
current for C2, assuring a snap action full "on" condition. Photocell resistance must
then be reduced to avalue lower than before in order to stop triggering the UJT and
SCR, hence the differential between "on" and "off" conditions.
The photocell can be replaced with agrounded emitter NPN transistor to make the
circuit sensitive to de input signals. This on/off ac switch can be used for photoelectric
controllers, temperature regulators, overheat protection, latch-on functions, ac motors,
driving compressors, conveyors, and fans.

SENSITIVE DC POWER SWITCH

The circuit in Figure 13.45 features a latching action. That is, once triggered, it
stays on. In this circuit
Power input = 0.1 volt at 25 µamp = 2.5 µwatts
Power output = 400 volts at up to 110 amps de = 44k watts

Power gain Out put

tt 44 X 103 — 17.5 xIce —92db
Input 2.5 X 10'

+20V
LOAD
OUTPUT
SENSITIVITY
SENSITIVE DC CONTROL
POWER SWITCH 10K

Figure 13.45

331
13 UNIJUNCTION TRANSISTOR CIRCUITS

HIGH GAIN PHASE-CONTROL CIRCUIT

The minimum size of the capacitor C2 in aconventional UJT/SCR phase-control
circuit is dictated by the minimum acceptable pulse amplitude at the output. For
reliable firing of high current SCR's acapacitor in the range of 0.20 µfd is necessary.
Once the minimum size of the capacitor and the required range of phase control are
determined the required current from the control element will be fixed. If the available
current from the control element is insufficient, one or more stages of amplification
must be added between the control element and the phase-control circuit.

22011

HIGH GAIN 2N49113

OR
PHASE-CONTROL CIRCUIT 2N24198

Figure 13.46

C PULSE
OUTPUT

The simple modification of the phase-control circuit shown in Figure 13.46 permits
an increase in the effective gain by afactor of up to 10,000 times and in many applica-
tions will duplicate the performance of two or three stages of transistor amplification.
In this circuit the larger capacitor, C2, is rapidly charged through the 6.8K resistors
at the beginning of the timing interval. The smaller capacitor, Cl, is charged through
the control element and since this capacitor is in series with C2 it can be charged
simultaneously with C2. The effective gain of the circuit is very large since asmaller
voltage change is required across asmaller capacitor than with the conventional phase
control circuit. Thus the current required from the control element is much less than
if C2 were charged directly. At the same time the full pulse energy from C2 is avail-
able at the output.
In designing this circuit, C2 is chosen large enough to provide the required output
pulse amplitude. Capacitor Cl is chosen small enough to provide sufficient gain for
the circuit and large enough to ensure regeneration at the peak point. Usually avalue
of 500 pf will be adequate to meet the latter requirement for the 2N489-2N494,
2N2417-2N2422 or 2N1671, and 100 pf will be adequate for the 2N2646 or 2N2647.

TRIGGERING CIRCUITS FOR DC CHOPPERS AND INVERTERS

The impulse commutation often used in de choppers and inverters can cause
premature triggering of the unijunction. The positive commutating pulse applied to
the cathode of the SCR, results in anegative pulse gate to cathode. If these negative
pulses reach base-one of the unijunction it may be triggered prematurely. When
transformer coupling is used, transients can be greatly attenuated by adiode bridge as
shown in Figure 13.47. A negative gate to cathode pulse at the SCR may be further
attenuated by the low impedance 1N91.
Supply voltage transients can be decoupled from the unijunction emitter by
choosing the impedance of Cl and C2 so the transient has negligible effect on V.
The sum of Cl and C2 constitute the total unijunction timing capacitance.
The triggering circuit of Figure 13.48 uses the UJT to drive the 2N526 from
cut-off to saturation. Since we are not using the energy in Cl to trigger the SCR,
the smaller .01 gf capacitor size can be used and thus achieve UJT operation to 20 kc.
The 1N4154 keeps the emitter-base junction of the 2N526 reverse biased except for

332
 UNIJUNCTION TRANSISTOR CIRCUITS 13

COMMUTATING
PULSE

TRIGGER CIRCUIT FOR ELIMINATION OF

TRANSIENT INTERFERENCE
Figure 13.47

1- 28V
3.3K

20 KC TRIGGER GENERATOR
Figure 13.48

the discharge interval of Cl. R5 limits the voltage amplitude of the trigger pulse to
the SCR. The 2N526 also isolates the SCR turn-off pulse from the UJT timing circuit.
The square wave inverter drive circuit shown in Figure 10.12 (Chapter 10) has
been used successfully as the control and trigger source for parallel inverters using
General Electric type C40 SCR's.

REGULATED AC POWER SUPPLY

The unijunction triggering circuit in Figure 13.49(A) uses the voltage developed
across the SCR's during blocking for the interbase supply as well as synchronization
for the unijunction transistor. The firing circuit is connected to the output of a single
phase bridge formed by the 1N1695's. Through the action of the bridge, the zener
diode and the resistor R3, a clipped and rectified voltage with a waveform as shown
in Figure 13.49(B) is applied to the UJT and its emitter circuit.

333
13 UNIJUNCTION TRANSISTOR CIRCUITS

- ILOAD •

It INI695
R4 i INI695
R3 IK 2.7K

3.3K
5W R2 Vi
390 4,
.50K
SPRAGUE 22V
5V 3IZ 286 BB IW
60 CPS 2N167IA

• - CI
VE T0.21.0
•
C356

1 INI695 i INI695

(A)

SUPPLY 0
VOLTAGE

VOLTAGE
ACROSS
ZENER
DIODE 0

VOLTAGE
ACROSS
CI 0
GATE
CURRENT
O

VOLTAGE
ACROSS 0
LOAD

(B)

REGULATED AC POWER SUPPLY AND WAVESHAPES

Figure 13.49

The regulating ability of the supply in Figure 13.49(A) results from having R4
in the circuit. The charging voltage for the capacitor is equal to the zener voltage
and is essentially constant over the half cycle prior to the instant when the SCR is
triggered. This is shown in the waveforms of Figure 13.50. The interbase voltage,
VBB, of the UJT is not constant during this interval, but is equal to the breakdown
voltage of the zener diode plus a small fraction of the line voltage determined by
the voltage dividing ratio of R3 and R4. Thus at any given phase angle the interbase

334
 UNIJUNCTION TRANSISTOR CIRCUITS 13

voltage will increase if the line voltage increases as shown in Figure 13.50. The peak
point voltage of the unijunction transistor is equal to the interbase voltage times the
standoff ratio and is given in Figure 13.50 to correspond to the two interbase volt-
age curves.
The emitter voltage follows the normal exponential charging characteristic since
the charging voltage, Vi, is constant. The UJT and SCR's trigger when the emitter
voltage equals the peak point voltage. It is readily apparent from Figure 13.50 that,
as the line voltage increases, the delay before the UJT and SCR's are triggered in-
creases and hence the conduction angle of the SCR's decreases. The decreased con-
duction angle reduces the power to the load, thus offsetting the increase of power to
the load otherwise due to the increase in line voltage. By proper choice of the voltage
divider ratio of R3 and R4 it is possible to obtain perfect compensation of the circuit
for small changes in line voltage.
HIGH LINE VOLTAGE
INTERCASE VOLTAGE, VaB
LOW LINE VOLTAGE
CHARGING VOLTAGE, V1

PEAK POINT
VOLTAGE
(Vp V8B)

EMITTER
VOLTAGE, VE

•
•

I
._
CONDUCTION
ANGLE
HIGH LINE —4
VOLT AGE

CONDUCTION I
ANGLE
LOW LINE
VOLT

ONE-HALF CYCLE
OF AC LINE

VOLTAGE WAVEFORMS OF SCR/WT REGULATED AC SUPPLY

WITH HIGH AND LOW LINE VOLTAGE
Figure 13.50

The circuit shown was adjusted to give optimum regulation at 25 volts rms output
and 115 volts input, and the component values listed were found to be suitable. For a
change in line voltage from 115 volts to 100 volts the change in output voltage was
less than 0.1 volt with any output voltage setting from 10 volts to 30 volts.
If regulation is desired over awide range of output voltage, aganged pot can be
used with R1, and the value of R4 can be changed with the position of the potenti-
ometer. The value of R2 is chosen to achieve the desired temperature compensation
in the ordinary manner. There is some interaction between the adjustment of R4 for
voltage compensation and the adjustment of R2 for temperature compensation, so
several successive adjustments may be required.

335
13 UNIJUNCTION TRANSISTOR CIRCUITS

TRANSISTOR CONTROL OF UNIJUNCTION

SHUNT TRANSISTOR CONTROL OF UJT
In circuits using a shunt transistor to control the UJT similar to the arrangement
in Figure 13.51, it is seen that Q1 can shunt some of the charging current supplied to
Cl by resistor RI in an amount dependent of the base drive to Ql. The more Q1 is
turned on, the greater the delay before the UJT is triggered. With R1 set for about
4.7K ohms, base current I Bto Q1 will then control the diversion of charging current
from Cl and retard or advance the triggering of the UJT. Q1 can prevent the trigger-
ing of the UJT if
V, (1 — n)
IB (13m)
hB E RI
where
IBis in amperes
V, = 20 volts, and
hF E = current gain of Q1

RESET

RI .10K + 4.7K

4.7K

OI
2N2I9 2
SIGNAL75K
INPUT

SIGNAL DROPOUT DETECTOR

Figure 13.51

The circuit of Figure 13.51 can be used to provide an indication of a momentary

dropout of an input signal. The signal monitored could be adc voltage, an ac voltage,
or apulse voltage. The time between the disappearance of the signal and the indica-
tion of afault can be adjusted as desired.
Capacitor Cl will be charged through RI continuously. In the presence of an
input signal the NPN transistor will discharge CI in a periodic manner so that the
voltage at the emitter of the UJT will not reach the peak point voltage and neither
the UJT nor the SCS will be triggered. If the input signal disappears or the time
between pulses exceeds the preset value, the UJT and the SCS will be triggered and
provide a de output signal. The output signal will remain until the SCS is turned
off by momentarily opening the reset switch. The 100K resistor in the anode gate of
the SCS is used to prevent the rate effect from interfering with the reset action.

SERIES TRANSISTOR CONTROL OF UNIJUNCTION

A transistor in series with Cl instead of in shunt with it can be used to regulate
the charging rate of the capacitor and thereby retard or advance the triggering of

336
 UNIJUNCTION TRANSISTOR CIRCUITS 13
the UJT. Such acircuit is shown in Figure 13.52. An additional NPN transistor, Q3,
is required if it is desired to keep one side of the input signal at the potential of the
lower line. Series control often offers an advantage in noise immunity in asystem.

INPUT
SIGNAL
V2

PULSE
OUTPUT

TI-SPRAGUE TYPE 31 Z204

SERIES TRANSISTOR CONTROL OF WT

Figure 13.52

HYBRID TIMING CIRCUITS

The unijunction transistor can he used in conjunction with conventional PNP or
NPN transistors to obtain versatile timing circuits such as symmetrical and nonsym-
metrical multivibrators, one-shot multivibrators, variable frequency oscillators, and
time delay circuits. The advantages of these circuits include: (1) the output at the
collector of each transistor is very nearly an ideal rectangular waveform, (2) the
circuits will tolerate large variations in hFE or Ico of the transistors as compared to
conventional circuits, (3) the circuits are not prone to "lock-up" or non-oscillation,
(4) the timing stability is excellent, and (5) asingle small timing capacitor CTcan
be used, avoiding the use of electrolytic capacitors in many applications.
The hybrid timing circuits can use either germanium or silicon transistors as
desired. The basic circuits for PNP or NPN transistors are shown in Figures 13.53(A)
and 13.53(B). In both of these circuits, the junction transistors form a conventional
flip-flop with the unijunction transistor serving the timing and triggering functions.
Each time the unijunction transistor conducts, the discharge current from the capacitor
CTdevelops apulse across RAwhich triggers the flip-flop from one state to the other.
The basic circuits as shown in Figures 13.53(A) and 13.53(B) will operate at
frequencies from about 1cycle to 500 cycles, and at temperatures above 75°C. Fre-
quencies from 1cycle per minute to 100 kc can be obtained by proper choice of Cr
and RAand suitable flip-flop design. The operating temperature range may be extended
to 150°C by the use of silicon transistors.

337
13 UNIJUNCTION TRANSISTOR CIRCUITS

The basic hybrid timing circuits in Figures 13.53(A) and 13.53( B)can be adapted
to perform desired functions by connecting resistors or potentiometers, as indicated
below, between the circuit points Cl, C2, E, and G.

(A;

BASIC HYBRID TIMING CIRCUITS USING PNP AND NPN TRANSISTORS

Figure 13.53

SYMMETRICAL MULTIVIBRATOR (SQUARE WAVE GENERATOR)

RT

E 0 M.A., 0 G (FIXED)

Vo
E 0-/V\A"-y,\/-0 G (VARIABLE)
Ri>3K R2

Connecting the resistor between points E and G in the basic circuits gives asquare
wave generator which has perfect symmetry. By the use of a2 megohm potentiometer
the frequency may be varied continuously from 1 cps to 500 cps. The frequency is
f= 1/2 RTCT.

ONE-SHOT MULTIVIBRATOR

RT
C(0- '/V", OE (FIXED)

Vo _11
-_
1...t ...i

OE (VARIABLE)
tURTCT
RI>3K R2

In the quiescent state, Q2 is on in Figure 13.53(A), therefore a positive pulse at

the base of Q2 will trigger the circuit. For Figure 13.53(B), QI is on in the quiescent
state, therefore a negative pulse at the base of QI will trigger the one-shot. At the
end of the timing interval, the unijunction will be triggered and cause the circuit to
revert to its quiescent state. This circuit has the advantage of a fast recovery time so
it may be operated at ahigh duty ratio without any loss of accuracy.

338
 UNIJUNCTION TRANSISTOR CIRCUITS 13
NON -
SYMMETRICAL MULTIVIBRATOR

R TI v
o_l
Cl

E (VARIABLE)
RI >3K tI (RTI + RI) CT
02
t2"=. OR T2 T RI) CT
R T2

Ii RI CT
GO '\AA
RI
RI R2CT

OE (FIXED) 12- RI + R2

R2

The timing capacitor CTwill be charged through the resistor RTI or RT., which is
connected to the positive collector. The diodes will isolate the other resistor from the
timing capacitor. The two parts of the period (ti, ti,) can thus be set independently by
RTI and RT2 and may differ by as much as 1000 to 1.

NON-SYMMETRICAL MULTIVI BRATORS (Constant Frequency)

RI >3K
CI O-----W

E
(2 RIA-R21CT

0-111111-V\A"
RI>3K

This configuration gives a multivibrator which has a constant frequency but a

variable duty cycle.

MULTIVIBRATOR
Figure 13.54 shows a unijunction transistor multivibrator circuit which operates
at 400 cycles. The length of time during which the unijunction transistor is off (no
emitter current flowing) is determined primarily by RI. The length of time during
which the unijunction transistor is on is determined primarily by R2. Assume power
is applied to the circut at time t= 0. Current will flow through R2 and the diode to
ground. The capacitor will be charged through RI with the right hand side rising
towards +20V. In Figure 13.54 the emitter voltage rises from point A as the capacitor
voltage increases. When the emitter voltage reaches the peak point voltage (point B),
the UJT is triggered on. The emitter voltage falls to the value determined by the inter-
section of the load line formed by R1R2/R1+R2 and the emitter characteristic, point C.
At the same time the voltage across the diode drops by an equal amount and the diode
becomes reverse biased. The capacitor is then discharged through R2 with the left
hand side rising towards +20V. During this interval the current through the emitter
of the UJT is the sum of the current through RI and the discharging current from
the capacitor.
The UJT remains stable in the negative resistance region as long as the emitter
sees the high resistance of R2 in series with the capacitor. After the capacitor is
discharged to a point where the diode again becomes forward biased, the current
through R2 will be diverted into the diode and the emitter current will fall to avalue
determined by the load line formed by RI (point D). Now unstable, because of the
low impedance of the forward biased diode, the UJT will turn off and its operating

339
13 UNIJUNCTION TRANSISTOR CIRCUITS

VI

0 O

UNIJUNCTION MULTIVIBRATOR
Figure 13.54

point will move to E. This cycle will repeat with the operating point of the UJT
moving around the characteristic in an EBCD sequence, as shown in Figure 13.54.
During the on time of the UJT the capacitor is discharged through R2 and the
emitter current decreases. This in turn increases the interbase resistance and produces
a slight increase in the interbase voltage as indicated between points C and D on
the waveform.
The frequency of the multivibrator is inversely proportional to the capacitor.

= A
-
C

where A = 40 for R1 = IIK and R2 = 27K. The UJT off time is determined primarily
by RI and the on time by R2.
Vi - VE MIN/
t
i= RI C In (13n)
[

- Vp

t2 = R2 C in [Vi -
I-VP VE(MIN) (13o)

where VE(MIE) is measured at

I
E= V, (R1 -I- R2) ( 13P
)
RI R2
which is point C on the waveform in Figure 13.54.
In Figure 13.55, the diode is replaced by the emitter-base junction of the NPN
transistor. This turns the transistor on and off when this diode is forward and reverse
biased, respectively. The collector load has a negligible effect on the timing of the

340
 UNIJUNCTION TRANSISTOR CIRCUITS 13
circuit. It should be noted, however, that the load must be large enough to permit
the minimum base current of
Vi — VP
R2 -I- (13q)
RI
to drive the transistor into saturation. It is not necessary to supply the transistor from
the same power supply as the multivibrator. Any NPN transistor can be used in this
circuit if the emitter-base breakdown voltage is adequate (BVEB ≥ 15V). The 7A35,
alow-cost silicon mesa with an emitter-base voltage rating of 15 volts and aminimum
hrE of 50 at 50 ma, is recommended for use in this application.

20V

0.2V

TRANSISTOR -
UJT MULTIVIBRATOR
Figure 13.55

The specification sheet for the unijunction types 5E35 and 5E36 give design curves
and performance capability for the UJT multivibrator.

FREQUENCY DIVIDER
The simple unijunction relaxation oscillator circuit can easily be adapted for fre-
quency division by cascading several of these basic circuits and synchronizing from a
master oscillator. From each divider stage there is available a sawtooth waveform as
well as pulse outputs of either polarity.
The divider circuit in Figure 13.57 consists of aclass C Hartley oscillator followed
by three basic unijunction relaxation oscillators each having its own "free-running"
frequency when unsynchronized. Each unijunction stage functions as a relaxation
oscillator synchronized to the preceding stage by pulses coupled through C4, C6,
and C8. Frequency division by two (÷ 2) will result with maximum divider
stability when the oscillator free-runs at about three times the period of its synchro-
nizing pulse. About 5% increase in period will result in the first and second dividers
because of the parallel value of the emitter timing capacitor plus the sync pulse
coupling capacitor.
The ideal timing resistor (RI, R2, R3) for each stage can always be determined
by checking the maximum and minimum resistance values before the stage drops out
of synchronization; the divider stage that follows should be connected since it does
load the previous stage.
The UJT relaxation oscillator can be synchronized by applying positive pulses at
the emitter or negative pulses at base-two. At the emitter the pulse amplitude require-
ment is approximately % of that required at base-two when using the 2N2646. Since
base-two synchronization offers less loading on the pulse source and since a negative
pulse of suitable amplitude is readily available, this method of synchronizing is used

341
13 UNIJUNCTION TRANSISTOR CIRCUITS

B2 SYNC PULSE

1ST
DIVIDER

'77777/ EMITTER

B2 SYNC PULSE
WAVEFORM

2ND
DIVIDER

EMITTER WAVEFORM

B2 SYNC PULSE

3RD
DIVIDER

EMITTER WAVEFORM

UJT FREQUENCY CIVIDER WAVEFORMS

Figure 13.56

1390 CPS 695 CPS 347.5 CPS 173.75 CPS

MASTER OSCILLATOR Isr DIVIDER 2nd DIVIDER 3rd DIVIDER
2.26 r, 21 1, 21 (+2) •

25 V
G
, II I 12K R2 I.2K R3 12K 20 1A.

i
CI 2.2K
.068 T5K C6 100K 240K
I2V 120K C. C8
001

1.5 MA C2 0.01
.0068 B
2 0.0?
2N27I2
C.5
8
N264 a, 292646 292646
250.f
15)/ 7451_129 C5 Cl C9
100K
(GE) .047 .047 .047

LI -450MHY SLUG TUNED COIL NOTE , ALL CAPACITORS ±10%

r 6 (Tyr WC ALL RESISTORS 1/2 WATT
DC RES. 48011

UNIJUNCTION FREQUENCY DIVIDER

Figure 13.57

in Figure 13.57. Using a high amplitude sync pulse permits wide variations in corn-
ponent tolerance. Total component variation for each divider including the unijunction,
can approach ±25% when dividing by two. If the pulse amplitude is too high it will
lock the divider stage on every sync pulse instead of counting down by two. For
division by two with a25 volt supply, synchronizing pulses from about 6 to 10 volts
may be used, with about 8 volts ideal. When the countdown is increased, however,

342
 UNIJUNCTION TRANSISTOR CIRCUITS 13

allowable component variation decreases. In addition, synchronizing pulse amplitude

becomes more critical. To illustrate, dividing by six (÷ 6) in asingle stage, synchro-
nized by a 11 / to 3volt pulse, permitted atotal component variation of only ±7%.
2

Two capacitors, Cl and C2, are used across Li rather than only asingle capacitor
for two reasons: abalanced tank to ground results in improved wave shape across the
resonant tank, and, the prime reason, rapid turn-on of current conduction by the
2N2712 results in a sharp synchronizing pulse with more than twice the amplitude
obtained when only asingle capacitor is used. If Li is tapped at the optimum point,
C3 can then be used for de blocking only. Any stable oscillator that will produce a
negative 6 to 8 volt pulse with sharp wavefront and a few microseconds wide, will
drive this unijunction divider system.
Capacitor C4 is selected to provide a 6 to 8 volt pulse at base-two of the first
divider. This pulse amplitude allows good locking action between the oscillator and
the first divider with minimum oscillator loading. In addition, feedback of the pulse
generated at base-two by the unijunction when the 1st divider triggers is minimized.
To completely alleviate the feedback pulse, a blocking diode can be used in series
with, or in place of, C4.
By adding a 1K to 2K resistor in series with each emitter timing capacitor, as
shown in Figure 13.58, an additional ±-5% circuit tolerance can be expected. An
advantage in adding the base-one resistors is the availability of apositive going pulse
at base-one. Duty cycle, up to about 5%, as well as the pulse amplitude are de-
pendent on the resistor values used.
When subjected to temperatures of 0°C to 70°C the frequency dividers remain
locked.

I
K TO 2K

ADDING 1K TO 2K RESISTOR IMPROVES CIRCUIT TOLERANCE

Figure 13.58

MISCELLANEOUS CIRCUITS
REGENERATIVE PULSE AMPLIFIER
The basic UJT relaxation oscillator may be adapted to form a regenerative pulse
amplifier by adding a resistor between emitter and ground. Resistors R3 and R4
should have a ratio such that the emitter voltage does not exceed the peak point
voltage for the quiescent state, similar to the level sensing circuits. The values of the
resistors should be large enough so that the UJT is not stable in the on state as dis-
cussed under relaxation oscillators. Figure 13.59 shows ageneral pulse amplifier with
three possible inputs and three outputs. Two trigger input pulses could be used for
coincident pulse detection. Either pulse by itself should not have sufficient amplitude
to trigger.

343
13 UNIJUNCTION TRANSISTOR CIRCUITS

OR

REGENERATIVE PULSE OR
AMPLIFIER CIRCUIT
Figure 13.59

TRIGGERS

PULSE GENERATOR (VARIABLE FREQUENCY AND DUTY CYCLE)

The frequency and duty ratio can be varied independently with the rectangular
wave generator shown in Figure 13.60. The UJT is used in a conventional sawtooth
generator and the two transistors serve to provide a positive going output when the
voltage at the emitter of the UJT exceeds the voltage at the emitter of the NPN
transistor as determined by the setting of the RATIO potentiometer. The loading of
the sawtooth by the transistors is compensated by feeding a current from the output
to the emitter of the UJT which is equal to the current diverted into the base of
the NPN transistor at the switching point. If this was not done the frequency would
be dependent on the setting of the RATIO potentiometer.
The ratio of the circuit as shown can be varied from 0 to 100% and the frequency
can be varied from approximately 60 cps to 1000 cps. Rise and fall times of the output
waveform are approximately 1/500 of the period of oscillation.

1N4009

+I5V

OUTPUT

PULSE GENERATOR (VARIABLE FREQUENCY AND DUTY CYCLE)

Figure 13.60

344
 UNIJUNCTION TRANSISTOR CIRCUITS 13
STAIRCASE WAVE GENERATOR
The circuit shown in Figure 13.61 can be used to generate a staircase waveform
over a wide frequency range. An NPN-PNP emitter follower output circuit is used
to achieve a high input impedance and a low output impedance to reduce the droop
in the output voltage between pulses. The bias for the NPN transistor is obtained
from the 1.8 megohm resistor across D3 and D4 and is effectively bootstrapped on
the output to maintain the high input impedance. The staircase wave is generated by
a diode-capacitor pump (D2 and C2) which is also bootstrapped on the output to
maintain equal amplitude on each step. The number of steps per cycle depends on
the ratio of Cl to C2 and the amplitude of the input pulse. For the circuit values
shown astaircase of 10 steps is obtained with a 12 volt pulse input having awidth =
4(Rg C2) microseconds, where Rg is the impedance of the pulse generator. The input
impedance of the amplifier as determined by the droop on the output voltage is
approximately 15 megohms, giving satisfactory waveforms at frequencies as low as
50 cycles.

+15V

C2
o
.01 PULSE
INPUT

DI -D4 = 1N4009

STAIRCASE WAVE GENERATOR WITH LOW IMPEDANCE OUTPUT

Figure 13.61

ONE-SHOT MULTIVIBRATOR (Fast Recovery and Wide Frequency Range)

This hybrid one-shot multivibrator circuit, Figure 13.62, is an improved configura-
tion which provides awide timing range, good timing stability, fast clean waveforms,
and operation over an extreme range of duty cycle. Even though silicon diodes and
transistors are used exclusively the overall circuit cost is low owing to the low cost
of the components.
In the quiescent state QI is off, Q2 is on and the emitter voltage of the UJT is
clamped to a low voltage through D2 and the collector of Q2. A negative trigger at
the input turns off Q2 and permits Cl to charge through Rl. When the UJT triggers,
the negative pulse generated across the 10 ohm resistor is coupled through D3 to
the base of Ql, turning off QI and setting the circuit back to its initial state. Capacitor
Cl is rapidly discharged through D2 and the collector Q2 resulting in fast recovery.
The circuit can thus be retriggered immediately after completion of a timing cycle
without loss in overall timing accuracy. Resistor RI provides the main time delay
adjustment. Resistor R2 provides a normalizing adjustment for RI to compensate for

345
13 UNIJUNCTION TRANSISTOR CIRCUITS

minor variations in the value of Cl, RI, D2, and the intrinsic standoff ratio (n) of
the UJT. If this normalizing adjustment is not required R2 can be eliminated and a
single IK resistor used in the collector of Q2.

+10v

o
-LF
TRIGGER
INPUT

ONE-SHOT MULTIVIBRATOR WITH FAST RECOVERY AND

WIDE FREQUENCY RANGE
Figure 13.62

VOLTAGE-TO-FREQUENCY CONVERTER
This voltage-to-frequency converter shown in Figure 13.63 gives an output fre-
quency proportional to the input voltage with 1 volt producing a frequency of 1 kc.
The input impedance is 100K. The linearity is better than 0.1% and the short term
equivalent input voltage drift is less than 0.5 millivolts.
Overall negative feedback is used to achieve the high degree of linearity and
stability. The transistors form an operational amplifier with an overall voltage gain of
5000 at the emitter of the UJT. Each time the UJT fires a fixed quantity of charge
is fed back to the input of the operational amplifier through Cl, C2, and the diode.

100K

VOLTAGE-TO-FREQUENCY CONVERTER
Figure 13.63

346
 UNIJUNCTION TRANSISTOR CIRCUITS 13

The average current fed back to the input is proportional to the frequency so that
the frequency must be proportional to the input voltage to maintain the summing
point of the operational amplifier at zero potential.
To adjust the circuit, close SW1 and set R2 to the point where oscillations just
start. Open SW1, apply 1 millivolt at the input and set R3 to the point where the
frequency is approximately 1cps. Apply 1 volt at the input and set C2 to the point
where the frequency is 1000 cps. If this setting is outside the range of C2 replace or
trim Cl, using mica capacitors only. The voltage supplies used for this circuit should
be at least as stable as the required measurement accuracy.

REFERENCES
"Sylvan, T.P., "Notes on the Application of the Unijunction Transistor," Pub. No. 90.10, 1961,
General Electric Company, Electronics Park, Syracuse, New York.
"Silicon Controlled Rectifier Manual", 2nd. Edition, General Electric Company, Rectifier Com-
<2)
ponents Department, Auburn, New York, (1964)

NOTES

347
13 UNIJUNCTION TRANSISTOR CIRCUITS

NOTES

348
 4 4
TUNNEL DIODE CIRCUITS

TUNNEL DIODE OSCILLATORS' -'

8)

Tunnel Diode Oscillators are attractive because of their high-frequency capability,

low power consumption, good frequency stability and extreme circuit simplicity. These
advantages enable a designer to produce stable miniature oscillator circuits with a
wide variety of uses. Figure 14.1 illustrates the basic "series-parallel" sinewave oscil-
lator. Design equations are also given. Additional design information will be found by
consulting the references at the end of this chapter.

CI

R2

%UT

R1 < -
R4 where Rd is TD's negative resistance.
— 3
112 = Ebb — Vd
V1
Id ±
R1

Cl = „
\ Igai (1— RTgal )
where gal is TD's initial negative conductance
RT
RTis circuit's total dc resistance and

is equal to RI
—R1±—R2 ± RS+ RUC (roll)
R2

Rs is TD's total series resistance.

Ci 1
C = where gd is TD's negative conductance.
— 11T ga w-
hence

L =1
w 2(c + Cl
1— RTgd /

BASIC TUNNEL DIODE SINEWAVE OSCILLATOR

AND DESIGN EQUATIONS
Figure 14.1

The circuits that follow illustrate the many applications and variety of tasks tunnel
diode oscillators are capable of performing. Brief descriptions accompany some circuits.
For more complete information readers should consult the specific reference as indi-
cated. An extensive reference list appears at the end of this chapter.

349
14 TUNNEL DIODE CIRCUITS

IN3714
+Ebb OUT

270

2.5µH
1N1692

This 1.1 mc oscillator senses temperature changes and translates them into frequency
variations. The main temperature sensing element is a mylar capacitor whose charac-
teristics yield a0.5 ke/*C temperature coefficient."'

TEMPERATURE SENSING OSCILLATOR

Figure 14.2

250

10

0.022
E bb I. 5 V

1N2939
OR
1N3712

A voltage variable capacitor tunes this oscillator electronically over the 12-22 mc
range."'
VOLTAGE CONTROLLED OSCILLATOR
Figure 14.3

350
 TUNNEL DIODE CIRCUITS 14

P. TO 50.11

LOAD

+ 2.5K 10K

VARICAP
TUNNEL BIAS
DIODE VOLTAGE
BIAS

460
OSCILLATOR FREQUENCY (MC)

440 P. -0.50 MW-•

420
400
380
360
340
320
300
280
260
240
220 •

10 100
VARICAP BIAS VOLTAGE (VOLTS)

This VHF oscillator can be electronically tuned over the 200-400 me range. Output
power is over 0.5 milliwatts." )

VOLTAGE CONTROLLED VHF OSCILLATOR

Figure 14.4

"\Mla
RA =101.1
Zi
n .11001).

L=16µh
nom
Cb RA

(EM,
RA =11011
Rb,,,,, ( f V
Zi n .19111
IN3712(TD-11
1 100011
Vbb ° VDc .110ms
i
n

loon 10011
o •

RA =36011
Cb = DC BLOCKING CAPACITOR
Zi n =127.811
RA = ATTENUATING RESISTOR

ZIA --4. R (1 +

Resistor R., is an attenuating resistor which varies the magnitude of the oscillator
swing. This enables the oscillator to operate over alimited, hence highly linear portion,
of the diode's conductance curve. Note low distortion in the oscilloscope display at the
bottom."
VARIABLE AMPLITUDE OSCILLATOR
Figure 14.5

351
 14 TUNNEL DIODE CIRCUITS

BIAS
MATERIAL (MA) (MW) FREQ. (GC)
Ge 40 1 6
Go As 45 1.5 3
Ga As 80 3 6
Go As 100 4 6

Two or more tunnel diodes placed in ahalf-wave cavity structure delivers 4 milliwatts
at 6kme.'
MICROWAVE OSCILLATOR
Figure 14.6

+I2V

IK

2012

Using aGeneral Radio Delay-Line (Type 314-S86 )this oscillator covers the 0.5-20 mc
range. Output is in the square wave category.

DELAY-LINE OSCILLATOR
Figure 14.7

* SELECTED DEVICE

SINEWAVE OSCILLATOR WITH "PLUG-IN" COILS

(Covers 3 to 260 mc range)

Figure 14.8

352
 TUNNEL DIODE CIRCUITS 14

R< IR d il

R=

Zin R (1+ )
-CR
WHERE Rc R IS THE SERIES
RESISTANCE OF THE CRYSTAL
Vbb AT RESONANCE.

FOR OSCILLATIONS , Re IYi n I<Ig d iI

'Yi n =

BASIC TUNNEL DIODE CRYSTAL

CONTROLLED OSCILLATOR")
Figure 14.9

Figures 14.10 and 14.11 show crystal controlled Citizens Band and Fire Depart-
ment oscillators. Both are useable in low power (microwatt) transmitters for short
range communications."'

THE OSCILLATOR FREQUENCY

OPERATES WITHIN THE TOLERANCE
OF THE QUARTZ CRYSTAL OVER A
+I.5V TEMPERATURE RANGE OF FROM
Vbb -55°C TO +85°C AND A BIAS
1N3712
RANGE OF FROM 110 TO 150mv.
(TD-I)

CITIZENS BAND 27.255 MC CRYSTAL

CONTROLLED OSCILLATOR
Figure 14.10

ANDERSON 3d OVERTONE
CRYSTAL, TOL 0.005%
RcR 25fL min.

338 mp.h THE OSCILLATOR FREQUENCY

nom OPERATES WITHIN THE QUARTZ
750S1 CRYSTAL TOLERANCE OVER A
+I.5V TEMPERATURE RANGE OF FROM
Vbb IN3712 -55*C TO +85°C AND OVER A
(TD-1) BIAS RANGE OF FROM 110 TO
150mv.

FIRE DEPARTMENT 47.100 MC CRYSTAL

CONTROLLED OSCILLATOR
Figure 14.11

353
 14 TUNNEL DIODE CIRCUITS

f0.5ma
I 300-500p.h

I.34V
MERCURY CELL _ T

100-250 mh
I Si
10 0.25
•---1
MOTOR
01 WINDING

R*

IK

Si 2N336
_
10 2.5mh 1500

* ADJUST R FOR COLLECTOR CURRENT

OF 0.5 ma WHILE MOTOR IS RUNNING

TUNNEL DIODES 0.5 ma UNITS

This circuit illustrates an application where the low power consumption, the low volt-
age requirements, and the excellent frequency stability of crystal controlled tunnel
diode oscillators provides the circuit designer with an ideal device for his job. The
complete circuit incorporates trimmers that can adjust the timing of the clock by a
few seconds per year. Three tunnel diodes give overall division ratio of 2,000 to 1.
Figure 14.13 pictures the finished chronometer.

CRYSTAL CONTROLLED CHRONOMETER (s

)

Figure 14.12

Figure 14.13 HIGH ACCURACY CHRONOMETER

354
 TUNNEL DIODE CIRCUITS 14

TUNNEL DIODE MICRO-POWER TRANSMITTERS“ ,5 )

Tunnel diode remote control transmitters have adequate range to remote control
toys, garage doors, window displays, etc. Where voice modulated they can be used
for short range communications, as in television studios, power plants, bowling alleys,
shopping centers, etc.
Circuits in Figures 14.15 and 14.16 can be built into miniature hand-held box chassis
as shown below.

Figure 14.14

WhiP
ANTENNA

(SEE FIG 14.17)

TUNNEL DIODE OSCILLATOR

I0-22pf

UNIJUNCTION TONE OSCILLATOR

SW' IN3716
PUSH TO SEND (4:1MA )
2N2840 UNIJUNCTION
E

MERCURY +
.22
CELL -

LI - 6 TURNS *16
(1/2" LONG, 3/8" I.D., TURNS SPACED 1/32")

Unijunction tone oscillator modulates this miniature transmitter used to remotely

control garage door.

TUNNEL DIODE-UNIJUNCTION REMOTE

CONTROL TRANSMITTER
Figure 14.15

355
 14 TUNNEL DIODE CIRCUITS

?
!WHIP ANTENNA

(SEE Fig. 14.17)

I0-22PF

PUSH
TO 200nh TUNNEL D ODE OSC
SEND IN3716 (47MA)
750.
Z.320./Z=5000CT

MERCURY - I.34V
CELL

LI -6 TURNS *16
(1/2" LONG, 3/8" ID., TURNS SPACED I/32")

Hartley oscillator using silicon transistor modulates tunnel diode transmitter.

TUNNEL DIODE-TRANSISTOR REMOTE

CONTROL TRANSMITTER
Figure 14.16

141/2"
A. SAFETY CAP SOLDERED TO ANTENNA TIP

B. 14 1/2 INCH .052" PIANO WIRE SOLDERED OR

BRAZED TO C
C. BANANA PLUG (E.E. JOHNSON 108-771)

D. BANANA JACK FORCED-TAPPED INTO 7/32"

DRILLED HOLE (E.F. JOHNSON 108-760)
E. 50 TURNS *24 FORMVAR OR ENAMEL COVERED WIRE
ADJUSTED TO 27 mc WITH GRID DIP METER
F. 1/2" X 11/4" SOLID COIL FORM MADE FROM
TEFLON OR POLYSTYRENE
G. TIP PLUG FORCE TAPPED INTO 7/32" HOLE
(E.F• JOHNSON 105-301)

Details of antenna and loading cod construction for Figures 14.5 and 14.6.

ANTENNA
Figure 14.17

356
 TUNNEL DIODE CIRCUITS 14

ANTENNA
LOADING
IN3716(TD-3) 200pfd j COIL

I.3mh

73.5 MC CRYSTAL CONTROLLED SELF-MODULATED

TRANSMITTER
Figure 14.18

FM TRANSMITTER 96 TO 110MC/S USING 4.7MA T. D.

A/4@ 25 .. E .125MV. TO GRN

'
..1001‘AC/S
.
R4
IN3716
SPEAKER OR
MICROPHONE
IL L2

RI R5 C5
4.5-25 pf

e Ï 2

LI 2 TURNS * * COPPER 3/BID SPACED 1/8" FROM GROUND END OF L2 (ADJUST FOR BEST STABILITY)
L2 6 TURNS*I6 COPPER 3/810 CLOSE-WOUND AND CONNECTED DIRECTLY TO C2. TAPPED ITURN
FROM GROUND.
CI 45- 25/ap.fd CERAMIC TRIMMER
C2 IS-Sk(4 VARIABLE
C3 800p.p.td (VOLTAGE NOT IMPORTANT-SELECT FOR SMALL SIZE )
C4 50p.fd 6VDC ELECTROLYTIC (VOLTAGE NOT IMPORTANT- SELECT FOR SMALL SIZE)
C5 I
p. d 35 vDC (VOLTAGE NOT IMPORTANT-SELECT FOR SMALL SIZE)
RI IBA 1/2W 5%
R2 1500 1/2W 5%
R3 4700 1/4W
R4 10K0 1/4W
R5 10K0 1/4v4
Ebb MALLORY RM-12R MERCURY CELL 134VDC-3600 MAH
Swl NORMALLY OPEN SPST "PUSH-TO- TALK "SWITCH
SPKR 2"PM SPEAKER
IN3716 (TD-3) 4.7MA AXIAL TUNNEL DIODE

This circuit has a200 yard range when used in conjunction with sensitive commercial
receiver.

FM WIRELESS MICROPHONE
(96 to 110 mc)

Figure 14.19

357
 !DO
TUNNEL DIODE CONVERTERS

td.
11 •2 ' 19-25)
50
The tunnel diode oscillator can be used in the design SYSTEM SENSITIVITY AT INC: 4µv (50mw REFERENCE)

"laNNfli
of "self-oscillating" converters. 5.55

IN3712

a
40

OSCILLATOR SWING IN nw rrns

to
(TO-I)
200mA REOUENCY

1
I
I
5.50

acroia
I-2µh 2211 1000p! o

I
» 30
270Pf SENSITI ITY
1209 I ce
—
e

I
1
m-- 5.45
cI71 5.46MC

S111131113
I
20

g
„
Ts 330p f 4700 t
e 15
Odb CONVERSION GAIN o

.0=
III
OUTPUT TO
CAR RADIO
10
INPUT FROM — 4110N
CAR ANTENNA
im F :
0.
2_0 j

II
r—r
OFF
I.5V SW-3 POLE DOUBLE .-4 ill 111
1 470. SW— THROW SWITCH 95 105 115 125 135 145 155 165 175 185 195 205 215 225 235 245
(B) PERFORMANCE CURVES BIAS VOLTAGE IN mv
_t.

CIVIL AIR PATROL CONVERTER

ANTENNA
(A) IN3712
(71)-1)

ANTENNA IN3712 560

(TD-I)
0.57µP

10000
56pf

1000 pf OUTPUT

0.57µA U 56pf H@
0.5741
150pf 170,ah +1.5V 7500 CRYSTAL
+I.5V4700 ii
Vbb
Vbb
CRYSTAL CONTROLLED
4711
CITIZEN BAND CITIZEN BAND CONVERTER
CONVERTER (D)
(C)
 NPUT FROM
TRANSMISSION LINE IN3712(TD-1) ANTENNA

e
OUTPUT IN3713
TO TV 300 (TD-1A
OHMS 033pf
1-4-1I II
100f 0.68pf 22
LO-3.0pf

IFOUTPUT
.0
)
2-8pf
300 430
Sw I pi 471
UHF
TUNER

J
(F
47 OHMS I.5V

LOW INDUCTANCE FEEDTHROUGH DC

SUPPLY

COMMUNITY TV "UP CONVERTER"

(E)

ANTENNA

SIIIIDIIID aCIOICI gaNNIIL

I.F.
OUTPUT

+I.5V

CAPACITIVELY TUNED TUNER

(G)

vi
Figure 14.20 SELF-OSCILLATING TUNNEL DIODE CONVERTERS
14 TUNNEL DIODE CIRCUITS

TO BIAS NETWORK

AMPLIFIER
X/4

TUNNEL
DIODE B
16 INPUT

OPEN OSC STRIPLINE

SHORT SIGNAL STRIPLINE A

— — — X/4 — — — —01

STRIPLINE LAYOUT
(A)

INPUT

AMPLIFIER
(30mc)

BIAS

LUMPED CONSTANT EQUIVALENT CIRCUIT

(B)

L-BAND SELF-OSCILLATING CONVERTER

Figure 14.21

3 KMC L-BAND CONVERTER PACKAGE

Figure 14.22

360
 TUNNEL DIODE CIRCUITS 14
300.0
FEED

LI 88-108MC INPUT

TD-9
4-135MV
IF OUTPUT
(200KC)

200 RI

10K

AFC VOLTAGE

LI - 4 TURNS *18-3/8" ID, APPROX. I/2"LONG

L2 - 4 TURNS *18 -3/8" ID, APPROX. I/2 "LONG
L3 -81/2" TURNS *18-3/8" ID, APPROX. 3/4" LONG TAPPED AT 5 TURNS
LIL2 -COUPLED END TO END, SPACED... 1/8" APART
RI - DEPENDS ON SUPPLY VOLTAGE. SELECT FOR BIAS OF APPROX.
I35MV ACROSS 2000 RESISTOR.

This converter is AFC controlled by a variable capacitance diode. The 200 kc IF

output is used here because of the type of receiver design (see Figure 15.21).

Figure 14.23 FM-AFC CONTROLLED CONVERTER

DIPOLE ANTENNA

7me (FM)

* GE BACK DIODE

Lwi
81 2 1,000 cps

39pf VV\
.50nh
114me 8D7*

R3.67

R2.330

LeelOnh I.4V
7me

RT (0.3-0.7)
STABILITY LESS de DRAIN

gd (I -RTgd ) VbR T
RI
Vb - E,

CI
- R,g, R2me-R,

Figure 14.24 TUNNEL DIODE TRANSCEIVER'm

This transceiver is tuned for a 114 me AM input signal and a 7 mc FM output signal.
The 1N3714 (TD-2) tunnel diode acts as 7 mc RF oscillator and frequency modulator
while the BD-7 back diode is the 114 mc detector.

361
14 TUNNEL DIODE CIRCUITS

VARIOUS INDUSTRIAL SPECIAL USES OF TUNNEL DIODES" , "'

TONE-FREQUENCY
SENSITIVITY CONTROL
10 MA. METER OR
10K 33K IK SPEAKER

BROADBAND IN3712
SELECTIVE PICK UP COIL (TD-1) 0.0Ie
CIRCUIT (2 TURNS NO.18-2" DIA )
X CRYSTALcb SWITCH OR
PHONES, KEY
X

=9v
_

.X'
I. WAVEMETER I. KEYING MONITOR NOTE:
2.PARASITIC 2. CODE PRACTICE OSC. AN SOR 16 OHM LOUDSPEAKER MAY BE USED.
DETECTOR BUT FOR OPTIMUM SOUND OUTPUT A HIGHER
SPEAKER IMPEDANCE IS NEEDED.

SENSITIVE BROADBAND CW KEYING MONITOR-CODE

PRACTICE OSCILLATOR-SENSITIVE AURAL/VISUAL
PARASITIC DETECTOR OR WAVEMETER
Figure 14.25

100 MC

IN3712 270 _1.5 VO6 M.A.

_L
INPUT
SENSITIVITY 500µV.
•I( o

CI 100kOd
2N2840 "C2
7.7 2N27I2 2N2712
.001 22 MIC.

CI 1.5- 5.0pf VARIABLE

C2 .047 TO 0.2µfd
LI Z- 0.2µ.h (6 TURNS #16, 3/8" I.D.)

loo me wireless telemetry link transmitter. The microphone picks up signal which is

amplified by 2N2712 ; second 2N2712 inhibiting CI turns off allowing Cl to charge up

and fire 2N2840 unijunction oscillator. Unijunction pulse modulates a tunnel diode
transmitter.

WIRELESS PULSE MONITOR

Figure 14.26

362
 TUNNEL DIODE CIRCUITS 14

+9V

0.05µ f
(1 SPEAKER
DC RESISTANCE
4 TO 60.0
3.3K
THRESHOLD IK
ADJUST

2NI304

1N3712
(TDI)
L IS 2 TURNS OF * 14
WIRE, SELF SUPPORTING,
PICK-UP 1.25" DIAMETER, TURNS
COIL ARE SPACED 1/8"

This circuit illustrates a 200 mc, RF radiation detector giving audible (1800 cps)
alarm oscillations. A small slot antenna or apick-up coil can be used as sensors.

RF RADIATION DETECTOR (u)

Figure 14.27

+9V

SPEAKER DC
RESISTANCE 4 TO 600

THRESHOLD
ADJUST

G.E. PHOTO
CONDUCTIVE
CELL A35A

This is avariation of the circuit shown in Figure 14.27. Here the sensor is a photo-
conductive cell giving alarm at below 0.1 foot candles of illumination near 5500
angstroms.
LIGHT DETECTOR
Figure 14.28

TUNNEL DIODE AMPLIFIERS'' ,2 '42'15 '

The performance of tunnel diodes in low noise amplifiers is especially attractive

at UHF and microwave frequencies where ferrite isolators, circulators, and/or hybrid-
couplers can be used to unilateralize the signal flow. At frequencies where these devices
are not available, stable gain is difficult to achieve. Tunnel diodes have been used at
L, S, C, and X band with excellent stability and low noise performance.

363
14 TUNNEL DIODE CIRCUITS

TERMINATION
50 OHM

3 2

THREE PORT CIRCULATOR FOUR-PORT CIRCULATOR

(A) (B)

RESISTIVE
TERMINATION

TUNNEL DIODE UHF

CIRCULATORS
Figure 14.29

TWO CASCADED THREE-PORT CIRCULATORS

(C)

SERIES STUB
4—TO
CIRCULATOR

POWER-SUPPLY LOW-FREQUENCY
TERMINATION , BYPASS

,--{- 1-1 1
V .4
PARALLEL ,--DIELECTR1C.
e"-RF
STUB
RF BYPASS BY
t'BIAS INSERTION

SIMPLIFIED TD PREAMP CIRCUIT PHYSI CAL ARRANGEMENT

(A) (B)

UHF PREAMPLIFIERS
Figure 14.30

THREE-PORT CIRCULATOR COUPLED

L- BAND AMPLIFIER
(C)

364
 TUNNEL DIODE CIRCUITS 14

Figure 14.31 TUNNEL DIODE SIX-GIGACYCLE WAVEGUIDE AMPLIFIER

PORT I PORT 2

e a Lo.
/2
PORT 4 PORT 3

e
AL-9o°

',TUNNEL DIODE
SIGNAL DISTRIBUTION IN
HYBRID—COUPLER TUNNEL DIODE AMPLIFIER
(A) (B)

AMPLIFIER
-3DB MODULE
•2 Zo IN3218A
yIN NO. I

-3DB R AMPLIFIER
yOUT -90"
.3
z. IN3218A E
MODULE
NO.2
BB

3DB HYBRID
L_

2
ZO 0 20 /I-R d I Rs/ IRd I 2
+ +
f. Id I -R d ft2 I-R d I 2/ I d I 2/I-Rd

[
f: Zo Rs 2 f2 2 Zoi I-R d I Rs/I-Rd 11 2
--I+ —+— + —0

fI
2 H ed1 I
-R dI 1 f 12 1
-R d 1 Z il -R d 1 Zi I
-R dI

Z •CHARACTERISTIC IMPEDANCE
2TIVU

Figure Z I-R dl• NEGATIVE RESISTANCE OF THE DIODE

14.32 HYBRI D-COUPLED TUNNEL DIODE AMPLIFIER AND GAIN EQUATION

(0)

365
 14 TUNNEL DIODE CIRCUITS

The tunnel diode is avery useful device in switching circuits because of its
1. Very high switching speed capabilities
2. Low power consumption
3. Well defined thresholding properties
4. Stable characteristics
5. Radiation resistance
It is the fastest switching device known, with transistion times as low as 27 pico-
seconds (27 X 10' second or the time it takes light to travel 0.3 inches). The speed
of most high speed circuits is limited by the circuit and package inductance and
capacitance and not by the tunnel diode.
Figures 14.33 through 14.35 show various types of low power consumption tunnel
diode multivibrators. Figure 14.36 through 14.41 is representative of circuits where
the tunnel diode is used with atransistor. The transistors are used to provide amplifica-
tion with the exception of Figures 14.38 and 14.39 where they are used as ashorting —
resetting element.
Figure 14.42 shows aselection of some high speed logic circuits developed to take
advantage of the tunnel diodes ultra-high-speed switching capabilities.

TUNNEL DIODE MULTIVIBRATORS' 2'

SHORTED
DELAY
LINE

WAVEFORM ACROSS 80mµsec

TUNNEL DIODE FOR
15 FT OF RG62/ U
CABLE AS SEEN ON
TEKTRONIX 581 WITH
PROBE. li s .33
Es =280mv
8m µ se c 10mµsec

Figure 14.33 RELAXATION OSCILLATOR USING A SHORTED DELAY LINE

Figure 14.34 TUNNEL DIODE MONOSTABLE OSCILLATOR

Abl)
 TUNNEL DIODE CIRCUITS 14

I.5V

I.2K
INPUT12pf
)
1 1 1 1 IN3712

OUTPUT

IN3712

TUNNEL DIODE FLIP-FLOP

Figure 14.35

HYBRID (TRANSISTOR-TUNNEL DIODE) MULTIVIBRATORS( 2'

Ebb —I°

3.3K 3.3K

NOTE: Vv ≥. 35 VOLTS

ASTABLE HYBRID OSCILLATOR

FIGURE 14.36

BISTABLE CIRCUIT USING

TUNNEL DIODE AND NPN
GERMANIUM ALLOY TRIGGER
TRANSISTOR
Figure 14.37

367
 14 TUNNEL DIODE CIRCUITS

TUNNEL DIODE COUNTERS" ,2)

E bb

t0.7MA
TRIGGER
INPUT

Jinn_

2N396

NOTE:ALL TUNNEL
DIODES ARE
IN3712

SERIES CONNECTED TUNNEL DIODES USED FOR 5:1

PULSE FREQUENCY DIVIDER OR STAIRCASE
WAVE GENERATOR
Figure 14.38

-0.65V

INPUT
OUTPUT

+I.5V
BINARY NO.1 BINARY NO. 2

LOW LEVEL TUNNEL DIODE COUNTER

Figure 14.39

368
 TUNNEL DIODE CIRCUITS 14

MISCELLANEOUS TUNNEL DIODE CIRCUITS ,2,

+10

ein

TUNNEL DIODE TIME DELAY CIRCUIT WITH TWO

CASCADED COMPLIMENTARY STAGES
Figure 14.40

—5.5V
—10 V
NOTE : VV≥ .35 VOLTS

(A) (B)

HYBRID LEVEL DETECTOR CIRCUITS

Figure 14.41

369
14 TUNNEL DIODE CIRCUITS

TUNNEL DIODE COMPUTER CIRCUITS'' ,

+6V +6V

+90mv
2660 1140

OUTPUTS

INPUTS

Ip =25mo 0 -51mo

TWO CASCADED MONOSTABLES FORM AN "OR" GATE

(A)

+6V +6V +6V

10270 333 206

+90mv +90mv +90mv

PULSE 22.70 I2nh

INPUT

OUTPUTS
210 lOnh

LEVEL
INPUT

Ip .20ma Ip =20ma 10=35ma

THREE CASCADED MONOSTABLES PROVIDE ADEQUATE GAIN IN "AND" GATE

(B)

200 MC
+6V PUMP

+3V

OUTPUTS
TO NIPO
TO
PINO 300
GATES

+3V 1/2 -3V

NIPO GATE +814- PINO GATE

DELAY

BASIC PUMPED TUNNEL DIODE TRANSISTOR LOGIC GATES SHOWN INTERCONNECTED

(C)

Figure 14.42

370
 TUNNEL DIODE CIRCUITS 14

IK 750

INPUT

This circuit operates as aslideback sensing circuit' to give adc output which is pro-
portional to the positive peak of a repetitive input signal. With proper choice of the
tunnel diode and the input circuit layout it is possible to measure the peak amplitude
of pulses as narrow as one nanosecond. The circuit is similar to an operational ampli-
fier with avoltage gain determined by the ratio R,B/RIN.

TUNNEL DIODE PEAK SENSING OPERATIONAL

AMPLIFIER
Figure 14.43

IN3606 6.8K IN3604

20V
60 CPS

RI
100K
INPUT

A simple peak reading voltmeter circuit using a tunnel diode together with a silicon
controlled switch to give a dc output proportional to the positive peak of the input
signal. Voltage gain is equal to (R2 + R3 )/R1.

AC OPERATED PEAK READING VOLTMETER

Figure 14.44

371
 14 TUNNEL DIODE CIRCUITS

R2

OUTPUT

A tunnel diode pair used in conjunction with an operational amplifier which functions
as a sampling circuit with the output proportional to the input signal at the instant
corresponding to the leading edge of the sampling pulse. Effective rise-time can be
in the nanosecond range depending on the tunnel diodes used, the rise-time of the
sampling pulse and the construction of the input circuitry. Voltage gain is determined
by the ratio R2/R1.

OPERATIONAL SAMPLING CIRCUIT USING

TUNNEL DIODE PAIR
Figure 14.45

+I5V

OUTPUT

I5V

1 1
INPUT
AC OR PULSE

A practical version of an operational sampling circuit using the principles shown in

Figure 14.45. Voltage gain of the circuit is 100. Pulse synchronizing and pulse gener-
ating circuit details are not shown. This circuit can also be used to measure the differ-
ential peak point current of tunnel diode pairs.

PRACTICAL EXAMPLE OF OPERATIONAL SAMPLING

CIRCUIT USING TUNNEL DIODE PAIR
Figure 14.46

372
 TUNNEL DIODE CIRCUITS 14
REFERENCES

(1) Gottlieb, E., Giorgis, J., "Tunnel Diodes — A Four Part Series," General Electric Application Note
90.48. (Reprinted from June 14, 21, 28 and July 5, 1963 issues of Electronics.)
(»"Tunnel Diode Manual." Chapter 4, General Electric Company, Semiconductor Products Depart-
ment, Syracuse, NewYork 13201.
() Burrus, C.A., "Millimeter Wave Esaki Diode Oscillators," Proceedings of the IRE, p. 2024,
December 1960.
(4) Gottlieb, E.. "Tunnel Diode Oscillators — Don't Sell Them Short," Electronic Design, March 1963.
(8) Gottlieb, E., Cleary, J.F., "Tunnel Diode Remote Control Transmitters," Radio Electronics, June
1963.
() Nagle, J.J., "Crystal-Stabilized Tunnel Diode Oscillators," Electronics, p. 40, September 1, 1961.
(» Wafters, R.L., "A Quartz Crystal Controlled Tunnel Diode Oscillator," General Electric Research
Lab Memo Report p. 203.
(8) Wailers, R.L., "A Quartz Crystal Chronometer," Electronics, p. 129, September 29, 1961.
(
9>Ishii, K., Hi:4%s, C.C., "Extending Tunnel Diode Operating Frequency," Electronics, p. 43, June
1, 1962.
( 10 Puffer, J.K., "Voltage Tuning in Tunnel Diode Oscillators," Proceedings of the IRE, p. 1155,
June 1960.
au Haneman, F.G., Thomson, G.W., "Varactor-Tuned Tunnel Diode Oscillator Now Practical,"
Electronics, p. 50, September 21, 1962.
(( ,)Hauer, W.B., "A 4 Mw, 6 Erne Tunnel Diode Oscillator," Digest of Technical Papers — 1962
International Solid-State Circuits Conference, p. 68.
" 8) Ishii, K., Hoffins, C.C., "Microwave Tunnel Diode Operation Beyond Cutoff Frequency," Proceed-
ings of the IRE, (Correspondence), p. 370, February 1963.
Bammel, S.E., "Tunnel Diode Radio Frequency Generator," Popular Electronics, p. 44, February
1963.
UM Kim, C.S., Hopkins, J.B., "High Frequency and High Power Operation of Tunnel Diodes," Digest
of Technical Papers — 1961 International Solid State Circuits Conference, p. 22.
Trambarulo, R., Burrus, C.A., "Esaki Diode Oscillators from 3-40 ICmc." Proceedings of the IRE
(correspondence), p. 1776, October 1960.
(17) Sterzer, F., Nelson, D.E., "Tunnel Diode Microwave Oscillators, Proceedings of the IRE, p. 744,
April 1961.
" 8) Gottlieb, E., "Tunnel Diode Sinewave Oscillators," Electronic Design, August 2 and August 16,
1961.
" 8) Iizuka, K., "Leadless Transceiver Probe Works Underwater," Electronics, pp. 56-59, July 19, 1963.
(28) Kim, C.S., "Tunnel Diode Converter Analysis," IRE Transactions on Electron Devices, p. 394,
September 1961.
Christensen, B., "Measurement of Tunnel Diode Conductance Parameters," Proceedings of the
IRE, (Correspondence) p. 1581, October 1961.
" 2) Semiannual Report of Advanced Equipment Studies, WDL Technical Report TR 1481 Contract
AF04 (647 )-532.
(
23 >Sterzer, F., Presser, A., "Stable Low Noise Tunnel Diode Frequency Converters" RCA Review,
p. 3, March 1962.
(2»Pucel, R.A., "Measurement of the Conversion Conductances of Esaki Mixer Diodes," IRE Trans-
actions on Microwave Theory and Techniques, MTT-9, 8, November 1961.
(88) Pucel, R.A., "Theory of the Esaki Diode Frequency Converter," Solid State Electronics, p. 167,
Pergamon Press 1961, Printed in Great Britain.
(2» Gottlieb, E., "Practical Tunnel Diode Converter Circuit Considerations," Solid State Design,
p. 31, September 1962.
(27) Hubbard, D., "Pulse Counter FM Discriminator Design," Electronic Equipment Engineering,
p. 44, July 1962.
(28 )Gottlieb, E., and Wolfram, A., "Design of Tunnel Diode UHF-TV Tuners," Semiconductor
Products Magazine, p. 36A, March 1962.
(28) Reindel, J., "A Compact Tunable Tunnel Diode S-Band Receiver," The Microwave Journal, p. 92,

December 1961.
(9"Chang, K.K.N., Heilmeier, G.H., Prager, H.J., "Low Noise Tunnel-Diode Down Converter Having
Conversion Gain," Proceedings of the IRE, 48, p. 854, May 1960.
(u)Dickens, L.E., Gneiting, G.R., "A Tunnel Diode Amplifying Converter," IRE Transactions on
Microwave Theory and Techniques, p. 99, January 1961.
(82) Eng, S.T., "Low Noise Properties of Microwave Backward Diodes," IRE Transactions on Micro-
wave Theory and Techniques, p. 419, September 1961.
(38) Follmer, W.C., "Low Frequency Noise in Backward Diodes," Proceedings of the IRE, p. 1939,
December 1961.
(84) " Tunnel Detector Models A and B," Reindel Microwave Engineering, San Diego, Calif.

0 » Barnes, F.S., Morris, L., "A Tunnel Diode Frequency Multiplier with Gain," Proceedings of the
IRE, p. 1940, December 1961.
(»6) Stockman, H.E., "Tunnel Diode Super Regenerative Parametric Motor," Proceedings of the IRE,
p. 1586, October 1961.
(an Sikorski, ME., "Sensitive Tunnel Diode Pressure Transducers," Digest of Technical Papers —
1962 International Solid State Circuits Conference, p. 74 and 106, February 15.
488) Mason, W.P., "Semiconductor Devices as Pressure Transducers," Electronics, p. 35, February 23,
1962.

373
14 TUNNEL DIODE CIRCUITS

"" Miller, S.L., Nathan, MI., and Smith, A.C., "Pressure Dependance of the Current-Voltage Char-
acteristics of Esaki Diodes," Physical Review, Letters p. 60, 4 No. 2, January 15, 1960.
"" Rogers, E.X., "Experimental Tunnel Diode Electromechanical Transducer Elements and Their
Use in Tunnel Diode Microphones," Journal Acoustical Society of America, p. 888, 34. No. 7,
July 1962.
(41) Phelps, J.H., "A Tunnel Diode RF Radiation Detector," General Electric Application Note 90.43,
April 1962.
"" MacGlashan, D.W., "New Tunnel Diode Preamplifier Improves Phased Array Radar," Electronics
p. 57, September 28, 1962.
ow sic, J.J., "Absolutely Stable Hybrid-Coupled Tunnel Diode Amplifier," Proceedings of the IRE,
p. 1321, July 1960.
Fleri, D., Boyet, H., "Investigation of Traveling Wave Parametric and Hybrid Coupled Tunnel
Diode Amplifier," Technical Note RADC-TR-61-231.
(") Yariv, A., Cook, J.S., "A Noise Investigation of Tunnel Diode Microwave Amplifiers," Proceed-
ings of the IRE, pp. 739-743, April 1961.
Goto, E., et al, "Esaki Diode High Speed Logical Circuits," IRE Transactions on Electronic
Computers, EC-9, p. 25, 1, March 1960.
"" Herzog, G.B., "Tunnel-Diode Balanced-Pair Switching Analysis," RCA Review, p. 187, XXIII,
No. 2, June 1962.
08) Gibson, J.J., "An Analysis of the Effects of Reactances on the Performance of the Tunnel-Diode
Balanced-Pair Logic Circuit," RCA Review, p. 457, XXIII, No. 4, December 1962.
(1, )Miller. H.S., and Powlus, R.A., "An Evaluation of Tunnel Diode Balanced Pair Logic Systems,"
RCA Review, p. 489, XXIII, No. 4, December 1962.
(50 )Axelrod, M.S., et al. "Some New High-Speed Tunnel-Diode Logic Circuits," IBM Journal, p. 158,
6, No. 2, April 1962.
(5" Bergman, R.H., et al, "High Speed Logic Circuits Using Tunnel Diodes," RCA Review, page 152,
XXIII, No. 2, June 1962.
"" Hwang, Y.C., et al, "Analysis of a Pumped Tunnel Diode Logic Circuit," IRE Transactions on
Circuit Theory, p. 233, Volume CT-9, No. 3, September 1962.
(53 >Sear, B., et al, "The Enhanced Tunnel Diode Logic Circuit," Digest of Technical Papers — 1963
International Solid States Circuits Conference.
'> Berry, D.L., and Fisch, E.A., "High Speed Tunnel Diode Memory," Digest of Technical Papers —
1961 International Solid States Circuits Conference, p. 112.
(5" Chaplin, G.B., and Thompson, P.M., "A Fast-Word Organized Tunnel-Diode Memory Using
Voltage-Mode Selection," Digest of Technical Papers — 1961 International Solid States Circuits
Conference, p. 40.
(") Cole, A.J., et al, "The Engineering of a Fast Word Organized Tunnel Diode Store," Digest of
Technical Papers — 1962 International Solid States Circuits Conference, p. 40.
"" Schindler, H.R., "UHF Analog Digital Converter," Digest of Technical Papers — 1963 Inter-
national Solid States Circuits Conference.
(7" Bush, E.G., "A Tunnel Diode Counter for Satellite Applications," NASA Technical Note D-1337,
June 1962.
00 > Sylvan, T.P., "Tunnel Diode Slide-Back Sensing Circuits," Electronic Equipment Engineering,
p. 60-64, September 1963.

NOTES

374
 15
cc
EXPERIMENTERS e.
CIRCUITS

.05f
200011
2N107 HEAD
AUDIO PHONES
INPUT

SIMPLE AUDIO AMPLIFIER

Figure 15.1

+ I.5V

3.3K

470K 201.dd

20,.‘fd
2N27Il
2N27I2
MIC INPUT °—I OUTPUT
2N2926
1500

LOW IMPEDANCE MICROPHONE PREAMPLIFIER

Figure 15.2

Ip.fd (3V) 2N107

2000fi

I
O
INPUT + - HEAD
PHONES
2211
3.0V

NOTE: ADJUST R FOR OPTIMUM RESULTS

DIRECT COUPLED "BATTERY SAVER" AMPLIFIER

Figure 15.3

375
 15
33K

EXPERIMENTERS CIRCUITS
47K 2NI415
220K
150K

72

10K
• o

TO SPEAKER
_to

CRYSTAL
CARTRIDGE
SW

6V 6V

-r
-+
RI - BASS CONTROL - 50K LINEAR TAPER
R2 - TREBLE CONTROL - 50K LINEAR TAPER
PERFORMANCE DATA
R3 - VOLUME CONTROL - 10K AUDIO TAPER
T1 - DRIVER TRANSFORMER -PRI 2K/SEC 1.5K C.T. MAX POWER OUT
T2 - OUTPUT TRANSFORMER-PRI 10012/SEC V.C.(3.2,8,1611 MW 300
Q 10% DIST
NOTE: ALL RESISTORS 1/2 WATT
DISTORTION 60 CYCLES -3.0%
0100 MW 1.0 KC - 1.5%
5.0 KC - 3.0 %

SIX VOLT PHONO AMPLIFIER

Figure 15.4
 CRYSTAL
CARTRIDGE INPUT

EXPERIMENTERS CIRCUITS
FREOUENCY RESPONSE RI - VOLUME CONTROL-5K AUDIO TAPER PERFORMANCE
OF FOUR TRANSISTOR AMPLIFIER R2 - TONE CONTROL-25K LINEAR TAPER
MAX POWER
MAXIMUM BASS POSITION TI- DRIVER TRANSFORMER
OUTIP 10% DIST 400 MW
MAXIMUM TREBLE POSITION ------ PRI. 5K/SEC. 3K, C.T.

+5 T2 - OUTPUT TRANSFORMER
DISTORTION 100 CYCLES -5%
------ PRI. 20012 C.T./SEC. (3.2,I3,16n)
0100 MW 1KC -2%
O NOTE ALL RESISTORS 1/2 WATT 5KC -5%

db 5

10

-15
10 10 2 10 3 10 4

AMPLIFIER LOADED WITH 3.211 VOICE

COIL- SPEAKER RESONANCE @ 130 CPS

15
Figure 15.5 NINE VOLT PHONO AMPLIFIER
15 EXPERIMENTERS CIRCUITS

1.5 V

CODE PRACTICE OSCILLATOR

Figure 15.6

SW 1 8201-2. VOLUME

KEY
SOK

— 45V 25K
TONE 100

2N2I60 UNIJUNCTION

SW 2

3 .01/..cfd

° PHONES

TO 01 p.f d
loo 0 1SPKR
8-16S1
TO 100 ,
a
TO SPKR
RESISTOR
POS. IPHONES
POS.2 PHONES-SPEAKER
POS.3 SPEAKER

P-S

WIRING DETAILS OF SW 2 (BACK VIEW)

(MALLORY TYPE 3I23J)

UNIJUNCTION TRANSISTOR CODE PRACTICE OSCILLATOR

Figure 15.7

378
 EXPERIMENTERS CIRCUITS 15

NOTES:
RATE-ADJUSTABLE FROM 40(LOW LARGO) TO 220(HIGH PRESTO) BEATS PER MINUTE
RI -ADJUSTS HIGH RATE LIMIT 20K
R2-ADJUSTS LOW RATE LIMIT
R3-IRC TYPE 013-328
POTENTIOMETER (LOG TAPER)
22 1/2V
SPKR-UTAH MODEL SP358 3.4 2 V.C.
SIZE 31/2' MAGNET IOZ
(HOWEVER, ANY SPEAKER
CAN BE USED).

I2K
r«,A.A.e-Cflp
SW 25VDC
120V 4:1) NOMINAL
60rb
APPROX. 4MA

UNIJUNCTION TRANSISTOR METRONOME

Figure 15.8

22K

METRONOME
Figure 15.9

379
15 EXPERIMENTERS CIRCUITS

FRONT SIDE BACK

DOOR DOOR DOOR

1p,fd
REMOTE SPEAKERS
25V

UNIJUNCTION HOME SIGNAL SYSTEM

Figure 15.10

10-20V
METER 0-.5 MA 330
CALIBRATED 3900 IW
eoo
0-6000 RPM
5E29,2N2647
OR 2N493
2N2926 UNIJUNCTION INI769 OR
3300 1000 2500 GE-4JZ9 X 82B
E
8V NO. OF
CYLINDERS
4 6 8

TO CI IN » fd FOR 2 33 22 .15
POINTS CYCLE ENGINE

CI IN » fcl FOR 4
.33 .68 47
CYCLE ENGINE
NOTE: WITH 6 VOLT NEGATIVE GROUND
SYSTEMS USE SEPARATE 6 VOLT DRY
CELL IN SERIES WITH AUTO BATTERY
OR USE SEPARATE 12 VOLT DRY BATTERY

GENERAL AUTOMOTIVE IGNITION INFORMATION

TWO CYCLE FOUR CYCLE

4 CYL. 6 CYL. 8 CYL. 4 CYL. 6 CYL. 8 CYL.

SPARKS/REV, 4 6 a 2 3 4
SPARKS/SEC. AT 600 RPM 40 60 80 20 30 40
TIME/SPARK AT 600 RPM 25 MS 16.7 12.5 50 33.3 25
SPARK/SEC AT 6000 RPM 400 600 800 200 300 400
TIME/SPARK AT 6000 RPM 2.5 MS 1.67 1.25 5.0 3.33 2.5
CAMSHAFT SPEED TO EQUAL EQUAL EQUAL HALF HALF HALF
CRANKSHAFT SPEED
CAM DEGREES/SPARK 90° 60° 45° 900 60° 45°
CRANK DEGREES/SPARK 90° 60° 45 0 180° 120° 90°

ULTRA-LINEAR HIGH PRECISION TACHOMETER

(For Automotive Type Ignition Systems with 12 Volt Negative Ground)

Figure 15.11

380
 EXPERIMENTERS CIRCUITS 15

+I2V
° (AUTO FRAME)

330
4.7K
T
150 MFD
25V

+ 5MFD
0.33
2N2I60 50V
- 25V

AMPLIFIER
2N32I

330
6.2K SPKR

5MFD
25V

50V
1N4009 IN4009
NOTE: "RIGHT"
0 "RIGHT"
AND "LEFT"-I2V -I2V
TAPPED OFF FROM RIGHT
AND LEFT FLASHER o 'LEFT"
LIGHTS ON AUTO DASH -I2V
BOARD. DIODES PREVENT
SHORT CIRCUIT. (A)

0 "LEFT"
+I2V

330 "RIGHT"
° +I2V

YIN4009

AMPLIFIER
2N32I 50MFD

= 25V
330

2N2 160
-1-50V
e o -I2V
-I2V (AUTO FRAME)
(B)
NOTE: "RIGHT" AND
"LEFT"+12V TAPPED OFF
FROM RIGHT AND LEFT FLASHER
LIGHTS ON AUTO DASHBOARD.
DIODES PREVENT SHORT CIRCUIT.

AUDIBLE AUTO SIGNAL MINDER

(Not Adaptable to 6.0 Volt Operation)

Figure 15.12

381
15 EXPERIMENTERS CIRCUITS

R-F COUPLING
COIL
2-3
1TURNS

.01 .01 .01

TO TO TO
81

ONES
SPEAKER
PHONES

CLOSED CIRCUIT
PHONE JACK

UNIJUNCTION CW MONITOR
Figure 15.13

100K
OUT
LI

SHARP
L.
FRONT
W AVE

OUTPUT

LI - 450 MHY SLUG

TUNED COIL
0.6 AT IKC
OC RES 480II

1 KC OSCILLATOR
Figure 15.14

PUSH SWITCH
3.3K
0-31 . 9%,

1MA

/
470K .01
'WS OUTPUT
2N27I2 OR
2N2926
500 pfd IN4009

10K

500pfd- CRYSTAL
100 KC
T

CRYSTAL JAMES KNIGHT CO TYPE H-93 OR EQUIVALENT

100 KC CRYSTAL STANDARD

Figure 15.15

382
 EXPERIMENTERS CIRCUITS 15

10 V(ó) 2.0 MA
TO
30 V a 5.0MA.

47K

CRYSTAL JAMES KNIGHT CO. TYPE H-93

UNIJUNCTION 100 KC CRYSTAL STANDARD

Figure 15.16

1N34A
OR
1N64
MILLER 2000.D
LOOP II HEAD
STICK II PHONES
#6300
OR
EQUIV.

ONE TRANSISTOR RECEIVER

(AM Broadcast Band)

Figure 15.17

2N107
T1
2K
2N107
5
111' 10µf
PHONES
o
MILLER kMEG -
LOOP
STICK 365 pf 100I<
*6300 3V
OR
EQUIV.

TI -PRI 200K11
SEC IK
ARGONNE
AR100 OR
EQUIVALENT
3V SW

TWO TRANSISTOR RECEIVER

(AM Broadcast Band)

Figure 15.18

383
15 EXPERIMENTERS CIRCUITS

FERRITE CORE
ANTENNA
232 µ h

3650

Figure 15.19 THREE TRANSISTOR RECEIVER (AM Broadcast Band)

EXTERNAL ANTENNA
MAY BE CONNECTED
IN MANNER SHOWN
,-, DOT TED

CI - 2 GANG CAPACITOR LI - LOOPSTICK MILLER

BOTH SECTIONS 100- CAT NO 2000, OR
3650 MILLER CAT. NO. EQUIVALENT
2112, OR EQUIVALENT
L2 -ADJUSTABLE 220µ. H-275µ H
MILLER PART NO.42A224
CBI, OR EQUIVALENT

Figure 15.20 AM BROADCAST BAND TUNER

4711
ANTENNA

1470K

2N2926

BUILD RECE VER TO THIS POINT IF I FOR RELAY OPERATION IN REMOTE CONTROL
ONLY SPEECH RECEPTION IS DESIRED1 APPLICATIONS ADD THIS RELAY CIRCUIT

LI - 15 TURNS *24 AWG TAPPED AT 6 TURNS, PROPORTIONED AS SHOWN 6 TURNS/9 TURNS ON CTC *SPCI I-4L
(CAMBRIDGE THERMIONICS CORPORATION I
L2- 180 TURNS AWG ON FERROXCUBE 1408 -FID BOBBIN, IN 1408- P100 -385 CUPCORE, HELD BY 1408 BRACKET
ASSEMBLY. (FERROXCUBE CORPORATION OF AMERICA, SAUGERTIES, NEW YORK 1
RELAY- OMEGA SALES HR300 REED RELAY
RFC - 22µHENRY DELAVAN TYPE *1537-44 (DELAVAN ELECTRIC CORPORATION, 270 QUAKER ROAD, EAST
AURORA, NEW YORK

SUPERREGENERATIVE 27 MC RECEIVER
Figure 15.21

384
 0(» (1620 100pa I/I5V
30011
1 0047#1 FEED y 1N34A
1N679 LINE
L2
4 - 0047f
10-1 04 2NI121

TD-9 N404 T .
01µ1

S111131113 SllaINI3INIII3dXa IMMIIIIIIIIMIIIIMIMI

1/2MA TD

2.7K
K .1,Lf

200 10K
2.4K .22µf
33« AUDIO
TAPER
33pf 470p

AFC
10K LIMITER DEMODULATOR AUDIO

CONVERTER OSCILLATES 1ST I.F AMPLIFIER 2ND IF AMPLIFIER

AT ONE-HALF SIGNAL 200KC/S 200KC/S
FREQUENCY i CENTER FREQUENCY CENTER FREQUENCY
1N1692 4 200µf /15V

1012 200,1.1/15V

NOTEI DOTTED LINES INDICATE SUGGESTED MODULAR BREAKDOWN

II7V 60 C/S t6.3V R M.S.
LI - 4 TURNS #I8 3/8" I.D., APPROX, 1/2" LONG
L2 - 4 TURNS #18 3/8" ID., APPROX. V2" LONG
(LI A L2 COUPLED END TO END, SPACED APPROX. 1/13") INI692
L3 - 8 1/2 TURNS 018 3/8" I.D. CENTER TAPPED, APPROX. 3/4" LONG STANCOR
P-6465

POWER -SUPPLY— 12 VOLTS

FM BROADCAST BAND TUNER

(88 to 108 MC)

si
Figure 15.22
 15 EXPERIMENTERS CIRCUITS

.001 L3

670 KC I ANTENNA
CRYSTAL= 2Nl7O 3001 LI
T .00: T ool
Pf

150K
AUDIO INPUT
IV RMS FOR 00% MOD.

6V -I-. I I0»fd
LI,L3- 40-300µhy FERRITE CORE
ANTENNA (J.W. MILLER TYPE 2002)
iov CHASSIS
O GROUND
L2 -8 TURNS *22 WIRE WRAPPED AROUND
BOTTOM LI

Courtusy Electronics World

LOW POWER AM BROADCAST BAND TRANSMITTER
(670 Kc Crystal Controlled-400 Microwatts)

Figure 15.23

CI 5-I5pf BANDSPREAD VARIABLE LI 57T B &W NO. 3016

C2 5-55pf BANDSET VARIABLE L2 35T MINI -DUCTOR COILS
C3 6-80pf FINAL TUNING VARIABLE I" DIA 32T/INCH

LOW POWER VFO CW TRANSMITTER

(80 Meter Amateur Band—I00 Milliwatts)

Figure 15.24

386
 EXPERIMENTERS CIRCUITS 15

EVEREADY
e 724 OR
EQUIVALENT 6V
(SEE FIG 15.29)

PNP TEST SOCKET

TERMINAL
STRIP (MOUNT 680
ON METER) I/2W10% G.E. METER
TYPE DC-9I
/ 21 2 3 • 0-3 MA
OR EQUIVALENT

GAIN
SWITCH CRAFT *1004 200K
I/2W 200K
PUSH BUTTON SWITCH
5% I/2W 5%

oo
ó kb

LEAKAGE

METER SCALE
NPN TEST SOCKET

INSTRUCTIONS FOR TRANSISTOR TEST SET

BATTERY CHECK: INSERT 560 OHM RESISTOR BETWEEN E AND C (EITHER SOCKET). IF METER
DOES NOT READ FULL SCALE, REPLACE BATTERY (EVEREADY TYPE 724 OR
EQUIVALENT)
LEAKAGE TEST: INSERT TRANSISTOR IN APPROPRIATE SOCKET. METER READING INDICATES
CONDITION WITH RESPECT TO LEAKAGE.
GAIN TEST. DEPRESS GAIN BUTTON AND NOTE INCREASE IN METER DEFLECTION. AN IN-
CREASED DEFLECTION TO THE RIGHT EQUAL TO AT LEAST ONE DIVISION ON THE
GAIN SCALE COMPARED TO THE DEFLECTION DURING LEAKAGE TEST INDICATES
ACCEPTABLE CURRENT GAIN.
OPENS AND SHORTS TEST,. A SHORTED TRANSISTOR WILL BE INDICATED BY A FULL SCALE
METER DEFLECTION IN LEAKAGE TEST. AN OPEN TRANSISTOR WILL BE INDI-
CATED BY NO METER DEFLECTION IN BOTH LEAKAGE AND GAIN TESTS.

TRANSISTOR TEST SET

Figure 15.25

387
15 EXPERIMENTERS CIRCUITS

1.2 K PUSH TO READ

=IL
S3

I +
6V

L J
NPN PNP

TEST GE IN 169
40 SOCKET
50 I
4.7 K

7. I R2
IK

PARTS
SI -3 POLE 6 POSITION NON -SHORTING S3- S4 NORMALLY OPEN PUSH
SELECTOR SWITCH SWITCHES
M -100, A FULL SCALE METER
S2-4 POLE 2 POSITION SWITCH
METER S INTERNAL RESISTANCE

ADJUST
TO SELECTOR
WHEN RESULT
TEST SWITCH SI
TO POSITION

I co VcE, = 6V I READ METER DIRECT

I, 16 = 20 0 A 2 READ METER DIRECT
IC IB =100 µ A 3 READ METER DIRECT
'CEO VcE= 6V 4 READ METER DIRECT
ICES VCE= 6V 5 READ METER DIRECT
/ES VES = 6V 6 READ METER DIRECT

CALCULATE :
Ic METER READING
FE I, =20 µ A 2
h h FE - 1. - 20µ A

CALCULATE :
IC METER READING
hFE IB =100µ A 3
h FE - I, - 100µ A

CALCULATE : WHERE :

lc, 'CO ic, = METER READING

11 1, I,=20 µ A 2 hie
4X 106 Ic2 =
- METER READING
WITH S4 CLOSED

CALCULATE

hie 4.100µ A 3 h1. - IC, - IC2

20 X10 -6

WITH 150 0 RESISTOR CONNECTED TO

6V. C-E OF TEST SOCKET,FULL -SCALE METER
4
BATTERY DEFLECTION WILL RESULT WHEN S3
IS PRESSED .

TRANSISTOR TESTER
Figure 15.26

388
 EXPERIMENTERS CIRCUITS 15

TRANSISTOR TESTER SHOWING READOUT CHART

Figure 15.27

INTERNAL VIEW OF TRANSISTOR TESTER

Figure 15.28

389
 15 EXPERIMENTERS CIRCUITS

The 100 pa meter is in anetwork which results in a nearly linear scale to 20ga,
ahighly compressed scale from 20 pa to 1ma and anearly linear scale to full scale at
10 ma as shown in the photograph. The network permits reading leo, IEO, ICES, and I EE0
to within 10% on all transistors from mesas to power alloys without switching meter
ranges or danger to the meter movement.
By making RE-I- R1 equal to 12K the scale will be compressed only 1pa at 20 pa.
Potentiometer R2 should be adjusted to give 10 ma full scale deflection. The scale can
then be calibrated by comparison with a standard conventional meter. By placing
selector switch in position 4 and connecting a second meter and a decade box in
series with C-E of test socket both meters will track.
If the NPN-PNP switch is in the wrong position, the collector and emitter junctions
will be forward biased during the I F.) and I
RO tests respectively. The high resulting cur-
rent can be used as acheck for open or intermittent connections within the transistor.
The test set also measures hFE with 20 pa and 100 pa base current. Depressing the
hr. button decreases the base drive 20% permitting hr, to be estimated from the cor-
responding change in collector current. The tests are done with a 330 ohm resistor
limiting the collector current to approximately 12 ma and maximum transistor dissipa-
tion to approximately 20 mw. Therefore, this test set can not harm atransistor regard-
less of how it is plugged in or how the switches are set.
"Battery test" has been designed to give full scale meter deflection of 10 ma when
the battery voltage is 6volts. This is achieved by connecting 150 ohms from C to E
of the test socket. This test assumes precision resistors.

120 A
TI IN1692 2W
II7V NEON
60'. PANEL
LIGHT I5V
6.2V REG.
100µfd
ZENER DIODE-GE 4J24 X6.2B ZENER1
isv
DIODE 4,
71- STANCOR P-6465
(117V PRI -6 3V, .64 SEC)

REGULATED POWER SUPPLY

(For Use With Fig. 15.25 & Fig. 15.26 Testers)

Figure 15.29

NOTES

390
SILICON CONTROLLED 16
SWITCHES

Part 1— Understanding PNPN Devices

INTRODUCTION
The silicon controlled switch, SCS, is a PNPN structure with all four semicon-
ductor regions accessible, rather than only three as is customary with silicon controlled
rectifiers( SCR ).• Accessibility of the fourth region greatly expands circuit possibilities
beyond those of conventional transistors or SCR's.
In fact, the wide usage of the SCS since its introduction two years ago has war-
ranted the development and introduction of new types based on planar technology.
The reasons for its wide acceptance are varied.
To some, it is an integrated circuit consisting of aPNP and an NPN transistor in a
positive feedback configuration. As such, it offers fewer connections, few parts, lower
cost, and better characterization than is available from two separate transistors. To
others it is an SCR with an "extra lead" by which they can completely eliminate rate
effect problems. Some prefer to use it as a complementary SCR being triggered by
negative going pulses. Many find the high triggering sensitivity ideal for timing and
level sensing applications. By viewing the SCS as a transistor with an additional
"latching" junction, some have developed very useful bistable circuits with high
turn-on and turn-off gains.
Underlying these technical values are the inherent high temperature capabilities
of silicon, the ruggedness and reliability of a design for military usage, and the low
cost due to existing high volume transistor facilities which proved readily adaptable
to SCS manufacture.
This chapter cannot cover fully the wealth of device and application data avail-
able. Instead it endeavors to give the circuit designer a"feel" for the SCS so that he
can quickly design and evaluate circuits. To this end the construction techniques
and the characteristics resulting from them will be discussed. Qualitative equivalent
circuits will be derived from several points of view. Circuits for measuring SCS char-
acteristics will be suggested. "Rules of thumb" to speed circuit design are included,
but detailed device characteristics are not included since these are found on the
specification sheets. Finally, groups of circuit configurations are shown to illustrate
how the SCS can be used.
For a device to be useful it must be understood. In turn, the more versatile a
device is, the harder it is to thoroughly understand but the greater the rewards once
the effort is made. As in the early days of transistors, PNPN devices are still primarily
discussed in terms of mathematical models to advance device design. These, however,
do not give a circuit designer an easy intuitive familiarity with the device that he
needs. The following discussion derives PNPN characteristics from currently well-
understood transistor behavior.

THE EQUIVALENT CIRCUIT

Converting the PNPN into familiar equivalent circuits aids in understanding it.
Figure 16.1 shows a variety of symbols and equivalent circuits appropriate to
PNPN's. The basic structure in Figure 16.1(A) can be considered an NPN transistor
with adiode in series with the collector as shown in Figure 16.1(B). By grouping the
*See Reference 4 at end of Chapter 1.

391
16 SILICON CONTROLLED SWITCHES

(A) (
B) (
C) (D)

(E)

(F)

(G) (H) (I) (J) (K)

SYMBOLS AND EQUIVALENT CIRCUITS

Figure 16.1

top three regions together the device resembles a PNP transistor with a series diode
as shown in Figure 16.1(C). Neither of the circuits suggests the regeneration inherent
in aPNPN, and thus the two transistor circuit as shown in Figure 16.1(D) is a more
accurate representation. To these transistors we can add the R., rb' and Cob para-
sitics, Figure 16.1(E), which are inherent in all semiconductors. This circuit in turn
leads to a distributed circuit of several transistor pairs joined by the sheet resistance
of each semiconductor layer. While this final complex circuit is most versatile, it gen-
erally can be avoided. The common SCR symbols in Figures 16.1(G) and 16.1(H)
ignore the central N-region; the Shockley diode in Figure 16.1(1) has leads to the
outside regions only; while the silicon controlled switch in Figures 16.1(J) and
16.1(K) has leads to all four regions. The best choice of equivalent circuit depends
on the specific parameters of interest and the geometry of the device.

PNPN GEOMETRY
The details of the PNPN geometry determine which elements of an equivalent
circuit are significant. The sectional view in Figure 16.2(A) leaves little area for

392
 SILICON CONTROLLED SWITCHES 16

4 ANODE 4 ANODE

GATE 2 ICATHODE

(A) (B)

(I) 2 IRING GATE 2 ICATHODE

GATE CATHODE
(D)
(C)

CATHODE
GATE
ANODE 4 2 ICATHODE
(4)

ANODE 4
3
ANODE
GATE

CATHODE 2
GATE

3 ANODE
GATE

(F)

SECTIONAL VIEWS OF PNPN GEOMETRIES

Figure 16.2

connections to the central junctions, therefore is only suitable for a four layer diode.
Its equivalent circuits can ignore re,' but must include Cob and the collector breakdown
voltage since the latter two determine the maximum blocking voltage under transient
and dc conditions, respectively. Figures 16.2(B) and 16.2(C) show common SCR
structures which add an N-region to aPNP transistor. The gate lead can be attached
at one side (Figure 16.2(B)) or in ahole at the center of the N-region (Figure 16.2(C)).
A planar SCR version is shown in Figure 16.2(D). The anode region can be
brought out to the surface along with the other regions by a number of different
processes. The silicon controlled switch series 3N58, 3N59, and 3N60 has the structure
as shown in Figure 16.2(E). It is basically an NPN transistor to which has been
added an additional P-junction so located that a PNP transistor is formed. A new
planar SCS structure is shown in Figure 16.2(F). It is also basically an NPN transistor
surrounded by a P diffused ring to form a PNP transistor across the surface. Since
the P-base and P ring-anode can be diffused simultaneously this structure is no more
difficult or costly to manufacture than aplanar transistor. Yet it makes all four layers
readily accessible to leads and concentrates the current near the surface where cooling
by radiation is optimum, while enjoying the parameter stability inherent in oxide

393
16 SILICON CONTROLLED SWITCHES

passivated planar structures. As can be expected, such varied geometries yield equiva-
lent circuits which quantitatively are quite different.

BIASING VOLTAGES
The simplest equivalent circuit, shown in Figures 16.1(B) and 16.3(A) shows
how the biases on all regions are interrelated.

VBE

VSAT VD > VBE > VSAT

BLOCKING REVERSE PNPN
BIAS BIAS CONDUCTING
(A)
(B) (C) (0)

PNPN BIASING

Figure 16.3

To start with, NPN transistor action can only occur if the collector is positive with
respect to the emitter. This is illustrated in Figure 16.3(B). Referring to Figure
16.3(A), if current is to flow through the anode (4), it in turn must be positive
with respect to the collector. When the anode is returned to a positive voltage, col-
lector current is controlled by the base (2). Reverse biasing the emitter junction
keeps the transistor cut off. The voltage across the PNPN is sustained across the
collector-to-base junction. This description shows that the center junction breakdown
determines the maximum blocking voltage, which is defined as the maximum permis-
sible positive anode voltage. Generally the emitter junction has a low voltage break-
down to enhance emitter efficiency and therefore beta. If the anode is returned to a
negative voltage the diode becomes reverse biased and the transistor's emitter and
collector interchange roles (Figure 16.3(C)). The maximum reverse voltage, i.e.
the maximum negative anode voltage that can be applied is limited to the diode break-
down voltage plus the breakdown voltage of the inverted transistor. The latter is the
transistor's emitter breakdown voltage. The common manufacturing processes result
in the collector and diode breakdowns being equal and in the emitter breakdown
being much lower. Therefore PNPN specifications show equal blocking and reverse
ratings.
This equivalent circuit provides further insight. If the emitter junction is reverse
biased the collector, or anode, cannot conduct as long as the collector junction break-
down is not exceeded. In lieu of reverse biasing, the base can also be left disconnected
or connected to the emitter through aresistor or ashort. This leads to lower collector
breakdown corresponding to BVeleo, BVcEit, and BVcEs, respectively.
To turn the PNPN on the base is forward biased, the base current increasing about
ten fold for each 0.1 volt increase in base voltage. This is true until regeneration
occurs as will be shown later. Once the PNPN is on, it is seen that the collector and
anode differ in potential only by the diode forward voltage.
The above discussion, based on the equivalent circuit of Figure 16.1(B), applies
equally well to the circuit of Figure 16.1(C) if polarities appropriate to the PNP

394
 SILICON CONTROLLED SWITCHES 16
transistor are substituted. In this case, however, the PNP emitter breakdown is equal
to the collector breakdown while the diode breakdown is less than 15 volts. This
results in the blocking voltage being substantially higher than the reverse voltage.

BASIC TWO TRANSISTOR EQUIVALENT CIRCUIT

PNPN devices designed for very high holding currents or for gate turn-off resemble
the transistor-diode circuit in Figure 16.3(B) at low currents. In general, however,
the PNPN is important because it behaves like two complementary transistors in a
regenerative feedback configuration.

aNpN(I8 -1- I(

(A) (B) (C) (D)

TWO TRANSISTOR EQUIVALENT CIRCUIT OF PNPN

Figure 16.4

Figure 16.4 shows how the two transistor circuit is derived. The diode in Figure
16.3 is now the emitter junction of the PNP transistor. Base current into the NPN is
multiplied by the NPN beta and becomes base current for the PNP. After being
multiplied by the PNP beta it reinforces the initial NPN base current. If the rein-
forcing current exceeds the initial base current, i.e. if (13NrN) (13pNp) ≥ 1the currents
build up regeneratively driving both transistors into saturation. Therefore the product
(13Np:4) (PrNr) is the critical factor which determines if the PNPN will switch on.
To keep the PNPN non-conducting the betas must be kept sufficiently low so that
(PsrN) (fipsr) < 1. To do this it is necessary to realize that beta (ht.) is afunction
of VCE, I C, VBE, and temperature as shown in Figure 16.5. These parameters will be
analyzed in detail in the next few paragraphs.

hf • hfe
hhe

VCE IC v
B, TEMP.

PARAMETERS CONTROLLING hr e
Figure 16.5

Beta increases as the collector junction breakdown voltage is approached, in turn

causing the collector current to increase. Therefore, raising the anode near the col-
lector breakdown voltage can trigger the device. Figure 16.6 shows asuitable equiva-
lent circuit.

395
 16 SILICON CONTROLLED SWITCHES

EQUIVALENT CIRCUIT OF PNPN TRIGGERED BY

COLLECTOR BREAKDOWN
Figure 16.6

Figure 16.7 plots le as afunction of In, VBE, and I c for atypical silicon transistor.

When the base is reverse biased I Bis very nearly loc.. When open circuited the base
will float at apotential of about 0.5 volt and the collector current will rise as leo takes
on the role of base current. The slope of the curve, by definition he., continues to
increase until reduced emitter efficiency reverses it.

100 —

ID 10 —
IN ma CHANGE
I— OF SCALE

1 —• + o I 10 100 MA
'C
1O 1 I I
1 1
I 1 I I
VBE C
SILICON I
-, 0.4 V 05 06 0.7 0.8 V
AND
UNDER

COLLECTOR CURRENT VS .le, VBE AND leo

Figure 16.7

Figure 16.7 shows that reverse biasing the base, or at least keeping it below 0.4
volt makes the base current very nearly la), and h.. very nearly zero ensuring that
(PNPN) (fipt.p) < 1. With the base forward biased between 0.4 and 0.5 volts, beta
may increase sufficiently to cause triggering. Since leakage current flows out of the
base, this would be defined as triggering with anegative input current. If triggering
occurred at 0.5 volts, this corresponds to zero input current. Generally, specifications
will show the maximum forward current required to trigger.
The above discussion ignores the interaction between the two transistors, the
presence of parasitic resistors, and the impedance of the measuring instruments.
Figure 16.8 shows atypical curve tracer plot at the cathode gate of aPNPN as an ac
voltage is applied to it. Starting at point A the device is blocking and Ice is being
diverted by the base. As the base becomes forward biased, base current may increase
as would be expected for anormal transistor. The device triggers on when point B is

396
 SILICON CONTROLLED SWITCHES 16

GATE
CURRENT

GATE VOLTAGE -4.

4- NEGATIVE ( E (POSITIVE)

_——

CATHODE GATE (NPN BASE) CHARACTERISTICS

Figure 16.8

reached. Immediately the base voltage jumps to point C and traces out curve C D E
F G. From Eto F current is being pulled out of the base tending to turn off the device.
If the anode current is low enough, the device turns off at point G, rapidly returning
to point A to complete the cycle.
If the curve tracer source impedance is low, it acts as a shunt for the feedback
current from the PNP collector. This permits the loop gain to approach unity very
closely yet not trigger the PNPN. This is illustrated by the negative current leading
to B', where switching occurs. The point B' may lie above or below the axis for
different devices.
If the anode current is too large to be turned off by the base (i.e. the gate) the
base is driven negative to H where it is clamped by the emitter junction zener break-
down. Curve HGED will continue to be retraced until the device is turned off
when the cycle can begin at A again.

CATHODE GATE EQUIVALENT CIRCUIT

Figure 16.9

397
 16 SILICON CONTROLLED SWITCHES

This locus can be interpreted using the equivalent circuit of Figure 16.9. The
base resistance is shown in two portions to better represent its distributed nature. The
zener represents the .emitter junction breakdown voltage. At point A of Figure 16.8,
IRis only 'Co as the zener and NPN transistor are both cut off and PNP beta is gen-
erally very low. At point B the product of betas results in triggering. The load current
I. now divides into IA' and I Al. L., causes the base voltage to increase to C. The ampli-
tude of the jump is proportional to I A. Vui continues to rise to D as the ac source
supplies more current. Since the base resistance is modulated downward when the
PNPN is on, ri, and ri,' decrease as current is increased.
As the ac source drops in voltage, L is partially diverted into the source via n, in
the region E to F of Figure 16.8. In this case rb is modulated upward becoming a
much higher impedance. At G enough of L has been diverted that the NPN transistor
cannot stay in saturation and turn-off begins. It is obvious that if the device did not
turn off the zener clamps the negative excursion of the base with rb determining the
maximum base current.
Now if R source is zero and n, is also low it is seen that the shunting effect on the
feedback current is much greater resulting in the locus to B.
Qualitatively the same curves are seen when the triggering input is to the base
of the PNP. Since rb and ri,' are much lower the jump from B to C is smaller. Since
the PNP emitter breakdown voltage is much higher than the NPN emitter breakdown,
much higher anode currents can be turned off.

RATE EFFECT

CATHODE
GATE

(A) (B) (C)

RATE EFFECT EQUIVALENT CIRCUIT

Figure 16.10

PNPN devices may be triggered on if anode voltage is applied suddenly or if

they are subjected to high frequency transients. This phenomenon, called rate effect,
is readily explained by the equivalent circuit of Figure 16.10. Figure 16.6 shows how
the zener breakdown of the center junction supplies the base currents necessary to
trigger the PNPN. For high frequencies, the Cob capacitance of Figure 16.10(A) is a
low impedance resulting in substantial base currents and triggering. The base currents
are I» = C„b dV/dt where V is the increasing anode voltage. The equivalent circuit
in Figure 16.10(B) suggest ways of suppressing rate effect. By shorting the cathode
gate to cathode rb, diverts the Cob charging current, preventing its forward biasing
the NPN transistor. Similarly the anode gate can be shorted to the anode to advantage.
If it is desired to maintain de triggering sensitivity, the shorts may be capacitors.
Reverse biasing a gate will only be effective if a low impedance bias source is used.
Again, acapacitor can be used to generate the low impedance.

398
 SILICON CONTROLLED SWITCHES 16

A far more elegant solution is shown in Figure 16.10(C). While the anode is
reverse biased (the switch closed) Cob charges up via the collector resistor. The
switch may now be opened as rapidly as desired.
It is obvious that if a highly rate sensitive device is required, for example, for
detecting transients, the addition of an interbase capacitor creates one by effectively in-
creasing C.b. Appropriate circuitry for minimizing rate effect is shown in Figure 16.20.

FORWARD CONDUCTING VOLTAGE

The anode-to-cathode voltage during conduction, i.e. the forward voltage, can be
evaluated using the equivalent circuit of Figure 16.11. The resistors rb2 and rb3 can be
considered as base or collector resistors, but since they carry minor carriers they are
strongly modulated and are much lower in resistance than their doping level and
geometry would predict. The currents IAi and IA2 are determined by the transistor
betas as well as by rb2 and rbs.

I
IA

i
IA Iv / 0
-
SAT PNP VBE PNP
t \
!BE
....... PNP 'AI I
VSAT PNP 1 \ rb3 rb4
'12 e r
b3

'Ai
42 1
,
11 VBE NPN T VSAT NPN

) VSAT NPN
rbl rb2
VII E
....s.'
1
NPN

FORWARD CONDUCTING VOLTAGE EQUIVALENT CIRCUIT

Figure 16.11

Forward voltage does not change much with temperature. At high temperatures
the resistors increase while W IT and VBE decrease. At low temperatures the resistors
decrease while VSAT and VBE increase to compensate.

HOLDING CURRENT AND VALLEY POINT

As IA is reduced the transistors are forced to operate in their low current, low beta
region. Eventually the betas become so low that (OBEs) (PENE) < 1and the PNPN
switches off.

i
IA

Ij VALLEY

'HOLDING

I
VALLEY --.> VF

HOLDING CURRENT AND VALLEY POINT

Figure 16.12

399
 16 SILICON CONTROLLED SWITCHES

Figure 16.12 shows a typical forward characteristic. The devices start to turn off
at the valley point i.e. where the forward voltage is lowest. But as the anode voltage
rises, the transistors come out of saturation raising beta, and the PNPN remains con-
ducting. At the holding current increasing voltage cannot raise beta enough and the
device switches off. If the gates are left open in the equivalent circuit of Figure 16.11,
loop gain is high; the valley current and holding current are very low and nearly
equal. If, however, the cathode gate is shorted to the cathode, rbi will divert part of
IA2 lowering loop gain, and raising both the valley current and holding current. These
currents now are separated considerably since the valley point is reached while the
transistor betas are high. As aresult of the high betas aslight change in anode voltage
can change the ratio of I A, to I
A, to sustain conduction.
It is important to differentiate betvireen holding current and valley current. If the
anode, while at the valley point, sees an ac short circuit load i.e., a capacitive load,
the device will turn off. The reason for this is thoroughly developed for applications
based on the unijunction" transistor and will not be discussed here. With a resistive
load, however, the PNPN will conduct until the holding current is reached. Where
the load characteristics are uncertain, the anode current should exceed the valley
point current to assure conduction.

TRANSIENT RESPONSE TIME

Figure 16.4 indicates how an input base current is amplified by both transistors
and fed back to the input. Each transistor introduces a delay which depends on its
frequency response (f or fr) and the input current. Once regeneration starts, how-
ever, the "input current" is only limited by the maximum anode current and the
PNPN turns on rapidly.
Two limiting cases are of interest. If the input current is small, there is substantial
delay followed by arapid turn-on. With large inputs and low anode currents the NPN
transistor can be driven into saturation before regeneration is fully established. The
equivalent circuit resembles that in Figure 16.3(A).

RECOVERY TIME
The circuit in Figure 16.13(A) assumes the PNPN is turned off at the cathode

CATHODE
GATE

(A) (B)

Figure 16.13 RECOVERY TIME EQUIVALENT CIRCUITS

gate. This is achieved by diverting all of IA, and pulling current out of the NPN
transistor base. Following the NPN storage and fall time the PNP is deprived of
base drive and in turn stops conducting. To shorten recovery time it is seen that the
*See Chapter 13.

400
 SILICON CONTROLLED SWITCHES 16
turn-off current should be as large as possible. By not overdriving the NPN prior to
turn-off, storage-time can be shortened. In other words I A2 should be reduced or
diverted. Returning rbi to ground prior to turn-off partially diverts I
A.. An anode-to-
anode gate short would also aid recovery by reducing I A..
The turn-off input should be maintained until the anode rises to its maximum
voltage, least the PNPN retrigger due to rate effect or residual charge in the PNP
during its fall-time.
Turning off the PNPN by reverse biasing the anode requires the equivalent circuit
of Figure 16.13(B). Rapidly reverse biasing the anode causes the anode junction to
recover isolating the anode from the rest of the device which now behaves as an
NPN transistor. If its base is open, eventually the base charge will recombine and
the transistor turns off. Connecting Ili to ground or a negative bias helps turn off
the NPN more rapidly.
During recovery, there is aspike of anode reverse current while the anode junc-
tion recovers, after which the device appears to have recovered. However, once the
anode rises above ground it will conduct again unless the NPN transistor has recov-
ered. Therefore proof of recovery is the anode's ability to withstand full voltage.

BASIC CIRCUIT CONFIGURATIONS

CIRCUIT CONFIGURATIONS BASED ON NPN TRANSISTOR
Since the SCS is basically an NPN transistor with an anode junction added, circuit
configurations based on its transistor characteristics can be developed. Figure 16.14
indicates that ignoring the anode makes the SCS a conventional NPN transistor.
Current into the base (G) results in collector current through R. Connecting alarge
resistor from the supply to the anode allows regeneration which in effect raises the
NPN beta.

OUTPUT

INPUT

--s. TIME

SCS AS A VARIABLE GAIN TRANSISTOR

Figure 16.14

As the waveforms show, when the base is forward biased (above Vim )the output
current is pNPN IB. As soon as the anode-gate voltage drops anode current starts to
increase beta as indicated by the steeper turn-on towards saturation. As the transistor
begins to cut-off, the collector is not driven as hard into saturation, hence rises slightly
before turning off completely. The amount of regeneration can be varied by changing
the anode resistor. Variability from unit to unit and with temperature makes the

401
 16 SILICON CONTROLLED SWITCHES

circuit more suitable for feedback applications such as ACC rather than for fixed
gain amplifiers.

SCHMITT TRIGGER

Figure 16.15

The circuit in Figure 16.15 can be considered a PNP transistor operated common
base, driving a common collector NPN. With the variable resistor shorted out only
linear amplification occurs. As the resistor is increased regeneration makes the circuit
perform as aSchmitt trigger. The 3N58 series SCS has sufficient built-in NPN satura-
tion resistance to ensure regeneration.
RAin Figure 16.14 can be decreased sufficiently that although base drive is removed,
the feedback via RAis sufficient to keep the NPN transistor saturated. If the feedback
is not excessive the PNPN can be turned off with a negative pulse at the base as
shown in Figure 16.16(A). Alternately very little energy is required for turn-off from
the anode. This is referred to as the latching mode of operation.

(
B)
LATCHING MODE

Figure 16.16

Figure 16.16(B) shows a bistable circuit resulting from the Schmitt trigger of
Figure 16.15 when regeneration is increased. The output is in phase with the input.
The cathode gate may be left open for maximum sensitivity or connected to the
cathode for faster recovery.
Decreasing RA still further in Figure 16.14 prevents turn-off from the cathode
gate. The PNPN can now be considered to have two parallel loads isolated by the
anode junction diode. (Thus, for example, they may be returned to different voltages.)
The PNPN is switched on and off just as a conventional SCR but the load R. is not
subjected to the switching transients.

402
 SILICON CONTROLLED SWITCHES 16

Finally RAmay be used alone, and the SCS considered an SCR. In circuits oper-
ating from dc, however, rate effect is suppressed if the anode gate is returned to the
supply voltage via alarge resistor.

CIRCUIT CONFIGURATIONS USING HIGH TRIGGERING SENSITIVITY

One of the unique features of the SCS is its high triggering sensitivity. This sensi-
tivity can be used in many ways as suggested in Figure 16.17. At moderate tempera-
tures where leakage current is not excessive sensitivity permits using high triggering
source impedances with minimal loading as in Figure 16.17(A).

0 O
® O

chadt
I

Hi R
R2
R - .R2
RI. NOISE

1
,-
0 O
0

DC INPUT

, TD

STROBE o_A__A_ ..

SENSITIVITY
Figure 16.17

If anode transients as in mechanical resetting give rise to rate effect, an anode

gate resistor suppresses it as shown in Figure 16.17(B) but decreases gate sensitivity
somewhat. High sensitivity initially, allows suppressing rate effect with ample sensi-
tivity remaining.
Noise on the triggering input can be attenuated by aresistor divider as in Figure
16.17( C). If the noise is frequency sensitive a capacitor across RI attenuates only
low frequencies, while acapacitor across R2 attenuates high frequencies. High trig-
gering sensitivity allows RI and R2 to be large permitting the use of small inexpensive
capacitors to shape frequency response. Figure 16.17(D) shows an alternate circuit
for suppressing high frequency noise.
As the triggering point is approached, the PNPN becomes more sensitive to noise,
temperature, or voltage transients. The circuit in Figure 16.17(E) avoids these prob-
lems if the sensed dc input is below ground. To the dc level a precise amplitude
strobe pulse is added. The de level determines whether the strobe pulse reaches the
triggering voltage. This circuit offers ahigh input impedance over a wide tempera-
ture range.
Indicator lamps, solenoids, and relays represent aclass of loads which will operate
from ac to dc. Ac cannot be used with transistors and neither transistors nor SCR's
exhibit latching without significant circuit complexity. In Figure 16.17(F) apositive
pulse triggers the SCS on. The emitter resistor raises both the cathode and cathode

403
 16 SILICON CONTROLLED SWITCHES

gate potentials. This causes the capacitor to charge by current out of the cathode gate.
As the full wave rectified ac anode supply drops to zero the SCS turns off and the
capacitor discharges into the cathode gate. While the discharge current is still in
excess of the triggering current the anode voltage rises retriggering the SCS for the
next half cycle. Therefore, once the SCS is triggered on, it continues to retrigger
itself. To turn off the SCS a negative input pulse is used to discharge the capacitor
breaking the retriggering cycle. If desired the cathode resistor may be the load, elim-
inating one component.
By adjusting the anode to anode-gate resistance as shown in Figure 16.17(G) it
is possib?e to set the cathode gate triggering current to aprecise value. Since triggering
current is temperature sensitive this factor should be taken into consideration. Once
the SCS triggers, its temperature rises due to increased dissipation. This in turn
reduces the triggering current. In feedback control systems this phenomenon results
in abuilt-in hysteresis that eliminates erratic triggering.
While the triggering voltage level can be used as a threshold detector better
precision is possible with tunnel diodes. The SCS is useful in amplifying the low
level output as shown in Figure 16.17( H). The anode waveform can be used to reset
the tunnel diode if desired. If large anode currents are required ac coupling from
the tunnel diode will prevent leakage current from changing the tunnel diode threshold.

THRESHOLD CIRCUITS
A variety of threshold circuits are feasible offering awide range of characteristics.
Positive or negative inputs can be sensed, with either polarity output. In Figure
16.18( A ) the SCS triggers on when the anode voltage rises above approximately
VRI/R1 + R2. The threshold can be set by the resistors anywhere within the break-
over voltage rating. Since this SCS circuit resembles the unijunction transistor a
capacitor from anode to ground generates large positive pulses across the cathode
resistor.
If the anode is ignored for amoment, the rather similar circuit in Figure 16.18(B)
is really abias stabilized NPN transistor. When the anode voltage exceeds the stabilized
collector voltage the transistor saturates. The voltage divider of Figure 16.18(A)
may be replaced by a single resistor as in Figure 16.18(C) if an appropriate supply
voltage is available. The anode rising above +V triggers the SCS. Note that aresistor
must be used in series with the anode gate.
In some applications it may be preferable to apply the input to the cathode gate
as in Figure 16.18(D). The zener diode sets the threshold voltage, the diode pro-
tecting the gate from excessive current while the input is near ground. The gate resistor
is for diverting leakage.
To trigger on a negative waveform the circuit in Figure 16.18(E) can be used.
Unless the maximum cathode waveform voltage does not exceed the cathode to gate
breakdown the diode is necessary to avoid loading the input.
Where "two terminal" threshold devices are required the circuit in Figure 16.18(F)
breaks over just above the zener voltage. The zener may also be connected from anode
gate to cathode or cathode gate to anode, thus freeing one gate for control of sensi-
tivity or recovery time if desired.
Figures 16.18(G) and 16.18(H) replace the zener with a resistance divider. In
Figure 16.18(1) the SCS will allow any arbitrary de voltage across it but is made rate
sensitive by the capacitor. It therefore triggers when a "rate threshold" is exceeded.

CIRCUIT CONFIGURATIONS FOR TURNING OFF THE SCS

PNPN devices readily turn on but are much more difficult to turn off. This had
led to jokes such as: First engineer, curiously, "How long did it take that PNPN to
 SILICON CONTROLLED SWITCHES 16

+V

+V

(A) (B) (C)

(D) (E) (F)

POS
BIAS

NEG BIAS

(
G) (H)
(I)

THRESHOLD CIRCUITS
Figure 16.18

turn off?" Second engineer, frustratedly, "I don't know; I've been trying to get it off
since 9 this morning without success!" Thus it is important to consider carefully the
available means for turning off the SCS when closing acircuit configuration.
The simplest turn off is achieved by operating from ac as in Figure 16.19(A),
the SCS turning off when the anode becomes negative. Figure 16.19(B) shows full
wave rectified ac can be used provided the anode voltage drops to zero each half cycle,
i.e., provided no filtering capacitance or inductive load is used. When operating from
adc supply, the anode can be opened as in Figure 16.19(C). A resistor to the anode
gate suppressed rate effect when the switch is reclosed. Figure 16.19(D) turns off
the SCS by reverse biasing the anode when the switch is closed. The capacitor charg-
ing current through RLminimizes rate effect. Re should be as large as possible to
avoid rate effect when the switch is opened. Figure 16.19(E) uses ashunt transistor
to divert the SCS current permitting recovery. By transformer coupling the turn-off
pulse, the load may be in series with either the cathode or anode. Inductive loads can

405
16 SILICON CONTROLLED SWITCHES

'. RRE

AC SOURCE FULL WAVE ANODE OPENED CAPACITOR

RECTIFIED AC COMMUTATION
(A) (B) (
C) (D)

DC

4C

SHUNT TRANSISTOR SERIES CAPACITOR SERIES CAPACITOR CATHODE GATE

PARALLEL LOAD SERIES LOAD
(
E) PULSE
(F) (
G)
(H)

ANODE GATE ANODE PULSE

PULSE CATHODE PULSE
(J)
(
I)
(
K)
MULTIPLE TURN OFF
(L)

LOAD IN ANODE GATE AC LOAD WITH DC

(
M) FOR LATCHING
(N)

TURN-OFF METHODS
Figure 16.19

406
 SILICON CONTROLLED SWITCHES 16
be made to ring to turn off the SCS, or inductance may be added to turn off resistive
loads. Figures 16.19(F) and 16.19(G) illustrate this for high and low resistance
loads, respectively. The equations shown indicate the practical limits for RL and C.
Figures 16.19(H) and 16.19(1) indicate that the gates can be used to turn off the
SCS. The range of anode current that can be turned off and the "turn-off gain" are
quite different for the 3N58 series and the 3N80 series. Just as a positive pulse to
the anode gate turns off the SCS, anegative pulse to the anode as in Figure 16.19(J)
achieves the same result. The resistor RA is a function of RL. Moving the load into
the anode results in Figure 16.19(K). Where a number of devices are to be turned
off simultaneously a transistor can be used with the preceding circuit as shown in
Figure 16.19( L).
Often it is desirable to have the load connected to the anode gate. The anode
current to hold the device on is substantially less than the load current permitting
turn-off gain and rate effect suppression in Figure 16.19(M).
Substantial ac loads can be controlled by small turn-off inputs in the circuit of
Figure 16.19(N). The dc current exceeds the holding current to keep the SCS on,
once it is triggered. On negative half cycles the ac load disconnects preventing turn
off. While the diode is reverse biased the SCS can readily be turned off by several
of the methods above.

CIRCUIT CONFIGURATIONS FOR MINIMIZING RATE EFFECT

When a PNPN device appears to take milliseconds to recover, it is found that
while recovery in fact occurs within a few microseconds, rate effect turns the device
back on when voltage is reapplied. Figure 16.20 suggests several ways of suppressing

RESISTOR LOAD IN
RRE ADDED ANODE GATE BIAS

(B) CATHODE GATE

(Al
REVERSE BIASED
(C)

MINIMIZING RATE
EFFECT CATHODE GATE TRANSIENT TRANSIENT
REVERSE BIASED REVERSE BIAS GATE SHORT
Figure 16.20 (D) (E) (F)

407
16 SILICON CONTROLLED SWITCHES

rate effect. The simplest, in Figure 16.20(A), consists of adding an anode gate
resistor which charges the center junction capacitance while the anode is open. Figure
16.20(B) transfers the load to the anode gate so that the switch carries less current
and rate effect is eliminated. Figures 16.20(C) and 16.20(D) illustrate two methods
of reverse biasing the cathode gate to decrease rate effect. In Figure 16.20(D) the
diode in effect generates a bias voltage which may be shared by other devices, if
desired.
Often a reverse bias can be generated during the voltage transient. In Figure
16.20(E), the anode rises more slowly than the anode gate.
Loop gain can be suppressed by using acapacitor as shown in Figure 20(F). The
capacitor shorts out the anode junction on a transient basis; the shunting resistor
allowing the capacitor to discharge when the switch is open. Shorting the anode
gate to the anode can be considered avariation of this circuit.

CIRCUIT DESIGN "RULE OF THUMB"

It is often handy to be able to cheek the feasibility of acircuit at a glance. This
can be done readily with the help of afew basic ideas.
1. When the PNPN is blocking make sure the voltage ratings are not exceeded.
While blocking, there is no transistor action and the device can be considered
to be three interconnected diodes as shown in Figure 16.21. Figure 16.21 also
indicates which SCS rating determines each diode breakdown.

REVERSE
VOLTAGE
RATING
GA
BLOCKING
4"
--""-- VOLTAGE
RATING

Gc GATE TO
CATHODE
RATING

VOLTAGE RATINGS
Figure 16.21

2. The SCS cannot be turned on unless both end junctions are forward biased.
If agate is open circuited it may be considered forward biased. Generally it is
necessary to forward bias only one junction, the second becoming forward
biased by the resulting transistor action.
3. Consider power supply and noise transients which may cause inadvertent
triggering.
4. Check the circuit for rate effect. Be sure the gates are shunted or reverse
biased while the anode voltage is rising. Generally, it is sufficient to control
one gate only.
5. The effects of capacitors connected from anode to cathode must be carefully
evaluated since extremely high peak currents and consequent high junction
temperatures may result. The junction thermal mass and transient thermal
resistance allow calculation of the maximum junction temperature.
6. A simple but useful equivalent circuit of the SCS while conducting is shown
in Figure 16.22. Using the cathode as a reference, the anode appears as an
approximate 1 volt battery with an ohmic series resistance. The anode gate

408
 SILICON CONTROLLED SWITCHES 16
can be considered the collector of a saturated NPN transistor. The saturation
offset voltage can generally be ignored and the saturation resistance is modu-
lated over about a 2:1 range, inversely with anode current. The cathode gate
or base of the NPN exhibits the conventional VBE (SAT) of asaturated transistor.
The variable resistor represents re', which is modulated over a range of 10:1
by the magnitude and direction of gate current. The zener, i.e., emitter-base
breakdown limits the maximum gate reverse voltage.

VSATVOFFSETNPN
I GA

SIMPLIFIED EQUIVALENT CIRCUIT DURING

CONDUCTION
Figure 16.22

7. It is easy to overlook some of the more subtle aspects of turning off a PNPN
by means of reverse biasing a gate. Figure 16.23(A) shows that a cathode
gate input is effective in turning off the SCS. In effect the cathode is reverse
biased preventing PNPN action. What remains is a saturated PNP transistor
which turns off as carriers recombine. A positive input to the anode gate is
much less effective since it cannot reverse bias the anode junction.

GOOD FFAAIIRR
POORTURNOFF POOR
11_
IL

GOOD
TURNOFF(A) (B)
V

(
C)

GATE TURN -
OFF POSSIBILITIES
Figure 16.23

When the load is moved to the cathode as in Figure 16.23(B), the cathode junc-
tion can no longer be reverse biased but the anode gate becomes more effective in
turn-off.
Figure 16.23(C) modifies the above discussion if the anode is shunted by a
capacitor. The cathode gate is as effective as before, possibly more so since rate effect
is also suppressed. A positive input to the anode gate, however, tries to raise the
forward voltage across the SCS. The capacitor holds it down forcing the anode current
below the holding current and the SCS turns off. A negative input to the anode gate
is coupled by the forward biased anode junction to the capacitor pulling the anode
below ground. On releasing the anode gate the SCS can recover while the anode is
reverse biased.

409
16 SILICON CONTROLLED SWITCHES

MEASUREMENT
The test conditions given in defining and specifying the electrical characteristics
suggest appropriate test circuits. While many of the tests can be performed on a
Tektronix 575 Curve Tracer care is required both in setting the CRO and in interpret-
ing the waveforms. Furthermore, the settings and waveforms often change considerably
with operating point making interpretation more difficult. Suitable settings for the
Tektronix 575 Curve Tracer are beyond the scope of this chapter and are discussed
in aseparate General Electric Application Note.

DC MEASUREMENTS
The junction breakdown voltages are readily measured using techniques identical
to those for diodes or transistors. Measurements with the SCS forward biased (either
blocking or conducting) require special care. First, it is essential that the conditions
existing at all four leads be specified. Second, the test circuitry must avoid voltage
transients or rate effect. Since hum or noise pick up can trigger the SCS, circuit
layout should take appropriate precautions. Anode to cathode capacitance must be
avoided unless its effect on holding current, peak anode current, and temperature
are considered.
Several methods of specifying triggering parameters are possible. In the interests
of measurement precision, the triggering voltage range is measured using a low im-
pedance voltage source at the gate. The triggering current, however, is derived from
acurrent source.
Figure 16.24 shows a simple test set for measurement of 3N58 characteristics.
Push buttons are used throughout. With no buttons depressed, the SCS has an 800
ohm anode load resistor and 10K from gate to ground. The voltmeter primarily moni-
tors whether the SCS has triggered. Pressing the VG= MIN button should not trigger
the SCS. Pressing the V6T c MAX button should. On releasing the button, VPcan be
read. The RESET button allows the SCS to recover. Pressing the I GTc button should
again trigger the SCS. Pressing the IHbutton should result in the anode voltage remain-
ing at approximately one volt. The zener triggers the SCS in case it inadvertently
turned off prior to this test. Figure 16.25 shows acomparable circuit for a3N59.

65011

400S1

DC PARAMETER TEST SET FOR 3N58

Figure 16.24

410
 SILICON CONTROLLED SWITCHES 16

V ATA MIN

V OTA MAX

I, BUTTON
IS DP DT

DC PARAMETER TEST SET FOR 3N59

Figure 16.25

TRANSIENT MEASUREMENT
Recovery Time
As with dc measurements it is essential that conditions at all four leads be specified
for meaningful measurement. The definition of recovery time generally used for PNPN
devices applies to the SCS also. The defining waveform is shown in. Figure 16.26.
Initially the device is conducting. A capacitively coupled negative transient equal to
the anode supply voltage reverse biases the anode. The device is said to have recov-
ered if the anode voltage rises to the anode supply voltage without the unit retriggering.
The recovery time is defined as the time from the initiation of the negative transient
until the anode voltage crosses through zero.

V CC

IL RECOVERED PNPN

or UNRECOVERED WAVE FORM

VF
0-=--& — -a

i —e. TIME
,
v„

Figure 16.26 ANODE WAVEFORM DEFINING RECOVERY

MERCURY
RELAY

Figure 16.27 RECOVERY TEST SET

411
16 SILICON CONTROLLED SWITCHES

A suitable circuit for measuring recovery time is shown in Figure 16.27. When-
ever the mercury relay contacts open a positive pulse appears at the anode which
results in the 2N1711 shorting the gates together. This is a most effective way of
triggering the SCS. It also permits shorting the cathode gate to cathode as is required
by the 3N59 specification. Once the SCS turns on, the triggering circuitry is com-
pletely isolated. Closure of the mercury relay contacts supplies the prescribed negative
transient to the anode. The capacitor is increased until the SCS just recovers and
the recovery time is recorded. The capacitor value will, of course, depend on the
load resistance RA.

Turn-On Time
By considering the SCS as an NPN transistor with an additional diode in series
it is obvious that at least all the factors affecting transistor turn-on time are also
applicable here. Gate biases prior to the turn-on transient, control delay-time. The
magnitude of gate current also determines how rapidly regeneration will start. A
suitable test circuit for the 3N58 is shown in Figure 16.28. A mercury relay of the
make before break variety is used. The anode load resistor, the initial impedance
from gate to cathode and the triggering current resistor are chosen. When the upper
relay contact opens, trigger current is applied. Eventually the contact recloses and
the bottom contact opens. This permits the capacitor to charge, shorting out the SCS
with the 2N1711. As soon as the zener clamps the capacitor the anode is permitted
to rise to the supply voltage. The bottom contact recloses discharging the capacitor.
The cycle now repeats. The zener is primarily for limiting the 2N1711 emitter reverse
voltage. A similar circuit for the 3N59 is shown in Figure 16.29.

CRO
TRIGGER
I.5V

5µs
500pps

CONNECT
POWER SUPPLY
BEFORE
INPUT PUL SE

Figure 16.28 3N58 TURN -

ON TIME TEST SET

DEVICE
UNDER
TEST
CRO lOOK
TRIGGER

CONNECT POWER
SUPPLY BEFORE
INPUT PULSE

Figure 16.29 3N59 TURN -

ON TIME TEST SET

412
 SILICON CONTROLLED SWITCHES 16
Rate Effect — Dynamic Breakover Voltage
It is asimple matter to apply afast anode voltage to the SCS. One precaution is
necessary, however. Using the circuit in Figure 16.30 it is important that the anode
voltage be raised until the SCS triggers and then decreased until the SCS ceases to
trigger. The latter is the dynamic breakover voltage. The reason for this is as follows:
while VA is increasing the center junction capacitance charges slightly with each
closure of the relay, then maintains the charge while the anode becomes reverse
biased as the relay opens. Therefore to get the capacitance to charge fully due to a
single closure it is necessary to discharge it first by causing the SCS to trigger.
MERCURY
RELAY

RATE EFFECT
TEST SET
Figure 16.30

A capacitor may be used to vary the rate to rise with RDdischarging the capacitor
between cycles. The CRO input capacitance must be isolated from the SCS to get
the fastest waveforms. The gate impedance and bias voltage can be varied as desired.

Part 2— SCS Characteristic Curves

Two sets of characteristic curves are shown representing the two different SCS
structures. One set of curves pertains to types 3N58 through 3N60 which are grown
diffused devices, fixed-bed mounted on a ceramic disc and housed in aTO-12 case.
The other set of curves pertains to the more recent types 3N81 through 3N86 which
are planar devices housed in aTO-18 size package.
The planar devices offer higher voltage and current ratings at lower cost and are
therefore the preferred types for new designs. Care should be exercised in substituting
PLANAR devices for the 3N58-3N60 series due to the different gate-to-cathode im-
pedances required for the two products. Particular attention should be given to the
differences shown by the curves for anode holding current ( ) and anode gate current
to trigger (IOTA) as afunction of gate to cathode impedance.
These differences result from the lower internal resistances inherent with the planar
product. The lower resistances give the 3N81-3N86 distinct advantages in gate turn-off
and dissipation characteristics but cause a profound effect on Li and I OTA when the
cathode gate is shorted to the cathode as is done in the 3N59 characterization.
Lower internal resistance in the planar product permits substantially higher current
ratings for the anode gate. In many cases, this allows placing the load in the anode
gate rather than the anode thus improving immunity to noise, eliminating rate effect
problems (dvidt) and presenting circuit possibilities with high turn-off gain.
SCS types 3N81 and 3N82 represent "the center of the line." They are thoroughly
characterized and yet manufacturable at high yield to maintain uniformity and low
cost. The 3N83, 3N84 and 3N85 are functionally-oriented less demanding types. The
3N86 is apremium high performance type for the most demanding applications.

413
16 SILICON CONTROLLED SWITCHES

.9

.8

VAc •40V
17 1 •8000
RAc•101(9

.2

-75 -50 -25 0 +25 +50 +75 +100 +125 +150

AMBIENT TEMPERATURE -T
A -•
C

.8

.7

.6

e
e ,

RL. 8000

5
o

VAC •4OV

-75 -50 -25 0 +25 +50 +75 +100 +125

AMBIENT TEMPERATURE -TA- n

Figure 16.31

414
 SILICON CONTROLLED SWITCHES 16

Roc .00

Roc •IK

A WITH ONOC LIMIT

SPREECI
W
FI .10 K S

Roc •10KII

-75 -50 -25 0 +25 +50 +75 +100 +125 +150

AMBIENT TEMPERATURE - •C

10

R., •00

---SPECIF CATION ss
LIMIT (Roc •1010

.2

.05
Roc •10KA

.02

.01 75
-25 +25 +75 +125 +175

TRIGGERING (3N81, 3N82) AMBIENT TEMPERATURE -T.-•C

415
 cm
10 100

SallaLIMS aaT1OUINOD NODIIIS

10

50
5 5.0

20

2 2.0
10

SPECIFICATION •SPECIFICATION LIMIT

Ioo •SOMA (Roc 10 K) Roc •OD
LIMIT (Iwo)

MOLDING CURRENT-4 -MA

1 1.0

Roc •1
K11

• 2
.5 0.5

Roc • KO
U

•ICAA

.2 0.2
'
5

ANODE o
Ioo •OUA o

0.1 • 2
Roc •10K/1
Roc •10 Kil

.1
.05 0.05

.05
Roc 10KD

.02 0.02
.02

.0175 0.01 .0175

-25 +25 +75 +125 +175 -75 -25 +25 +75 +125 +175 -25 +25 +75 +125 +175

AMBIENT TEMPERATURE AMBIENT TEMPERATURE -TA -•C

AMBIENT TEMPERATURE -TA -•C
 SPECIFICATION LIMIT -•*"...
2.04 Al la•200MA
WITH I•0
1.4

1.3
4•100MA
SOMA

AGO VOLTAGE DROP -V, -VOLTS

12
1.3

I. •SOMA

SILICON CONTROLLED SWITCHES

1
0

•10MA

0.8

0.9

-75 -50 -25 0 +25 +50 +75 +100 +125 +150

AMBIENT TEMPERATURE -T.- C
20 40 60 so 100 120 140 160 180 200

ANODE CURRENT-I.-MA

16
Figure 16.32 FORWARD (3N81, 3N82)
 16 SILICON CONTROLLED SWITCHES

.9

.7
IA IONA

e
'
6

IA • 00MA
.5
lac INA
.4

.
2
o

o
-75 -50 -25 0 +25 +50 +75 +100 +125 +150

AMBIENT TEMPERATURE -TA -•1

IA •10MA Roc •10KII

Roc IKII

Roc • 00

-75 -50 -25 0 +25 +50 +75 +100 +125 +150

AMBIENT TEMPERATURE -TA -•C

Figure 16.33
418
 SILICON CONTROLLED SWITCHES 16

.40

IA •100MA

'c .30
IA •10MA

IGA • 3MA
Roc •10K11

ew

î
-25 0 +25 +50 +75 +100 +125 +150
AMBIENT TEMPERATURE -TA- C

16

,SPECIFICATION LIMIT
(Roc •10K)
4

ROC •10K13

12

10

IA •100MA

Roc • KO

4
GC •on

-75 -25 0 +25 +50 +75 +100 +125 +150

AMBIENT TEMPERATURE -T C

TRANSIENT (3N81, 3N82)

419
 16 SILICON CONTROLLED SWITCHES

2.0
SPECIF CATION
LIMIT

.5

.77
RPM COLLECTOR SATURATION VOLTAGE -Vc E

Ic.50MA
IB.5MA

0.5

lc •10MA
Ie•IMA

O
-75 -50 -25 0 +25 +50 +75 +100 +125 +150

AMBIENT TEMPERATURE -T
A -•C

2.0
COLLECTOR SATURATION VOLTAGE -%mar VOLTS

1.5

IA OMA

le SOMA
I8 .5MA

1.0

IA •10MA

0.5
IA •100MA
NPN

O
-75 -50 -25 0 +25 +50 +75 +100 +125 +150
AMBIENT TEMPERATURE-TA - C

Figure 16.34 COLLECTOR SATURATION (3N81, 3N82)

420
 SILICON CONTROLLED SWITCHES 16

0.8

0.6
PNP CURRENT GAIN -PNP hrE

VcE •-2V

0.4

0.2

-0 I -02 -0.5 -10 -2.0 -50 -10

COLLECTOR CURRENT -Ic -MA

60

VcE -2V

It SPECIFICATION,
LIMIT
5
01 02 0.5 10 2.0 5.0 10 20 50 100

COLLECTOR CURRENT— lc —MA

Figure 16.35 CURRENT GAIN (3N81, 3N82)

20

15
J

It 10
It
o
E •0
o

o
o
 16 SILICON CONTROLLED SWITCHES

1.5
1.0
3N58— — —
UMMIMMUMMIMMIMMMUMM
3N59-
MageUMMUMMUUMMIMIMM
MMMUMMUM
mummumme-A59 limmumm
mummummum._ mom
IMMMIUMMMIUMIemAIIMMMR
MMOIMMIIMMUMUMMICAIMM
mmummum amen.
3N58 (i
") MINIM
o
WIMMUMMUMMUMMUMUMMU
MUMMMMMUMUMMUMMMUM
.............MMIMMUM
IMMUMMMMUMMMIMBUBM
-0.5 MMIUMMUMUMMUMMUMMM
-50 0 50 100 150
-50 0 50 100 150
TEMPERATURE-S C
TEMPERATUR E-*C
TRIGGERING VOLTAGE TRIGGERING CURRENT

'LITA VS R GC

.001
10 100 1K 10K 100K 1
MEG
RGc-a

NORMALIZED ANODE GATE TRIGGERING CURRENT VS. CATHODE GATE RESISTANCE

1.8

1.6
0
o
1.4
o

1.2

LO
TRIGGERING 5 10 15 20 25 30 35 40
(3N58 TO 3N60) VAc (VOLTS)

Figure 16.37 NORMALIZED ANODE GATE TRIGGERING CURRENT

VS. ANODE TO CATHODE VOLTAGE
 SILICON CONTROLLED SWITCHES 16

3.0 1.5 nnnanannnaennannnann

nannanannannnannanan
nannnannnnnannnnanna annannannannanannann
nannannannananananan nananananananannannn
nanannunnannannanan umnannuinnannunnnannm
nanannannannanannann annannannannannannan
2.0 1.0 nannannnnannannannna
ǹ
Mann« Manna
ummomm. 4.100mA mummm Sennannannnanannanna
o U ..... miemmommimmimmen
mummanummilimiim
Banana@ 4.50mA Banana m
mmumaseumm
io nnannnnn nnannannann 0.5
mummenwenum m
nannnnanannnanannnan mmerewaimmmusemmumm
nannanannanannannann ammumwemmnemmilialem
nannanannannannannan mmummummommumm
nannannannananananan amommumaummummom
-50 0 50 100 150 -50 0 50 100 150
TEMPERATURE- °C TEMPERATURE - °C

FORWARD VOLTAGE HOLDING CURRENT

Figure 16.38 FORWARD (3N58 TO 3N60)

GATES OPEN Gc SHORTED G

A SHORTED BOTH GATES
SHORTED

BREAKOvER VOLTAGE 70 50 80
0 TO 20
VER) VOLTS
REVERSE VOLTAGE 80 80 4 0.5
VR VOLTS

0 0.5 TO 1 2 TO 3 2 TO 3
IH MA

0 0.5 2 4
I9, MA (TO FIRE)

10 TO 60
IGF ,MA (TO FIRE) -TO IA µA

VG ,c VOLTS (TO FIRE) 0.4 TO 0.6 0.5 TO 0.8

0.2 TO
IGFA mA (TO FIRE) 0 TO 8µA 1.0 MA

VGFA VOLTS (TO FIRE) 0.4 TO 0.6 0.6 TO 0.9

TYPICAL ANODE CHAR

Figure 16.39 3N58 TO 3N60 SERIES

5.0
SCS CENTER JUNCTION
CAPACITANCE
4.0
90 -TH PERCENTILE
\ MEDIAN —
z 3.
0
10 -TH PERCENTILE
2.0
e
1.0

10V 20V 30V 40V 50V

VOLTAGE VAc (ve

CENTER JUNCTION CAPACITANCE

Figure 16.40 3N58 TO 3N60 SERIES

423
 16 SILICON CONTROLLED SWITCHES

3N58 3N59

IGC= 20µ A IGc =100 µ A IGA >.3MA I GA =IMA

(
Ru r10 K)
IA(
MA) I
4(MA) IA (
MA ) IA (MA )
1 10 100 1 10 100 10 100 10 100

+I
25° C 1.00 LOO .95 .65 .65 .70 .50 .50 .60 .65

+ 25° C 1.10 1.15 1.05 .70 .70 .70 .45 .50 .60 .60

-65°C 1.40 1.45 1.40 .75 .75 .75 .45 .50 .55 .55

TURN ON TIME

MINIMUM DYNAM I
C BREAKOVER
VOLTAGE IN

-3 N58 CONFIGURATION 13 V
-3 N59 CONFIGURATION 35V
-3 N58 CONFIGURATION WITH
VGC ' - IV 50 V

-3 N59 CONFIGURATION WITH

VGA ' + 1V 80 V

STATIC BREAKOVER VOLTAGE 80V

DYNAMIC BREAKOVER

30
MMBUMMUMMMUMMUMMMMM MMUMMUMMUMMUMUMMIM
MURMUR« MMUMMMUMMUMMMUMMMMIIM
SCS 3N58
MMIIMMMMMIMIMMMMMIMM
MMUR G= P
u MIMMUMMUMM MMIIMMMUMMUMMMUMMMUMM
MMMIMMUMUMM MMIBBBMMIMMIMMUMMUMMM
MMUMMUMMUMMIMMUMMIM
MMUMMUMMIMMUM 100 MA
MUMMUMMMIMMM il MMMMUMMMUMUMMUM
MUMMUMMMUMMMUCROM MUMMUMMUMMUMM 100 MA
MUMMMMMIUMMLI 10 MA 11 MUMMMUMMUMMUMMMUMQ «
mummommommemm —gem UMMMUMMUMMOM 20
MMUMMLIa OMMOIMMIMMIM MU M MIUMM 1
= M
- OMO M M!
imMOMMMOMM:à111 MMMEMOIM

maiiaMMIUMMII »mmaellm
-50 0 50 100 150 -50 0 50 100 150
TEMPERATURE -° C TEMPERATURE -° C
RECOVERY TIME
RECOVERY TIME

TRANSIENT (3N58 TO 3N60)

Figure 16.41

424
 SILICON CONTROLLED SWITCHES 16

Part 3— SCS Circuit Applications

The circuits chosen for this section are representative of the wide range of appli-
cations open to a four terminal SCS. They were selected to illustrate basic principles
such as suppression of rate effect and methods of turn off. The SCS is applied as a
high gain DC amplifier; an SCR; a complementary SCA; a latching NPN transistor
and as aPNP-NPN integrated transistor pair. Additional circuit data is available from
the editor on request.

+ I2V

100K
MR RATE
EFFECT I

ALTERNATE
INPUT 3N81 WHEN Rs DECREASES SUFFICIENTLY
OR TO FORWARD BIAS THE SCS, THE
z 100K y Y 3N84 ALARM IS ACTIVATED.
POSITIVE
SET IK INTERCHANGING Rs AND THE
PULSE
TO IM POTENTIOMETER TRIGGERS THE
TRIGGERS
SCS -I2V SCS WHEN Rs INCREASES.

TEMPERATURE, LIGHT, OR RADIATION SENSITIVE RESISTORS UP TO IMEGOHM

READILY TRIGGER ALARM WHEN THEY DROP BELOW VALUE OF PRESET
POTENTIOMETER. ALTERNATELY, 0.75V AT INPUT TO 100K TRIGGERS ALARM.
CONNECTING SCS BETWEEN GROUND AND-I2V PERMITS TRIGGERING ON
NEGATIVE INPUT TO GA.
(A) ALARM CIRCUIT

USE 3N8I FOR HIGHER CURRENT LAMPS

ANY OF SEVERAL INPUTS PULLS IN COMMON ALARM RELAY WITH LAMPS

GIVING VISUAL INDICATION OF TRIGGERING INPUT. LOW RESISTANCE
LAMPS DECREASE INPUT SENSITIVITY.

(B) MULTIPLE ALARM CIRCUIT

+I2V

100K

EFFECTIVE INPUT

SET 12 VOLT
ZENER

INPUT TRIGGERS SCS

IK TO 250K
UNLESS WITHIN ±IV
-12V OF GROUND

(C) ALARM TRIGGERED BY DEVIATION FROM GROUND

Figure 16.42 VOLTAGE SENSING

425
 16 SILICON CONTROLLED SWITCHES

95 TO 105V
DC FOR LATCHING
AC FOR NON-LATCHING

RESET METHODS

il-
(A)

RESET -IV 3 MA FOR

5,,.S MAX LOAD
+ V .ON
0.OFF
INITIALLY 10K

(b)

SCR REPLACEMENT

+12V FOR 95-120 DC OR RESET METHODS

LATCHING • RECTIFIED AC
(AS ABOVE, PLUS')
AC FOR
¡W
NON-LATCHING 150K
(c)
3.9K ,„ 3 MA FOR
NE-8I RESET 3 µ S MAX LOAD

+2.6v.ON
(»OFF
INITIALLY IOK 3N83
(d)

INPUT

SEVERAL STAGES
NEON DRIVER
BETTER CIRCUIT
(A) NEON

170 V

I5K

+ 12 V 00000

LIKE NEON DRIVER BUT

WITH DIFFERENT
2.2K CURRENTS AND
VOLTAGE

+ 2.6V ON
O OFF
INITIALLY
3N83

10K X

(B) NIXIE TUBE

Figure 16.43
426
 SILICON CONTROLLED SWITCHES 16

ON AT +6V
+6V OFF AT 0
INPUT

680K 220K

ALTERNATE
220K 3901( POWER SOURCE

ALTERNATE
ON AT OV -6V
INPUT
OFF AT -6V

RAT ING SEC VOLTS RMS

LAMP VOLTS AMPS SCS TI * T2

24 24 035 3N8I 34 24

327 28 04 3N 8 I 40 28

330 14 08 3N8I 20 14

344 10 .015 3N8I 14 10

1829 28 07 3N8I 40 28

INCREASED VOLTAGE GIVES NORMA BRIGHTNESS IN HALF

WAVE CIRCUIT

RECTIFIER PREVENTS
ON AT +6V AC FEEDBACK INTO

1
+6V OFF AT 0
INPUT INPUT

TÉ
O

220K

ALTERNATE
220K 390K
POWER SOURCE

ALTERNATE OFF AT OV -6V

INPUT ON AT -6V

(c) INCANDESCENT LAMP DRIVERS

+ 24V

T2

ANOTHER STAGE
3N8I OR
3N84

39K

INPUT
0 2V OR 07V

o
110V
AC
C22
o
BRIDGE RECTIFIERS
HANDLE TOTAL LAMP LOAD
THE 2N2646 OSCILLATOR TURNS ON THE 2N527 FOR APPROX.
20i£SEC AT A IKC RATE IF THE INPUT IS AT 07 VOLTS THE
SCS TURNS ON GENERATING A PULSE TO TRIGGER THE SCR
DRIVING THE LAMP. BY USING A BRIDGE RECTIFIER AND A IKC
PULSE RATE THE LAMPS GIVE NORMAL BRILLIANCE. A 0.2V
INPUT DOES NOT TURN ON THE SCS AND THEREFORE THE LAMP

(D) DRIVING 110V INCANDESCENT LAMPS BY LOW LEVEL LOGIC

LAMP DRIVERS

427
 16 SILICON CONTROLLED SWITCHES

+I
2V

OUTPUT

2.0 V _
FL

THE RESISTOR DIVIDER CONNECTED BETWEEN QI AND 02 SUPPLIES IH TO 01

AFTER INPUT A TRIGGERS IT. IT ALSO PREVENTS INPUT B FROM TRIGGERING 02
UNTIL DI CONDUCTS . CONSEQUENTLY THE FIRST B INPUT PULSE AFTER INPUT A
IS APPLIED WILL SUPPLY CURRENT TO RL .

(A) PULSE SEQUENCE DETECTOR

+I
2V

IK

OUTPUT
(NC )
3N8I
2.0 V INPUT B OR
3N84
_FL

(NC )

2.0 V INPUT A

UNLESS INPUTS A AND B (2 TO 3V AMPLITUDE ) OCCUR SIMULTANEOUSLY NO VOLTAGE

EXISTS ACROSS RL. LESS THAN IMICROSECOND OVERLAP IS SUFFICIENT TO TRIGGER
THE SCS . COINCIDENCE OF NEGATIVE INPUTS IS DETECTED WITH GATES GA INSTEAD OF
Gc BY USING THE SCS IN A COMPLEMENTARY SCR CONFIGURATION .

(B) PULSE COINCIDENCE DETECTOR

LOGIC
Figure 16.44

428
 SILICON CONTROLLED SWITCHES 16

VON V OFF R . R G R C

+1 -1 100 470 10 K I
NPUT
+1 -1 100 100 3.3 K
+I -1 100 0 IK 3N8I

+I -3 100 0 330

OUTPUT

RG . RL

-24 V

LOAD IN CATHODE -OUTPUT IN PHASE WITH I

NPUT

+24V

R =RL
V ON V OFF

10 K
3.3 K OUTPUT
IK

3N81
INPUT

LOAD IN ANODE -OUTPUT OUT OF PHASE WIT H INPUT

INPUT PULSES OF IND I

CATED AMPLITUDE WI
LL TRIGGER
BISTABLE CIRCUITS .OPPOSITE PHASE INPUT CAN BE
APPLIED TO RG . FOR DIFFERENT SUPPLY VOLTAGES ADJUST
RL TO KEEP LOAD CURRENT CONSTANT .

BISTABLE MEMORY ELEMENTS

MEMORY ELEMENTS
Figure 16.45

+I
2V

1N4009
T MAY BE
INP UT I OMI TTED
SQ UARE ON LAST
WAVE -J STAGE

INPUT 1 +2 i +4
STA GE 1 1

STAGES ARE TRIGGERED BY POS I TIV E GO I

NG EDGE .THE SCS IS TURNED ON AT THE CATHODE GATE ; TURNED
OF F AT TH E ANODE GAT E. THE ANODE -TO -CATH ODE IN4009 SU PPR ESSES POS I TIV E TRANS I
ENTS WHIL E
TH E SCS IS RECOVER ING . THE I
NPUT STAGE GENE RATES FAS T POS I TIV E EDGES TO TRI GGE R THE CO UNTER .
o
BINARY COUNTER

COUNTERS
Figure 16.46

429
 16 SILICON CONTROLLED SWITCHES

SHIFT PULSES ARE GENERATED BY THE UNIJUNCTION TRANSISTORS .

THE INTERVALS BETWEEN PULSES ARE CONTROLLED BY Cr AND RT.
A DIFFERENT RT CAN BE SELECTED FOR EACH STAGE OF THE
COUNTER AS SHOWN .

(
A) RING COUNTER WITH VARIABLE TIMING

9+170 V

15K

+I
2V t20% L 100K
6

IK 68 K

68 K
1-r ° - 6V
4.7K 4.7 K
ITo sv sC2fe,i
pf
10 TO 20»
.002 00 'V'el(
ze- N83
5KC MAX

47 K 47 K

o 6V±20%

(G) NIXIE TUBE RING COUNTER

Figure 16.47

430
 SILICON CONTROLLED SWITCHES 16

+20V

IOK

4TK

.002
SET
PUSH -
BUTTON TO SUCCEEDING
STAGES

IN4009

TRIGGER LINE

2N27I4 J1_
SHIFT PULSE 5-10µS
RESET PULSE>I00µS
-6V

THE SHIFT PULSE TURNS OFF THE CONDUCTING SCS BY REVERSE BIASING THE
CATHODE GATE. THE CHARGE STORED ON THE COUPLING CAPACITOR THEN
TRIGGERS THE NEXT STAGE. AN EXCESSIVELY LONG SHIFT PULSE CHARGES UP
ALL THE CAPACITORS, TURNING OFF ALL STAGES. GROUNDING AN ANODE GATE
WILL "SET" THAT STAGE.
(C) 20 KC RING COUNTER

SHIFT PULSE
prf .10KC
pw.I0 TO 20µS

l-FRESET PULSE
7V FOR > 100µ5

FIRST STAGE SECOND STAGE LAST STAGE

RING COUNTER OPERATES FROM 1.0 TO 6.0V REQUIRING ONLY 6 MILLIWATTS AT L5V.
THE RESET PULSE TURNS ON THE FIRST STAGE WITH ITS TRAILING EDGE.
MAXIMUM SHIFT PULSE WIDTH INCREASES WITH VOLTAGE AND APPROACHES 704 FOR
A 6.0 SUPPLY. MINIMUM PULSE WIDTH IS 10µS.

(D) EXTREMELY LOW POWER RING COUNTER (LESS THAN 6MW)

RING COUNTERS

431
 16 SILICON CONTROLLED SWITCHES

+I8V

INTERRUPTED
+I5V TO REGISTER
(1.0 AMP MAXI

SHIFT PULSE LINE TO REGISTER

Ji-

A 16 VOLT POWER SUPPLY CAN BE SYNTHESIZED AS SHOWN USING

IN1692 RECTIFIERS. A SHIFT PULSE INPUT SATURATES THE 2142714
DEPRIVING TIC DARLINGTON COMBINATION (2N2714 AND 2N2868) OF
BASE DRIVE. THE NEGATIVE PULSE SO GENERATED ON THE I5V
LINE IS DIFFERENTIATED TO PRODUCE A POSITIVE TRIGGER PULSE
AT ITS TRAILING EDGE.

(A) SHIFT REGISTER DRIVER

+I8V
10K

INTERRUPTED
*330 LAMP +I5V
80MA 41, I4V
100K

FROM TO NEXT
.02
PREVIOUS STAGE
STAGE
---
SHIFT
PULSE
IN4009
IL OR 1N4154

BASIC SHIFT REGISTER STAGE

THE SHIFT PULSE AMPLITUDE IS LESS THAN 15 VOLTS.

IF A STAGE IS OFF, THE SHIFT PULSE WILL NOT BE
COUPLED TO THE NEXT STAGE. IF IT IS ON, THE
DIODE WILL CONDUCT TRIGGERING THE NEXT STAGE. JUST
PRIOR TO TFIE SHIFT PULSE THE ANODE SUPPLY IS
INTERRUPTED TO TURN OFF ALL STAGES. THE STORED
CAPACITOR CHARGE DETERMINES WHICH STAGES WILL BE
RETRIGGERED.

(13) SHIFT REGISTER

2N27I4
IL
SHIFT PULSE
pr1 ,.51(C
pw•I5 TO 40µS

SHIFTING CIRCUITRY

RE TRIGGERING LINE

THE SHIFT PULSE TURNS OFF ALL SCSS. THE TRAILING EDGE OF THE TURN OFF PULSE IS
DIFFERENTIATED AND TURNS ON THE APPROPRIATE STAGES. THE 2N27I4 WILL EASILY DRIVE
TEN STAGES.

(C) SHIFT REGISTER

Figure 16.48 SHIFT REGISTERS

432
 SILICON CONTROLLED SWITCHES 16

+I
8V
RESET
*330
LAMP
PULSE
AMPLITUDE
IS EITHER 3N84 3N84
IOR 3V 2711

INPUT

AONE VOLT AMPLITUDE PULSE TRIGGERS SCS 1BUT HAS

INSUFFICIENT AMPLITUDE TO TRIGGER SCS # 2. A TLIREE
VOLT INPUT PULSE IS DELAYED IN REACHING SCS ^1 BY THE
10 K AND .004,f INTEGRATING NETWORK . INSTEAD , IT
TRIGGERS SCS #2 THEN RAISES THE COMMON EMITTER
VOLTAGE TO PREVENT SCS FROM TRIGGERING . THE 100 K
RESISTORS SUPPRESS RATE EFFECT .

PULSE AMPLITUDE DISCRIMINATOR

Figure 16.49

100 V
ANODE SUPPLY ANODE SUPPLY
r.481 220
VA Xeov VOLTAGE OR VOLTAGE OR
HIGHER TO 3N82 HIGHER TO
VA
220 K R LOAD MINIMIZE MINIMIZE
lUTE TRANSIENTS
TRANSIENT 10 K
3N8I PROBLEMS
THRU
3N85

SWITCH NOT GROUNDED SWITCH GROUNDED SWITCH AND LOAD GROUNDED

SWITCH CLOSED TO TRIGGER SCS

VA ='100 V 1.1‘,100 V

220 K 3N8I
THRU
3N85

3N8I
THRU
3N85

SWITCH GROUNDED SWITCH AND LOAD GROUNDED

SWITCH OPENED TO TRIGGER SCS

CONTACT ISOLATORS ELIMINATE CONTACT BOUNCE , ISOLATE NOISE ON THE

CONTACT LINES AND REDUCE CONTACT CURRENT.THE LOAD CURRENT
INCREASES RAPIDLY AND LATCHES ON . THE SCS CAN BE RESET TO THE OFF
STATE BY AUXILIARY CIRCUITRY .THE CIRCUITS ARE READILY ADAPTED TO
NEGATIVE SUPPLY VOLTAGES .

CONTACT ISOLATORS
Figure 16.50

433
16 SILICON CONTROLLED SWITCHES

OUTPUT

R,C DETERMINE HALF THE PERIOD; Re THE REMAINDER.

R, • R2 FOR SQUARE WAVE OUTPUT.

THE POTENTIOMETER VARIES PULSE WIDTH WITHOUT VARYING FREQUENCY.

THE OUTPUTS ARE TRANSIENT FREE SQUARE OR RECTANGULAR PULSES,
EQUAL AND OPPOSITELY PHASED. SYNCHRONIZATION IS OPTIONAL.

(A) SOUARE WAVE PULSE GENERATOR

A POSITIVE TRANSIENT SUCH AS THE

POWER SWITCH CLOSING CHARGES C THROUGH
L TO A VOLTAGE ABOVE THE SUPPLY VOLTAGE
IF Q IS SUFFICIENT. WHEN CURRENT RE-
VERSES, THE DIODE BLOCKS AND TRIGGERS
THE SCS. AS THE CAPACITOR DISCHARGES,
THE ANODE GATE APPROACHES GROUND
POTENTIAL DEPRIVING THE ANODE OF HOLD-
ING CURRENT. THIS TURNS OFF THE SCS
AND C CHARGES TO REPEAT THE CYCLE.

(B) RLC OSCILLATOR

INPUT
(C) TACHOMETER, SINGLE PULSE
GENERATOR, POWER LOSS
IR
DETECTOR, PEAK DETECTOR
UP TO 100V
A POSITIVE GOING INPUT CHARGES
IN4148
INPUT C THROUGH THE IN4148 AND R. THE
DIODE KEEPS THE SCS OFF. A NEG-
ATIVE GOING INPUT SUPPLIES
3N81 OR ANODE-GATE CURRENT TRIGGERING
ON82
IM PENDING ON THE SCS DISCHARGING C
ONVOLTAGE) THROUGH RL.
OUTPUT
220II
RL

24V

20M 20M

'LOAD"e°14A
prf •ICPS
DUTY FACTOR 50%

0.1µf 0.1µ1
PULSE GENERATORS

Figure 16.51
ELECTROLYTIC CAPACITORS ARE UNNECESSARY TO GENERATE A ICPA
FREQUENCY. AS AN SCS TRIGGERS ON, THE 0.2 µ f COMMUTATING
CAPACITOR TURNS OFF THE OTHER ONE AND CHARGES ITS GATE
CAPACITOR TO A NEGATIVE POTENTIAL. THE GATE CAPACITOR CHARGES
TOWARDS 24 VOLTS THROUGH 20M RETRIGGERING ITS SCS, BATTERY
POWER IS DELIVERED TO THE LOAD WITH 88% EFFICIENCY. THE 20M
RESISTORS CAN BE VARIED TO CHANGE pi OR DUTY FACTOR.

(D) LOW FREQUENCY OSCILLATOR -FLASHER

434
 SILICON CONTROLLED SWITCHES 16

RESET
0 +100V +100V
°TIME DC
IK OK R 11TO
2,7,07
100K

TO IOMEG
500a RL 3N82
TO 50K OR
IN4148 3N85

00K 13N82
OR 100K
3N85

-6V -I2V
LOAD CURRENT STARTS
INPUT PULSE TURNS CFF SCS.
APPROX. 0.5 RC AFTER
SCS TRIGGERS AFTER DELAY
SWITCH IS THROWN
OF APPROX. RC

(A) TIMING CIRCUITS

THE SWITCH IS NORMALLY CLOSED

CHARGING C AND CAUSING THE SCS
TO BLOCK. THE DELAY IS INITIATED
3N5 2 BY OPENING THE SWITCH AND
100K DISCHARGING C THROUGH R.
SINCE R IS CONNECTED FOR ONLY
50V HALF OF EACH CYCLE THE DELAY
RMS
IN4148 IS LENGTHENED BEYOND THE RC
INPUT
TIME CONSTANT. THE DELAY IS
RL VARIED BY R,C, AND THE SETTING
10K
2W 5000 OF THE POTENTIOMETER. FOLLOWING
TO 50K THE DELAY THE SCS CONDUCTS
ALTERNATE HALF CYCLES.

(B) AC OPERATED TIME DELAY

+24V

270

SQUARE OUTPUT
TRIGGER
PULSE 22V FOR
INPUT
20 TO DOMS

10K
LOAD

A POSITIVE PULSE TO THE GATE OF THE SCS TRIGGERS

IT ON, SUPPLYING POWER TO THE RELAY LOAD AND CAPACITOR 1501 AND 4.7K DETERMINE STRETCH IN'ERVAL.
UNIJUNCTION TIMING CIRCUIT. AT THE COMPLETION OF CAPACITOR (501 AND 100K DETERMINE CIRCUIT RECOVERY
THE TIMING INTERVAL BASED ON RC A NEGATIVE PULSE TIME. RESISTOR 4JK SUPPLIES 1,, DURING STRETCH
TO THE ANODE TURNS OFF THE SCS. INTERVAL. RATIO OF 2700 TO 10K LOAD CONTROLS
OF SCS.
(C) 10 SECOND TIMER (D) PULSE STRETCHER

TIMING (MONOSTABLE)
Figure 16.52

435
 16 SILICON CONTROLLED SWITCHES

NOTES

446
 17
cc

SILICON SIGNAL DIODES &

SNAP DIODES

SILICON SIGNAL DIODES

Semiconductor diodes are used extensively in all types of electronic circuitry. Many
of the chapters in this manual illustrate applications in which diodes are used, from
detectors in radio receivers to gating and logic elements in computer circuits. The first
semiconductor diodes, made before the invention of the transistor, were silicon point
contact diodes used as detectors in radar receivers. Later, germanium point contact
diodes and gold bonded diodes were introduced which could be used in avariety of
applications. The demand for high operating temperatures and low leakage currents
led to the development of the silicon alloy junction diode and the silicon diffused mesa
diode. Reliability and superior electrical characteristics of the silicon diode together
with declining prices has caused it to be used in place of germanium diodes in an
increasing number of applications.
In addition, by utilizing various properties of silicon diodes several special types of
diodes have evolved, i.e., varactor diodes, stabistor diodes, snap diodes, etc. The snap
diode is of particular interest because it makes possible highly efficient harmonic
generators, and also pulse generators having high repetition rates with extremely short
transition times (as low as 0.1 nanoseconds ).

PLANAR EPITAXIAL PASSIVATED SILICON DIODE

Silicon diodes can be made using any of the transistor fabrication techniques
including alloying, growing, meltback, or diffusion. But on the basis of inherent relia-
bility and overall electrical parameters the planar epitaxial passivated (PEP) diode
structure has proven superior to all others. Some of the significant advantages of the
PEP silicon diode include
1. High forward conductance due to use of epitaxial material.
2. Low, uniform, leakage currents due to passivated surfaces.
3. Low capacitance due to small planar junction.
4. Low reverse recovery time due to accurate control of lifetime with gold doping.
5. High reliability due to passivation and rugged mechanical structure.
Fabrication of the diode starts with awafer of low resistivity single crystal silicon.
A thin epitaxial layer of high resistivity silicon is grown on the wafer. A layer of silicon
oxide is formed over the entire wafer and the oxide is removed from small circular
"windows" by means of photographic techniques. The planar junctions are then
diffused through the windows in the oxide. Gold is plated on the back of the wafer
and diffused into the wafer at a temperature determined by the required reverse
recovery time. The wafer is cut into pellets each forming a complete diode, and
contacts are made to the front and back of the pellets. Each pellet is then mounted
in aglass package and the package is sealed.
Formation of the junction under astable silicon oxide layer results in apassivated
diode which is immune to contaminants which plague other types of silicon diodes.
The effectiveness of the passivation is substantiated by atight distribution of reverse
leakage current, aparameter which is usually very sensitive to surface conditions, and
by the close correlation between the measured values of the electrical parameters and
the theoretical values. The use of an epitaxial structure reduces the bulk resistance of
the diode and thus makes it possible to achieve simultaneously a high conductance
together with alow capacitance and alow reverse recovery time.

437
17 SILICON SIGNAL DIODES & SNAP DIODES

CUT-AWAY VIEW OF PEP SILICON DIODES

Figure 17.1

Figure 17.1 shows the cross section and mechanical structure of the two popular
diode glass packages. The double heat sink (DHD) diode is smaller than the conven-
tional (D0-7) glass diode, yet it has a higher dissipation and greater reliability.
These are due to the elimination of the "S" spring and fusion of the pellet directly to
the Dumet leads. The heat generated in the pellet is dissipated via the leads. This is
brought out by Table 17.1 which gives the thermal resistance and power dissipation
as a function of the spacing between the heat sink and the end of the diode body.

438
 SILICON SIGNAL DIODES & SNAP DIODES 17

HEATSINK STEADY
SPACING STATE POWER
FROM END THERMAL DISSIPATION
OF DIODE RESISTANCE AT 25 C/MW
BODY `C/MW
DO-7 DHD DO-7 DHD

.062" .389 .250 450 700

.250" .500 .319 350 550
.500" .700 .438 250 400

DIODE THERMAL RESISTANCE AND POWER

DISSIPATION
Table 17.1

DC Characteristics
The characterization of the PEP silicon diode is greatly simplified by the close
correlation between the theoretical and the actual parameters. The de characteristics
are generally specified by means of the following parameters and characteristic curves.

1000
SHADED AREA INDICATES
25 ° C GUARANTEED LIMITS OF
CONTROLLED CONDUCTANCE
TYPES IN3605 IN4152
IN3606 IN4153
IN3608
100 IN3609
FORWARD CURRENT (IF ) MILLIAMPERES

10

0.1

150 ° C 25°C —55°C

001 0 I0 1.2
02 04 06 08

FORWARD VOLTAGE (VF) VOLTS

TYPICAL FORWARD DC CHARACTERISTICS OF PEP

SILICON DIODES
Figure 17.2

1. Forward Voltage. The maximum value of the forward voltage, VF, is generally
specified at one or more values of forward current, IF. For controlled conductance
diodes such as the 1N3605, 6, 8, 9, 1N4152, and 3 both the minimum and maximum

439
17 SILICON SIGNAL DIODES & SNAP DIODES

values of forward voltage are specified at six values of forward current. The relation-
ship between the forward voltage and forward current for a typical PEP silicon diode
is shown in Figure 17.2 at three values of ambient temperature. The shaded area indi-
cates the guaranteed range of forward characteristics for the controlled conductance
types at 25°C junction temperature. The tight control of forward conductance is very
desirable in the design of diode logic circuits where it permits greater design margins
or additional logic stages»
Forward de characteristics of the PEP silicon diodes closely follow the theoretical
equation

I
F= Is [exp (V F— Rs
)
(17a)
nKT
where
Is = diode saturation current
Rs = diode series ohmic resistance
q electronic charge (1.60 x 10 -"coulomb)
K = Boltzmanns constant (1.38 x 10 watt see/°K)
T = absolute temperature (°K)
NOTE: I= Is [exp (x)] = Is (e).

At low forward currents where Iv Rs << VF, and with the exponential term much
larger than one, then 17( a)becomes

IF= exp ci-Vr 17(b)

nKT
or
= ,IKT
q n \ Is / 17(c)

Figure 17.3 shows"» the deviation of the forward characteristic of asilicon PEP diode
from the true exponential equation as given by 17( c). The error is less than 1% from
Zta to 2ma. At low currents the error increases because the exponential term in 17( a)
approaches one. At high currents the increase in error is due to the effect of the IFRS
term in 17 (a).

A TYPICAL DEVIATION IN Vf FROM

5
A TRUE EXPONENTIAL RELATIONSHIP
FOR IN3605 PEP DIODE
P
- 4

05 1.0 5 10 50 100 500 1000 s000 e,000

IF •

A TYPICAL DEVIATION IN V, FROM A TRUE EXPONENTIAL

RELATIONSHIP FOR 1N3605 PEP DIODE
Figure 17.3

440
 SILICON SIGNAL DIODES & SNAP DIODES 17
Parameter n in the above equations is dependent upon the impurity gradient in
the junction and the carrier lifetime in the semiconductor material. At low values of
forward current, carrier recombination in the junction depletion layer is the pre-
dominant factor in determining the relationship between forward voltage and current,
and n 2. At high values of forward current the relationship between forward current
and voltage is determined primarily by minority carrier diffusion, and n 1for non-
gold doped diodes. The characteristics of the normal gold doped PEP silicon diode
can be approximated with reasonable accuracy by assuming that n= 2over the entire
current range. (At 25°C this gives nKT/q = .052 volt). nis shown in Figure 17.4 for
both gold doped and non-gold doped diodes.

700

600
/7• I25

SD300 71.2.00'
NON -GOLD DOPED DIODES )
_>
D.500

uJ 400
o

o
77• 2.00
o
cc 300 I
N3605
(GO LD DO PED DI
ODES )
e
o
Il-

200

10 -10 10 - 8 0-7 10-8

FORWARD CURRENT (IF) IN AMPERES

1) FOR TWO TYPES OF PEP DIODES

Figure 17.4

Dynamic resistance, r
o,of the diode at a forward current, IF, is given by the

equation

ro — nKT R8 17(d)
qIF

Since Rs is typically 1to 2ohms for aPEP diode, the dynamic impedance is inversely
proportional to the current up to about 10 ma.
Forward voltage-temperature coefficient can be determined by taking the voltage
differential of 17( a) with respect to temperature (remembering that Is is afunction of
temperature). Figure 17.5 shows that for a 1N3605, 1N4152, and SD300, (dVF/dT)
is astrong function of forward current.

441
17 SILICON SIGNAL DIODES & SNAP DIODES
1.0

u
(S0300)
NON-GOLD DOPED DIODES
2
1.5

GOLD DOPED DIODES

(IN 3605, SDI00)

.01 10 100
FORWARD CURRENT (IF )IN MILLIAMPERES

V, TEMPERATURE COEFFICIENT AS A FUNCTION

OF FORWARD CURRENT
Figure 17.5

The empirical equations which describes these relations are: for the 1N4152 and
1N3605 series-gold doped diodes
dVr
= —1.92 0.6 log'. IF (17e)
dT
and for SD300 non-gold doped diodes
dVr
dT = —1.66 + 0.33 log'. I
F (17f)

where Ir is in milliamperes and dVr/dT is mv/°C. The constant terms in 17(e) and
17(f )are functions of Is, 7), and T (the absolute temperature), while the coefficients of
the log,. IFterms are proportional to ,,IC/q. For germanium the constant term is larger
than for silicon, while the coefficient of the log term is small. Thus, dVr/dT for ger-
manium is not as strong afunction of I Fas it is with silicon.
2. Breakdown Voltage. The breakdown voltage, Bv, is normally specified at a
reverse current of 5 p.a. The breakdown voltage increases with temperature up to the
point where the reverse leakage current becomes comparable with the current at which
the breakdown voltage is measured. The breakdown characteristic of a PEP diode
may not be as sharp as that of a non-epitaxial diode. The shape of the breakdown
characteristic can be explained theoretically, and life tests have shown that this is not
as indicative of reliability as it is with other types of diodes.
3. Reverse Current. The reverse current, In, is specified at a voltage below the
breakdown voltage. The magnitude of the reverse current is dependent on the area
of the junction and upon whether the diode has been gold doped or not. Thus, for a
given area the IRof a non-gold doped unit (SD300) will be two to three orders of
magnitude less than the I. of a gold doped unit (1N3605). Typical leakage currents

442
 SILICON SIGNAL DIODES & SNAP DIODES 17
of these two types of diodes at 30 volts and 25°C are 0.02 and 20 nanoamperes re-
spectively. Reverse current increases exponentially with temperature as indicated by
the equation

II: = IRO exp 8(T — T.) (17g)

where I Ris the reverse current at temperature T, 1E0 is the reverse current at tempera-
ture T., and 8is the fractional increase of I Rwith temperature. For the PEP silicon
diodes (1N3605, 1N4152) 8 .1 0.0551°C. The reverse current will increase by a
factor of ten when the temperature is increased by 2.30/8 = 42°C. At low values of
reverse voltage the reverse current is proportional to the square root of the voltage
owing to the spreading of the depletion layer. At values of reverse voltage comparable
to the breakdown voltage, the reverse current increases rapidly due to avalanche multi-
plication and localized breakdown effects.

AC Characteristics
1. Capacitance. The capacitance normally specified for adiode is the total capaci-
tance which is equal to the sum of the junction capacitance and the fixed capacitance
of the leads and the package. The capacitance, C., is specified at afrequency of 1mc
with zero applied bias. Since the typical capacitance of some PEP silicon diodes is less
than 1.0 pf it is necessary to use athree terminal bridge configuration to achieve an
accurate measurement. The junction capacitance is inversely proportional to the square
root of the reverse voltage and increases linearly with temperature.
2. Rectification Efficiency. The rectification efficiency, RE, is defined as the ratio
of dc load voltage to peak rf input voltage to the detector circuit, measured with 2.0
volts rms, 100 mc input to the circuit. Load resistance is 5K and the load capacitance
is 20 pf. The rectification efficiency is determined primarily by the conductance, reverse
recovery time, and capacitance, and provides an indication of the capabilities of the
diode as ahigh frequency detector.
3. Transient Thermal Resistance. The transient thermal resistance of a diode is
presented by acurve such as Figure 17.6 showing the instantaneous junction tempera-
ture as afunction of time with constant applied power. This curve permits adetermina-
tion of the peak junction temperature under any type of pulsed operation. By means
of asimple analytical procedure, described in Reference 2, this curve can be used to
determine the peak junction temperature under any type of transient operation and
hence provides avaluable method of insuring the reliable operation of diodes in pulse
circuits.<2)
4. Forward Recovery Time. If a large forward current is suddenly applied to a
diode, the voltage across the diode will rise above its steady state value and then drop
rapidly, approaching the steady state value in approximately an exponential manner.
This effect is caused by the finite time required to establish the minority carrier density
on both sides of the junction. The forward recovery time is the time required for the
diode voltage to drop to aspecified value after the application of a step of forward
current. The forward recovery time increases for agiven area device as the breakdown
voltage increases and the capacitance decreases (increasing resistivity), and as the
reverse recovery time decreases (decreasing lifetime). Under some extremes of resis-
tivity and lifetime, the forward recovery time can be longer than the reverse recovery
time. For a given diode the forward recovery time also increases as the rate of rise
of the forward current is increased, and decreases as the forward current flowing prior
to the current step is increased. If the amplitude of the forward current step is suffi-
ciently small the effect of the junction capacity will predominate and prevent the diode
voltage from overshooting its steady state value.

443
17 SILICON SIGNAL DIODES & SNAP DIODES

1.2

IN4043 _
e
2
1.0
o (HEATS1NK SPACING 0.250"
FROM END OF DIODE BODY)
C.-
-

o 0.8

(7)
IN914,A,B _
cr 0.6
IN916,A,13
_1
IN4009
2

0.4

t) N4I48
0.2 N4I49
cc N4154
N4446
N4447
N4448
» N4449
o
10 -3 10 -2
10 -I 1 10 100
DURATION OF PEAK SQUARE WAVE
FORWARD POWER PULSE-SECONDS

MAXIMUM TRANSIENT THERMAL RESISTANCE

Figure 17.6

V,
(o) APPLIED
VOLTAGE 0 1

V2

v,
(b) DIODE
VOLTAGE
O

V2 - -

If
to —*I tb 4-
(c) DIODE
CURRENT I,2

In

TYPICAL DIODE REVERSE TRANSIENT WAVEFORMS

Figure 17.7

5. Reverse Recovery Time. \\*ben aforward biased diode is subjected to a reverse

voltage step, alarge reverse current will flow for ashort time as a result of the stored
charge consisting of the minority carriers on both sides of the junction. The typical
 SILICON SIGNAL DIODES & SNAP DIODES 17
voltage and current waveforms involved as shown in Figure 17.7. Initially, acurrent
I Fis flowing in the diode and avoltage VFappears across it. When the reverse voltage
step occurs at t= 0areverse current In flows which is determined by the magnitude
of the applied voltage and the loop impedance of the circuit. At the same time the
forward voltage decreases by an amount approximately equal to Rs (I F± Li )due to the
reversal of the current through the diode. The reverse current remains constant at Li
for atime t« (the constant current phase) and then rapidly decreases, approaching the
dc reverse current value. At the same time the diode voltage goes negative and
approaches the value of the applied reverse voltage.
The reverse recovery time of a diode, t,„ is specified as the time between the
application of reverse voltage and the point where the reverse current has dropped
to aspecified value, Ir. The specification must also include the forward current, Ip,
the initial reverse current, Ir., and the loop impedance of the test circuit. The specifi-
cation of the reverse recovery time of diodes is difficult to use for circuit design pur-
poses because the recovery time is given only for one arbitrary test circuit and bias
condition. Due to the wide variety of possible circuit arrangements and bias conditions
encountered in diode applications, it is impossible for the manufacturer to control and
specify the reverse recovery time corresponding to each special condition encountered.
However, for most design requirements an accurate estimation of the reverse recovery
time can be obtained by use of a quantity called the effective lifetime, r, and the
ratio of the forward and reverse currents. Figure 17.8 can be used for this purpose
together with Figure 17.9 which gives the typical effective lifetime of the PEP silicon
diode as afunction of temperature for various values of forward current.
The use of Figure 17.8 and 17.9 in estimating the reverse recovery time of aPEP
silicon diode can be best described by means of the following design example.
Problem: Estimate the typical recovery time to 5 ma reverse current (Im) when
the forward current is 20 ma ( IF) and the initial reverse current is 15 ma
(Li) at atemperature of 75°C.
Solution: Enter the left side of Figure 17.8 at Li/I, = 15/20 = 0.75 and follow
horizontally (dotted line) until the t, vs. 1,1/If line is reached. From the
tir scale on the horizontal axis, it is seen that t. = 0. 31p. The ti, portion
of the curve is estimated by moving downward parallel to the general
contour lines until reaching the line corresponding to 1,2/If = 5/20 =
0.25. The total switching time is thus 0.44p. From Figure 17.9 the effec-
tive lifetime at I
F= 20 ma and T3 = 75°C is 6.0 nsec, hence the calcu-
lated values are
constant current phase t. = (0.31) (6.0) = 1.86 nsec.
reverse recovery time t,, = (0.44) (6.0) = 2.64 nsec.
For additional material on the reverse recovery time of diodes see References 3 and 4.
6. Stored Charge. Increasing use is being made ef stored charge, Qs, as aparameter
for characterizing the reverse recovery time of diodes. For a given diode type and
structure there is a direct correlation between the reverse recovery time in a given
circuit to agiven set of conditions and the stored charge so that the two measurements
are equivalent. However, the use of stored charge as the specified parameters offers a
number of significant advantages over the use of reverse recovery time.
1. Stored charge is a single unambiguous figure of merit for a diode which can
be specified without an elaborate set of test conditions and test jig construction
details. It is generally sufficient to specify only the forward current at which the
stored charge is measured.
2. The test circuit for measurement of stored charge is simple and relatively inex-
pensive. A direct meter readout is possible even with high speed diodes, and
the use of an expensive sampling scope is avoided.

445
 17 SILICON SIGNAL DIODES & SNAP DIODES

3. Reproducibility of stored charge measurements are better than the reproduci-

bility of reverse recovery time measurements.
4. Comparative reading of stored charge can be made even on ultra-fast recovery
diodes which can not be measured on the fastest sampling scopes.

10

2
t
o,VS Id /If

0.5

0.2

01 0
02 04 06 08 I0 2
1/7

CURVE FOR DETERMINING REVERSE RECOVERY

TIME UNDER VARIOUS DRIVE CONDITIONS
Figure 17.8

IF
12 50 MA
40 MA
30 MA
EFFECTIVE LIFETIME (r) NANOSECONDS

20 MA
10

10 MA
8

o
—50 -25 0 25 50 75 100 125 150

JUNCTION TEMPERATURE (Ta ) DEGREES CENTIGRADE

EFFECTIVE LIFETIME OF PEP SILICON DIODES

VS. TEMPERATURE AND FORWARD CURRENT
Figure 17.9

446
 SILICON SIGNAL DIODES & SNAP DIODES 17

PULSE
GENERATOR

-V, V2

BASIC DIODE STORED CHARGE TEST CIRCUIT

Figure 17.10

The basic circuit for measurement of stored charge is shown in Figure 17.10.
In this circuit the diode under test (DUT) is biased by aforward current which flows
through DI, the DUT, RI, and the bias current meter Ir. A short positive pulse at a
known frequency, f, is coupled from the pulse generator through Cl to the DUT.
This pulse reverse biases the DUT and forces the charge stored on the DUT through
D2 into the output current meter L. The current through the meter L will be propor-
tional to the charge stored on the DUT. If the forward voltage across the DUT is set
to zero by adjusting Vi, an output current I, will flow which is proportional to the
capacitance of the DUT.
L = fVr ft
s Ir (17h)
where fis the pulse frequency, Vs the amplitude of the pulse, C„, s the average capaci-
tance of the diode over the range of reverse voltage from 0 to V„, t s the pulse width,

and Ir the reverse leakage current of the DUT measured at a reverse voltage equal
to V,,. The storage charge is defined by the equation

Qs
= I. — It
-- (17i)

where Is is the output current at the specified value of forward current, and L the
output current with azero bias voltage across the DUT. Inasmuch as the above defini-
tion of Qs involves the difference between two bias conditions it reduces the depend-
ance of the measurement on the pulse voltage and the reverse current of the DUT, and
thus provides a more significant parameter for characterizing the diode. Effects of
leakage current, junction capacitance, pulse amplitude and pulse width can be con-
sidered separately by the designer when estimating the performance of a diode in a
given circuit.
Certain precautions must be observed when building and using the test circuit of
Figure 17.10 for measurements on high speed diodes. The pulse generator must have
afast rise-time. It is particularly important that the 0 to 10% rise-time of the pulse
be short to prevent losing part of the stored charge before the voltage has reached
the level required to forward bias D2. The pulse generator should have ahigh output
voltage and a low output impedance so that a large reverse current can be forced
through the DUT resulting in aminimum amount of stored charge being lost through
recombination. Diode DI should be an ultra-fast recovery type since any charge store
on DI will subtract from Qs of the DUT. However, the reading for Qs of the DUT can
be corrected if Qs of DI is known. Diode D2 must be adiode with fast turn-on, low
leakage, a moderately low Qs, and a high conductance and pulse current capability

447
17 SILICON SIGNAL DIODES & SNAP DIODES

to permit the flow of the large reverse current of the DUT. The voltage V, should
be adjusted at the different measurement condition to maintain the voltage at point A
constant. If this is not done a portion of Qs will be lost owing to the capacitance
between point A and ground together with the difference in voltage required at
point A to forward bias D2. Likewise the output current meter must have asufficiently
low resistance to avoid an appreciable change in voltage across C2 at the different
measurement conditions. In the construction of the test circuit particular care should
be taken in minimizing the inductance through Cl, the test clips, the DUT, D2, C2,
DI, and C3. Typical test conditions for measurement of high speed diodes would
be: f= 100 kc, V, = 10 volts, t,. = 100 nanoseconds, t, = 0.3 nanoseconds, and IF
= 10 milliamperes.
The test circuit, the definition of stored charge, and the measurement precautions
given above are essentially equivalent to those given in the JS-2 proposed standard
on stored charge, and in method 4062 of MIL-STD-750.
For agiven type of diode the stored charge is directly related to the effective life-
time, r, and to the reverse recovery time in a given test circuit with a given set of
test limits. The relationship between stored charge and effective lifetime for the
IN3605, 1N4152 family of diodes is given by T 1.5 (Qs/IF), where IF is the current
at which Qs is measured or specified. Using this relationship and the curves given in
Figure 17.8 it is possible to predict the reverse recovery time from the stored charge
value. For example, assume a 1N3605 diode has a stored charge of 35 picocoulombs
measured at IF = 10 ma and it is desired to determine the reverse recovery time, t,,,
for If = 10 ma, L., = 10 ma, and L., = 1ma. The effective lifetime is
T = 1.5 (35/10 )= 5.25 nanoseconds
and from Figure 17.8
t,, = 0.57r = 3.0 nanoseconds

Diode Comparisons and Trade-Offs

As in all designs, the design of a diode to perform a given function requires a
series of compromises. An improvement in one parameter is usually accompanied by
the deterioration of another parameter. This can be seen in Table 17.2 where the
important parameters are shown for a series of diodes with different areas, levels of
gold doping, and resistivities. Junction areas of the SD100, SD300, and SD500 are
the same, while the junction area of the SD600 and SD800 are twice and fourteen
times the area of the SD100, respectively. Gold doping levels for the SD100, SD500,
and SD600 are approximately the same, while the SD400 has less; the SD800 is only
lightly doped and the SD300 has none. Resistivities of all the diodes are about the
same with the exception of the SD500. It has a higher resistivity which increases the
breakdown voltage and reduces the capacitance of the diode. This, however, is accom-
plished at the expense of the reverse recovery time.
Notice that the SD300 which has no gold doping has amuch lower leakage current
than the SD100 and a higher conductance; however, it has a slightly larger capaci-
tance and amuch higher reverse recovery time.
The increasing conductance of the SD600, SD400, and SD800 is due to the in-
creasing areas of these diodes. The price paid for this is an increase in capacitance
and recovery time. Because of the successive lighter levels of gold doping used as the
device area is increased, the leakage current of these devices does not increase in
proportion to the increase in area.
A parameter not shown in Table 17.2 is forward recovery time. However, as was
pointed out earlier in this chapter, the forward recovery time may increase as the level
of gold doping is increased (reverse recovery lowered) and as the resistivity is in-
creased (breakdown voltage increased ).

448
 SILICON SIGNAL DIODES & SNAP DIODES 17

DEVICE SD100 SD500 SD300 SD600 SD400 SD800 UNITS

Junction Area A A A 2A 5.7A 14A

Gold Yes Yes No Yes Yes Yes*
Resistivity Mod. High Mod. Mod. Mod. Mod.
Breakdown 60-90 60-90 60-90 volts
60-90 90-160 60-90
Voltage
Max. Leakage nano-
01
Currents @ 30 30 30 • 50 50 50
at 10V amps
volts, 25°C
Capacitance pico-
1-2 0.6-1.4 2-4 2-5 4-9 15-30
at 0volts farads

Reverse Recovery
Time tn. (h = I F nano-
2-4 3-5 100 2-4 6-10 10-18
= 10 ma, recove ry seconds
to 1ma)
Conductance milli-
IFat Vr = 1volt 100 100 150 250 500 900
amperes
@ 25°C
JEDEC 1N3604-68 1N914 1N3600
Registered 1N4009 1N914B 1N4150
Types 1N4154 1N916

*Lightly doped
COMPARISON OF DIODE CHARACTERISTICS
Table 17.2

DIODE ASSEMBLIES
PEP silicon diodes are available in matched pairs and matched quads for use in
applications where close matching in the forward characteristics is required. These
units are sealed in small epoxy packages to preserve the identity of the diodes and
minimize temperature differentials between diodes. The diodes used in these assem-
blies have all of the high performance capabilities of the standard PEP silicon diodes,
and in addition are matched within very tight limits for VFover arange of forward
currents and over awide temperature range. Vp's are matched to better than 10 mv
(3 mv typical) from 100 /La to 10 ma and to better than 20 mv from 10 ma to 50 ma
over the entire temperature range of —55°C to +125°C. Further, diode pellets can be
assembled into any configuration in multi-leaded TO-5, TO-18, and flat packages. The
degree of matching Vp for pairs or quads of pellets can be as good or better than
obtained with the diode assemblies already discussed.
An example of the application of a diode matched quad in a sampling bridge
circuit is shown in Figure 17.11. A negative pulse at the input will trigger the block-
ing oscillator generating apulse approximately 100 nanoseconds wide. The pulse at
the output winding will forward bias the diodes in the bridge with acurrent of approxi-
mately 20 milliamperes. This produces the effect of aclosed contact between terminals
1and 2with atypical impedance of 5ohms, and atypical offset voltage of less than
2millivolts. Between pulses the bridge diodes are reverse biased by the charge on the
0.1 ilfd capacitor, and the equivalent impedance between terminals 1and 2is typically
1000 megohms.

449
17 SILICON SIGNAL DIODES & SNAP DIODES

+I5V 0.1 *MATCHED QUAD SUCH

AS GE IN4307 OR
GE I2X235
22052
I
—H14
6.2V
TI IN709

330$1

>I .2
IN3605

330 TI =FERROXCUBE 266TI88

pf G.E.
TOROID WITH 5 TURNS
TRIGGER 2N9I4
ON EACH WINDING OR
INPUT o 44 7-70.22 OTHER PULSE
u
- - IN3605 IN3605 TRANSFORMER

DIODE SAMPLING BRIDGE WITH BLOCKING OSCILLATOR

DRIVING CIRCUIT
Figure 17.11

STABISTORS
Stabistors are single or multi-pellet diodes which have tightly controlled forward
voltage characteristics and which are always used in a forward biased condition. Two
examples of the multi-pellet stabistor (or low voltage reference diode) are the 1N4156
and IN4157. The 1N4156 contains two diode pellets in a single glass package while
the 1N4157 contains three diode-pellets in asingle glass package. Both have a tightly
controlled VPcharacteristic over an I Frange of .01 to 100 ma. Stabistors are used as
low voltage regulator diodes, as amplifier non-linear bias elements, and as a level
shifting diode in diode-transistor logic circuits such as shown in Figure 17.12. When
the multi-pellet stabistor is used as alow voltage regulator, the temperature coefficient
of the stabistor will be larger than a breakdown diode of comparable voltage. How-
ever, this is offset by the stabistor's tighter initial tolerance, lower dynamic impedance,
and absence of noise at low currents.

+V +V

IN 3604
DC LEVEL SHIFTING
DIODE IN DIODE
TRANSISTOR LOGIC
Figure 17.12

450
 SILICON SIGNAL DIODES & SNAP DIODES 17

SNAP DIODES
The normally undesirable recovery characteristics of a conventional diode are
improved and controlled in the snap diode. This results in adevice ideally suited for
highly efficient harmonic generators and pulse generators with extremely short tran-
sition times.
Under conditions of forward bias the diode will store a finite amount of charge.
The amount stored is primarily dependent upon the lifetime of the material and the
magnitude of the forward current. If the diode is suddenly reverse biased, after having
been forward biased, it will conduct in the reverse direction for a finite time until
all carriers stored in the diode have been removed as shown in Figure 17.13. The
length of time the reverse current flows (storage time) is a function of the initial
charge stored, the diode lifetime, and the amount of reverse current. As soon as the
stored charge at the junction goes to zero, the diode begins to turn off. A well designed
snap diode will turn off linearly as shown in Figure 17.13. This is in contrast to the
complex error function turn-off characteristic of a conventional high-speed planar
epitaxial diode.
Rg

(A)

eg o

Id SNAP DIODE
O

CONVENTIONAL
t'— 1 DIODE

(13)

REVERSE RECOVERY OF A DIODE

Figure 17.13

Turn-off or snap-off time is a function of carrier gradient at the junction, diode

capacitance, package inductance, initial charge stored, and loop impedance. It is
therefore difficult for the circuit designer to calculate the turn-off time. Circuit and
package inductances and capacitances should be minimized, however, and the loop
impedance adjusted to minimize the turn-off time. (If the impedance is too low, the
L/R time constant becomes too large, while if it too large, the RC time constant
predominates. )
Turn-off time is generally given on the specification sheet for a particular set of
forward and reverse currents. Thus, the SSA550 and SSA551 snap diodes have a
maximum snap-off time of 0.5 nanoseconds for a forward current of 1 ma and a
reverse current of 20 ma. Snap-off time may be limited by the package, circuit, or test

451
 17 SILICON SIGNAL DIODES & SNAP DIODES

equipment. For example, the SSA552 and SSA553 have a typical snap-off time given
as 0.2 nanoseconds. This figure is probably limited by the package inductance and test
equipment available at the time of measurement. For extremely short snap-off times, the
SSA556 and SSA557 should be used since these units have a "pill" package construc-
tion with only 0.15 nanohenries of inductance. They have been tested in strip line
circuits where the snap-off time has been measured as 0.1 nanoseconds using a sam-
pling scope of 0.1 nanosecond rise-time.
While it is difficult to predict the snap-off time, the charge stored during forward
bias and the storage-time under reverse bias conditions are easily calculated. The
charge stored can be obtained by solving the charge continuity equation

(17i)

where i d is the conduction current across the junction and r is the recombination
lifetime.
For the case of a rectangular supply voltage with the shunt and series circuit of
Figure 17.14, the stored charge becomes.

Qr = r(ir — v4 )(1 — e— ti/T) (171)

where

Rg
and
R
R = -—e- •— for the shunt circuit;
(R„ RL)
and

Rg RL
and
R = Fi g RL for the series circuit. If tr > > rthe stored charge becomes

= — r (17k)

The storage-time, ts, is also obtained by solving equation (171) for the charge
recovered under reverse bias conditions.* The charge thus recovered is
Qr = (14 vii) t/r
(171)
where

= e-L for the shunt circuit;

fi g
and
= e' — for the series circuit.
(Rg RL)

When Q, goes to zero the diode snaps off so that the storage-time t5 is obtained from
equation (171) as
Or
ls = rIn [
(17m )

The series circuit provides aconvenient method of measuring the diodes lifetime.
If the forward bias current is applied for a time much larger than the diodes lifetime,
and the reverse current is of sufficient amplitude that the storage-time is much less
*Because of the method of manufacture, over 95% of the charge is recovered during the storage time.
This is not true for aconventional diode.

452
 SILICON SIGNAL DIODES & SNAP DIODES 17

than the lifetime, then the lifetime can be calculated to be

= iLf ts (17 n )
iLf /
Thus it is only necessary to measure the two currents and the storage-time to calculate
the lifetime.

SNAP
DIODE

Cf Cf

eg eg o

o
e,
ttH
e,
tt 4

o o
e0 e. _

SHUNT SERIES
(A) (B)

SERIES AND SHUNT CIRCUIT WITH RECTANGULAR SUPPLY

Figure 17.14

If a sinusoidal supply is used with a rectangular and dc current, then the charge
stored for the series and shunt circuit of Figure 17.15 is
WIMIt
1— e— T/gor) 2 (1 ± e—tr/wr) (17o)

(7) +e
where
R = Rg Rr'
(R s + RL)
and
EMI
= Rg for the shunt circuit;

and
R = Rs ± RL
and
I
LI = for the series circuit.
Rs ±

For the case where rr/T<<w, then the charge stored becomes
Qf = 2Imf/w (17p)

453
 17 SILICON SIGNAL DIODES & SNAP DIODES

SNAP
R0 DIODE

E.Sinwt K1+101%0

E.

R9+R L I
R
R.R 9 +R L
RO

K RL +R9
Rg+R L

89o •
i• 0

SHUNT SERIES
(A) (B)

SERIES AND SHUNT CIRCUITS WITH SINEWAVE SUPPLY

Figure 17.15

The charge recovered during the half cycle of reverse bias becomes
Q. = TKir 7"Vd
e—th.—
(VT) ? + cc?
I
N, sin cot COI
L,
COS CO

where
[(i)
•2 4- (' • )2
+

K = 1for the shunt circuit and

K= R8 for the series circuit. If 7,-/co << 7' then

( + R8)
QN= Qt — (1- cos wt ) (17r)
Equations (17p) and (17r) can be combined to give the snap off angle
= cos' (1— 2Ix dim )
If the peak forward and reverse currents are equal, o= 180°. Some form of self bias
or different values of current must be used if the diode is to snap off before reaching
180°. On the other hand if the above inequality does not hold, then the diode will snap
off at some angle before 180° even if the forward and reverse peak currents are equal.
Because of alarger lifetime (20-100 nanoseconds) the SSA550, SSA551, SSA554,
and SSA555 should be used when the frequency is roughly below 100 mc. The reason is
that alarger charge can be stored during the half cycle of forward bias which in turn
allows a larger reverse peak current. Above about 100 mc it is desirable to use the
SSA552, SSA553, SSA556 and SSA557 with lifetimes of 1-5 nanoseconds, otherwise
all the stored charge might not be removed during the time of reverse bias without an
excessively high peak reverse current.
Figure 17.16 shows a simple pulse generator which utilizes a sinusoidal supply
and ashunt-series circuit. The pulse width and its phase relationship with the 50 mc

454
 SILICON SIGNAL DIODES & SNAP DIODES 17
source are adjustable by means of the dc voltages. The rise and fall times are probably
inductance limited. The construction details, together with other configurations are
given in Reference 6.

H = 2nsec/CN1
V = 0.5 V/CNI

H = 2nsec/CM
V = 0.5 V/CM

TIME —.

510 510
rEpc
i
E„

50 .002 r- -
.002 SSA550

SHUNT-SERIES
PULSE CIRCUIT
7Vp_, RL SO RESPONSE
SSA550
SONIC (SCOPE INPUT)
Figure 17.16

REFERENCES
(1)Kvamme, E.F., "Controlled Conductance Applications," General Electric Application Note 90.40.

(2)Gutzwiller, F.W., Sylvan, T.P., "Power Semiconductor Ratings Under Transient and Intermittent
Loads," General Electric Application Note 200.9.
(3) Chen, C.H., "Predicting Reverse Recovery Time of High Speed Semiconductor Diodes," General
Electric Application Non( 90.36.
01 Ko, W.H., "The Reverse Transient Behavior of Semiconductor Junction Diodes," IRE Transac-
tions, ED-8, March 1961, pp. 123-131.
(5) Giorgis, j., "The Logarithmic and Temperature Coefficient Characteristics of the 1N3605 and
1N3606 Diode," General Electric Application Note 90.47.
(5) Giorgis, J., "Understanding Snap Diodes," Electronic Equipment Engineering, November 1963.

455
 17 SILICON SIGNAL DIODES & SNAP DIODES

NOTES

456
 cc
TRANSISTOR MEASUREMENTS 18

INTRODUCTION
Accurate measurements demand athorough knowledge of measurement principles
and pitfalls. To simplify these measurements, such that they are non-discretionary
go-no go types, requires in addition, prior information about the device characteristics
and their probable distribution. Transistor measurements in particular, due to the
extreme power sensitivity of signal transistors and the active amplifier nature of the
device, impose great demands on the skill and ingenuity of the test-equipment
designer.
To obtain precision and accuracy in transistor measurements, not only must the
definition, meaning, and limits of each test be considered (as well as the actual meas-
urement methods), but attention must also be given to the effect of the measurement
upon the device. To illustrate: the transistor is anon-linear device and under normal
dc bias conditions the emitter-base voltage drop in a germanium transistor is about
250 millivolts. If linear (small-signal) measurements are to be made, it becomes
obvious that the rapid curvature of the forward-biased diode characteristic precludes
the usual "one order of magnitude less" argument normally applied to signal/bias
relationships for small-signal measurements and demands even smaller peak-to-peak
signal excursions.
In addition, the transistor is acurrent amplifier and the effect of the input signal
on the output current must be considered. Thus, prior knowledge of probable input
impedance and device current gain becomes necessary. For example, assuming an
ideal transistor at low frequency and neglecting parasitics, in measuring hi.

hi. = and hr. =

I,,
e. = 0 e,. = 0
then,
eb
Ii,= and i, = hf. ib
r.
from the theory (see any basic transistor text) hi, = hr. r.
(1 — a.)

(since hf, = )) so that ie ;

KT
also, r. = —
q/E (see any basic transistor text) where K = Boltzmann's constant ,

T= temperature in degrees Kelvin, and q is the charge of the electron. Now,

KT
= 26 x 10' volts at room temperature; and, assuming

I
C= IE (within 10% )

26 x 10"
r. =
IC

is very much less than I

C, (say ie = 0.1 Ic) for small signal measurements.

457
18 TRANSISTOR MEASUREMENTS

Then,
eh eh Ic
= 0.1 I, =
•

r,. 26 x 10 -3
or,

I
C
96 X 10-e 0.1 l
c whence eh 5- 26 x 10 -4

so that the maximum signal swing, eh, should be in the order of 2.5 millivolts and is
largely independent of gain or collector current. However, when the transistor is driven
from acurrent source it is seen that since

eh max =lbn,ax 111..,

then
eh
ib max =

or,

95 x 10'
ib
hre r,. , „ 25 x 10 -e
Of. max A IC

whence,
IC
"" = 10 hr....

Here aknowledge of the probable range of hr.. expected is quite important. Thus,
depending upon whether a current source or a voltage source is used in small signal
measurements, rare must be exercised to insure that small signal conditions truly exist.

REVERSE DIODE CHARACTERISTICS

General
leo or 1E0 are the leakage currents within the safe operating region of reverse
voltage and are intended to yield comparative, evaluative information as to permissible
operation, surface condition and temperature effects on operation.

The breakdown voltage tests are indicative of the maximum voltage that can be
applied to the device and serve to indicate the voltage at which "avalanche-breakdown"
and "thermal-runaway" take place.

The curves of Figures 18.1 and 18.2 are arbitrary but representative ones for tran-
sistors and are included to explain what some of the reverse diode characteristic tests
mean, and the points at which they are taken. In Figure 18.1, the collector to base
reverse voltage of a transistor versus the leakage current is displayed; the points of
interest are point A, the leakage current (Icno in this case) at a specified collector to
base junction voltage, and point B, the breakdown voltage (BVE,B0 in this case) at a
specified leakage current. Figure 18.2 illustrates some points which must be considered
when accurate breakdown voltage measurements are desired. The two transistors
shown have different reverse voltage characteristics. The load line of the measuring
instrument which is to approximate a constant current source may give slightly or
grossly erroneous readings if care is not exercised in measurement technique. The true
values of breakdown voltage are shown at points A. The slightly erroneous readings
are at points B on the two characteristic curves while the grossly erroneous data is at
points C.

458
 TRANSISTOR MEASUREMENTS 18

(EMITTER OPEN)

DESIRED LEAKAGE
CURRENT INFORMATION
ICB DESIRED BREAKDOWN
VOLTAGE INFORMATION

I
am I SPECIFIED VCB

vca BVcB0 SPECIFIED Ici3

REPRESENTATIVE COLLECTOR -
BASE JUNCTION REVERSE CHARACTERISTICS
Figure 18.1

COMPARISON OF MEASUREMENTS ON TWO TRANSISTORS SHOWING ERRORS THAT MAY

ARISE DUE TO TECHNIQUE- i.e., LOAD LINE CONSTANT CURRENT APPROXIMATION IS POOR
AND DOES NOT MEASURE DEVICE AT SPECIFIED CURRENT

BV„ o CHARACTERISTICS
TRANSISTOR I— TRANSISTOR 2

Cao

LOAD LINE
CONSTANT CURRENT
APPROXIMATIONS

V„ REVERSE VOLTAGE

BV I•1l MEASUREMENT TECHNIQUES

Figure 18.2

DC TESTS
The following abstracts include the definitions of particular tests and the associated
simplified circuits. The current measuring (ICBO, I ERO, etc.) circuits are discussed in
more detail in the next section.
1. IcB0, commonly called Ico, is the dc collector current which flows when aspeci-
fied voltage, VcBo, is applied from collector to base, the emitter being left open
(unconnected). The polarity of the applied voltage is such that the collector-
base junction is biased in areverse direction. (Collector is negative with respect
to the base for aPNP transistor.)
leo is greatly dependent on temperature and in some instances, transistors
must be handled with gloves to prevent heating the transistor by contact with
the operator's hand.

459
 18 TRANSISTOR MEASUREMENTS

1, , MEASUREMENT
Figure 18.3

2. IEso, commonly called I E0, is the de current which flows when a specified
voltage is applied from emitter to base, the collector being left open (uncon-
nected). The polarity of the applied voltage is such that the emitter-base
junction is biased in areverse direction. (Emitter is negative with respect to the
base for aPNP transistor). Io also is greatly dependent on the temperature and
the same precautions apply as for leo determination.

'EE O MEASUREMENT
Figure 18.4

3. IcE0 is the dc collector current which flows when aspecified voltage is applied
from collector to emitter, the base being left open (unconnected). The polarity
of the applied voltage is such that the collector-base junction is biased in a
reverse direction. (Collector is negative with respect to the emitter for a PNP
transistor.) IcEo is greatly dependent on temperature and the operator should
use gloves when handling transistor before measuring.

1-
T
v„

, MEASUREMENT
Figure 18.5

4. ICES is the de collector current which flows when a specified voltage is applied
from collector to emitter, the base being shorted to the emitter. The polarity
of the applied voltage is such that the collector-base junction is biased in a
reverse direction. (Collector is negative with respect to the emitter for a PNP
transistor.)

I . MEASUREMENT
Figure 18.6

460
 TRANSISTOR MEASUREMENTS 18

5. Ices is the dc emitter current which flows when aspecified voltage is applied
from emitter to collector, the base being shorted to the collector. The polarity
of the applied voltage is such that the emitter-base junction is biased in a
reverse direction. (Emitter is negative with respect to the collector for a PNP
transistor.)

_ VEE

MEASUREMENT
Figure 18.7

6. BVcE Tests —BVcEo, BVcER, BVcER, BVcEv

A BVcE test is ameasurement of the breakdown voltage of atransistor in
the common emitter configuration. For the measurement to be meaningful, a
collector current must be specified.

r;PE-CFIET-31 BVcEct
I CIRCUIT I
es4 I 1_ CONSTANT —CURRENT
BVCEV_y_ GENERATOR
VTVIA

v
TR
- • LT

(NOTE: BASE CONTACT IS S POSITION SWITCH)

Figure 18.8

In measuring BVcE breakdown voltages, a constant value of collector

current, Ic, is caused to flow in the reverse direction (collector is negative with
respect to the emitter for aPN Ptransistor) and the collector to emitter voltage,
VcE, is read on the meter. This voltage reading is the BVcE breakdown voltage
required.
In addition to a collector current specification, the condition of the base
lead must be specified.
a. BVczo is the common emitter breakdown voltage (for a specified collector
current, I
c)when the base is left open (unconnected).

b. BVcER is the common emitter breakdown voltage (for a specified collector

current, Ic) when aresistor of aspecified value, R, is connected from the
base to the emitter.
c. BVcEs is the common emitter breakdown voltage (for a specified collector
current, Ic) when the base is shorted to the emitter.
d. BVcEv is the common emitter breakdown voltage (for a specified collector
current, Ic) when the base is biased with a voltage with respect to the
emitter.

461
 18 TRANSISTOR MEASUREMENTS

e. BVccx is the common emitter breakdown voltage (for a specified collector

current, Ic) when the base is terminated through a specified circuit to the
emitter.

It should be strongly emphasized that BVcc, by itself, is meaningless

unless: acollector current is specified, the condition of the base lead is specified
(by the use of a third subscript), and, if the measurement is for BVcEE or
BVcEv, a definite resistor, R, or a definite voltage, V, are specified, or for
BVcEx adefinite circuit is specified.

7. BVcEo is a measurement of the breakdown of the collector-base junction with

the emitter open. A collector current, Ic, must be specified.

I CONSTANT-CURRENT I
GENERATOR

Mum MEASUREMENT
Figure 18.9

The emitter is left open (unconnected) as specified by the third subscript.

A collector current, Ic, is caused to flow through the collector-base junction
and the voltage drop VcE is the breakdown voltage, BVcao. Polarity is such
that the collector-base junction is biased in a reverse direction (collector is
negative with respect to the base for aPNP transistor).
8. VRT (reach through). Reach through voltage is that voltage which, when ap-
plied from the collector to base, causes the collector space charge layer to
expand into the emitter junction.

SIMPLE GO-NO GO V MEASUREMENT

Figure 18.10

In Figure 18.10, if, when switch "S" is closed, I c does not increase, the

punch through voltage is greater than Vcc. Punch through may also be meas-
ured by the use of the circuit shown in Figure 18.11.

VTVM
INPUT
R >10 MEG

ALTERNATE GO-NO GO \flu MEASUREMENT

Figure 18.11

462
 TRANSISTOR MEASUREMENTS 18

If VRR is less than 1volt, then VRT > (

VCC —1) volts.
The above Vim. tests are go-no go in character. By making Vcc variable
actual values may be determined; for example, in the circuit shown in Figure
18.12 one can adjust Vcc until the VTVM reads 1.0 volt, then VRT equals
VCB — 1volts.

VTVM
INPUT
R>I0 MEG

V,,, MEASUREMENT
Figure 18.12

CURRENT MEASUREMENTS
1. General
In this section the elaboration of the basic circuit into actual test equipment
(both qualitative and quantitative) is delineated. The necessity of saving time
in measurement is considered of importance; and means that constant voltage
and constant current techniques will be used. (Constant within the accuracy
requirements desired.)
Certain problems arise concommitant with constancy. A voltage source, by
definition, makes it difficult to limit the current through the ammeter in the
event of device failure; and current sources have large open-circuit voltages prior
to test, which can be damaging to the operator; and, due to circuit capacity, if
the device has an extremely short thermal time constant, the unit under test
may be damaged from the large instantaneous currents that can flow.
For the above reasons voltage and current "clamps" are resorted to in
order to have the required constancy and are discussed, with their limitations,
in conjunction with each class of test.
2. Clamp Circuits
In the circuits shown in Figures 18.13 through 18.16, the measurement of
IeBo is accomplished. In Figure 18.13, the basic form of the circuit is shown.
There is some error in this simple arrangement in establishing the test voltage
conditions since there is a small voltage drop across the meter. Also, if a unit
is shorted or has an excessively high leakage current, the microammeter may
be damaged. For meter protection the circuit of Figure 18.14 is used. The
diode used here is a large area diode which has a reverse leakage current
greater than that which is intended to be measured. If a 1N91 is used the
maximum leakage current which could be measured would be approximately
10 »a since this is the maximum reverse current which the 1N91 will conduct
when a small reverse voltage is impressed across it. To avoid this current
limitation and still protect the microammeter the circuit shown in Figure 18.15
is used. This circuit is basically a form of bridge so that if the drop through
the limiting resistor is not enough to bring the reference point (the collector)
below the clamp voltage, current flows through the diode and the voltage
at the reference is that of the clamp supply less the forward drop in the diode.

463
 18 TRANSISTOR MEASUREMENTS

LARGE
AREA
DIODE
VOLTAGE VOLTAGE

SUPPLY SUPPLY

BASIC Irno I, CIRCUIT WITH

CIRCUIT METER PROTECTION
Figure 18.13 Figure 18.14

When the drop through the limiting resistor exceeds the allowed value, the
current through the diode tries to reverse; thereupon, the diode becomes
back biased and the reference point is driven by a current source, where
Iiimit (which is considered afault condition, but meter
protection is accomplished by this current limiting).
Since the current under fault conditions is greater than the desired limit
(and it is desired to keep the overload on the ammeter as small as possible )it is
desirable to make the protection voltage much larger than the clamp voltage;
preferably 10 times larger. The reverse current of the clamp diode at the clamp
voltage must be considered, for it adds to the meter overload, and must have
abreakdown voltage much greater than the clamp supply. When the currents
that are being measured are appreciable (in the order of milliamps) the addi-
tional currents flowing through the reference (clamp) supply must be considered.
Thus if 1MA is the limiting current allowed, the clamp bleeder should carry
much greater currents (>10 MA) so that the clamp voltage does not change.
Where the test voltage is fairly low the drop through the ammeter or reading
resistor must be considered for this subtracts from the supply to the tested
device.
The go-no go test equipment of Figure 18.16 is designed to indicate only
that the device possesses specified, or better, characteristics. Generally this type
of equipment is designed individually for each requirement and has only
limited flexibility.

CURRENT LIMITING RESISTOR

• R REF VOLTAGE LOW CURRENT

v PROTECTI ON SOURCE DIODE

V TES T-
GO - NO GO
OR CLAMP
POINT AT
CLAMP - VOLTAGE
SUPPLY V TEST

ITEST V SOUR CE + V TFST

COMPLETE I, GO-NO GO I,
TEST CIRCUIT TEST CIRCUIT
Figure 18.15 Figure 18.16

464
 TRANSISTOR MEASUREMENTS 18
From the Figure 18.16 circuit go-no go BVeno tests can be made by using
acurrent source whose value is that at which BVeno is defined. In this case the
Ven voltmeter will indicate that the voltage is less than (km, is excessive), equal
to, or greater than the required test BVeno voltage (Ien° is less than the allowed
current limit). The current for the voltmeter must be considered, and its
accuracy at the limit point ( VT) must be checked to put the reject-line on the
meter at the correct point. Once this has been done the readings are as
accurate as the initial calibration and the stability of the power supply. To
prevent overloading the voltmeter and to avoid the large open-circuit voltages
at the test point, the current source is often voltage-clamped where the desired
test voltage is less than that of the clamp. When this is done the circuit bears
aclose resemblance to the kilo test circuit of Figure 18.16.

LARGE-SIGNAL (DC) TRANSISTOR CHARACTERISTICS

The large-signal transistor characteristics may be divided into two categories with
the line of demarcation being the difference between high-frequency pulse response
and the dc parameters useful in control-circuit and some computer applications. The
pulse response characteristics are discussed in alater section.
In the following curves Figures 18.17 and 18.18, the significant points of interest
are described on the transistor family of curves where le vs. W Eis plotted for various
In values.
RANGE
EXPANDED
TO ILLUSTRATE
POINTS

VARIOUS
VALUES OF

VCE(SAT)
R (
SAT) — SPEC Ic

RANGE OF
VCE (SAT) VCE

KNEES IN 1B FAMILY WILL APPROXIMATELY DESCRIBE A

FORWARD DIODE CURVE.

VCE (SAT) AN D R(SAT) FUNCTIONS OF I

, AND 1-
Figure 18.17

\ I
\I
IC(MAX) STEADY STATE IS AT

POINT OF INTERCEPT OF
Vms „KNEES AND ALLOWED
DISSIPATION CURVE.

MAX POWER
DISSIPATION
CURVE

I. STEADY STATE
Figure 18.18

465
 18 TRANSISTOR MEASUREMENTS

LARGE SIGNAL DEFINITIONS AND BASIC TEST CIRCUITS

1. hrE is the static value of the forward transfer current gain in the common
emitter configuration and is measured as shown in Figure 18.19. It is the de
collector current, Ic, divided by the de base current, Is; hFE = —
Ic

PROTECTION
RESISTOR
(OPT I
ONAL)

h, , MEASUREMENT
Figure 18.19

The collector voltage, WE, and the collector current, le, must be specified. A
go-no go test for lice may be used, as shown in Figure 18.20.

I CONSTANT CONSTANT
CURRENT CURRENT
GENERATOR GENER ATOR
'7=

L J

GO -
NO GO h, CIRCUIT
Figure 18.20

In the method shown in Figure 18.20, In is adjusted to give the base current
required for an hrE of the required value, Ic is adjusted to the specified value
, I
C
"=nra•
If VcE as read on the meter is less than that given in the test specifications,
then the hrE for the transistor is greater than that required. If VcE is greater
than the value specified, then hrE is less than the required value.
2. VCE (NAT) is the voltage from collector to the emitter, VCE, for a given Ic and I
E
while biased in the collector saturation region. The test is very similar to that
for hrE in Figure 18.20. Ic and Is are adjusted to their specified values and VCE
as read on the meter connected from collector to emitter is VCE (SAT).

466
 TRANSISTOR MEASUREMENTS 18
3. VBE is ameasurement of the base to emitter voltage, Vs, when in the common
emitter configuration and biased according to instructions given in the test
specifications. A circuit similar to Figure 18.20 for hrE may be used with the
addition of avoltmeter (VTVM) between base and emitter.
4. h1E is the equivalent (slope intercept) resistance equal to VBE/IB. This test
is generally made at a specific Is which is sufficient to saturate the device
when it is driven by aspecified Ir. This information finds maximum applica-
bility in switching and computer applications.
5. hut is equivalent to hiE except with the transistor operated in agrounded-base
configuration. This resistance is an indication of the forward drop in the
emitter, and finds application in some power transistor considerations, in bias
requirements for some small-signal transistors, and in some regulated power
supply applications.
6. Ic MAX must be considered for two different applications,
a. Steady state—Ic max. is determined by the intercept of the curve of the
"knees" of the collector saturation points with the maximum allowable
power dissipation curve.
b. The second consideration of Ir max. involves the duty-cycle of the on
times for switching applications and is dependent on the duty cycle of
the circuit being used.

VAR IOUS
POWER

I, MAX AT DIFFERENT DUTY CYCLES

NOTE: DRIVING POWER IN THE

BASE MAY NEED TO BE
SUBTRACTED FROM MAXIMUM
IC ▪ (S) MW ALLOWED POWER (DEPENDING
ON PERCENTAGE OF TOTAL)
▪ (A) MW IN ORDER TO PLOT POWER
I, MAX "STEADY STATE" CURVES AT LEFT.

VC E

I CHARACTERISTICS

Figure 18.21

SOME TEST CIRCUITS

Methods of test and equipment for almost all parameters may be divided into
two basic categories: (a) quantitative and evaluative equipment for engineering,
and (b) go-no go equipment for use when the limits of allowed variance of a
particular parameter have been determined and specified. The equipment required
for the engineering measurements of dc parameters consist primarily of precise power
(current and voltage) supplies, and reliable and precise (as well as often very sensitive)
voltmeters and ammeters. The following section will be devoted to both quantitative
and go-no go equipments and circuits in use.

467
 18 TRANSISTOR MEASUREMENTS

1. hEs measurement is accomplished in the circuit of Figure 18.22. The potenti-

ometers are adjusted in the base and collector circuits to establish the proper
measurement conditions; namely, since hE E is a function of both VrE and Ir,
these two quantities must be specified. When the desired l e and Ves conditions

are established the hEs can be determined. As has been stated hEE = 'ens; thus
two current reading resistors, RI and R2, are inserted into the base and collector
circuitry respectively. RI is made very much smaller than RB, and R2 is made
very much smaller than R. Using a Helipot, R3, whose resistance is much
larger than R2, the voltage drops across RI and R2 can be compared. When RI
is equal to R2, for example, and a null is established on the VTVM when the
Helipot reads twenty thousandths (20/1000) of full scale then the hEE =
1000/20 or 50. If RI = 10 R2, agreater range of the Helipot can be used and,
in the example above, anull would be established at two hundred thousandths
(200/1000) on the Helipot indicating hE s = 1000/200 x 10 = 50. On the
physical test equipment the Helipot could be calibrated in hEE for direct reading.

NOTE: IN ALL OF THE hFE AND VcE (SAT) TEST CIRCUITS, IT MAY BE

NECESSARY TO "CLAMP" THE BASE AND COLLECTOR SUPPLIES

TO PREVENT DAMAGE TO EXTREMELY SENSITIVE AND LOW—
POWER UNITS.

RI«R B

CALIBRATED IN hr E (HELIPOT)

R3>>R2
DIFFERENTIAL
MILLIVOLTMETER LOW RI MAY BE SOME MULTIPLE
CURRENT AND SENSITIVE OF R2 AND ACT AS
MULTIPLIER OF hFE

READ ON R3

QUANTITATIVE h, MEASUREMENT
Figure 18.22

2. hrs go-no go equipment is normally built using aconstant collector current and
classifying hr. according to required base current as shown in Figure 18.23.
When the desired Ves and Ie measurement conditions are known, acircuit can
be built as shown to classify the devices. If VrE reads below the specified
measurement condition, the hE E is greater than that established by the fixed
resistors and supplies; if the Vv 5 reads higher than that established as a
measurement condition, the hr s is lower than that established by the circuit.
3. The WE (sAT ) measurement, Figure 18.24, is often made by applying a speci-
fied Ir to the transistor and increasing IBuntil an abrupt change in Ves indi-
cates that the collector voltage has dropped below the knee of the collector
curve; however, in specifications both le and I B are specified. IB is usually

468
 TRANSISTOR MEASUREMENTS 18

0002Ic
—AAA
IcrSPECIFIED
CONSTANT

AMMETER

TVcc

CLASSIFIES h„ BY

VcE INDICATION

hi
., CLASSIFIER
Figure 18.23

sufficient to saturate the device; and, in go-no go testing, noting that Vci.; is
below some specified voltage, or that it is within certain specified limits is
normal procedure. The latter being of particular importance in computer
applications where maximum and minimum Vck; (SAT) values are relied upon.
Two circuits in which measurements can be performed are shown in
Figure 18.24.

ONE OR MORE
Ic'S MAY BE
SPECIFIED

IN PLACE OF THE VTVM MILLIVOLTMETER SHOWN ABOVE A REFERENCE (NULL)

COMPARATOR MAY BE USED FOR GO-NO GO TESTS

IN9IS
FOR METER PROTECTION I%

I% MERCURY
REF CELL
DIVIDER REFERENCE
VOLTAGE

VI•E (SAT) MEASUREMENT

Figure 18.24

469
18 TRANSISTOR MEASUREMENTS

JUNCTION TEMPERATURE MEASUREMENTS

JUNCTION TEMPERATURE (T 3)
The measurement of junction temperature, depends on one of two temperature-
sensitive mechanisms inherent in the junction device. These are the exponential rise
of the reverse diode saturation current, and forward diode voltage decrease with tem-
perature. In most instances experience has shown that calculated theoretical changes
of leo and VFare too gross (due to rather large "second-order" effects) to be sufficiently
accurate indices of junction temperature; and the test device must, in fact, be calibrated.
This requires that the unit be temperature cycled in an oven (allowing sufficient time
for the device to stabilize at each temperature or using a large, high thermal-
conductivity heat sink) and aplot of the desired index vs. temperature be made. Power
is applied to the device in the forward direction, or through the application of bias
current. This power is then momentarily switched off and the built-in thermometer
checked by asuitably gated meter. The off time is either kept negligibly small when
possible, or else considered in determining the average input power.
Both the leo and VFmethods are alike in having alarge possible error due to the
thermal response-time of the device. If the temperature at the junction declines
rapidly, the resultant apparent value of T., will be lower and fall somewhere between
the true T1 and that of the thermal mass.
The reverse-current method suffers the additional handicap of charge-storage in
the junction when the forward current is reversed. This charge must be swept out by
the reverse voltage before atrue indication of Icno can be obtained, a race between
charge and thermal decays results. In the large area device of relatively small effective
lifetime, the error will probably not be large, but the current metering system must
be gated to prevent the charge-decay currents from registering. No peak-reading
detectors can be used; although if the charge decays rapidly enough compared to the
measuring time, and TTis reasonably constant during this interval; an average reading
metering system is sufficiently accurate, if suitably calibrated.
In the case of the small-area, long lifetime device the problem is more difficult.
The masking effect here precludes reverse measurements and only forward measure-
ments are feasible; there are still storage problems, but switching presents the major
difficulty. Fast-acting mercury relays are generally used to prevent contact bounce
and carry the required currents without large contact drops.
There are decided advantages to using forward voltage drop as the T., index from
the point of view of the circuit requirements. Since the detector (meter) circuit is
driven by avoltage source the system is less liable to pick up extraneous hum that
can plague the reverse-current measurements. (Particularly when Ica° is low, as in
silicon devices, where the current reading resistor is necessarily large.) Unfortunately,
however, the change of VPis comparatively small and the "thermometer" is therefore
relatively insensitive. This may require differential amplifier techniques in the detector
circuit for precise measurements of TT.

THERMAL IMPEDANCE
Once ameans of measuring T, has been developed, the measurement of thermal
impedance is readily accomplished. The simplest means of measuring the case tem-
perature — such as a thermocouple or large heat sink — may be used, and different
powers are fed into the transistor while measuring Tr. By defining thermal resistance as
the input power required to raise T., to some arbitrary temperature, (say 70°C) and
measuring this power at different ambients, sink or case temperatures, we may write
the following definition:

470
 TRANSISTOR MEASUREMENTS 18

if xwatts = 70°C T3 from 25 °C Link

and ywatts = 70 °C T3 from 45 °C Link
Then,
45° -25 ° 20
= — per watt
x-y watts x-y
we can draw aderating curve through these intercepts as shown in Figure 15.25

POWER /TEMPERATURE
DERAT1N6 CURVE
(SLOPE

20 25 4045 60 70 80 :00
TEMPERATURE - C

POWER VS. TEMPERATURE DERATING CURVE

Figure 18.25

TEST CIRCUIT FOR JUNCTION TEMPERATURE MEASUREMENTS

1. Description of Operation
Under certain conditions, the forward drop of a semiconductor junction
varies linearly with temperature. By setting up these conditions and using a
test circuit similar to that of Figure 18.26, it is possible to determine the
temperature of a transistor collector junction for various power dissipations in
the transistor.

E≥: 100V
PS
Vc SUPPLY
RI 4 N.C.
•
R4 11 12 3
10K 3 N.O.
I —_,;
CR3 114
SCOPE IN495 I R6 I IE SUPPLY
_10K,1/2W i '2
1
71 17

I
W.E. 2751311 K2 R2 K1 11 W.E.27513
•
ezt RI 3K,5W,W.W. 8
IN93

CRI IS USED TO
R5 j SUPPRESS OSCILLATIONS
110 V 60".• I5K,5W,W.W.' ,
CR2
IN93
R3
2K,5W,W.W.

NOTE: POLARITIES SHOWN FOR NPN. TO

USE FOR PNP, REVERSE POLARITY
OF POWER SUPPLIES AND DIODE
CR3.

Figure 18.26 THERMAL MEASUREMENTS TEST CIRCUIT

471
 18 TRANSISTOR MEASUREMENTS

The circuit shown is one of several variations which can be used. IC1 is a
mercury relay (W. E. 275 B type) which interrupts the circuit in which the
transistor is heated. K2 is another relay of the same type that puts the transistor
in atemperature measuring circuit when it is not in the heating circuit. The
relays operate at 60 cps. The transistor under test is heated for about 80% of
the time and its forward drop (temperature) measured during the other 20%.
If the scope were put directly on contact No. 3 of K2, the presentation would
be similar to that shown in Figure 18.27.

HEATING MEASURING HEATING

TIME TIME TIME

11 -K2 CLOSES
12 -KI OPENS
13 -KI CLOSES
14 -K2 OPENS

1B Vf
1
1
3 -t2 < 4 MSEC

2 -1 1} AS SMALL AS
ht-t3 POSSIBLE

1 4-r-
tr

2 1
3

TIME -•

OSCILLOSCOPE PATTERN
Figure 18.27

In this presentation, V, is the forward drop of the collector junction while

it is in the measuring circuit, and VCB is the collector to base voltage while in
the heating circuit. The scope vertical amplifier is normally set to the range
that will best show the variations in V. Under this condition, Ws is of such
magnitude that it would overdrive the scope and cause distortion of the V,
presentation. To prevent this situation, aclamp consisting of R4 and CR3, is
inserted between the scope and contact No. 3 of IC2. This minimizes the
possibility of overdriving, but still allows the monitoring of Vf. Since Vfvaries
linearly with temperature, the changes in junction temperature can be deter-
mined by measuring the changes in V.
Now, back to the conditions mentioned earlier. The first of these is that
the measuring current (I,) through the junction during the measurement must
be held constant. This requirement is met by using apower supply (PS) with
V .= 100 volts and ahigh resistance (111).

Another condition is that If be set to such avalue that dV,/dT will be a

constant over awide range of temperature T. Based primarily on calibration
tests of several types of transistors, If should be adjusted to give aVf 500 mv
at 27°C for silicon junctions and aVf 200 mv at 27°C for germanium junc-
tions. This is accomplished by adjusting the value of RI. Once the conditions
are met, the final requirement is that the value of dV,/dT be known.
dVddT for different transistors can be determined by placing the units in
an oven, adjusting If to the value specified in above paragraph and then
measuring Vfat different oven temperatures. Sufficient time must be allowed

472
 TRANSISTOR MEASUREMENTS 18
for the junction temperature to reach that of the oven as mentioned earlier.
This would be the most accurate value of dVf/dT to use since it is deter-
mined for each transistor on an individual basis. A more convenient, but less
accurate method, would be to take the average value of several transistors of
the same type. Here the accuracy of the value of dVf/dT would be dependent
on the spread, but in general would be within the accuracy of the temperature
measuring circuit described.
2. Procedure for Determining Junction Temperature
a. Determine dVf/dT for the transistor collector junction.
b. With Ve = 0, and IE= 0connect transistor to terminals CBE of test circuit.
Handle transistor in such amanner that its temperature is not raised above
ambient (use gloves, etc.). Adjust R5 for time relationships shown in
Figure 18.27.
c. Adjust RI for a reading of Vf on the scope equal to 500 mv ± (27° — T
amb.) X dVf/dT.
d.
Set Vc and JEto desired bias conditions.
Vf)
e.
Note change in V. TJuno = Tomb +
dVf/dT
3. Procedure for Determining Thermal Resistance from Junction to Ambient
a. Determine junction temperature as above.
b. Measure power input to the transistor to give this temperature rise.
= VcE max. X Ii max. X duty cycle).
c. Thermal resistance from junction to ambient (Om) is then computed,
Ta.mblent
eiA =
Pin

EXAMPLE:
A 2N657 transistor (a silicon NPN mesa with pellet mounted directly
on flat metal header) is calibrated in an oven with It adjusted to give a
Vf (V08) of 500 mv at 27°C. The slope dVf/dT was found to be 2.5
mv/ °C. It was desired to find what power was required to raise the junction
125°C above ambient and to determine the thermal resistance from junction
to ambient at 149°C; room temperature = 24°C.
1. The transistor was connected to the terminals provided on test set up.
Ve = 0and II: = O.
2. RI was adjusted to give a Vf of 500 ± 3° (2.5 mv/°C) or 507 mv.
(This took aresistance of nearly 20 megohms.)
3. For the junction temperature to rise 125°C, the voltage Vf in step 2
would have to drop by 313 mv (125 x 2.5). VeE supply was set at 25v.
IEwas then increased slowly until Vf dropped to (507 -313) or 194 mv.
4. The voltage from C to E read with aWeston analyzer was found to be
20.0 volts. (This is an average voltage). The current in the emitter,
read with a Weston analyzer in the emitter current lead, was found
to be 33.3 ma. (Average value.) Thus the power dissipated in the tran-
sistor was approximately equal to

20.0 X 33 I.v X E.v

or 834 mw. Pin =
0.8 duty cycle

473
18 TRANSISTOR MEASUREMENTS
T1 T4
5. Since 01A = D
1 in

then eJA_ 24 0.149° C/mw

834
4. Procedure for Determining Thermal Resistance from Junction to Sink
The thermal resistance from junction to sink is auseful parameter for com-
puting operating junction temperature of a sink mounted transistor from the
input power and sink temperature. Junction to sink thermal resistance can be
calculated using the same procedure as used for 0,A with the exception that
sink temperature is now used instead of ambient temperature. The heat sink
will be more efficient if it is placed in contact with the surface on which the
pellet is mounted. For instance, units which have the pellet mounted on the
header should have the heat sink placed in contact with the header, giving an
excellent thermal path. The contact between the sink and the transistor header
could be achieved by holding the unit tightly against a2" x2" x %" piece of
copper by asteel washer clamped down on the transistor flange. Holes are only
large enough so that the insulated transistor leads can pass through. Silicone
grease is spread over all contact surfaces to provide a better thermal path
between the transistor header and the copper. The sink temperature can now
be measured by placing the thermocouple between the bottom of the copper
fin and the nut as indicated in Figure 18.28.

TRANSISTOR

HEAT SINK NUT

THERMOCOUPLE LEADS

THERMOCOUPLE PLACEMENT
Figure 18.28

Once case temperature is established, e's can readily be obtained by using

the same procedure as used to find 3%. 0

SMALL SIGNAL MEASUREMENTS (AUDIO) OF TRANSISTOR

PARAMETERS
The two most familiar matrices (the zand y) proved to be difficult to apply to
transistors in practice, for driving the collector of a transistor with a current, in
measuring z.B, required large source impedances; and driving the input to the
transistor with avoltage source, as in measuring yu., could produce large errors due
to the current sensitivity of the device. (Base currents when multiplied by ht, could
cause current clipping in the collector.)
To overcome these disadvantages the hor hybrid matrix was proposed and became
commonly used. The device characteristics that make the hmatrix most useful at audio
and low rf frequencies change appreciably as the frequency is increased. Above
30 mc the terminal requirements become increasingly difficult to obtain; measure-
ments at these higher frequencies will be discussed in next section, (High Frequency
Small Signal Measurements of Transistor Parameters).

474
 TRANSISTOR MEASUREMENTS 18
Consider the terminal requirements of the h matrix, and how they may be
obtained in practice. The matrix is described as follows:
he = edi, when e2 = 0(Input impedance, short circuit output)
h. = el /e2 when i, = 0(Reverse voltage ratio, open circuit input)
112, = 12/i, when e2 = 0(Forward current gain, short circuit output)
11,2= i2/e2 when i, = 0(Output admittance, open circuit input)
These matrix quantities are defined for either common base, common emitter or
common collector configuration. Originally 270 cps was the audio frequency used in
parameter determination, but today 1kc is used more frequently although both are
still common.
In establishing the correct a.c. conditions several considerations are of importance.
In establishing these conditions, the desired percentage of accuracy will be used as
the factor which will determine how well the ideal measurement conditions are
realized. 1/(Desired Percentage of Accuracy) will be called (DPA) -1 ;thus, if the
desired accuracy is 5% then 1/.05 = 20 or (DPA -= 20. The following notes on
each measurement show where errors may be introduced and indicate what conditions
must be established for measurements to be of desired accuracy.

COMMON BASE CONFIGURATION

1. bib (hub) hlb = eg

eg enolse
VTVM
z,

v„
SIGNAL
GENERATOR

IE
CURRENT
SOURCE

h MEASUREMENT
Figure 18.29

For desired accuracy,

Zv Zg Zg'
zg zg' zg zg , (DPAY' 11113 (MAX)
≥ (DPA) -'hob MAX (for all tests)
en.,.. <<e ghib MIN

2. he, (hub) he, =

475
18 TRANSISTOR MEASUREMENTS

Z,
SHIELD
r

SIGNAL
GENERATOR

e, 1- efl.se

1E
CURRENT
SOURCE

h„ MEASUREMENT
Figure 18.30

z. = effective leakage impedance

For desired accuracy,
e„ <<V,b
I
c R2 <<Vb

z,'
z. > > ,≥ (DPAP hib MAX

enoi «10' 4 eg

—
1 ≥ (DPA)' hob MAX

3. hrb (h21b) hfb JUMPER FOR

CALIBRATION
OF Ilfb 1.0

/ I 2=eziRL

cIt
SIGNAL -Ay- RL VTVM e2-t
- enoise
GENERATOR / =
• z9 ,

SHIELD
VCC

CURRENT
SOURCE

Figure 18.31 hi,, MEASUREMENT

V2
=
For the desired accuracy use the same considerations as for hie and,
1
Hob MAX
RL
(RI, is normally less than or equal to 100 ohms average)
z„ z„' ' (DPA)'
zg z„
i„ <<Ic

4. he,. (h22b) h0,. = in ;ig ey since L. is small.

e„

476
 TRANSISTOR MEASUREMENTS 18

SHIELD je
41—

o
ea
9
(!)
RL VTVM
enoise

RI
Vec

Figure 18.32 h„ MEASUREMENT

For the desired accuracy use the same considerations as for hrt, and,
ej: hob MIN RL>>enol

1
z.>> ≥ (DPA)'Rh
t. MIN —
Mob

[ ICBM ± (1 ± hFII) I
E] RL<<VCC
QWL (DPAY' Rh at measuring frequency
To satisfy some of the above Rh requirements and yet have xi. large enough
to have sufficient sensitivity; a parallel resonant circuit of low series R is
bridged across Rh to reduce the dc drop.

COMMON EMITTER CONFIGURATION

When considering practical measurements of grounded emitter parameters it is
also necessary to consider the dc bias requirements. It immediately becomes apparent
that each transistor will require base bias adjustments to obtain specified base condi-
tions. Since it would be preferable to avoid this time consuming operation and particu-
larly so when many units must be measured, aquasi grounded emitter circuit is used.
Through the use of high Q, parallel resonant circuits, the device sees agrounded base
bias supply and an ac grounded-emitter configuration. Of course this technique is
applicable to fixed-frequency measurements only. It is also necessary to consider the
current multiplication of input measuring currents appearing in the collector circuit.
To maintain small signal requirements steps are taken to insure that these collector
signal currents will be much less than the de bias currents. (See Introduction, to this
chapter.)
1. hi.(1111.) hi. =
V CC

4—
02

VTVM

SIGNAL Zv
GENERATOR
NORMALLY CLOSED
CI PRESS-TO- READ
SWITCH
1E

VE
zQ. L
Figure 18.33 h,. MEASUREMENT

477
18 TRANSISTOR MEASUREMENTS

Coils used are high Q toroids in which de saturation must be considered

when certain bias conditions are used.
For the desired accuracy,

ig <<
life MAX

I
ERI <<Vc,
Zr Zp
(DPA) -1 hi,» MAX
Z, Zg —E Z, Zg —E Zp Zg

1<<re at specified I
E
wC
kT
where r, 26 Çl at I
F: = 1ma (see Introduction this chapter)
qIE
coC2>> h..
blIN

The press-to-read switch is incorporated to prevent charging Cl to VE

when no transistor is in the socket. Otherwise, the discharge of the capacitor
may destroy aunit as it is inserted into the socket for test.
9. hr. (hi.2.) h,, ei
ec

e
g

1 I SIGNAL
R2 'GENERATOR
e, +en.00
CI _
VTVM PRESS -TO-
READ
zv

Vec C2
tI,

h, MEASUREMENT
Figure 18.34

Cl, C2, and RI are the saine as for

For desired accuracy,
I. R2 <<V..
e. <<V..

z. > > —°
zzy ≥ (DPA)' hi. MAX
Zp Z,

e..i.. «h.. MIN eg

1
(DPA) ' hoe MAX
Zg

. e2
3. hi. (112,..)
1g RL

478
 TRANSISTOR MEASUREMENTS 18
JUMPER TO CALIBRATE hie .1

SIGNAL
GENERATOR

Figure 18.35 h,, MEASUREMENT

For the desired accuracy, use the same considerations as for hi0 and,
enolee «is RL

1
RL<< is generally about 50 ohms.

4. h.. (11) h, = ; e"

e. Ri,

SHIELD

I
L

RI
t. se
e,
9
CD
R2
SIGNAL
GENERATOR

L.
RL VTVM L_
PRESS TO READ

Figure 18.36 h MEASUREMENT

z., RI, R2, Cl, and C2 same as for h,.

For the desired accuracy,
zi,>> hi.21.2x (R. -I- RL)
el.!" «hoe MIN RLeg

e. <<Vo.

COMMON COLLECTOR CONFIGURATION

Common collector parameters may be calculated from measurements of common
base and common emitter. Notice that the two parameters not identical to those in
common emitter configuration are in one case almost equal to hi. and in the other
almost equal to 1.
1. hi. = hi.
2. hr. (hi2.) h.. =
e.

479
18 TRANSISTOR MEASUREMENTS

SIGNAL
GENERATOR

PRESS -TO-
READ

Figure 18.37 h, MEASUREMENT

Driving. conditions are the same as for h,.; however, es <<VER, also
h,. 1.0 and deviations from unity are difficult to measure.
. es
3. h,. (112,.) ht.= ;12

SIGNAL
GENERATOR

Figure 18.38 h,, MEASUREMENT

Driving considerations are the same as for 14, if R1, is kept small; otherwise,
zo ≥ (DPA) -1 (R. +
hf. hf.
1
h " = 1+ hrb

4. hor = ho.

GENERAL
Some of the parameters mentioned are particularly difficult to measure, the
terminal requirements difficult to obtain, or particularly sensitive to temperature.
When measuring 11,b it is found that as this parameter approaches unity, the difference
is increasingly hard to detect. Instead, hr. could be measured and h,b calculated; or an
attempt to measure 1-I- hrb could be made instead. A circuit for measuring 1± ha,
is shown in Figure 18.39.

1+ = , = e!
i
s RL

480
 TRANSISTOR MEASUREMENTS 18

CALIBRATE I.h b 1.0

WITH JUMPER

L_

SIGNAL
GENERATOR

IE VTVM
RL V CC
zp .C)L e2+ eno,

1 h, MEASUREMENT
Figure 18.39

Considerations for obtaining accuracy are,

z„ Z.'
zg' (DPA) -1 (hib -I- Rt.)
z. (DPA)'
enolee << (1 hfb MAX) RI. in

wC2> > hoe MAX

However, since RLappears in the collector loop, the collector is not really short
circuited, and RLmust therefore be kept quite small. On the other hand, it must be
insured that ig << IE(in the order of 0.1 ma RMS for 1.0 ma 1E). Now the maximum
current that will flow through RLwill be 4, when hu, = 0, therefore in practice
RL= 10' X 10 2 or about 10 mv at most. Since, too, it is preferable to measure up
to hib = 0.999, the ability to measure 1-I- hn, max. X j
5 RI,= about 10 microvolts is
necessary. Some available VTVM's do not have sufficient sensitivity for this measure-
ment and either selective VTVM's or pre-amplifiers must be used; at this point, noise
and "pick-up" become important considerations.
Similar important considerations also arise in measuring h... In order to maintain
the collector signal current within the required small signal level, one must start with
10 amps and areading resistor of 50 ohms max, assuming 1.0 ma de collector current.
This output signal of 5mv is the maximum signal level in the collector. To measure h,.
up to 1000, one would have to insert abase signal current of 10 -7 amps; and calibrating
by inserting this signal into the 50 ohm resistor, it develops that only 51.Lv of signal are
available and the permissible noise background is less than 0.5 eiv.
To illustrate amethod whereby most of these difficulties may be eliminated by a
different technique of measuring, the circuit of Figure 18.40 is considered.
In this instance aconstant signal voltage (say 10V) and a unit of resistance are
used that will limit the signal current to that permissible in the collector circuit. At
50 ohm and 0.1 ma areference signal of 5mv exists, which is readily measurable. The
unit of resistance is 100 K. Now units of resistance are inserted in the base circuit (ac)
until the collector current returns to the reference level. The number and fractions
thereof of units of resistance will read hr, directly; and the result is that acalibrated
decade resistance box is used to read 111.. At 1 kc accuracy is not limited by the
resistors, but rather by the 1/2 to 1% resetability of the VTVM pointer. By using a

481
 18 TRANSISTOR MEASUREMENTS

DECADE OF 1
Kft EACH STEP
01 % DEPOSITED
CARBON RESISTORS
HUNDREDTHS

• DECADE OF IOKS1 EACH STEP

Vm
TENTHS

DECADE OF 100Krt EACH STEP

hf. =NUMBER OF UNITS UNITS

INDICATED BY DECADE
BOXES + IUNIT DECADE OF 10 MEG EACH STEP

TENS
NOTE. BY INSERTING A 20db
ATTENUATOR BETWEEN
THE SIGNAL GENERATOR
AND THE DECADES, THE 1UNIT OF RESISTANCE
READINGS OF hte ARE 100 KB
MULTIPLIED BY 10.

R, VTVM

500

NORMALLY
CLOSED
PRESS
TO READ

ALTERNATE h, MEASUREMENT
Figure 18.40

selective VTVM with an expanded scale, such as the Hewlett-Packard 415B,

(VSWR indicator) resetability and accuracy can be improved to better than 0.2%.
The limitation now is the accuracy with which the temperature of the unit under test
can be maintained since hr1 is temperature sensitive.

HIGH FREQUENCY SMALL SIGNAL MEASUREMENTS OF

TRANSISTOR PARAMETERS
GENERAL
The subject of high frequency h parameter measurements is considered in this
section. Measurements from 100 kc to above 300 mc are considered.
1. Common Base -Common Emitter
Several considerations must enter into making asmall signal measurement
other than the high frequency techniques. Of importance is the time required
and, in common emitter measurements, the effect of the de shunt paths. For
both of these reasons, all of the common emitter measurements are made in the
pseudo grounded emitter configuration where, to dc, the circuit appears common-

482
 TRANSISTOR MEASUREMENTS 18
base. This was described in the last section. All of the considerations described
there are equally applicable at high frequencies.

2. Broad-Band Measurements
Common base broad-band measurements are feasible up to 100 mcs with
care in circuit layout and due attention to socket capacity, etc. Common
emitter measurements are broad-band in a very limited sense. By picking a
sufficient number of spot frequencies data are obtained to draw a curve of
parameter vs. frequency. The spot-frequency approach results directly from
the circuits which will be described.

INPUT IMPEDANCE :(111b, lb.)

I. 200 kc to 5mcs
For this measurement the British Wayne-Kerr Model B601 Itridge was
found to be the most suitable. By using suitable multiplier taps it will measure
from a few ohms to more than one megohm of R parallel and reactances of
± several hundred ¡if with reasonable accuracy. However, some reactance
errors arise in measuring low parallel R values, due to inductance inside the
bridge.
A receiver is used as the bridge detector. A unit with a few av sensitivity
and afrequency range of 200 kc to 5 mcs. This detector sensitivity is manda-
tory, since the maximum signal voltage the bridge applies to the input of the
transistor must be less than 5mv, if overdriving the unit and distortion are to
be avoided. Since small-signal conditions are to be maintained, the ac cur-
rents permissible should be at most 10% of the de bias currents. Assuming
1.0 ma I E and 50 ohms of hie then the maximum input signal voltage is
10 x 50 = 5 mv. Now for common-emitter operation, (assuming 1 + hfb
of .01), the base current is 10' amps. For 500 ohm of hi, the maximum signal
swing is 10' x 5 x 102 = 5mv. These figures are arbitrary, but realizable, and
show the need for care. A suitable substitute is to incorporate means of reading
the ac current in the collector; and, abiding by the 10% rule, the input signal
is adjusted to the maximum permissible. The signal generator used is aTektronix
190 with the attenuator fixed to limit the input signal to the bridge. Since the
Tektronix 190 starts at 375 kc this is the lowest frequency measured. Another
generator, such as the Hewlett-Packard 650-A will extend the low frequency
range. Test circuits are in plug-in boxes, for connecting to the bridge and are
shown in Figure 18.41( A).
2. 1to 100 mcs
At higher frequency the small signal terminal requirements of h param-
eters (viz, open and short circuits) are progressively more difficult to obtain.
In general, the input impedances are lower due to decreasing current gain
and shunt reactance effects. The requirements of low driving signal voltage
and the detector sensitivity demanded are even more stringent.
The Wayne-Kerr Model 701B Admittance Meter is used with a Halli-
crafter SX-82A receiver as the null detector. Mathematical conversion from
the parallel admittances to the required series R. -±- jX, will be necessary. The
generator used here is aMeasurements Corp. Model 80 with a2mc to 420 mc
frequency range. Since the Wayne-Kerr Model 701-B bridge has a 3:1 step-
down transformer built in, the signal input to the bridge is limited to 10 mv
maximum. The circuits used in measurements are shown in Figure 18.41(B).

483
 18 TRANSISTOR MEASUREMENTS

R fC
SIGNAL GEN P- P
RECE IVER
TEKTRONIX 411,
--111 WAYNE-KERR
190 13601 BRIDGE (DETECTOR)

'«Î—II
TTTT TEST CONNECTORS

TEST BOX

hib
0,1
hie 3x,.0>fd 0,1

r
1. BRIDGE

L
V CC

BRIDGE DIAL RANGES:

IE SUPPLY C TO 240 pl
R TO 100 KG

(A) UP TO 5 MC

hit)
SIG. ADMITTANCE
GEN. BRIDGE DE T ECTO R 0.001 M MY
(MODEL (wAyNE- 9-411HALLICRAFTER
*80) KERR) SX-62-A
BRTID
O GVI
C
TERMINAL
0.02
VC
• 4.7K 04. r.02_1_
... 9.001
H.1? 4000
NULL
VOLTMETER 5.IK

IMM

IE SUPPLY V
c SUPPLY

LAYOUT IS
EMPHASIZED
hie E

WAYNE-KERR DETECTOR
SIG. GEN.
13701 G. R. CQ 30 /AC
TEKTRONIX
ADMITTANCE "UNIT" I. FAlAPL
•190
BRIDGE 4111216-A TO
BRIDGE

750

VE

E
TO VE
Vc SUPPLY
SIP PLY

(B )UP TO 100 MC

Figure 18.41 h., AND h,,. MEASUREMENT

484
 TRANSISTOR MEASUREMENTS 18

3. 30 Mes and Higher

Two different Rohde and Schwartz Diagraphs are being used above 30 mc.
One, Model ZDV, BN3561 operates from 30 to 300 mc; another, Model ZDD,
BN3562 operates from 300 to 2400 mc. These diagraphs measure the imped-
ance or admittance of an unknown by measuring the reflection coefficient
between a reference and an unknown transmission line. All shorts and opens
at advanced frequencies can be established by using transmission lines of the
appropriate length; that is, an open quarter-wave line is an ac short and an
open half-wave line is an ac open. The system used is basically a 50 ohm
system and measurement of 111b or hi, may be read directly from the Smith
chart display of the diagraph.

OUTPUT ADMITTANCE (hob, h..)

1. 200 Ice to 5mcs
The same equipment is used here as for the h,t, measurements. However,
as much as 1.0 volts rms (although less is preferable) can be applied at the
collector. The slope of the characteristic is reasonably constant over a large
range of V« .
A conversion from 11,, ± jX, to G ± jB is necessary. Circuits are in plug-in
boxes.

190 B601 RECEIVER CIRCUITS ARE IN

GIG
BRIDGE (DETECTOR) PLUG-IN BOXES
GEN

- I mmm
TEST
BOX

NOTE: CIRCUIT USES 5 MHY

RFC IN BASE FOR I- 5MC RANGE
hob
liRIDGE

- -

BRIDGE
2K

1
_j
_J

V SUPPLY

350 KC - IMC

11,, AND ho,. MEASUREMENT UP TO 5 MC

Figure 18.42

2. 500 kc to 200 mcs

The Boonton Radio Corp. Model 250 RX meter is used to make these
measurements. The bridge measures Il i.± C, and has a built-in signal gen-
erator and heterodyne detector. The "RX" meter measures 11, from 15 ohms to
over 100 kohms and —80 pf to +20 pf (with means of extending this range by
adding external reactance).
Since de currents of up to 50 ma may flow through the bridge, the

485
18 TRANSISTOR MEASUREMENTS

shunt-feed problems are alleviated somewhat, and the entire bias supply is
"floated" with respect to the bridge as follows:

THE hob/Yob SWITCH IS A SELECTED

hib

LOW LOSS,LOW C,LOW L TOGGLE TYPE

47 K 5 IK
HI LO

'1,De METER
YOD
SWITCH
c-HI • I
005µ fd 005µfd
o o
+ e

h,, AND h„, MEASUREMENT UP TO 200 MCS

Figure 18.43

The built-in positive feed-back in the common base configuration, due to

" capacity, etc., will often make the resistance term appear negative.
overlap "

The bridge, of course, is not designed to measure —R. Yet by balancing the
bridge at R = 10k, for example, and rebalancing with the unit inserted one
can calculate the effective —R term. The built-in capacity is sufficient to
warrant great care to prevent any more from being added by the external
circuit, and ashield between emitter and collector should be included in the
physical circuit. A comparison of the measuring circuit of Figure 18.44, and
that of an oscillator clarifies the above requirement for minimum capacitance.
Also note that hob may not be measurable at some frequencies, and an ac
by-pass may be switched in, in order to measure the parallel equivalent of
yob, which is also useful in determining h,1 at high frequencies.

ho b TEST CIRCUIT OSCILLATOR CIRCUIT

COMPARISON OF h , TEST CIRCUIT WITH THAT OF AN OSCILLATOR

Figure 18.44

3. 30 Mcs and Up
The Rohde and Schwartz Diagraph is also used on output measurements at
higher frequencies. However, since the diagraph is a50 ohm system, the' reso-
lution above 2.5 kohm is difficult; thus, on some devices the real part of hob
and h., may be difficult to determine except to say that it is less than 1/2.5 kor
0.4 millimhos.

486
 TRANSISTOR MEASUREMENTS 18

FORWARD CURRENT RATIO (ri m ,hf,AND flab )

Maintaining a high impedance, broad band current source in the presence of
capacity is difficult. The problem arises in determining what signal current is being
injected into the transistor, i.e., in calibrating the unity input current. It is convenient
to assume that when the current is jumpered into the collector reading resistor to
calibrate the set, this current will then flow into the transistor too. However, even
5agf of capacity of the emitter socket has acapacitive reactance of only 1.5 k ohms
at 20 mcs, which is not agood current source if R. = 25 ohms and hlb = 200 ohms.
This can cause a10% current change, and much larger errors in frequency when meas-

uring fhfb, (the slope of hfb with frequency is relatively small) since a a.. f •
1-I- I—fh.

Another factor rises which must be considered. The input impedance of the tran-
sistor looks inductive below fhfb, and at some point becomes resonant with the
terminal capacity. If the real part of hlb is larger than the reactive part, then the
Q of the circuit exceeds unity and more current flows in the emitter. At this juncture,
the current gain appears to exceed unity. It is the nature of hfb to return to unity at
high enough frequency, as an examination of the equivalent circuit will show. Of
course, hfb could be measured at many frequencies while resonating out the terminal
capacity for each step. This is done for hf. and fhfb, but is time-consuming. Time
consuming, too, is the recalibration operation in fbfb measurements, but this time has
been reduced as much as possible in the circuit shown in Figure 18.46. The switch-
ing is made automatic, and the gain is changed to correct for the difference between
hfb-. (low frequency) and unity. This too is automatically switched between calibrate
and measure positions. With a flat 3 db pad (General Radio type), the detector
becomes a reference indicator. Now the frequency is found where both readings
are equal.
The phase of hfb at any frequency may be found by using a parallel (and as
nearly identical as possible — but without the transistor) channel as a reference. The
two channels are amplitude and phase balanced without the transistor. The transistor
is then inserted, amplitudes rebalanced, and the peak vector voltage between the

190
SIGNAL
GENERATOR REFERENCE
• METER

INPUT
ATTENUATOR

DETECTOR

• SHIELD
PENTODE
AC ----r -
It
CURRENT
SOURCE WIDESAND
AMPLIFIERS

2000

h,. AND f„ MEASUREMENT UP TO 10 MCS

Figure 18.45

487
 18 TRANSISTOR MEASUREMENTS

channels measured. An Advance Electronics Corporation "Vectrolizer" is used. This

consists of a peak reading diode differential detector and de amplifier/voltmeter.
The usual considerations of signal currents in the collector still apply. Lead-length
is critical in this equipment and disc type by-pass capacitors are preferable.
1. hr and f.. to 10 mcs is measured in the arrangement shown in Figure 18.45.
2. ht,, fbn, and phase of ato 100 mcs is measured as shown in Figure 18.46.
Two basic methods of calibrating unity current are shown in Figure 18.47.

50i/ CHANNEL I
COAX.
"DISTRIBUTED"
CURRENT COAXIAL WIDE-BAND
SOURCE RELAYS 50 < AMPLIFIERS

c'•*,^^^/J«_I 5011

Vc
NULL

SIGNAL
METER
SPLITTER --•
•

CURRENT 5011
SOURCE PHASE COAX.
ATTENUATOR
AMPLIFIER
TRAIN
50 o AS ABOVE
GAIN
CONTROL

CHANNEL 2
NOTE CALIBRATE OUTPUT NULL WITH COAXIAL RELAYS IN POSITION ® .MEASURE IN POSITION it

AND PHASE OF MEASUREMENT UP TO 100 MCS

Figure 18.46

SHUNT
DC FEED

METHODS OF CALIBRATING UNITY CURRENT

Figure 18.47

488
 TRANSISTOR MEASUREMENTS 18

Signal generators used are either the Tektronix Model 190, up to 50 mes,
or the Measurement Corporation Model 80 up to 100 mcs, and beyond. The
distributed amplifiers used are the Hewlett-Packard Model 460A or the
Spencer-Kennedy Model 201, the latter having a 200 mcs cut-off frequency.
Detectors are the Hewlett-Packard Model 401-B or the Boonton Electronics
Company Model 91-B. The "Vectrolizer" has already been described.
Finite termination transfer constants can be measured on the diagraph
which when coupled with a knowledge of the other h parameters measured
will yield the hrt,, hrb, hr or hr.. The computation involved is somewhat long
and tedious and with any large number of measurements would almost require
acomputer. In the measurement of hf. at high frequencies another test facility
has been developed which will perform this measurement at certain fixed
frequehcies. 20, 40, 100, and 200 mcs are currently used. This measurement
is essentially used to determine the ft of adevice where f. is equal to ht. times
the frequency of measurement if the hr. vs. frequency characteristic is de-
creasing at 6 db/octave at the frequency of measurement. ft is defined as the
frequency at which ht. = 1.

e
e, zL
'cal

e,
e, ib hie ib
z + hie

1-F ZL
zgl+1zo zg
'col iz gl+ ihiel hie
—zg

zt_
( +
1+ Zg I )
I
h ie

I
Z g

IF h =
ZL
fe ib 1+
Zg
hfe
c
i (i b) (h fe )' ¡
cal ) hi e
1+
Zg

Figure 18.48 BASE ERROR TERMS

489
 18 TRANSISTOR MEASUREMENTS

(i o) (Fi fe )

z
z9

hfe (ACT.)
he hoe
1+ 1+
zg

hfe (MEAS)

hfe (MEAS) SHOULD =hfe (ACT)

lit L.

hie!
h (MEAS.).
l
oco fe hfe (ACT.)

1+ —

Figure 18.49 COLLECTOR ERROR TERMS

a. fi Measurement
In ahigh frequency mesa transistor, the ft point or the frequency where
hr. = 1, usually occurs at a frequency in the order of several hundred
megacycles which makes measurement of this quantity quite difficult. This
is in addition to the device parasitics interfering with the measurement.
To avoid such difficulties, hr., (the short circuit current gain of atransistor),
is measured at afixed frequency somewhat below the ht. = 1value. The ft
point can then be very closely approximated by applying the relationship
of ft = (hr.) as mentioned. In the particular test set described
provisions were made to check 11, at two fixed frequencies an octave apart.
This, in effect, tells:
1. If the particular transistor under test has any useful gain at these
frequencies.
2. If the transistor is following the theoretical 6db/octave slope.
3. If the second condition holds, what the value of ft is.
For example, two sets of similar design will be described for two dif-
ferent types of mesa transistors. The fixed frequencies of one are 100 and
200 mcs, and the other, 20 and 40 mcs.
Problems which must be avoided in the measurement of ft are:
1. The signal level applied to the base must not be too high for a small
signal measurement.
9. The signal fed into the base must be asuitable current source.
3. The output reading load must be well defined.

490
 TRANSISTOR MEASUREMENTS 18

To illustrate where these problems arise, consider the errors in calibration

in the input circuit of Figure 18.48, and in the output circuit of Figure 18.49
when the transistor is inserted. Combining these two terms results in Figure 18.50
where the total relationship of measured hr, as compared to actual hr0 is shown.
The object of this measurement is to get the measured value of hr. to equal
or to approximately equal the actual hr. value. Therefore, both the input and
output error terms must be minimized; i.e., the variation of the input loop
impedance when changing from the calibrating load to the input impedance

z,

(MEAS). ) ht. (ACT.)

h,, ho,

z, 1+ !
-7_

ERROR TERMS IN h, MEASUREMENT

Figure 18.50

of the transistor under test must be minimized and the magnitude of the output
admittance, h.., as compared to the load must be minimized. In other words,
ht. h..
-- and — must be < 1.
z,, YL
The signal current generator uses a 10 k ohm series resistor to the base of
the transistor and is placed through a double sided copper clad shield which
tends to reduce the shunt capacitance across the resistor since at high fre-
quencies shunt or stray capacities lower the impedance of acurrent source. To
compensate for the residual capacitance in the test set described and therefore
raise the current source's effective impedance at the base of the transistor
socket, a high Q parallel resonant circuit is placed to ground. (One of the
methods which can be used to tune the resonant circuit is to install it physically
in the test circuit and then connect an RX Bridge as closely as possible to the
base terminal of the transistor socket. Set the C dial on the RX meter to 0pf.
Tune the capacitor in the test set and the II, dial on the RX meter until the
meter on the RX bridge nulls. Then read the 11,, dial. This is the effective
impedance which normally is from 4 to 8 k ohms depending upon the fre-
quency of the test set.)
Some mesa transistors tend to exhibit an output impedance, 1/h.., in the
order of from 50 to 100 ohms at high frequency. Therefore, in order to measure
this type of transistor with accuracy the magnitude of the load admittance
terms, yL, must be greater than 100 millimho (or RL < 100). In order to
realize this condition, transmission line techniques are applied. Not only does
the transmission line transform the 3k ohms resistance of the if millivoltmeter
used as a detector to approximately 1 ohm, but the standing wave voltage
transformation permits operation at lower signal levels. Effectively a quarter
wave transmission line is placed from the collector of the transistor socket to
the rf millivoltmeter. In practice, it is found much easier to cut a piece of
cable shorter than the actual quarter wave length and use avariable ceramic
capacitor at the if voltmeter end of the cable to ground. When adjusted,
this capacitor electrically extends the line to exactly aquarter wave length.
With mesa transistors in a psuedo-grounded emitter configuration which
is used in this circuit, amesa transistor may break into oscillation. Therefore,

491
 18 TRANSISTOR MEASUREMENTS

aseries RC circuit, using a 10 ohm resistor, is placed from collector to ground.

This effectively lowers the collector impedance at frequencies other than the
frequency of interest and discourages unwanted oscillations.
Figure 18.51 is the diagram of the test set. High frequency construction
techniques are used. Shielding is of utmost importance, and the input circuit
must be isolated from the output circuit to avoid leakage of signal which
could cause a calibration error. (In this case, the hase from the collector.) In

20 MC 40 MC 100 MC 200 MC

CI 3-12 pf 3-12 pf I5-7 pf I.5-7pf

C2 0.1 µ f 0.1 µ f 0Olp.f 0.01 µ f

C3 0.1µf 0.1 µ f 0 010 0.01µ f

C4 3-12pf 3-12pf I.5-7pf 1.5-7pf

LI 10µ h 2.2µ h 060 µ h 0.15µ11

L2 82µ h 47p.h 4 7,, h 4.7p. h

ÁI 2-500n 2- 500e 2.2K 2.2 K

IN SERIES IN SERIES

* CRI SHOWN FOR PNP OPERATION OF CIRCUIT (3-IN540'S IN SERIES)

DIAGRAM OF hr,. TEST SET

Figure 18.51

constructing this test circuit, double sided copper-clad board is used. Com-
ponents are physically placed such that lead length, is kept to a minimum.
To eliminate lead inductance of the transistor under test, a socket is used
which allows close connection of the circuit to the transistor header. A rectifier,
CR-1, is connected from emitter to ground to insure that C2 does not
charge-up when the test socket is empty. This prevents destroying the next
transistor to be tested. In Figure 18.51 the circuit is connected for PNP opera-
tion of the test set. A switchable attenuator box is used instead of the range
switch of the rf millivoltmeter. The rf millivoltmeter used in this test set has
about a 1db non-linearity from scale to scale and within ascale. To avoid this
error and still use the instrument, an alternate method is required using asingle
point on the voltmeter (say full scale on the 3 mv scale) and working around
that level with aswitchable attenuator.

492
 TRANSISTOR MEASUREMENTS 18

Figure 18.52 ATTENUATOR BOX

Figure 18.52 shows the attenuator box. Three switchable pads are incor-
porated enabling any combination of the three pads to be used. This in effect
keeps the rf millivoltmeter on the same scale (3 mv scale) and within that
scale, the pointer is always no less than 2/
3 of full scale. The design formulas

for these pads were taken from Reference Data for Radio Engineers* using
unbalanced ir networks keeping the input and output impedances equal to
50 ohms.

POWER GAIN MEASUREMENT

GENERAL
In a practical and useful amplifying device there is one question of paramount
importance, how much will it amplify at the frequency (or band of frequencies) of
interest? In short, what is the power gain? Obviously where the amplifier has insuffi-
cient gain to fulfill the minimum requirements, the device is of only passing interest.
Other important considerations may include flat frequency response, amplifier stability
with temperature variation and other environmental changes, effective operating life
of the device and total power consumption. Power gain, however, is still of primary
interest and will be discussed in this section.
From the standpoint of the circuit designer the power amplifier should, among
other things, he a unilateral device with no internal feedback of any sort, and have
equal input and output driving point impedances. It should contribute no noise of its
own to the signal being amplified, have aperfectly fiat gain/frequency response, and
a large gain-bandwidth product. Transistors, however, are not unilateral devices.
Depending upon the circuit configuration being used (common base or common
emitter) and the particular frequency, the internal feedback may be either negative
or positive, and may even shift phase from one to the other. This effect is not unique
to transistors, of course, but these internal aspects do necessitate some thought in
defining Power Gain. Consider the case of an amplifier with positive feedback. When
the feedback power is great enough to overcome the associated circuit losses, the
device will oscillate. Describing the power gain of an oscillator is, of course, mean-
ingless. With no signal applied and any signal at all out of the device, its apparent
gain, according to the usual definitions, is infinite! This suggests the need for addi-
tional constraints in the definition of gain. Gain may be described under neutralized
or unilateralized conditions, with attendant problems of defining measurement of the

*Published by International Telephone and Telegraph C pany.

493
18 TRANSISTOR MEASUREMENTS

degree of undaterality. Cain may also be defined with certain boundary conditions,
or stability criteria, for example, when gain is measured with only that feedback
required to make the output driving-point impedance appear infinite. This will be
discussed later.
Problems of gain measurement break down into three specific phases:
a. Means of measuring input and output powers of the transistor.
b. Determining the effects of the circuit on the device.
c. Determining the effects of the device upon the circuit.
To be still more specific: in (a.) the generator and load impedances are adjusted
to match (either resistively or complex conjugate) the transistor for maximum power
gain. It must also be insured that the device is not over-driven either current or
voltage-wise. In other words, assurance must be maintained that small signal condi-
tions apply. Due to the extreme signal sensitivity of the usual low-power transistor,
the measuring of ac powers in the order of 1to 10 microwatts (ac currents in the
order of microamperes and ac voltages of afew millivolts) is of concern. As aresult
the measurement problem is more complex than may be immediately apparent.
In (b.) spurious paths or parasitic strays can introduce unwanted feedback, and the
particular terminations used must not permit the transistor to operate in aregion where
internal feedback can cause potential unstability. This is the "gain" of an oscillator
paradox. The ideal way to guarantee that the above conditions do not exist is to
measure the two port impedances when terminated at the other end by the apparent
required match, to see that no signs of negative-resistance exist. This latter condition
leads to (c.).
In any circuit with R, L, and C components, abasic loaded Q is present. Assume
that this circuit is the complex conjugate match for atransistor. When this transistor
is inserted, its output conductance appears across the circuit and the circuit Q should
decrease to half the original value. Now consider what would happen were the
device to have positive feedback. With enough feedback the output of the transistor
has anegative resistance component which absorbs some of the circuit losses and the
Active Q now increases. Even if this feedback is internal, rather than caused by
unknown and uncontrolled strays, it is difficult to state with confidence the true gain
of the transistor. However, ameans of using the bandwidth of the circuit as acriterion
of stability is available. Thus, the Active Q may be made less than that of the circuit
Q alone. This approach will not suffice for negative feedback where the solution
relies on the neutralizing techniques which are to be discussed shortly.

MEASURING POWER GAIN

Power gain depends on the particular definitions used and the frequency or band
of frequencies being considered. These definitions are as follows:

1. C= or G — P.,..7! '
•where = current amplification gain
i
t r it
This is the low frequency case and is the actual gain between Rg ,, and
Rim., and is maximum when 11 1,... = R and Rt. = P,0, iii..

where E., = open circuit generator voltage.

2. (circuit gain or available power)
CTranstlureris the output to available power ratio. The closeness of matching
conditions to the two-port impedances of the amplifier will determine how
closely CTapproaches G.,.. avallable•

494
 TRANSISTOR MEASUREMENTS 18
3. G4,1110314

This is the gain of the transistor with only the real part of its input and
output impedances matched to the load and generator.
4. Gmaxlmum available

The real parts are matched and the reactances are tuned out, that is, the
saine impedance but of opposite phase. This is the complex-conjugate match
and is the most true gain obtainable. Close attention is required to distinguish
between this and pseudo gains which may appear larger due to positive
feedback.

OUTPUT MATCHING NETWORK,

— 1 WITH Eovr. f(POWER IN LOAD)

K WHEN PL . K

¡ DEVICE \
, UNDER,
13 TEST 5"

R4

SIGNAL L_ J
GENERATOR
MATCHING NETWORK VTVM
COMPLEX eOUT
WITH AVAIL " K R5
MATCH
'RESISTIVE GENERATOR"

L._
WITH RI »R2, 2(Ft2+ R3) » R2 Z1 »R L MAX.

R2+ R3 AND IF EouT el( RLOAD). R4+ R5. RL

THEN e
l It

GENERATOR

/ 390
,
,M .
r.__ is, ,// TEST SOCKET
/..._
3K 3K

Ff UlTASILE
9Y -PASS
1/(,< III)

RF CHOKE

HI CREO
COWPER

225 V Va

1K
• I
0.1

HEWLETT-PACKARD111-11
4000
VTVIA 100
.02

330K
e l -3
130

5.411

POWER GAIN MEASUREMENT CIRCUITS

Figure 18.53

495
 18 TRANSISTOR MEASUREMENTS

All of the foregoing definitions, with the possible exception of (1) may be considered
as classes and are often divided into sub-classes as determined by the considerations
mentioned earlier when discussing the phases of the measurement problem. As to the
particulars of each measurement set: while it may be possible to measure the
current amplification gain in (1) and (3), it is usually easier to have switchable Rn and
RLso arranged that the available generator power is kept constant and an output volt-
age is obtained proportional to the power in the load. It should be noted that this circuit
is also applicable to (2) as long as aresistive generator is desired or necessary. The
device, potentially unstable if complex-conjugate matched, may be usably stable if
only one terminal is complex matched and the other resistively terminated. For prac-
tical reasons the generator is usually the resistive match as shown in Figure 18.53.
Measurement of (2) often takes the form of the circuit shown in Figure 18.54.
This is afunctional IF test.

TEST
SOCKET VTVM
I TI
455KC fB C \
SIG 10 Ok
GEN 12.5Kû "

___ 500
I .
SAME TYPE OF
VTVM
TO SET L-- — TRANSFORMER AS TI
LEVEL 0I
F TRANSFORMER
(CALIBR)
(BI-FILAR WOUND)

BK

BIAS RESISTORS CHOSEN FOR 100 y fd

IE .1.0MA FOR AVERAGE UNIT.

FUNCTIONAL IF POWER TEST

Figure 18.54

To reproduce the measurements from set to set, the transformer loaded imped-
ances, losses, and bandwidth must be specified. The layout is standardized and pre-
cision resistors and meters are used to establish the de bias conditions. Since gain
varies with temperature, means of controlling or at least monitoring temperature
should be included. The use of attenuators to set relative levels on the VTVM is
encouraged, rather than relying on the linearity and accuracy of the VTVM.
For complex-conjugate matching, and also for asimple method of measuring high-
frequency gain, the ir network has proven very useful as an impedance transformer.
With care, the losses in the network can be kept low (in the order of 1db). It should
be remembered that this network acts as a filter, and bandwidth measurements
should not be made. Where bandwidth is important the use of variable link coupling
networks will prove more satisfactory.
In the following circuit, Figure 18.55, the detector is coupled into the generator
at the calibrate jack. The network is then adjusted for amaximum reading. Assuming

496
 TRANSISTOR MEASUREMENTS 18
the losses of the input network are constant with small variations of match, and the
input impedance of the transistor is close to the 50 ohms of the detector, the output
will be the zero db reference setting, and only the losses in the output network are
important. By keeping these losses small with proper network design, the losses can
then be considered as part of the transistor's gain.

NEUTRALIZATION
The need for neutralization arises when internal feedback exists. The device is not
unilateral and variations of load affect the input impedance. This fact enables one to
devise methods of determining when neutralization has been accomplished. There are
two accurate measuring techniques. One uses a resonant load and sweeps the input

HIGH FREQUENCY MATCHING NETWORKS ,

CALIBRATE

GEN 4- TEST SOCKET

DETECTO'i
5K
Bi ‘C

SIG GEN

TO \/, SUPPLY
•
DETECTOR USED BOONTON ELECTRONICS CORP
MODEL 9I-B (0.003V FULL SCALE DETECTO
SENSITIVITY )

DC
CHOPPER
AMPLIFIER

HIGH FREQUENCY POWER GAIN

Figure 18.55

with avariable frequency signal current source. As the signal goes above and below
the resonant frequency, the load becomes first capacitive and then inductive. If ahigh
impedance sensitive detector is used to look at the input voltage, the changing
impedance is seen at the input due to reflected load changes. At frequencies up to
5or 10 mes such detectors are available, but in the VHF range a different approach
is used. The second approach, applicable at most frequencies, is to measure the feed-
back voltage appearing at the input when a signal is applied at the output. This is
precisely what is done in measuring ha,.
In both methods some out of phase feedback is applied in parallel with the device,
so as to cancel either impedance changes or feedback voltage. Means of amplitude
and phase control will need to be incorporated in the neutralizing network to avoid
over-compensation. Simplified circuit diagrams are illustrated in Figure 18.56 to show
some of the various feedback schemes used. The feedback networks are lumped-
constant types at lower frequencies and transmission line types at VHF.

497
 18 TRANSISTOR MEASUREMENTS

COMMON BASE TRANSISTOR

e Cc
OUTPUT

INPUT
INPUT
OUTPUT
WHICH
WHEN
REDRAWN IS:

R/C FEEDBACK,
L_ __R * _J
NEUTRALIZING NETWORK
SOMETIMES R/L
USED INSTEAD

COMMON EMITTER

NOTE:

FEEDBACK MAY OFTEN

BE TAKEN FROM A "TERTIARY"
WINDING OR LINK COIL
INPUT
OUTPUT

NEUTRALIZATION MEASUREMENTS
Figure 18.56

LINE STRETCHER
TO ADJUST PHASE

OUTPUT

SCHEMATIC OF TRUE GAIN MEASUREMENT

Figure 18.57

To check the true gain of atransistor, unilateral amplifiers are used in the feedback
path to supply the power consumed in the feedback (neutralizing) network, thereby
not loading the transistor's output, as shown in Figure 18.57.

498
 TRANSISTOR MEASUREMENTS 18

TRANSISTOR NOISE MEASUREMENTS

GENERAL
The noise output from an amplifier consists of two parts:
1. Output due to noise generated at the input-terminals.
2. Output due to noise generated inside the amplifier itself.
Part 1of the noise power output is predictable since the available noise-power in
any resistor is
P. = kT1-3
- (18a)
where,
k = Boltzman's constant
T = Absolute temperature (°K)
B = Effective bandwidth
and this effective bandwidth is

i3 — fG(f)
ee' df (18b )
—G
0
By measuring the gain with frequency, integrating and dividing by the maximum
gain, the equivalent rectangular power pass-band is found. Since noise-power at the
output consists of two parts, and one of these may be predicted, this may be used
to specify the noisiness of an amplifier. The index used for this purpose is called the
noise factor and is defined

F Total noise power out

Power gain x Noise power due to source resistor (18e)

Or,
Ps
F
G •P.

(Ps)..t
But since G _ ' where Ps is signal power
(P8)1.
(Ps)in (Signal \
F= Ps P. Noise I.
(18d)
(Ps).. t • (Ps).., Signal\
• p" Ps V Noise )..t

Noise Figure (NF )= 10 log F. Expressed in terms of voltage and resistance, the avail-
able noise-power can be written

p. =4
-R.
= KTri (18e )

Or,

= NI 4KT-1
3R.
- (18f)

At room temperature, 4KT = 1.6 x 10' joules.

MEASUREMENT OF NOISE FIGURE

In equation (18f )E. is the noise voltage at the input. Now asignal is added at the
input (1,times E.) such that the output level with signal is much greater than the noise

499
 18 TRANSISTOR MEASUREMENTS

output. This value y is the signal-to-noise ratio and "calibrates" the output level of
the entire measuring system. When the signal is removed, the output level should
drop to 1/7 of this calibrated level provided the amplifier is perfect. Since the amplifier
contributes some noise, the level will not drop that far. The ratio between the actual
level of noise background and the ideal case is the noise factor and the noise figure
may be read on the db scales of the VTVM used. Since the noise voltage fluctuates,
sufficient capacitance must be added across the meter movement of the VTVM to
integrate the noise voltage with time. If an average-reading meter (calibrated in RN1S
of asine wave) is used, then the meter will read 11% lower on noise than on sinusoidal
signals, and the "calibration" signal must be reduced accordingly for correct measure-
ments. If atrue RMS meter or bolometer is used, this correction is unnecessary.
Since the unknown signal is present during the calibration process, the measured
Noise Figure is not the true Noise Figure.
According to equation (18d )
Signal \
Noise
F
Signal \ (18g)
Noise Jo...
The input during calibration is S',. = (Ps )1. + P.. The noise input is N'1. = P..
and,
S'in = , (P,.), ..
—
N' P. (18h)
The apparent output signal S'.., = G [(Ps ) ± P.] ± PE. The apparent output noise
= GP. ± PE, where PEis the noise generated in the transistor. Therefore,

S'„„, G [(Ps),. ± PE
N'00. — GP. ± PE (18i)
The measured noise factor
S 'In (Ps),« SI.
1± 1-1-
N',„ P. N,,.
FM— = (18j)
S'.., G [(Ps),. + Pn]+ PE — 1 ± Sont

N'„„, GP. ± PE No„,

since G (Ps )1. is the true output signal = Sm.', and GP. + PE is the true output
noise = No.,.
By re-arranging equation (18j )
S,„ No., NI.
1+ e 1+
N,„ S
= =F (18k)
S.., N
1±
N.., S,,.. +

or the true noise factor

N,„
1
SI.
F= (181)
1±

From equation (181) it is seen that if So., is much greater than the noise back-
ground level F approaches Fb, since this also implies Sin> >N,..
One other complication is that the noise output of the transistor under test is far
below the level of sensitivity of most commercially available meters, so that an amplifier
must be used to raise the noise level to areadable level. Unfortunately, this amplifier
can contribute noise of its own and degrade the readings.

500
MIIIIMIMIMMIIMB TRANSISTOR MEASUREMENTS 18

It is easily shown that the total noise factor of acascade system is

Fg —1 F. —1
FT= F, -I- -I- (18m)
Ga GIG2
So that G should be made as high and Fg as low as possible to avoid these errors.
(Removing the device under test while observing the noise background will supply a
quick check on post-amplifier degradation. The output level should drop 20 db or more.)
A much more convenient way to make noise factor measurement is to use a noise
diode. It is known that the output noise current from such anoise diode is

I
N2 = 2q Inc B Inc = plate current in diode
(18n)
q = electron charge =effective bandwidth
If the source resistance is Rg,the available noise power is
I
N' R„ 2q Inc B Rg
(18o)
4 4
This is the noise power generated by the diode alone. The noise power due to Rg is
N, = KTri (18P)
and this is in addition to Si.
The excess noise generated in the amplifier is NEand the power gain is G and if M
is defined as the ratio of noise power output with diode turned on to noise power out-
put with diode turned off, then

M = (KTB ±2q B RgG + NE)

(18q)
KTI3-G NE
Or,

2q I
pc G

4 S (18r)
M —1 =
KT G NE N)..
and since,
2q Inc T3 Ft,
4 (18s)
KTÉ.
we have,
S l3 g
2qIncR
F = N /In 4 (18t )
S M-1

2q
But at T = 290°K (17°C), 4 KT = 20 (volts) -1

So equation (18t )can be written as

F 20 Lai,Rg (18u)
M-1
Usually M is chosen to be equal to 2therefore the noise factor is,
F = 20 Inc Rg (18v)

EQUIVALENT NOISE CURRENT AND NOISE VOLTAGE

Because of the internally generated noise, the output noise current is not zero when
the input is open, and for the same reason the output noise voltage is not zero when the

501
18 TRANSISTOR MEASUREMENTS

input is short-circuited. Since the noise current and noise voltage output are solely
dependent on the transistor it seems that a noise specification based on those two
quantities would be more generally useable. In the following derivation the relation-
ship between open circuit noise current, short-circuit noise voltage and noise factor
will be shown. A noisy amplifier may be substituted by a noise-less amplifier with
equivalent noise-current and noise-voltage sources connected to the input, as shown
in Figure 18.58.

•î,

Figure 18.58 THEVENIN'S EQUIVALENT OF NOISY AMPLIFIER

The total noise-power at point A is proportional to

4Kit
iT = R, 11,2 is (18w)
The first term is the noise-current generated in Fi g and since the noise factor,
all noise
F
noise due to R.
then,
ex' iR g
F= 1 (18x)
4KTS -ti-
,+ 4Kit

= effective bandwidth — ,1 feG(f)df

UMAX

where,
G(f) = gain as function of frequency
GMAX = maximum gain.
Defining,
.
=
4KTB
iN 2
2q13-
equation (18x) will be,
Re qv 2q le qv
F= 1+ R. ± 4 KT
and since,

—
2q -= 20 (volts)' at T = 290°K,
4 KT
F = 1+ R, + 20 1.„. Fi g (18aa )

In Figure 18.58 the noise-voltage source may be thought of as alossless resistor

and the current source as a parallel shot noise generator due to an equivalent dc
current
To find the optimum value on the noise factor the derivative of F equation (18x)
is taken with respect to R,, and this optimum noise factor is found to be

F„, = 1+ — 1+ 2Ni 20 Re g', Lc,

2KTB (18bb )

502
 TRANSISTOR MEASUREMENTS 18

for,

R. = R.., =
iN .
= j
1120 I.,
(18cc )

From equation (18bb) it is seen that the optimum noise factor can be found analytically
if el. 2and ite are known. This is also the noise factor which will be measured if ameas-
urement is made with asource resistance 110.2.
Combining equations (18x )and (18bb ).
Ropt
F = 1+
Fopt Ra
(18dd )
2 Llopt Rg
Therefore, if Ropt and R,t are given, the noise factor can be found for any source
resistance R..
Defining afactor k, as

k =.
1 [ Rg Ro
pt

2 Ro rt

equation (18dd) becomes

(18ee )
F = 1± (F.pt —1) k

FACTOR k VS. -L
Ropt

Figure 18.59
25 5 I 2 3 4 5678
R 9
RT, rà

For example, the optimum noise figure (NF)0 .t is given as 1.5 db or Fopt = 1.4. The
optimum source-resistance is 1000 ohms. What is the noise factor in a circuit where
R. = 8k ohms. The ratio R./11..t = 8, and from the Figure 18.59, k is found to be 4.
Therefore, the noise factor will be
F = 1± (F0pt k= 1+ (1.4 —1) <4 = 2.6
NF = 4.1 db

MEASUREMENT OF (P) 1
2 AND (rD,2)% FOR TRANSISTORS
/
The schematic in Figure 18.60 is used to measure (eN 2)%.

METER
TRANSISTOR NARROW
ATTENUATOR LINDER 0-0 BANDPASS

TEST FILTER

GENERATOR Rg

//

SET UP TO MEASURE (et)'

Figure 18.60

503
 18 TRANSISTOR MEASUREMENTS

R. must be chosen so as to be much smaller than the input resistance of the

transistor. It is known from transistor-analysis that
r.
rb'
2
ef,V

To make in equation (18aa )the dominant term,

R.
R...> >R. or R.<<

The measurement-procedure is as follows:

a. The back-ground noise-level is noted.
b. The signal generator is connected through asuitable attenuator, and the level
of the generator is adjusted until the device output level is 20 db above back-
ground level.
c. The required input level is measured from which e,, can be determined.
To measure the equivalent noise-current, an almost identical circuit is used. The
only difference being R. replaced by a high resistor inserted in series as shown in
Figure 18.81.

METER
TRANSISTOR NARROW
TENU ATOR•-ii-W /-• UNDER •--*EIANDPASS
V R'
9 TEST FILTER

GENERATOR

-..-

Figure 18.61 SET UP TO MEASURE (Gi) 1

/
2

A condition which must be satisfied is

4KTB <<
iN
R.'
2

If the background noise level is V. and the input voltage V gives E volts out, then
equivalent noise-current is
V VN
— •—
R. E
It should be strongly emphasized that eN and iN must be measured under the same
operating conditions to have any practical significance, and also the necessary correc-
tion must be made for the lower meter reading on noise.

MEASUREMENT OF NOISE FACTOR WITHOUT USING SIGNAL GENERATOR OR

NOISE DIODE
The concept of equivalent noise current and equivalent noise voltage can be used
to measure noise factor without asignal generator or noise diode. Since the noise factor
depends on the source resistance, and every resistor is athermal noise source by nature,
the source resistance can be utilized as anoise generator. The method is based on three
measurements, from which the noise factor can be computed
1. The noise voltage at the output, input open-circuited.
2. The noise voltage at the output, input short-circuited.
3. The noise voltage at the output, the desired source resistance connected to the
input.
One necessary condition in this method is that the input resistance to the device
be known, or be measurable.

504
 TRANSISTOR MEASUREMENTS 18

EQUIVALENT NOISE CIRCUIT

Figure 18.62

ej is the noise voltage generated in the source resistance R„

e.' is the equivalent noise voltage, input shorted

cio ,
pis the true equivalent noise current, input open
is the noise voltage generated in the input resistance

The above circuit, Figure 18.62, is re-drawn as a current equivalent in Figure 18.63.

NOISE CURRENT EQUIVALENT CIRCUIT

Figure 18.63

The relationships between currents and voltages are

• „, 2 e cg e"
1g = Is = R: • = s

The total current flowing into the parallel combination of R„ and RI.
e -I- es' 2
IT = g 11,2 (0 2 ''"' (18ff )
RI.
The measured open circuited equivalent noise voltage is due to
(18gg)
Combining (18ff) and (18gg )gives

+e s'
= e R: o
e
(
18hh)

The noise factor

± es' ± e. 2 2

2 R.' es 2 , R,
F =iT = — 1-F -t- =-— — (18ii )
ig 2 Ri.

505
18 TRANSISTOR MEASUREMENTS

From this last equation it is seen that F can be expressed in tfrms of voltage ratios;
and, therefore, only output voltages have to be measured. Equation (18ii )is not too
useful since we can not measure ea separately.
The noise factor may also be expressed as,
F — [total voltage across parallel R,, and Ri.]'
[voltage across parallel R. and Ri,, due to ia]'

er'
F= =

[
2 2
(1811)
Rg Rift Rin

R, + Rs. e2 LRa +
Multiplying both sides of (18jj) by es' and solving for —
es'

=F RI.' es'
(18kk )
ea' (Ri. + Ra)' eT 2
Substituting the identity,
• e.' es'
= •=
• es' ea'
and equation (18kk )into equation (18ii ), and solving for F,
1
F
1+ --
1— e.' RI. (1811)
eT 2 ( R„
Ri.
According to equation (18cc ),

• = e"
•
ix'
and since,
ex' e
and,
•N
I , e.

• = .1
es R (18mm)
e.'
and equation (1811) becomes,
1
F—
1 + ( Fl a
\Rol», /
(18nn )
1 — 2 2

es' Ri.

Ner' output voltage when Fl is connected to inputa

Nes' output voltage, input terminals shorted

Ne.' output voltage, input terminals open
• Ri. I
e.'
Rh, = input resistance of transistor.

506
 TRANSISTOR MEASUREMENTS 18
Thus, the measurement of noise factor is accomplished without the use of anoise
generator or diode.

TRANSISTOR NOISE ANALYZER

A more convenient way to measure equivalent noise voltage and current is to use
the Quan Tech Transistor Noise Analyzer Model 310. This is an instrument where
equivalent noise voltage and current can be read directly at three different center
frequencies, namely at 100 cps, 1kc, and 10 kc. The noise voltages and currents are
read in volts per square root cycle (V/ Vcycle) and Amperes per square root cycle
(A/ Vcycle).
Example:
Transistor 2N123
VcE = —5 V
IE = 1mA
Equivalent short-circuited noise voltage —
es = 1.8 x 10 -9 V/ Vcycle
Equivalent open-circuited noise current ix = 2.5 x 10 -"A/ Vcycre
(measured at 1kc)
This gives
1.8 x 10'
Ropt — 2.5 x 10 -12 = 720 ohms

and
F." = ex ix
1 1 + 1.8 x 2.5 1.564
2KT 8
Optimum noise figure = 1.94 db.

CHARGE CONTROL PARAMETER MEASUREMENT

The measurement of the charge parameters (described in Chapter 6) are discussed
in this section. The four parameters which are currently specified on G.E. specification
sheets are measured in the manner shown in the following paragraphs. NPN configura-
tion is used for circuit layouts, but PNP measurements can be accomplished by revers-
ing the polarity of V1., and Vcc. One consideration which should be mentioned before
the actual circuits are introduced is that of measurement accuracy. In any measure-
ment of switching speed, determination of the pulse voltage magnitudes and the bias
voltages is extremely critical. In these parameter measurements, an attempt was made
to minimize the number of critical pulse and bias voltage measurements necessary.

r„, EFFECTIVE LIFETIME IN THE ACTIVE STATE

The circuit used to measure r a is shown in Figure 18.64. Inasmuch as the circuit

Ycc

PULSE WIDTH SC:.µ SEC TEK TYPE

REP. RATE 2.KC 545 SCOPE

I/2W, 1% CARBON FILM

VIN

RUTHERFORD PULSE TEKTRONIX CURRENT PROBE

GENERATOR, MODEL B-7 P6016

T. TEST CIRCUIT
Figure 18.64

507
 18 TRANSISTOR MEASUREMENTS

contains no dissipation limiting resistor, extreme caution should be used to assure that
Vcc •Ic does not exceed the dissipation limits of the device.
To perform the actual measurement, the following steps are taken:
1. Before the device is inserted into the test socket, VI. amplitude is set to below
+ 0.3 volts.
2. Vcc is set to +4 volts. (This voltage may be lowered when dissipation is an
important factor, but should not be made lower than +2 volts.)
3. A Tektronix Type 131 Amplifier and Tektronix Type 545 Oscilloscope (or
equivalent) are set up so that the collector current at which measurement is
desired produce a scope deflection equal to 3 cm. The current at which the
measurements should be made is that I c for which the device dissipation rating

is approached by the Vcc •Ic product. This point is used for the measurement so
that the T. obtained will be the true minimum and be accurate for "worst-case"
design techniques.
4. The device is now inserted into the test socket. CAUTION: If the base lead
accidently touches the collector lead during insertion, the device may be
destroyed, unless an electrically current-limited power supply is used.
5. The input voltage is now increased until the Ic deflection is 3cm (or the desired
Ic value).

6. T. is the time constant of the resulting pulse waveform as shown in Figure 18.65.
It is not necessary to record the input pulse amplitude.

T MEASUREMENT WAVEFORM
Figure 18.65

Tb, EFFECTIVE LIFETIME IN SATURATED STATE

The test circuit for measuring Tb is shown in Figure 18.66
PULSE WIDTH .10 US •VCC
REP RATE à2KC
1% CARBON
FILM ** BL

VIN2 r--; TO TEKTRONIX 545

VIN

RUTHERFORD PULSE
GENERATOR,MODEL B-7

Tb TEST CIRCUIT
Figure 18.66

The following steps are taken to perform the Tb measurement:

1. Vcc is chosen to be approximately one-half the transistor's breakdown voltage

508
 TRANSISTOR MEASUREMENTS 18
(about 10 volts for most alloy switching transistors).
2. RLis chosen so the current flowing when the transistor is saturated is equal
to amedian current. (For alloy types where 100 ma is the maximum current
permissible, RLcould be from 200 ohms to 1K for Vec = 10 volts. In switch-
ing transistors of the mesa type, \Tee = 10 volts and RL = 1K are common
conditions.)

3. R1 is normally from 2 to 5 times larger than RL.

4. Vi., is the quantity varied in order to make the Tb measurement. The transistor
is saturated at two different values of V1,,, and the change in storage time is
measured. Ease and accuracy of the measurement may be enhanced with the
use of aRutherford Model B7 pulse generator since V,,. may be varied by the
built-in decade attenuator.
5. The unit is inserted into the test circuit.

6. Two values of VI,, are chosen which fulfill the conditions that the circuit
# (forced 13, forced lire, or Vcc R1/Vis RL) is not more than M of the device 14.5.
7. The storage time portion of the trace is observed as shown in Figure 18.67.
Only àts and Viss/V is, need be recorded. àts is observed as the V.., value is
switched between VI», and \The by manually switching the generator's pulse
amplitude.

8. Tb is obtained by using the relationship that Tb = In tvts

,....

\Vim/
(If Viss 1= 2.72 Visi, then n, = -ts.)

; VIN2
TURN OFF
POINT

t
s

In (VI
N2
7Vj7)

Figure 18.67 MEASUREMENT WAVEFORM

CBE, AVERAGE EMITTER JUNCTION CAPACITANCE

Figure 18.68 is circuit used to measure CBE. It should be noted that the input pulse
used is to reverse bias the base emitter diode and is not of the polarity which would
turn the base-emitter diode on. To obtain the actual value of c, the following steps
are taken
LOW CAPACITANCE PROBE
PULSE WIDTH USEC TO TEKTRONIX
REP RATE A2 KC 545
OPEN
I
% CARBON

0,
FILM

v,, 7
RUTHERFORD
MODEL B-7

Figure 18.68 o„,, TEST CIRCUIT

509
18 TRANSISTOR MEASUREMENTS

1. Normally, V1,, is from 10 to 20 volts and depends somewhat on junction break-

down voltage, i.e., 10 volts may be too high for alow breakdown unit.
2. Insert the transistor into the test socket.
3. VBEtransient is observed on the oscilloscope as shown in Figure 18.69. The
value of CBE is obtained from the relationship shown below the curve.
4. One measurement of capacitance is made to determine measurement gear
capacity by performing the same steps with the test socket empty. Measurement
gear capacitance is subtracted from the measured CBE to determine the
actual CBE.

TIME (µS)
MN At
"a r' 10K Ztv
v IN > > v BE I
vBE
I CeE dV

v BE VIBE (OFF)

C. MEASUREMENT WAVEFORM
Figure 18.69

COMPOSITE CIRCUIT FOR Ta, re, Glib

The similarity of the T., Tb, and CBE test circuits allow that they may be combined
in one flexible test circuit as shown in Figure 18.70. The appropriate RI and RLcondi-
tions allow for the various parameter measurements.

vcc

RL .0, 10011 ,200 51, SOUL,

IK, OR OPEN.
MUST BE CA PA BLE OF ATTACHING
RI = IK, 2K, CU RRENT PR OBE FOR RL. O
5K,(0K
SOC KET MUST HAV E LOW
CAPACITANCE i. e. <I pf

COMPOSITE CIRCUIT FOR ro ,rb, AND CBE

COMPOSITE CIRCUIT
Figure 18.70

QB*, TOTAL CHARGE TO BRING TRANSISTOR TO EDGE OF SATURATION

The circuit used to measure Qs * is shown in Figure 18.71. Capacitor, C, is chosen
to supply adequate charge to the device being tested without requiring an excessive
VI,, pulse. For alloy transistors a5 to 100 pf variable capacitor with the capability of
switching in additional capacitance, in steps of 100 pf,
is used. Mesa transistors require
a 3 to 50 pf range. It is important that low inductance capacitors be used. General

510
 TRANSISTOR MEASUREMENTS 18

Vcc

TO TEKTRONIX 545
(OR EQUIVALENT)

(1,* TEST CIRCUIT

Figure 18.71

Radio precision capacitors, Hammarlund type air dielectric capacitors, or their equiva-
lents are satisfactory. In any case, excessive capacity between the base lead and circuit
ground must be avoided.
QB* is afunction of collector voltage variation and collector current. Thus, meas-
ments are made for various Vec and RI, combinations. The following steps are taken
to obtain QB* data.
1. Vcc is determined first. Several values of Vcc will be necessary to determine the
full QB* picture; however, data is taken for one Vcc value and various RLvalues.
We values of interest range from BWE0 value to avalue of 1or 2volts.
2. The unit is now inserted into the test socket.
3. The product C( V — VRE) is the charge which is placed into the transistor to
bring it to the edge of saturation. A value of Vi., is chosen which is sufficient to
permit enough charge to pass into the base of the transistor to bring it to the
edge of saturation. This, of course, will also depend upon the range of capaci-
tance available. Vt, is normally between 5 and 20 volts, so that V1,.> >VBE.
The capacitor used should be carefully chosen for large variation so as to render
the test set more valuable.
4. With Vcc and V1,, adjusted, data can be taken. Record the values of Vcc and
Vt.,. A typical oscilloscope pattern is shown in Figure 18.72.

vcc

_ _ _É -90% FROM Vcc

—
TO VCE SAT.
VCE (SAT.)
100%

Q.* COLLECTOR WAVEFORM

Figure 18.72

As C is increased, the peak of the waveform will approach VCE(BAT). Co is

the value of capacitance necessary for the peak to reach 90% of the waveform
from Vcc to VCE(SAT), while Cioo is the value of capacitance necessary for the
peak of the waveform to reach VCE(SAT).

511
18 TRANSISTOR MEASUREMENTS

5. QB*00 and QB*100 are the products of Cao ( VI. — VBE) and Goo (V1. — VBB) re-
spectively. QB* values are then plotted against 'cg (i.e., Vcc — VCEB1AT) )as shown
in Figure 18.73. Rf.

vcc2

vCC2 .)C100 vcci

QC9 Qits o
Qmoo B90
(
. QC100
VCCI OB .f (COLLECTOR CURRENT )
0C90
Oc. f (V OLTAGE )

ICS (MA)

OB* .( VIN -VBE )C

Cl.* PLOT VS.

Figure 18.73

These plots are generally linear over awide collector current and voltage
range for alloy and diffused transistors. The intercept on the QB* axis is called
Qc and is the part of QB* which varies with collector voltage. The part of QB*
which varies with leg is called Qs. Thus, QB* = QB Qc. If desired, QBand
Qc can also be plotted separately.

CALIBRATION OF CAPACITOR ,C,ON C

la* TEST SET
A simple method of calibrating the capacitor on the QB* test set is available if the
circuit in Figure 18.74 is used. The fact that the reactance of the capacitor at 1.59 mc
(frequency chosen for convenience) is large compared to 10 ohms, permits the 10 ohm
resistor to be used as acurrent measuring device. Looking at the equations
Xc = (2r fC)'
Vs.= IXc
Or,
C = fXc)'

27r fVI.
If VI. = 1volt RMS and f= 1.59 mc, then,
C = (I) 10'
Using the 10 ohms to measure current,
I = VE/10 ohms
therefore,
C = VB(10).
Thus, the VTVM reading, VB, is used to calibrate C, and 0.1 mv RMS indicates 1pf, etc.
CALIBRATION OF CAPACITOR ON 0B* TEST SET
H.P. MOD
400C VTVPA

CAPACITOR B OSOCKET

CALIBRATION E
IVOLT RMS
Figure 18.74 159 MC

512
 TRANSISTOR MEASUREMENTS 18

o
4- INPUT 1VOLT RMS
1.59 MC
ADD E
SHORT

VR OUTPUT TO

H.P.MODEL
400 C VTVM
NEW REFERENCE

STRAY CAPACITANCE MEASUREMENT

Figure 18.75

If it is desirable to know the stray capacitance from the base to emitter in the
test circuit, asimilar measurement can be made as shown in Figure 18.75. The variable
capacitor is set at aknown value, say Ch so Garay = VR(10 -8 )— CI. Note that in this
determination of stray capacitance the normal circuit reference has been changed.
Care must be taken to insure that the old reference is not shorted to the new test
reference.

NOTES

513
 _2W2193 "
2N2193A
2N2194
FEATURES:
This family of General Electric devices are PLANAR EPI-
TAXIAL transistors designed for high speed switching and
• Low Leakage Current
11. LOW Let 111331/
2N2194A
high frequency amplifier circuits. le' Guaranteed current gain from
0.1 to 1000 ma. 2N2195
lt> High Breakdown Voltage
2N2195A
absolute maximum ratings (25°C unie.therwise ,pecitied)
.310H.
DIMENSIONS WITHIN
2N2193 2N2194 2N2195 ((DEC OUTLINE
MI Nos
Vohoge 2N2193A 2N2194A 2N2195A TO-5 325 mg
Collector to Base Ve110 80 60 45 volts
Collector to Emitter Wm) 50 40
Emitter to Base V8150 8 5 2
g volts N . pee ms me... we
adt MN. TM .01. um mcluel re7,
dlumel• Mee Inms sm.. emceed
Current 00
Collector 1, 1.0 1.0 1.0 amp w« Ihnured tmorn elm dmamele el
added dem
ece
Transistor Diuipation
(Free Air 25 °C)* PT 0.8 0.8 watts
OSTI Jr
p.
5pecmled lead.melem ep
ecne beteeen 050 and ISO g g 07:2\__11 5 "

(Free Air 25°C)** PT 0.6 watts

lee, the bee me, Pee. 150 antl I5
1«zootem-1
magraum el Oil dmerneler 0held
437
(Case Temperature 25°C)*** PT 2.8 2.8 N watts ol these tones 15e NM [Wen a K.
meelled lees may asette1...d MOTE 31
(Case Temperature 100°C)*•• PT 1.6 1.6 'veep. mn OE noles whde Imes.
entn, Mk muenl....
Temperature ed.

Storage Tn. *If— —65 to +300 —)** °C

Operating Junction T., «c(-- —60 to +200 —le. °C .02111NOTEI) —
*Derate 4.6 mw/°C increase in ambient temperature above 25°C
CONNECTED
**Derate 3.4 mw/°C increase in ambient temperature above 26°C
ir24
INTERNAL,

***Derate 16.0 mw/°C increase in case temperature above 25°C TO CASE

electrical characteristics: (25C'uni.., therv.i ,,•pocifled)
2N2193 2N2194 2N2195
2N2193A 2N2194A 2N2195A
Dr Cl-loRoc -rFniSTICS Min. Max.
ilff> Collector to Base Voltage fin = 100 ea) \Turin 80 60 45
Min. Max.
;:; '
,Z, 8 Min. Max.
IIle Collector to Emitter Voltage (i n = 25 ma) t 60 40 26
Emitter to Rasa Voltage Os = 100 sa) 5 5 volts
volts
Forward Current Transfer Ratio
(IC= 150 ma, Vcs = 10 V) t he. 40 120 20 60 20
(Ic= 10 ma, Vco = 10 V) hr. 30 15
(Ic = 1000MS, Vco = 10 V)t has 16
(10 = 0.1 ma, Vce = 10 V) hr. 15
(I °= 500 ma, Vcs = 10 V) t h.,s 20 12
(Ic= 10 ma, Vc.. = 10 V,Ts= —55°C) hao 20
Base Saturation Voltage fin = 150 ma, ID= 15 Ma) VBEISAT, 1.3 1.3 1.3 Volts
Collector Saturation Voltage go = 150111£1, In = 15 ma) VCIE,SAT, (0.36 volts max., 2N2193, 94,96 only)
VCECSAT, (0.25 volts max., 2N2193A,94A,95A only)
VCIUBAT, (0.16 volts typ., 2N2193A,94A,95A only)
r-, er:TERISTICS
Leakage Current (Vas = 30 V) Icen 10 100 mua
(VC. = 30 V,Ta = 150°C) IIcc e
oo
n 10 25 50 ca.
(V..= 60 V) inga
(Vcs = 60 V, Ta = 150°C) I:: 26 As.
Emitter Base Cutoff Current (V.. = 5V) I 50 mica
Emitter Base Leakage Current (Vs. = 3V) Itte 50 100 mi.ta

,JGY c.HARACTERISTICS
Current Transfer Ratio (Ic = 50 ma, Vox, = 10 V, f= 20 Me) ht. 2.6 2.5 2.5
Collector Capacitance Om = 0, VCIS = 10 V,f= 1Ma) Cob 20 20 20 pf

CHARACTERISTICS (See Figure 1)

l\. \: 15V)
Rise Time t. 70 70 nsec
Storage Time t. 150 150 nsec
ti 50 50 nsec
Fall Time

e
- 4)ELECTRIC
tPulse width -300 µSee, duty cycle
CHAPTER

GENERAL c 111111
 19 THE TRANSISTOR SPECIFICATION SHEET

Part 1—The Transistor Specification Sheet

The published transistor specification sheet is fully as important as the device it
describes since it provides the description necessary for sensible use of the subject
transistor.
Four general categories of information are presented. These are
1. astatement of broad device capabilities and intended service
2. absolute maximum ratings
3. electrical characteristics
4. generic or family electrical characteristics
Let's study each of these categories in some detail and use the specification sheet for
2N2193 through 2N2195 as aguide.

1. GENERAL DEVICE CAPABILITIES

The lead paragraph found at the top of the sheet furnishes the user with aconcise
statement of the most likely applications and salient electrical characteristics of the
device. It is useful in first comparison of devices as one selects the proper device for a
particular application.

2. ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings specify those electrical, mechanical, and thermal ratings
of a semiconductor device which, as limiting values, define the maximum stresses
beyond which either initial performance or service life is impaired.

VOLTAGE
The voltages specified in the Absolute Maximum Ratings portion of the sheet are
breakdown voltages with reverse voltage applied to one selected junction, or across
two junctions with one junction reverse biased and the second junction in some speci-
fied state of bias. Single junction breakdown either between collector and base or
between emitter and base has the form shown in Figure 19.1.

CURRENT

1: DRWARD
CURRENT

P N JUNCTION
FORWARD BIASED

BREAKDOWN
VOLTAGE
VOLTAGE

?LEAKAGE
CURRENT

14-- AVALANCHE
CURRENT

P N JUNCTION
[REVERSE BIASED

TYPICAL VOLTAGE CURRENT

CHARACTERISTICS OF A PN JUNCTION
Figure 19.1

516
 THE TRANSISTOR SPECIFICATION SHEET 19
The solid portion of the curve is the active, normally used portion of a diode or
any compound junction device. The dotted portion exhibits large dramatic changes in
reverse current for small changes in applied voltage. This region of abrupt change is
called the breakdown region. If breakdown occurs at relatively low voltage, the mecha-
nism is through tunneling or "zener" breakdown. The means of conduction is through
electrons which have "tunneled" from valence to conduction energy levels. A more
complete explanation of tunneling is contained in the Tunnel Diode Manual.*
At higher voltage levels conduction is initiated and supported by solid ionization.
When the junction is reverse biased, minority current flow (leakage current) is made
up of holes from the n-type material and electrons from the p-type material. The
high field gradient supplies carriers with sufficient energy to dislodge other valence
electrons, raising their energy level to the conduction band resulting in achain genera-
tion of hole-electron pairs. This process is called avalanche. While theory predicts an
abrupt, sharp (sometimes called hard) characteristic in the breakdown region, asoft or
gradual breakdown often occurs. Another possibility is the existence of a negative
resistance "hook." The hook usually occurs when zener breakdown is the predominant
mechanism. Figure 19.2 graphically illustrates these possibilities. In practice, silicon,
because of lower leakage current, exhibits asharper knee than does germanium.

VOLTAGE

LEAKAGE CURRENT
*I-- RESISTIVE
COMPONENT
NEGATIVE
SOFT KNEE
RESISTANCE

P N JUNCTION
REVERSE BIASED
CURRENT
AVALANCHE
4-
CURRENT

TYPICAL VARIATIONS IN BREAKDOWN

CHARACTERISTIC OF A PN JUNCTION
Figure 19.2

The family of the 2N2193 to 2N2195 silicon devices are measured for individual
junction breakdown voltages at acurrent of 100 microamperes. V0E0, the collector-base
diode breakdown voltage— with emitter open circuited or floating — is shown to be a
minimum of 80 volts for the 2N2193 and 2N2193A.
VE110, the emitter-base breakdown voltage — with collector open circuited or floating
—is specified at 8volts minimum for the 2N2193 and 2N2193A.
The breakdown voltage between collector and emitter is amore complex process.
The collector-base junction in any configuration involving breakdown is always reverse
biased. On the other hand, the condition applied to the emitter-base diode depends
upon the nature of base lead connection. The most stringent requirement is realized
by allowing the base to float. The next most stringent requirement is connecting the
*See references at end of Chapter 1.

517
 19 THE TRANSISTOR SPECIFICATION SHEET

base to the emitter through aresistor. A more lenient measurement is with base and
emitter shorted. Finally, the condition yielding the highest breakdown voltage is that
which applies reverse bias to the emitter-base junction. The symbols for the breakdown
voltage, collector to emitter, under the foregoing base connection conditions are VCEO,
VEER, VCER, and VcEx respectively. On some specification sheets the letter B, signifying
breakdown, precedes the voltage designation, i.e., BV cE o.

The generic shape of breakdown characteristics differs among transistors fabricated

by different processes. Figure 19.3 is typical of the planar epitaxial 2N2193. Note that
the BVcEo curve exhibits little current flow (IcEo) until breakdown is initiated. At break-
down a region of negative resistance appears and disappears at increased collector
voltage. The region of negative resistance is not suitable for measurement and specifi-
cation because of instability. The low current positive resistance region below (in volt-
age) the breakdown region is so low as to cause instrumentation difficulties. It is
desirable, therefore, to measure breakdown voltage at a current, in the breakdown
region, where the slope is positive. This current for the 2N2193 family is 25 ma.
Since BVcint and BVcEx as well as BVeno exhibit anegative resistance region, they
must also be measured in aregion of positive resistance. The voltage thus measured is
always less than voltage needed to establish breakdown. For this reason it has been
suggested that these voltages be named differently than breakdown voltages. One
proposal is to designate them as "sustaining" voltages with the prefix letter L substi-
tuted for B, i.e., LVcER. The nomenclature VOER (BUST.) has also been used.
1000

100

25 MILLIAMPERE SENSING LEVEL BV, Ex

BV,, s

(THESE LEAKAGE CURRENTS ARE

—
I EXAGGERATED)
Ice° IICES ICE%

BVc,e(SUSTA
COLLECTOR VOLTAGE V,
TYPICAL PLANAR EPITAXIAL COLLECTOR
BREAKDOWN CHARACTERISTICS
Figure 19.3

The behavior of alloy devices is sufficiently different to warrant separate considera-

tion. Figure 19.4 illustrates atypical family of breakdown characteristics. Since leakage
currents are appreciable in this class of devices they form an important part of break-
down consideration. In the specification of BVcEo, consideration must be given to Ico
multiplication. In this connection IcEo is approximately hFE X loo. This product may
exceed 100 µa (the usual BV cE osensing current) at voltages well below breakdown.
For this reason it is common to specify breakdown at acollector current of 600 µa.
Figure 19.4 shows the realistic increase in voltage resulting from the use of a600 µa
sensing current. The earlier statement that BV cro is avery conservative rating is par-
ticularly true of germanium alloy devices. It is primarily applicable to circuits with
little or no stabilization.

518
 THE TRANSISTOR SPECIFICATION SHEET 19

10K — 'CEO

2100A A SENSING CURRENT

0I

9 %0 90.0 I BVCBO
COLLECTOR VOLTAGE 110/c ,x

TYPICAL FAMILY OF ALLOY TRANSISTOR

BREAKDOWN CHARACTERISTICS
Figure 19.4

BVcEs is measured with the base shorted to the emitter. It is an attempt to indicate
more accurately the voltage range in which the transistor is useful. In practice, using
aproperly stabilized circuit, such as those described in Chapter 4, the emitter junction
is normally forward biased to give the required base current. As temperature is in-
creased, the resulting increase in ¡co and hsE requires that the base current decrease if
a constant, i.e., stabilized, emitter current is to be maintained. In order that base
current decrease, the forward bias voltage must decrease. A properly designed biasing
circuit performs this function. If temperature continues to increase the biasing circuit
will have to reverse bias the emitter junction to control the emitter current. This is
illustrated by Figure 4.1 which shows that VEE = 0 when Ic = 0.5 ma at 70°C for
the 2N525. VEE = 0is identically the same condition as abase to emitter short as far
as analysis is concerned. Therefore, the BVcEs rating indicates what voltage can be
applied to the transistor when the base and emitter voltages are equal, regardless of
the circuit or environmental conditions responsible for making them equal. Figure 3.4
indicates anegative resistance region associated with ICES. At sufficiently high currents
the negative resistance disappears. The 600 µa sensing current intersects ICES in the
negative resistance region in this example. Oscillations may occur depending on the
circuit stray capacitance and the circuit load line. In fact, "avalanche" transistor
oscillators are operated in just this mode.
Conventional circuit designs must avoid these oscillations. If the collector voltage
does not exceed VA (Figure 19.4) there is no danger of oscillation. VAis the voltage
at which the negative resistance disappears at high current.
To avoid the problems of negative resistance associated with BVcEs, BVcEE was
introduced. The base is connected to the emitter through a specified resistor. This
condition falls between BVcE0 and BVcEs and for most germanium alloy transistors
avoids creating anegative resistance region. For most low power transistors the resistor
is 10,000 ohms. The significance of BVcEE requires careful interpretation. At low volt-
ages the resistor tends to minimize the collector current as shown by equation (3s), in
Chapter 3. Near breakdown the resistor becomes less effective permitting the collector
current to increase rapidly.
Both the value of the base resistor and the voltage to which it is returned are
important. If the resistor is connected to aforward biasing voltage the resulting base
drive may saturate the transistor giving the illusion of a collector to emitter short.
Returning the base resistor to the emitter voltage is the standard BVcEE test condition.
If the resistor is returned to avoltage which reverse biases the emitter junction, the

519
 19 THE TRANSISTOR SPECIFICATION SHEET

collector current will approach leo. For example, many computer circuits use an emitter
reverse bias of about 0.5 volts to keep the collector current at cut-off. The available
power supplies and desired circuit functions determine the value of base resistance.
It may range from 100 to 100,000 ohms with equally satisfactory performance pro-
vided the reverse bias voltage is maintained.
In discussing the collector to emitter breakdown so far, in each case the collector
current is Ico multiplied by acircuit dependent term. In other words all these collector
to emitter breakdowns are related to the collector junction breakdown. They all
depend on avalanche current multiplication.
Another phenomenon associated with collector to emitter breakdown is that of
reach-through or punch-through. Silicon devices as typified by grown diffused, double
diffused, planar, mesa, and planar epitaxial structures do not exhibit this characteristic.
The phenomenon of reach-through is most prevalent in alloy devices having thin base
regions, and lighter base region doping than collector region doping. As reverse volt-
age is increased the depletion layer spreads more in the base than in the collector and
eventually "reaches" into the emitter. An abrupt increase in current results.
The dotted lines in Figure 19.4 indicate the breakdown characteristics of areach
through limited transistor. Several methods are used to detect reach through. BVcEx
(breakdown voltage collector to emitter with base reverse biased) is one practical
method. The base is reverse biased by 1volt. The collector current IcEx is monitored.
If the transistor is avalanche limited BVezx will approach BVcao. If it is reach-through
limited it will approach BVcEs.
Note that IcEx before breakdown is less than kn. Therefore, if leo is measured at a
specified test voltage and then the emitter is connected with areverse bias of 1volt,
the 'co reading will decrease if reach-through is above the test voltage and will increase
if it is below.
"Emitter floating potential" is another test for reach-through. If the voltage on an
open-circuited emitter is monitored while the collector to base voltage is increased, it
will remain within 500 mv of the base voltage until the reach-through voltage is
reached. The emitter voltage then increases at the same rate as the collector voltage.
VET is defined as (
W E — 1) where VCB is the voltage at which VEB = 1V.

CURRENT

The absolute maximum collector current, shown as 1ampere for the 2N2193, is a
pulse current rating. In this case it is the maximum collector current for which hEE is
specified. In some cases the current level at which hEE drops from its maximum value
by 50% is specified. In all cases judgement concerning adverse life affects is amajor
consideration. Also in all cases no other absolute maximum rating can be exceeded in
using this rating. In cases of very short, high current pulses, the power dissipated in
transition from cutoff to saturation must be considered so that thermal ratings are
not exceeded.

TRANSISTOR DISSIPATION

Transistor dissipation ratings are thermal ratings, verified by life test, intended to
limit junction temperature to asafe value. Device dissipation is shown for three cases.
The first indicates the transistor in free air at an ambient temperature of 25°C. The
2N2193 under these conditions is capable of dissipating 0.8 watt. Further, we must
derate at arate of 4.6 mw/ °C for an ambient temperature above 25°C. This thermal
derating factor can be interpreted as the absolute maximum thermal conductance

520
 THE TRANSISTOR SPECIFICATION SHEET 19

junction to air, under the specified conditions. If dissipation and thermal conductance
are specified at 25°C case temperature an infinite heat sink is implied and both dissipa-
tion and thermal conductance reach their largest allowable values. For the 2N2193
these are 2.8 watts and 16 mw/ °C respectively.
Both free air and infinite heat sink ratings are valuable since they give limit appli-
cation conditions from which intermediate (in thermal conductance) methods of heat
sinking may be estimated.

TEMPERATURE
The 2N2193 family carries a storage temperature rating extending from —85°C
to +300°C. High temperature storage life tests substantiate continued compliance
with the upper temperature extreme. Further, the mechanical design is such that
thermal/mechanical stresses generated by rated temperature extremes cause no elec-
trical characteristic degradation.
Operating junction temperature although stated implicitly by thermal ratings is
also stated explicitly as an absolute maximum junction temperature.

3. ELECTRICAL CHARACTERISTICS
Electrical characteristics are the important properties of a transistor which are
controlled to insure circuit interchangeability and describe electrical parameters.

DC CHARACTERISTICS
The first characteristics shown are the voltage ratings, repeated in the order of the
absolute maximum ratings, but this time showing the conditions of test. Note that
these and subsequent electrical parameters are measured at 25°C ambient temperature
unless otherwise noted. The 2N2193 has the highest rated breakdown voltages of the
series at Vcgo = 80V, VcEo = 50V, and VEE0 = 8V.
Forward current transfer ratio, hFE, is specified over four decades of collector
current from 100 microamperes to 1ampere. Such wide range in collector current is
feasible only in transistors having very small leakage currents. Note that hrE measure-
ments at 150, 500 and 1000 ma. are made at a2% duty cycle and pulse widths less
than or equal to 300 microseconds. This precaution is necessary to avoid exceeding
thermal ratings. Both the 2N2193 and 2N2193A have aspecified minimum current gain
at —55°C. A collector current of 10 ma. was chosen as being most useful to the circuit
designer who wishes to predict low temperature circuit performance.
Base saturation, VBE (SAT), specifies the base input voltage characteristic under the
condition of both junctions being foreward biased. The conditions of measurement
specify abase current of 15 ma. and acollector current of 150 ma. Base-emitter drop
is then 1.3 volts. This parameter is of particular interest in switch designs and is
covered in further detail in Chapter 3 (Equations 3u & 3v).
Collector saturation voltage, VCE (SAT), is the electrical characteristic describing the
voltage drop from collector to emitter with both base-emitter and collector-base junc-
tions foreward biased. Base and collector currents are stipulated. For the 2N2193
through 2N2195 these are 15 ma. and 150 ma. respectively. The quotient of collector
and base currents is termed "forced beta."
The principal difference between "A" and "non-A" versions of the 2N2193 family
lie in their maximum collector saturation voltages. "A" versions exhibit 0.16 volts
typically and are specified at 0.25 volts maximum. The "non-A" versions are specified
at 0.35 volts maximum. It is interesting to note that the 1.05 volt (minimum )difference

521
 19 THE TRANSISTOR SPECIFICATION SHEET

between VBE (SAT) and VCE (SAT) is the level of false trigger (noise immunity level) for
DCTL switches. In germanium alloy devices this level is generally less than 0.3 volt
and is seldom greater than 0.7 volt in other silicon devices (see Chapter 6). The wide
difference in VB.; (SAT) and VCE (SAT) is undesirable if Darlington connection of devices
is desired for saturated switching. The collector saturation characteristic of the com-
pound device demonstrates that the lead section is incapable of saturating the output
section. Modification of the circuit to provide separate connection of the input section
collector directly to the joint collector supply will provide the needed VEE (SAT) to
allow output section saturation.

CUTOFF CHARACTERISTICS
Chapter 1contains adetailed study of transistor leakage currents. This examination
deals with phenomena which predominate in alloy structures. The principal differences
in planar epitaxial devices lie in the relative magnitudes of the leakage current compo-
nents. The complete protection afforded by the passivation layer reduces surface
leakage to avery small value. Further, it reduces the surface thermal component by
decreasing recombination velocity. Figure 1.25(B) shows the variation with tempera-
ture of kilo for units of the 2N2193 family. It is interesting to note that the theoretical
semi-log plot of IcB0 vs. temperature is a straight line. At high temperatures planar
devices follow predicted behavior quite well. At lower temperatures, the temperature
rate is considerably less than that which would be predicted by the theoretical model.
The 25°C Imo and Imso maximum limits are both 100 nanoamperes. I CRO rises to
25 microamperes at 150°C, typically, and carries a 150°C upper limit of 50 pa.

HIGH FREQUENCY CHARACTERISTICS

The small-signal foreward current transfer ratio, lb., is shown as aminimum of 2.5
at 20 mc. This parameter is specified for those amplifier applications requiring control
of high frequency lb.. Chapter 18 treats the measurement of high frequency hr., in
detail. See also Chapter 2.

SWITCHING CHARACTERISTICS
Chapters 6and 18 on switching and measurements, respectively, discuss and define
transient response times td, t,, t., and tr. The circuit used to measure t,, t., and tr is
shown in Figure 19.5. The specified maximum rise, storage, and fall times are measured
in this circuit. The base of the transistor under test is clamped at approximately —1.5
volts by the diode returned to a—1 volt bus. As the point VI., is raised in potential the
base is unclamped and the transistor moved through the active region to saturation.
As noted in the referenced chapters, the switching times measured are highly circuit

0-1-51
—IV

S266G
If DIODE
Vin
Vour
1
K

100 0 40
OHMS OHMS OHMS

Vb SWITCHING 7V

sr
(2N2I 93, 2N2193A, 2N2 19 4 AND 2N2 19 4A ONLY)

Figure 19.5

522
 THE TRANSISTOR SPECIFICATION SHEET 19

dependent. By the time this description is published more thorough switching char-
acterization will be made available, which specify td, t,, t., and tr as afunction of the
ratio of collector current to foreward base current (forced beta).

GENERIC CHARACTERISTICS
Much information about the behavior of semiconductor devices is conveyed by
showing typical behavior. This information is presented graphically and differs from
other electrical specifications by not bearing the high statistical assurance associated
with maximum and minimum limits. Statistical confidence is assigned the generic
characteristics of some devices by showing 5th, 50th, and 95th percentile points of a
given characteristic. This sort of specification is found as part of very thoroughly
characterized devices such as the 2N335 and 2N396.

1000
1000

I
900
900 1 I

800
800
%
700 1
700
2 13WQ) 25°C
2 8WC)25 ° C
CASE CONSTANT
CASE CONSTANT 600
6 N in DISSIPATION
4, DISSIPATION
\ ea,
%
! 5
.2
40 2,
40 '0
\
\\ I8•5 MA/STEP
\ 1E05 MA/STEP

ill
30
30

/"......--......"----.1 •
20
0 Ci
20 I •
• .. ...
•
...„.
10
10 I -

-.__ \
s -- ....... 10 20
10
VcE (VOLTS) VaE (VOLTS)

2N2I93,A 2N2194, A

1000

900 I
2.8W 0 25"C
800 CASE CONSTANT
DISSIPATION
%
700

o
600
41;‹,
'0
500 0,
e0
1
e
400
. ...
'e .°
30
2
-
s te

20

10

0 5 10 15
VcE (VOLTS)
2N2I95, A

Figure 19.6

523
 19 THE TRANSISTOR SPECIFICATION SHEET

The specification sheet for the 2N2193 family includes collector family data for
the 2N2193, 2N2194 and 2N2195 and associated "A" versions. The hyperbola of con-
stant 2.8 watt 25°C dissipation is shown in Figure 3.6 to demark the area of permissible
static operation as defined by previously discussed thermal limitations. In addition, a
triangular area bounded by the collector current and collector voltage axes and aline
noted as "region defined by specification" is specified. This area is one that defines
the safe boundary for transient operation and should at no time be exceeded.
Semiconductor manufacturers go to great lengths in constructing their product
specification sheets because they realize the value of offering the designer adequate
information. If the device described therein is to be of use to the design engineer, is to
be used properly for optimum performance and reliability by the designer within the
limits specified by the manufacturer, the specification sheet must be accurate, com-
plete, and reliable. This requires precise and time consuming measurements, coupled
with costly hours of anlysis and preparation of the final specification sheet. The tran-
sistor specification sheet is, without doubt, the most important work tool the electronics
circuit designer has at his disposal. When understood by the designer and used intelli-
gently, many labor hours can he saved.

EXPLANATION OF PARAMETER SYMBOLS

SYMBOL ELEMENTS

A Ampere (a.c., r.m.s or d.c.), ambient, anode electrode

a Ampere (peak or instantaneous)
B, b Base electrode, breakdown

C, c Capacitance, collector electrode, cathode electrode

(Delta) A small change in the value of the indicated variable

E, e Emitter electrode

F, f Frequency, forward transfer ratio

G, g Gain, acceleration of gravity, gate electrode

h General symbol for hybrid parameter

I, i Current, input, intrinsic region of device

J, i Reference electrode

K, k Unspecified (general) measurement electrode. Also degrees Kelvin

L, I Inductance

N, n n-region of semiconductor device

0, o Output, open circuit

P, P Power, p-region of semiconductor device

O Charge

R, r Resistance, reverse transfer ratio

Temperature
Time

524
 THE TRANSISTOR SPECIFICATION SHEET 19

V Voltage (max., avg. or rms)

Volt (peak or instantaneous)

Watt (max., avg. or rms )

Watt (peak or instantaneous)

X Unspecified (general) parameter

Y General symbol for an admittance parameter

O (Theta) Thermal resistance

Z, z General symbol for impedance, impedance parameter

DECIMAL MULTIPLIERS
Prefix Symbols Multiplier Prefix Symbols Multiplier
tera T 10 12 centi c 10 -2
giga G 10 9 milli m 10 -3
mega M or Meg 106 micro P 10 -6
kilo K or k 103 nano n 10 -9
hecto h 10 2 pico 10 -12
deka da 10 femto F 10 -1 5
deci d 10 -1 atto a 10-13

PARAMETER SYMBOLS

BVcso *Dc breakdown voltage collector to base junction reverse biased,

emitter open-circuited (value of Ic should be specified).

BVcso *Dc breakdown voltage, collector to emitter, with base open-

circuited. This may be a function of both "m" (the charge carrier
multiplication factor) and the hn, of the transistor. Specify Ic.

BVCER *Dc breakdown voltage, similar to BVcE0 except aresistor value "R"
between base and emitter.

BVCES *Dc breakdown voltage, similar to BVcE0 but base shorted to emitter.

BVCEV ''Dc breakdown voltage, similar to BVcE0 but emitter to base junc-
tion reverse biased.

BVccx *Dc breakdown voltage, similar to BVcE0 but emitter to base junc-
tion reverse biased through aspecified circuit.

BVEE0 *Dc breakdown voltage, emitter to base junction reverse biased,

collector open-circuited. Specify I.

BVR Dc breakdown voltage, reverse biased diode.

Barrier capacitance.

Ceb *(Common base) capacitance emitter to base, collector open.

Input capacitance.

Cob *(Common base) collector to base Output capacitance measured

Co. *(Common emitter) collector to emitter.) across the output terminals.
+Test conditions must be specified.

525
 19 THE TRANSISTOR SPECIFICATION SHEET

f Frequency at which measurement is performed.

fhfb (Lb)
(Common base) small-signal short-circuit forward current transfer
ratio cut-off frequency.
fht. (f..) (Common emitter) small-signal short-circuit forward current trans-
fer ratio cut-off frequency.

f.... (f...) Maximum frequency of oscillation.

f
t
Gain bandwidth product frequency at which the small signal, com-
mon emitter, short-circuit, forward current, transfer ratio (hr.) is
unity or zero db.

—g Negative conductance.

Gpb
*(Common base) small-signal power gain.

GPE
*(Common emitter) large-signal power gain.

G.. *(Common emitter) small-signal power gain.

Gee (CONY.) *(Common emitter) conversion gain.

hfb (Common base)

hr. (Common collector)

Small-signal short-circuit forward
current transfer ratio, output ac
11.. (Common emitter) short-circuited.

hfJ (General)
1
hPE
*(Common emitter) static value of forward current transfer ratio,
I
F
liFE = —
Ill

hF E (inv.) Inverted hF E (emitter and collector leads switched)

hlb, hie, (Common base, common emitter, common collector, general) small-
hs., hit signal input impedance, output ac short-circuited.

h IE (Common emitter) static value of the input resistance.

hi.(real) (Common emitter) real part of the small-signal value of the short-
circuit input impedance at high frequency.
hob ,h.., (Common base, common emitter, common collector, general) small-
h.„ ho signal, output admittance, input ac open-circuited.
h, b,h.., (Common base, common emitter, common collector, general) small-
h.., ho signal, reverse voltage transfer ratio, input ac open-circuited.

I, i Region of adevice which is intrinsic and in which neither holes nor

electrons predominate.
*Test conditions must be specified.

526
 THE TRANSISTOR SPECIFICATION SHEET 19

I
E, I
C, Ill Dc currents into base, collector, or emitter terminal.

I
. Base current (rms)

ib Base current (instantaneous)

I
BX Dc base current with both the emitter and collector junctions
reverse biased.

I. Collector current (rms)

L, Collector current (instantaneous)

', Bo (Ico) *Dc collector current when collector junction is reverse biased and
emitter is open-circuited.

*Dc collector current with collector junction reverse biased and base
open-circuited.

'CEE *Dc collector current with collector junction reverse biased and a
resistor of value "R" between base and emitter.

I
CES * De collector current with collector junction reverse biased and base
shorted to emitter.

I
CEV *Dc collector current with collector junction reverse biased and with
aspecified base-emitter voltage.

I
CEX *Dc collector current with collector junction reverse biased and with
aspecified base-emitter circuit connection.

L Emitter current (rms)

i. Emitter current (instantaneous)

I
EBO (
IE0) *Dc emitter current when emitter junction is reverse biased and
collector is open-circuited.

I
ECS * Dc emitter current with emitter junction reverse biased and base

shorted to collector.

I
F * Dc forward current.

IF Forward current (instantaneous).

Ir Peak point current.

hull, Peak to valley current ration.

Ix Reverse current (dc ).

IR Reverse current (instantaneous ).

527
19 THE TRANSISTOR SPECIFICATION SHEET

Iv Valley point current.

Lc Conversion loss — ratio of available signal power to the available

intermediate frequency power.

L. Total series inductance.

N, n Region of adevice where electrons are the majority carriers.

n Intrinsic stand-off ratio (unijunction).

NF Noise figure.

P, P Region of adevice where holes are the majority carriers.

Pt (peak) Peak collector power dissipation for aspecified time duration, duty
cycle and wave shape.

Pc Average continuous collector power dissipation.

P. Power output.

pt (peak) Peak total power dissipation for a specified time, duration, duty
cycle and wave shape.

PT Average continuous total power dissipation.

QSB Stored base charge.

rb' Base spreading resistance equals hi. (real) when hi. (imagi-
nary) = O.

Isms (rBB 0 ) Device resistance between base 1and base 2, emitter open-circuited
(interbase resistance — unijunction).

rCE(SAT) Device resistance, collector to emitter, under saturation conditions

(saturation resistance, steady state).

RE Rectification efficiency (voltage ).

RI
U Circuit resistance between terminals K and J.

RL Load resistance.

r. Small signal series resistance.

TA Operating temperature (ambient )

Ti Junction temperature

528
 THE TRANSISTOR SPECIFICATION SHEET 19

TSTE Storage temperature

VE, Circuit voltage between terminals K and J.

VP Peak point voltage.

Va De reverse voltage.

Var Dc voltage reach-through (formerly called punch-through CrT).

At collector voltages above reach-through VRT = VCR —VER. (
VER
normally defined as 1volt).

VV Valley point voltage.

Yfl Small signal short circuit forward transfer admittance.

Zj j Input impedance.

z0 1 Output impedance.

NOTE: DC voltage and current terminologies (as listed herein) are valid only
when measurements are made under non-oscillating conditions. Care
must be exercised with avalanche transistors as they may oscillate when
making these measurements and give erroneous readings.

ABBREVIATED DEFINITIONS OF TERMS

1. Absolute Maximum Ratings — the value when so specified is an "absolute limit"

and the device is not guaranteed if it is exceeded.

2. Applied Voltage — voltage applied between aterminal and the reference point.

*3. Constant Current — one that does not produce aparameter value change greater
than the required precision of the measurement when the generator impedance is
halved.

*4. Constant Voltage — one that does not produce aparameter value change greater
than the required precision of the measurement when the genrator impedance is
doubled.

*5. Breakdown Voltage (BV) — that value of applied reverse voltage which remains
essentially constant over aconsiderable range of current values, or where the incre-
mental resistance = 0at the lowest current in avalanche devices.

6. Limits — the minimum and maximum values specified.

7. Noise Figure (NF) — at aselected input frequency, the noise figure (usually 10
log of base 10 of ratio) is the ratio of the total noise power per unit bandwidth at a
corresponding output frequency delivered to the output termination, to the portion
thereof engendered at the input frequency by the input termination, (whose noise
temperature is standard 290°K).
*Test conditions must be specified.

529
 19 THE TRANSISTOR SPECIFICATION SHEET

8. Open Circuit — acondition such that halving the magnitude of the terminating
impedance does not produce a change in the parameter measured greater than the
required precision of the measurement.
9. Pulse — aflow of energy of short duration which conveys intelligence.
10. Pulse Average Time (tw) — the time duration from apoint on the leading edge
which is 50% of the maximum amplitude to apoint on the trailing edge which is 50%
of the maximum amplitude.
11. Pulse Delay Time (td) — the time interval from apoint on the leading edge of
the input pulse which is 10% of its maximum amplitude to apoint on the leading edge
of the output pulse which is 10% of its maximum amplitude.

12. Pulse Fall Time (te) — the time duration during which the amplitude of its
trailing edge decreases from 90 to 10% of the maximum amplitude.
13. Pulse Rise Time (t,.) — the time duration during which the amplitude of its lead-
ing edge increases from 10 to 90% of the maximum amplitude.

14. Pulse Storage Time (t.) — the time interval from apoint 10% down from the
maximum amplitude on the trailing edge of the input pulse to apoint 10% down from
the maximum amplitude on the trailing edge of the output pulse.

15. Pulse Time (t.) — the time interval from apoint on the leading edge which is
90% of the maximum amplitude to apoint on the trailing edge which is 90% of the
maximum amplitude.

16. Short Circuit — acondition where doubling the magnitude of the terminating
impedance does not produce achange in the parameter being measured that is greater
than the required precision of the measurement.

17. Small Signal — asignal is considered small when halving its magnitude does
not produce achange in the parameter being measured that is greater than the required
precision of the measurement.

18. Spike — an unintended flow of electrical energy of short duration.

19. Supply Voltage (

VBB, Vcc, VEE) — the potential of the circuit power source.

20. Thermal Equilibrium — a condition where doubling the test time does not
produce achange in the parameter that is greater than the required precision of the
measurement.

21. Thermal Resistance (0) — the temperature rise per unit power dissipation of
the junction above the device case or ambient temperature under conditions of steady-
state operation (where applicable, "case" means device mounting surface).
22. Thermal Response Time (y,.) — the time required for the junction temperature
to reach 90% of the final value of junction temperature change caused by astep func-
tion in power dissipation when the device case or ambient temperature is held constant.

23. Thermal Time Constant (7,) — the time required for the junction temperature
to reach 63.2% of the final value of junction temperature change caused by step func-
tion in power dissipation when the device case or ambient temperature is held constant.
24. Base Voltage (
VBJ) — the voltage between the base terminal and the reference
point (J).

25. Collector Voltage (V03) — the voltage between the collector terminal and the
reference point (J).

530
 THE TRANSISTOR SPECIFICATION SHEET 91
26. Cut-off Current (Luc, IKJR, IMS, IILTX) — the measured value of (K) elec-
trode de current when it is reverse-biased by avoltage less than the breakdown voltage
and the other electrode(s) is (are) de open-circuited (Luc.) or
1. returned to the reference electrode (J) through agiven resistance (Ilux)
2. de short circuited to the reference electrode (J) (Lus)
3. reverse-biased by aspecified voltage (Luv)
4. under aspecified set of conditions different from the above
27. Depletion Layer Capacitance (C dep) — the transition capacitance of areverse-
biased pn junction. (Small signal as well as de conditions to be stated).
28. Diffusion Capacitance (C dif) — the transition capacitance of aforward biased
(with an appreciable current flow) pn junction.
29. Emitter Voltage (V53) — the voltage between the emitter terminal and the
reference point (J).
30. Floating Potential ( )— the de voltage between the open circuit terminal
(K) and the reference point (J) when ade voltage is applied to the third terminal and
the reference terminal.
31. Input Capacitance (Ci s)— the shunt capacitance at the input terminals.

32. Input Terminals — the terminals to which input voltage and current are applied.

33. Inverse Electrical Characteristics [Xx.1 — those characteristics obtained

when the collector and emitter terminals are interchanged.

34. Large-signal Short Circuit Forward-current Transfer Ratio (hp3) — ratio of the
change in output current (
AL) to the corresponding change in input current ( AL).

35. Large-signal Transconductance (Gnu) — the ration of the change in output

current (AL) to the corresponding change in input voltage (
AV 1).

36. Large-signal Power Gain (Ge) — the ratio of the ac output power to the ac
input power under the large signal conditions. Usually expressed in decibels (db).
(ac conditions must be specified).

37. Maximum Frequency of Oscillation (fi.,, or L..) — the highest frequency at

which adevice will oscillate in aparticular circuit.

38. Output Capacitance (C o )— the shunt capacitance at the output terminals.

39. Output Terminals — the terminals at which the output voltage and current may
be measured.
40. Power Gain Cut-off Frequency (L i)— that frequency at which the power out-
put has dropped 3db from its value at areference test frequency (Gp(f) = constant)
with constant input power.

41. Reach Through Voltage ( VRO (formerly referred to as "punch through volt-
age") — that value of reverse voltage at which the reverse-biased pn junction spreads
sufficiently to electrically contact any other junction or contact, and thus act as a
short circuit.

42. Real Part of Small-signal Short-circuit Input Impedance [111 1(real )] — the
real part of the ratio of ac input voltage to the ac input current with zero ac output
voltage.

531
 19 THE TRANSISTOR SPECIFICATION SHEET

43. Reference Point (electrical) — the terminal that is common to both the input
and output circuits.

44. Saturation Resistance [rK, (FAT)] — the ratio of saturation voltage to the meas-
urement (K) electrode de current.

45. Saturation Voltage [Vic/ fsem] — the de voltage between the measurement
electrode (K) and the reference electrode (J) for the saturation conditions specified.
46. Small-signal Open-circuit Forward Transfer Impedance (zf j)— the ratio of the
ac output voltage to the ac input current with zero ac output current.

47. Small-signal Open-circuit Input Impedance (z u )— the ratio of the ac input

voltage to the ac input current with zero ac output current.

48. Small-signal Open-circuit Output Admittance (h. j)— the ratio of the ac output
current to the ac voltage applied to the output terminals with zero ac input current.

49. Small-signal Open-circuit Output Impedance (z. j)— the ratio of the ac voltage
applied to the output terminals to the ac output current with zero ac input current.

50. Small-signal Open-circuit Reverse Transfer Impedance (z, j) — the ratio of the
ac input voltage to the ac output current with zero ac input current.

51. Small-signal Open-circuit Reverse Voltage Transfer Ratio (h, j)— the ratio of
the ac input voltage to the ac output voltage with zero ac input current.

52. Small-signal Power Gain (G 5)— the ratio of the ac output power to the ac
input power. Usually expressed in db.

53. Small-signal Short-circuit Forward Current Transfer Ratio (h i)— the ratio of
the ac output current to the ac input current with zero ac output voltage.

54. Small-signal Short-circuit Forward Current Transfer Ratio Cut-off Frequency

(fi.) — the frequency in cycles per second (cps) at which the absolute value of this
ratio is 0.707 times its value at the test frequency specified (Gp(f) = constant).

55. Small-signal Short-circuit Forward Transfer Admittance (yf j)— the ratio of the
ac output current to the ac input voltage with zero ac output voltage.

56. Small-signal Short-circuit Input Impedance (hb i)— the ratio of the ac input
voltage to the ac input current with zero ac output voltage.

57. Forward Voltage (V55) — highest value of positive voltage at which the forward
current equals the maximum specified peak point current ( IF= Ir).

58. Peak Point Current (IF) — value of the static current flowing at the lowest posi-
tive voltage at which giddy = 0.

59. Peak Point Voltage (VF) —the lowest positive voltage at which d1/d5 = O.

60. Peak to Valley Ratio I

F/I
v— the ratio of peak point current to valley point
current.

61. Valley Point Current (Iv) — the value of the static current flowing at the second
lowest positive voltage at which df/dv = 0.

62. Valley Point Voltage (V5 )— the second lowest positive voltage at which
df/dv = 0.

532
 SPECIFICATIONS 19

Part 2—Specifications
This portion of Chapter 19 consists of three parts:
1. C.E. SEMICONDUCTOR PRODUCTS SELECTION CHARTS
(Transistors, Special Silicon Products,
Functional Devices, and Diodes )* beginning on page 534.
2. G.E. SEMICONDUCTOR OUTLINE DRAWINGS.. .
beginning on page 575.
3. REGISTERED JEDEC TRANSISTOR TYPES CHART
(With Closest GE Type Interchangeability
Information ) beginning on page 590.
Since asemiconductor device, such as a transistor, can be specified and char-
acterized in any number of ways and under a variety of test conditions it is at best
difficult to offer detailed data on all types in a book of this nature. The presentation
of detailed information describing an individual device is more the purpose of the
specification sheet (see Part 1 of this chapter). Seasoned circuit designers will
always refer to the semiconductor device manufacturer's specification sheet as a prime
source of electrical and physical data when designing. But this usually comes after
device "selection."
If the circuit designer is to approach his design intelligently, he must
first know what devices are available to do the circuit job he has in mind; it is at
this point that the following selection charts will be valuable since they allow him to
take a broad look over the manufacturer's line of products (in this case G. E. Semi-
conductors) with the hope of filling his device requirements thus leading to circuit
design success.

To find General Electric Turn to page

NUMERICAL TYPE INDEX (See back of book)
TRANSISTORS 534
Silicon
Economy 534
NPN Grown Diffused 536
Power 539
Amplifiers 543
Switches and Amplifiers 546
High Speed Switches 549
Germanium
NPN Rate Grown 551
PNP Alloy 552
PNP High Frequency (PEB—Prolongated Exterior Base) 554
SPECIAL SILICON PRODUCTS 555
Reference Amplifiers 555
Silicon Controlled Switches 556
Unijunctions 558
FUNCTIONAL DEVICES (ACTIVE DISCRETE) 560
Choppers 560
Darlingtons 560
Differential Amplifiers 561
DIODES 562
Silicon
Signal (Mili Heatsink, DHD, DO-7, Diffused Junction, Kovar Tab, Point Contact) 562
Matched Pairs and Quads 566
Snap-off 567
NPN Microphoto 567
Germanium
Point Contact 568
Bonded Junction 569
Video Detectors 570
Tunnel Diodes 571
Back Diodes . 573
Gallium Arsenide
Tunnel Diodes 574
OUTLINE DRAWINGS 575
REGISTERED JEDEC TRANSISTOR TYPES WITH INTERCHANGEABILITY INFORMATION 590
*For other General Electric Product information see Chapter 20.

533
 61.
e SILICON TRANSISTORS

MIMMIMIMMmmilimilimmilm SNOIIVDIAIDadS
ECONOMY NPN Planar (See Outline Drawing No. 1)

Small Signal Amplifiers — Audio to 30mc (16A Product Line)

hFE hr.. W E., Pr Cr,s ft

Ves.10v
Vr•F:=4.5v Ir=2 ma lc.-.1 ma Vcg.10v Typical
Type Ir=2 MO F.1 kc Volts milliwatts pfd mc Comments

2N2711 30-90 — RI, Converter, IF, Audio Driver & Output for
18 200 7 120
2N2712 75-225 — AM & CB Radio.

2N2715(16D) 30-90 —
18 200 t 120 RF Converter, IF for AM & CI) Radio
2N2716(16D) 75-225 —
2N2921 — 35-70
2N2922 — 55-110 Higher Collector Voltage and 2 to 1 AC Beta
2N2923 — 90-180 25 200 7 120 (hte) Spread for Consumer and Industrial
150-300 Applications.
2N2924 —
2N2925 — 235-470
2N2926 — 35-470 18 200 -
. 120 Low Cost Spread Type.
2N3390 400-800 — _
2N3391 250-500
2N3391 A 250-500 Optimized Types for Ultra Ifigh Beta, Low Noise,
2 to 1 DC Beta (hgE) Spreads, High Collector
2N3392 150-300 Voltage For Consumer & Industrial Applications.
2N3393 90-180 _
200 120
2N3394 55-110
2N3395 150-500 Combines 2N3391 and 2N3392
2N3396 90-500 Combines 2N3392 and 2N3393.
2N3397 55-500 Combines 2N3391. 2, 3, 4.
2N3308 55-800 Combines 2N3390, 1, 2, 3, 4.

High Frequency Amplifiers and Oscillators — 10 mc to 950 mc Epitaxial (16G Product Line)

cno = 18
20 Nlin 200 1.3 1000 '1' \ & FM Tuner, IF and 111IF Oscillators.
16G2 Vcaow 30
 High Frequency Amplifier — 10 mc-250 mc, for Forward AGC (16K Product Line)
Forward AGC, VHF BF and IF Amplifiers (TV
16K :10 200 1.1 1000
le=4 ma. Zit FM).

High Frequency Amplifiers and Oscillators —262.5 kc to 100 mc Epitaxial (16L Product Line)

I6L2 20-40 250

I6L3 35-70 30 200 300 Very Low 2 mc Noise for AM RI' Stages.
16L4 60-120 350
16L22 20-40 — 250
I6L23 35-70 — 30 200 2.5 300 Low 2 me Noise for AM Converter %Rea..
I6L24 60-120 — 350
I6L25 100-320 — 30 200 22 400 high he>: for IF Stages.
16IA2 20-40 — 250
I6L43 35-70 — 18 200 22 300 General Purpose Types for FM and TV.
16IA4 60-120 — 350
I6L62 20-40 250
I6L63 35-70 1 200 300 High Frequency Applications in FM and TV.
—
I6L64 60-120 350

Large Signal Amplifiers and Medium Speed Switch — Epitaxial (16N Product Line)

2N2713(165) 30-90 Medium Power & Voltage. Low Vanr, lwe Hold-
18 200 7.0 120
2N2714(1611) 75-225 up to 200 ma.
2N3402 75-225 900 high Power. Medium, Voltage Lew VNAT, bra
25
(A tlachexi 8.0 120
2N3403 180-540 hold-up to 500 ma.
Ileataink
2N3404 75-225 'See Dwg. High Power. High Voltage, Low VNAT, !we
50 80
. 120
2N3405 180-5-40 No. 2) Hold-up to 500 ma.
2N3414 75-225 Medium Power. Medium Voltage, Lo'w VNAT, Ore
— 25 360 8.0 120
2N3415 180-540 — Hold-up to 500 ma.
2N34I6 75-225 — Medium Power, High Voltage, Low VSAT, bee
50 360 8.0 120
2N34I7 180-540 Hold-up to 500 ma.

High Speed Switch — Low Storage Time, Typical 3O nsec. Epitaxial, Gold Doped (16J Product Line)

J1
, 11,1 30 Min ig Similar to 2N9I4.
14 200 I 4.0 350
c.n 10,12 Ic=10 ma. Similar to 2N708.
 GROWN DIFFUSED — NPN Passivated

61
to

(See Outline Drawing No. 3)

MINIIMIIIIIIIMIIIIIMIIIIMIMIIIIIIIMMI SNOLLVDMID3dS
ht. heE I
3Vcso !coo Call PT

TYPICAL MINIMUM MAXIMUM TYPICAL MAXIMUM

VcE=5 V Icso= VcE=30 V VCII=20V
lE=1 ma VcE=5 y 50 jo lE=0 lE= —1 ma Power
f=1 kc I
c=1 ma IE=0 Te=25 °C f=1 mc. Diss

TYPe volts go 0 MW Comments

2N332 9-22 14 15 1.0 4 150

2N332A 9-22 14 15 .s 4 500

2N333( 13 ) 18-44 27 45 1.0 4 150

2N333A 18-44 27 45 .5 4 500

2N334 18-90 36 45 1.0 4 150

2N334A 18-90 36 45 .5 4 500

Audio Amplifiers
2N3350 31 37-90 as 45 1.0 4 150 Astable Oscillators
Chopper Circuits
2N335 A 37-90 45 45 .5 4 500 Flip-flop Circuits
Logic Circuits
2N335 B 37-90 45( 12 ) 60 .5 4 500 RF Amplifiers

2N336( 13 ) 76-333 75 45 1.0 4 150

2N336A 76-333 75 45 .5 4 500

2N3370 ,1 55(0 20-55(") 45 1.0() 2 125

2N337 A 55(1) 20-55( 11 ) 45 .5 2 500

2N338( 13 ) 9901 45-1500 0 45 1.0( ,) 2 125

2N338 A WO 45-1500 11 45 .s 2 500

2N470 10-25 — 15 .5 2 200

2N471 10-25 — 30 .5 2 200

2N471A 10-25 — 30 .5 2 200

2N472 10-25 — 45 .5 2 200

2N472A 10-25 — 45 .5 2 200

2N473 20-50 — 15 .5 2 200

2N474 20-50 — 30 .5 2 200

2N474A 20-50 — 30 .5 2 200

2N475 20-50 — 45 .5 2 200

2N475A 20-50 — 45 .5 2 200

Audio Amplifiers
2N478 40-100 — 15 .5 2 200 Astable Oscillators
Circuits Chopper
2N479 40-100 — 30 .5 2 200
Flip-flop Circuits
2N479A 40-100 — 30 .5 2 200 Logic Circuits
}IF Amplifiers
2N480 40-100 — 45 .5 2 200

2N480A 40-100 — 45 .s 2 200

2N541 80-200 — 15 .5 2 200

2N542 80.
-200 — 30 .5 2 200

2N542A 80-200 — 30 .5 2 200

2N543 80-200 — 45 .5 2 200

2N543A 80-200 — 45 .5 2 200

2N1248 — 15 min( 1+
) 6 0.01(s) 2 30

2N1276 9-22 10( 11 ) 40 1.0 2 150

2N1277 18-44 20(n) ao 1.0 2 150

continued next page
 61
ht. hi i: BV, so li so Ciiii Pi

MIIIIIIMIMMIIIIIMIM SNOUVDIAID3dS
TYPICAL MINIMUM MAXIMUM TYPICAL MAXIMUM

Ven=5v Icso= Vcs=30v Vcs=20v

I
g=1 ma Vcs=5v 50 ita lE=0 1E= —1 TO Power
f=lkc Ic=1 010 1E=.0 Ts=25°C f=1 mc. Diss.

Type volts 4.3 pf my/ Comments

2N1278 37-90 33( 11 ) 40 1.0 2 150 Audio Amplifiers

Astable Oscillators
2N1279 76-333 800 il 40 1.0 2 150 Chopper Circuits
1.004> Flip-flop Circuits
2N1417 30-200 — 15 2 150
Logic Circuits
It F Amplifiers
2N1418 30-200 — 30 10 2 150

4C28 9-19 15 40(4) 2.0 4 150

4C29 18-40 30 40( 4) 2.0 4 150

4C30 37-80 55 40M 2.0 4 150

4C31 76-300 115 40(4) 2.0 4 150

4D20 See leis 15-50( 10 ) 40(4) 1.0( 0) 2 150 Audio amplifiers

switches Low cost industrial
4D21 See hss 40-135( 10 ) 40( 4) 1.0( 8) 2 150

4D22 See he 120-250( 10 ) 40(4) Lee 150

4D24 See hem 15-50( 10 ) 15(0 1.0) 125

4D25 See hsg 40-135( 10 ) 15(0 1.0( 7) 125

4D26 See beg 120-250( 10 ) i-i'') 1

(See Outline Drawing No. 4)

2N2673 9-22 8-22 60 0.1 1 250 Audio Amplifiers

Astable Oscillators
2N2674 18-44 12-40 60 0.1 3 250
Chopper Circuits, Logic Circuits
250 . Flip-flop Circuits, 11F Amplifiers
2N2675 37-90 22-76 60 0.1 3
 2N2676 76-333 45-290 60 0.1 3 250 Audio Amplifiers
Astable Oscillators
2N2677 19-120( 9) 20-55( 22 ) 45 0.1 2 250
Chopper Circuits, Logic Circuits
2N2678 39-250(0 45-150(n) 45 0.1 2 250 Flip-flop Circuits, RF Amplifiers

NOTES: (I
) Typical hr. (4) VCB= 20 V, IE= 1 ma. (
2) We =20 V, TE= 0 (to) Pulsed measurement. (14) VCE= 3V, 1c= .02 ma.
(4) 'alto= 100 µa, IE= 0. (
7) VCB = 15 V,1E= 0 (
11 ) VCE =5V, lc =10 ma. (is) Ven =3V, In = 0, Tx =25 °C.
(2) "Waco IcEo = 100 pa. (
2) VCB= 12 V,IE= (12) VCE =10 V, IC=5 ma.
(
9) Vcc =20 V, le= 1ma. (IS) Also available in military types.

POWER — NPN Passivated Mesa( 5)

MINIMUM MAXIMUM
Power Dissipation
hrE (9) VCE0 VESO I
CB0 PT PT VCE (SAT) (2)
VcE.10v Free Air Case Temp I
c=2OO ma
I
c=2OO ma I
c=250µa I
E=250µa Veit =30v (t1225 °C @25 °C la=40 ma
Dveg. Ti=150 °C
Type No. Volts Volts ea Watts Watts Volts Comments

2N497(°) 5 12-36 60 8 250 0.8 4 5

2N497A 5 12-36 60 8 250 1.0 5 2 Audio Amplifiers
2N498(°) 5 12-36 100 8 250 0.8 4 5 Blocking Oscillators
2N498A 5 12-36 100 8 250 1.0 5 2 DC to AC Inverters
Amplifiers Linear
2N656(s) 5 30-90 60 8 250 0.8 4 5
Magnetic Tape Bias and
2N656A 5 30-90 60 8 250 1.0 5 2 Erase Oscillators
2N657( 21 5 30-90 100 8 250 0.8 4 5 Power Oscillators
Power Switching
2N657A 5 30-90 100 8 250 1.0 5 2
Pulse Amplifiers
2N2017 5 50-200 60 8 250 1.0 5 2 Regulated Power Supplies
2N2106 5 12-36 60(') 8 200(2) 1.0 5 5 Servo Amplifiers
2N2107 5 30-90 60(') 8 200( 2) 1.0 5 2 Servo Drivers
Solenoid Drivers
2N2108 5 75-200 60(0 8 200( 2) 1.0 5 2( 2)
High Voltage Series
2N2726 5 30-90 200 (
22 ) 10 100 1.0 5 2 Regulator
2N2727 5 75-150 200( 12 ) 10 100 1.0 5 2
continued nerd page
 MINIMUM MAXIMUM
Power Dissipation
hge (e
) VC» VEBO I
CHO PT PT VCB (SAT) (9)

SNOIIVOLIIDadS
VCE=10v Free Air Case Temp I
c=200 mo
I
c=200 ma I
c=250ga I
g=250ga Vca=30v @25 °C ( 25C 111=40 mo
Dwg. Ti=150 °C
Type No. Volts Volts go Watts Watts Volts Comments

7A30 5 12-36 40 8 10(7) 1.0 5 1.0 Typ.

7A31 5 30-90 30 8 io(7) 1.0 s 1.0 Typ. (Same applications as on
7A32 5 75-200 30 8 10( 7) 1.0 5 1.0 Typ. previous page)
7A35 5 50-200 40( 1) 160°1 10(7) 1.0 5 2(3)
2N1047 6 12-36 80 6 15() 1.0 40 7.5 (8)
2NI047A 6 12-36 80 6 350 1.0 40 7.5(8)
2N1047B 6 12-36 80 6 200 1.0 40 2.0(8)
2N1048 6 12-36 120 6 15() 1.0 40 7.5( 8)
2N1048A 6 12-36 120 6 350 1.0 40 7.5( 8)
2N1048B 6 12-36 120 6 200 1.0 40 2.0(8)
2N1049 6 30-90 80 6 15( 7) 1.0 40 7,5(8)
2N1049A 6 30-90 80 6 350 1.0 40 7.5(8)
2N1049B 6 30-90 80 6 200 1.0 40 2.0( 8)
2N1050 6 30-90 120 6 ism 1.0 40 7.5( 8)
2N1050A 6 30-90 120 6 350 1.0 40 7.5(8) (Same applications as above
2N105013 6 30-90 120 6 200 1.0 40 2.0( 8) but at higher power con-
ditions)
2N1067 7 15-75 60 12('°> 1000(11) - 5.0 -
2N1068 7, 15-75( 10 60 12( '° ) 1000( 1) - 10 -

I
c=250
VC« ma Case Temp." )
VBE= -1.5v @ 100 °C
Te=150 °C
2N2196 8 30-90 60(0 80 250 2.0 10 2
2N2197 8 75-200 60( 1) 80 250 2.0 10 2( 8)
2N2201 8 30-90 100 120 200 2.0 10 1.7
2N2202 12 30-90 100 120 200 1.0 10 1.7
2N2203 13 30-90 100 120 200 1.0 10 1.7
2N2204 14 30-90 100 120 200 1.0 10 1.7
2N2239 8 30-200 50( so) 8(17) 250 1.0 10 3

2N2995 13 30-90 100 120 200 1.5 10 1.7

7B1 a 12-36 60 80 200 2.0 10 1.7
7B2 8 30-90 60 80 200 2.0 10 1.7

2N2611 8 12-36 100 120 200 2.0 10 1.7

7B13 8 75-200 60 250 2.0 10 2
7B33 8 30-90 200(1s) 100( 14 ) 200 2.0 10 2
7B34 8 75-150 200( sr) 1000 4) 200 2.0 10 2
7C1 9 12-36 60 so 200 1.0 10 1.7
7C2 9 30-90 60 80 200 1.0 10 1.7
7C3 9 12-36 100 120 200 1.0 10 1.7
7CI3 9 75-200 60 250 1.0 10 2
7D1 10 12-36 60 80 200 1.0 10 1.7
7D2 10 30-90 60 80 200 1.0 10 1.7
7D3 10 12-36 100 120 200 1.0 10 1.7
7DI3 10 75-200 60 250 1.0 10 2 (Same applications as above
7D33 10 30-90 200(12) 100(44) 200 1.0 10 2 but at higher power con-
ditions)
7D34 10 75-150 200(12) 100(' 4) 200 1.0 10 2
7E1 11 12-36 60 80 200 1.0 10 1.7
7E2 11 30-90 60 80 200 1.0 10 1.7
7E3 11 12-36 100 120 200 1.0 10 1.7
7E13 II 75-200 60 250 1.0 10 2
7F1 12 12-36 60 80 200 1.0 4.0 1.7
7F2 12 30-90 60 80 200 1.0 4.0 1.7
7F3 12 12-36 100 120 200 1.0 4.0 1.7
7F4 12 30-90 100 120 200 1.0 4.0 1.7
7F13 12 75-200 60 - 250 1.0 4.0 2
7G1 13 12-36 60 80 200 1.5 10 1.7
7G2 13 30-90 60 80 200 1.5 10 1.7
7G3 13 12-36 100 120 200 1.5 10 1.7

7G13 13 75-200 60 - 250 1.5 10 2

7G33 13 30-90 200(12) 100 4) 200 1.5 10 2

continued nee pape
 MINIMUM MAXIMUM
Power Dissipation
hrE( 0) Wm VESO I
CBI) PT Pr VCE (SAT) (9)
VCE=10v Free Air Case Temp Ic=200 ma
I
c=200 ma Ic=250ga Ig=250ga Vcn=30v @25 °C «,. 25 °C 111=40 ma
Dwg T.i= 150°C
Type No. Volts Volts go Watts Watts Volts Comments

71, I 13 75-150 200( 12 ) 1000 -

0 200 1.5 10 2

NOTES: (I) VCER (I C= 16 ma. R = 1KD) (

2)Ti = 125°C (3) I = 10 ma (4)See outline drawing for attachment to heatsink. () Typ. It for all types,.- 15 MC
0,) Available as JAN types (MIL-S-19500/74A) (
7)Ti 1.5°C (5) 111 = 500 ma. 1B = 100 ma (
9) Pulsed Measurement: 300 gsec. pulse width, 2% duty cycle.

Yap.= 1V, lc = 750 ma (10 TJ= 175°C (

12 ) VCER (lc= 50 run. R = 5K1D (13 ) 1E = 1 ga (14 ) IC 100 ma (1 5) IE= 100 eat
\CHB (Ic =250ga, It =5K11) (17) VEBO (I E= 250µa )

Triple-Diffused NPN Passivated

MINIMUM MAXIMUM

Iwo hr z Power Dissipation

ICES Pr Pr VCE (SAT ) VCE ISAT/
VCE=1 5v VCE=5V VCEO @ 150°C I. Free Air Case Temp Ic=2 amps I
c=1 amp
Dwg. I
c=2 amp. I
c=500 ma @25°C @:00°C 1,3=250 ma 18=100 ma
Type No. Volts ma Amps Watts Watts Volts Volts

2N1616 14 15 min. — 60 10(4160(0 5 3 60 — —

2N1617 14 15-75 — 80 10@tt0(') 5 3 60 — —

2N1618 14 15-75 — 100 10@80( 0 s 3 60 ^ —

2N1724 14 20-90 — 80 2(D60V 3 50 1 —

2N1724A 14 50-150 — 120 2@1.00V s 3 50 6 —

2N1725 14 30-90 — 80 2 @ 60 V 5 3 50 1 —

2N2150 15 — 20-60 80 .1 @120V 2 2 30 — 1.25

2N2151 15 — 40-120 80 .1 ig120V 2 2 30 — 1.25

2N3220 15 — 20-60 80 .1 @100 2 2 30 — 1.25

2N3221 15 — 40-120 80 .1@100 2 2 30 — 1.25

2N3222 15 — 20-60 60 .1 @BO 2 2 30 — 1.25

2N3223 15 — 40-120 60 .1 (gi80 2 2 30 — 1.25

NOTES: co tcBo.
 AMPLIFIERS NPN Planar, Typical f, 130 mc
(See Outline Drawing No. 5)

Min. MAXIMUM POWER MSS. MINIMUM hFE

o
o

L,
Q.

MO
o

le=150 ma

Ic=150 ma
(SAT)

(SAT)
ma

ma
.;,-,e_
°)'

VCE=10V
C. 1,(-)

1c=1 ma
o E< Eórn Eci ,`-,ó Ró

VcE=5v
°<
8 «.'0 1--
.8 0-II 0-L^ --
Ic=150
6-II

f=1 kc
0- z, 6 -

• 18=15

e 18=15
II I d II Lil II
5111 tni .^- li 11 7t Il p II
il 7.

VISE
27

VCE
hrE

e
t 'oez
>e- -1- >'-'2 ctit@ ede) .?> .'>iz .' 5'. .?"'
VCR

✓
t
.
Typ e m

s
•

i
Volts Volts go Volts Watts Watts Comments

2.

2.
<

<

e
2N1889 40-120 80 5.0 1.3 30-100 75 15 7 0.8 1.7 35 20 20 - - High Voltage 2N1613.

2N1890 100-300 80 5.0 1.3 50-200 - - 7 0.8 1.7 - - - - - Higher voltage 2N1711.
•
2N1972 - 30 2( 7) 1.1( 7) 40 30 100 5 0.6 1.0 70 40 - - -

2N1973 75 Min.( 6) 80 1.2( 7) 0.9( 7) 76-200 75 15 7 0.8 1.7 - - - - -

2N1974 35 Min.( 5) 80 1.2( 7) 0.9(7) 36_90 75 15 7 0.8 1.7 - - - - -

2N1975 15 Min.() 80 1.2( 7) 0.9( 7) 18-50 75 15 7 0.8 1.7 - - - - -

2N1983 - 30 0.25(0 - 70-210 30 200 5 0.6 1.0 - - - - - High beta for high gain,
low noise amplifiers. .
1
,1 .

*a
2N1984 - 30 0.25( 5) - 35-100 30 200 5 0.6 1.0 - - - - - Amplifier Circuits. 3 ».
*el-
e
2N1985 - 30 0.251 51 - 15-45 30 200 5 0.6 1.0 - - - - - Amplifier Circuits. -

2N2049 - 50 0.4( 4) 0.8(a) 75 60 10 7 0.8 1.7 - - 60 - - High beta for high gain, low
noise amplifiers NF = 3db.

(See Outline Drawing No. 16)

2N870 40-120 80 5.0 1.3 30-100 75 15 7 .5 1.0 35 20 20 - - TO-18 Version of 2N1889.

2N871 100-300 80 5.0 1.3 50-200 - - 7 .4 .75 - - - - - TO-18 Version of 2N1890.

2N910 75 Min.( 5) 80 1.2( 7) 0.9( 7) 76-200 75 15 7 .4 .75 - - - - - TO-18 Version of 2N1973.

2N911 35 Min.( 6) 80 1.2( 7) (OM 36-90 75 15 7 .4 .75 - - - - - TO-18 Version of 2N1974.

2N912 15 Min.( 5) 80 1.2( 7) 0.9( 7) 18-50 75 15 7 .4 .75 - - - - - TO-18 Version of 2N1975.

continued next page
 Typical f, 130 mc (See Outline Drawing No. 16)

SNOILVDMIDUdS
MINIMUM MAXIMUM

VCEO Veso leso Var Vea

hen ht. Volts Volts VBE (SAT ) V•i: (SAT ) (SAT ) (SAT ) Cob @ Ws
Min. Max. VCE=1 OV 1C=10 ma le=1 0 ma Tr=150 °C
@le @Vee Ic=4 ma @lc @I
E 111=1 Ina 113=1 ma (,, VCB Ie=3 ma
f=100 mc le=1.5
Type ma Volts ma go Volts Volts Volts no pf Volts Comments

.01 5.0 10 100 45

2N929 40-120 — 45 5 0.6-1( 2) 1.0(2) 10 — — 5(rve)

.01 5.0 10 . 100 45

2N930 100-300 — 45 s 0.6-1(2) 1.0 (2) 10 — —
5(TYP) These devices are intended for applies-
1,5 Lions requiring high gain at low current.
.« 5.0 10 10
2N2483 40-120 — 60 6 — ,35(3) 10 — — 5(Tre)

.01 5.0 10 10 45
2N2484 100-500 — 60 6 .35( 3) 10 — — 5(rep)

Typical f, 130 mc (See Outline Drawing No. 16)

MINIMUM MAXIMUM
•
VCEO VEBo 117110 Va VCE
hre kft Volts Volts Vse (SAT) Vea SAT )
( (
SAT) (SAT Cob @ VeE
Min. Max. VIIE= 1OV I
C=10 Ma Il`=10 MO T I
— 150 ° C

@ IE @ VCE I
e=4 ma @ le @le Is=1 ma 111=1 ma 'V s Ic=3 ma
f=)00mc Is=1.5
Type ma Volts ma Ka Volts Volts Volts no pf Volts Comments

10 5. 0 1.0 100 30
200 _ _ 8 5 These devices are well suited for applica-
2N759 36-90 45 8 — 1.0 tions where the 2N335 and 2N336 have
been used and higher frequency devices or
1.0 5.0 1.0 100 30 smaller packages are required.
2N760 76-333- 45 8 — 1.0 200 — — 8 5

10 5.0 10 100 60
2N915 40-160 — 50 5 0.9 1.0 30 — — 3.5 10 These devices are intended for non-sat-
urating switching circuits, amplifier and
10 1.0 30 10 15 oscillator circuits.
2N916 50-200 — 25 5 0.9 0.5 10 — — 6 5
 NPN Planar Epitaxial Typical ft 900 mc (See Outline Drawing No. 17)

MINIMUM MAXIMUM

VCEO VEBO ICBO VBE Vez

IS PE ht. Volts Volts MT ) Vt E I
VB E ( SAT) (SAT) (SAT) Cob @ VCB
Min. Max. VcE=10v I
C= I0 MO I
C= I0 MO Ti=150°C
@le @ VCE I
C=4 TO @ IC @I
E Ia=1 ma Is=1 ma @Veil Ic=3 ma
f=100 mc 16=1.5
Type ma Volts ma iza Volts Volts Volts na pf Volts Comments

3 1 3 10 15 1.7
2N917 20 5 15 1 1 .87 .5 10 These devices are intended for use in
ultra-high frequency amplifiers and os-
3 1 3 Io 15 1.7 cillators, and in non-saturated switching.
2N918 20 6 15 1 10 1.0 .4 10

Kovar Tab (See Outline Drawing No. 18)

1.0 100 30
Kovar tab version of 2N759.
100571 — — 45 6 — — g 10

1.0 100 30 Kovar tab version of 2N760.

100571 — — 45 6 — 15 — — 8 10

NOTES (1)hfo (2) 111=0.5 ma. (3 ) 18=0.1 ma. (4) I

C= IO ma. and Ie = 1ma. (
4) 1c= 5 ma and 183=0.5 ma. (6 ) hFE = 1c = 10 ma, VCE=
(7) IC= 50 ma, la =5 ma.
e SWITCHES AND AMPLIFIERS ,'•",- NPN Planar Epitaxial

6L
Available in Seven Different Package Configurations: Three Power Packages, TO-5, TO-46, TO-50, and Kovar Tab

SNOUNDIAIDadS
a

I0
Max. MINIMUM lira

1:0

Fri
!"
X

i
c
I

i
_

°C
Case Temp @ 25
Free Air @25 ° C
a

SAT )
VCE (SAT )
a

Ic=150 ma

Ic=100 ma

Ic=150 ma

Im=150 ma
0 E

113=15 ma
0 o

Ilt — IS mn
E>

RBE:=100
Vcc=10v
b Eo Eou% Eó o ,oci
u, 8

VBE (
0- o a-
ii .
n liait
- 0- it 0 ii u, u ii
ii
i

VCER
g II . ii i 2 ii 2 7 r.

Iwo

PT

PT
• •
.
-1-
- >2 _> 2>1:: .!:2> _>>. 1,>.'

e
Dwg. vcit

<

<

<
No. Volts ma Volts

2.

2-

2.
Comments

••••

2.

e.
Type

C;
e
i.
2N2192 5 0.8 2.8
2N2350 t 100-300 10 1,1 0.35 1.3 30 15 5 0.4 5.0 75 35 Similar to 2N1711, but
15 35 15
11C702 19 lower Vaz(sAr.
0.3 1.0
2.8 0.8
2N2I92A 5
2N2350A 4 0.4 5.0
11CIBI 8 100-300 40( 2) 0.25 1.3 30 15 5 15 Similar to 2NI711, but
1.5 5.0 75 35 15 35
IICIF1 12 lower VcE(svr).
1.15 3.1
11C201520 20
1.0 50
2N2193 5 0.8 2.8
2N2351 4 40-120 50( 2) 0.35 1.3 60 25 8 0.4 5.0 30 20 Similar to 2N1613, but
15 20 15
11C704 19 lower Vca(mAr.
0.3 1.0
0.8 2.8
2N2193A 5
2N235I A 4 0.4 5.0
11C3131 8 40-120 50(2) 0.25 1.3 60 25 8 1.5 5.0 Similar to 2N1613, but
30 20 15 20 15
11C3FI 12 lower VCE(SAT).
1.15 3.1
11C203B20 20
1.0 5.0
2N2194 5 0.8 2.8 Similar to 2N696, but
2N2352 4 20-60 401 2) 0.35 1.3 30 25 5 15 - - 12 -
0.4 5.0 lower Ven(sAr.
0.8 2.8
2N2194A 5
2N2352A 4 0.4 5.0
Similar to 2N696, but
1105111 8 20-60 40( 2) 0.25 1.3 30 25 5 1.5 5.0 15 - - 12 -
1105F1 12 lower Vca(ser).
1.15 3.1
11C205B20 20
1.0 5.0
2N2195 5 0.6 2.8
2N2353 4 20 min. 25( 2) 0.35 1.3 30 50 5 - - - - Industrial Types.
.35 3.0
2N2195A 5 0.6 2.8
2N2353A 4 .35 3.0
11C7B1 8 20 min. 25( 2) 0.25 1 S SO 50 - - - - - Industrial Types.
11C7F1 12 1.5 5.0
11C2071120 20 1.15 3.1
.8 2.8 Similar to 2N1893 but
2N2243 5 40-120 80 .35 1S 60 15 7 30 20 15 20
2N2364 4 .4 5.0 - lower Vca(ser).
.8 2.8
2N2243A 5 .4 5.0
2N2364A 4
.3 1.0 Similar to 2N1893 but
11C710 19 40-120 80
.25 1.3 60 15 7 30 20 15 20 - lower Vcatsan.
IICIOB1 8 1.5 5.0
11C10F1 12 1.15 3.1
11C210B20 20
1.0 5.0
.8 2.8
2N2868 5 .4 5.0
2N2909 4
8 40-120 40 .25 1.3 30 15 5 1.5 5.0 30 20 - 20 - -
IICI1B1
IICI1F1 12 1.15 3.1
11C211B20 20 1.0 5.0
3 40-120 30( 2) .3 1.3 30 25 6 0.8 2.8 - - - 15 - -
11C1536
4JD12X043 21 Two 2N2193 transistors in a six lead TO-5 package
4JD12X047 21 Two 2N2195 transistors in a six lead TO-5 package

Kovar Tab (See Outline Drawing No. 18)

100-300M - 0.25( 5) 0.9( 5)30 15 5 100mw - 100-300 - 75 - - Kovar Tab of 2N2192, A

110551 (6)

40-120( 6) - 0.25( 5) 0.9( 5)30 15 7 100mw - 40-120 - 30 - - Kovar Tab of 2N2193, A

110553 4)

0.25( 5) 0.9( 5)30 50 5 100mw - 30-150 - - - - Kovar Tab of 2N2195, A

110557 (6) 30-150( 6) -

NOTES: Test Conditions in Italics (I) Typical ft for all types ,6= 130 Mc.
(2) \Tom

SNOILVDIAIDadS
(
2) For switching and amplifier applications.

(
4) him =Ic =10 ma, Vca =10V.

(
5) le= 50 ma, Is = 5 ma.
(
6) Storage Temperature on all types is - 65°C to +300 °C. Operating Temperature on all types is -65 °C to -1-200 °C.

6L
continued on next page
 6L
NPN Planar Passivated (1,3) (See Outline Drawing No. 5)

SNOLLVDIIDadS
Min. MAXIMUM POWER DISS. MINIMUM hen
o

2. le=150 ma
m0

Temp.
le=150 ma
0

• le=150 ma
0 o g E

< Yee (SAT)

< Van (SAT)

o

e 4=15 mo

e 4=15 mo
P e.

RBE≤10f6
VcE=10v
0> En
?.ri

@,00.0
Er!, ci ó
o o
0

O Free Air
e

1c100
uEtn

@25°C
ail, 97
-ii rd 27 ? 0 7 th ..ii

< VCER
ii . 11.11 II - ii - -›
I :

eCase
him e .. ii

• PT

PT
', CB
Typ e ,) Max.

•
Min. Volts go Volt Comments

o
2N696( 4) 20-60 40 1.5 1.3 30 100 5 0.6 1.0 - - - -

2N697( 4) 40-120 40 1.5 1.3 - 30 100 5 0.6 1.0 - - - - -

2N698 20-60 80 5.0 1.3 15 75 15 7 0.8 1.7 - - - - - High Voltage 2N696.

2N699 40-120 80 5.0 1.3 35-100 60 200 5 0.6 1.0 - - - - - High Voltage 2N697.

2N1613 40-120 50 1.5 1.3 30-100 60 10 7 0.8 1.7 35 20 20 20 - Lower leakage 2N697.

2N1711 100-300 50 1.5 1.3 50-200 60 10 7 0.8 1.7 75 35 35 40 - High beta 2N1613.

2N1837 40-120 50 .8 1.3 - 30 50 8 0.6 1.0 - - - - -

2N1893 40-120 100 5.0 1.3 30-100 _.. 90 15 7 0.8 1.7 35 20 20 - - lligh voltage 2N1613.

(See Outline Drawing No. 16)

2N717 20-60 40 1.5 1.3 - 30 100 5 .4 .75 - - - - - TO-18 Version of 2N696.

2N718 40-120 40 1.5 1.3 - 30 100 5 .4 .75 - - - - - TO-18 Version of 2N697.

2N718A 40-120 50 1.5 1.3 30-100 _ 60 10 7 0.8 1.7 - - - - - TO-18 Version of 2N1613.

2N719 40-120 80 5.0 1.3 35-100 60 200 5 .5 1.0 - - - - - TO-18 Version of 2N698.

2N719A 20-60 80 5.0 1.3 15 75 15 7 .4 .75 - - - - - TO-18 Version of 2N698.

2N720 40-120 80 5.0 1.3 35-100 60 200 5 .5 1.0 - - - - - TO-18 Version of 2N699.

2N720A 40-120 100 5.0 1.3 30-100 90 15 7 .4 .75 35 20 20 - - TO-18 Version of 2N1893.

2N956 100-300 50 1.5 1.3 50-200 60 10 7 .5 1.0 75 35 35 40 - TO-18 Version of 2N1711.

 Kovar Tab (See Outline Drawing No. 18)

0.7(6) 0.9( 6) 30 25 5 100mw Kovar tab of 2N696.

11B551 20-60( 5)

0.7( 6) 0.9( 6) 30 25 5 100mw - Kovar tab of 2N697.

116552 40-120( 5)

0.9( 6) /0 15 7 100mw - Kovar tab of 2N1613.

1113554 40-120( 5) 0.7( 6) 1

0.7(6) 0.9( 6) /
10 15 7 100mw Kovar tab of 2N1711.
11B555 100-300( 5)

1.3( 6) 0.9( 6) 40 15 7 100mw Kovar tag of 2N1893.

11B556 40-120( 5)

40-120( 5) 1.3( 6) 0.9(6) 30 25 5 100mw Kovar tab of 2N699.

11B560

NOTES: Test Conditions in Italics. 01 Typical ft for all types 130 Mc.
(2)Storage temperature on all types s -65 ° to +300 °C. Operating junction temperature on all types is -65° to +200°C.

(3) For switching and amplifier applications.

(
4) Also available in military types. (5) tiFE= lc =10 ma. VrE= 10V. (
6) lc =50 ma, la =5 ma.

HIGH SPEED SWITCHES". 3'- NPN Planar Epitaxial (See Outline Drawing No. 16)

M INIMUM MAXIMUM

VCER VCE0 VEBO I

CB0
hre Volts Volts Volts VBE (SAT ) V e SAT) too toff Cob @ Vel,
Min. Max. le=10 ma I, -10 ma Ti=150°C
(1-
Ïlc ',. Ves @le @Rom @to @ lE 18.1 ma lit=1 ma @Vcis

ma i.to Volts Volts Volts no nsec nsec pf Volts Comments

Type ma Volts ma ohms

10 1.0 30 10 100 15
30 - 6 10 Economy Irots. _

SNIOLINDI3IDadS
2N706 20 Min. 20 - 3 0.9 0.6

10 1.0 10 10 10 10 15
20-60 20 15 5 0.9 0.6 30 40 75 5 5 Economy units. high speed.
2N706A

10 1.0 30 10 30 10 20
15 5 0.8 0.4 15 40 70 6 10 Low leakage current. high speed.
2N708 30-120 20

10 0.5 - - 10 10 5
2N709 20-120 - 6 4 0.85( 6) 0.3( 6) 5( 2) 15 15 3 5 Very high speed switch.

10 1.0 10 10 10 10 15
2N753 40-120 20 15 5 0.9 0.6 30 40 75 5 5 High beta. High speed.

6L
continue on ne%1 page
 MINIMUM

61
MAXIMUM

VCER V,BO VEBO I

(Bo

SNOLLVDMIDadS
hIn: Volts Volts Volts VBE (SAT ) V,E (SAT ) t., t fr C,,i, (,, V, 1,
Min. Max. le=10 ma I, =10 ma 1
-J=150 °C
@le @W E talc @Rim @lc @I
E 4=1 ma 18=1 ma 0 Vete
Type ma Volts ma ohms ma ea Volts Volts Volts go nsec nsec pf Volts Comments

10 1.0 10ga 0 _ 100 20

2N834 25 Min. 3001 - 5 0.9 0.25 30 35 75 4 10 Low saturation voltage.
10 1.0 30 10 30 10
2N914 30-120 20
20 15 5 0.8 0.25 15 40 40 6 10 High speed. Low saturation voltage.
r
10 1.0 - - 10 10 20
2N2369 40-120 - 15 4.5 0.85 0.25 30 12 18 4 5 High speed switching.
10 .1.0 1µa 0 30 100 20
2N2481 40-120 30(2) 15 5 0.82 0.25 15 40 45 5 5 U.S. Navy Specification.

Kovar Tab See Outline Drawing No. 18)

10 1.0 10 10 10 100 15
10B551 30-120 20 15 5 0.85 0.25 25 45 50 6 10 Kovar tab version of 2N914.
10 1.0 10 10 10 100 15
10B553 30-120 20 15 5 0.85 0.4 25 40 70 - - Kovar tab version of 2N706.
10 1.0 10 10 10 100 15
10B555 20 Min. 20 15 3 0.9 0.6 30 - - - - Kovar tab version of 2N706A.
10 1.0 10 10 10 100
1011556 15
20-60 20 15 3 0.9 0.6 30 40 75 - - Kovar tab version of 2N708.

NOTES :Test Conditions in Italics. (1) Typical ft for all ypes 130 Mc.
(2) Storage temperature on all types is -65 ° to +300°C. Operating junction temperature on all types is - 65° to +200 °C.
(3) For switching and amplifier applications. (4) Storage temperature -55° C to +200° C. Operating temperature - 55° C to + 125 °C.
(5) TJ= 125 °C. (6) Ic 3 ma, Is...15 ma.
 GERMANIUM TRANSISTORS

NPN RATE GROWN (See Outline Drawing No. 22)

MINIMUM MAXIMUM MAXIMUM TYPICAL

Power PT
BEE BVCEO lam) Gain
Vco=1 v lE=0 Power fhtb

IC=1 MO Ic=300 fin Ven=15 v @ 455 kc Dissipation

db mw me Comments
Type volts AO

Preamplifier switch. Lamp driver. Schmitt

3 26.0-31.0 65 9 trigger. Waveform restoration. DC level de-
2N78 45-135 15
tection.

20 3 26.0-31.0 65 9 Applications same as 2N78.

2N78A( 7) 45-135

17-90(') 30 1.5 — 75 9 Trigger circuits. Gate circuits. Logic circuits.

2N167A( 7)
Reflex circuits. IF amplifiers. DC coupled
15(s) 5 23.5 65 9 audio amplifiers.
2N169 34-200

25( 3) 5 23.5 65 9 General purpose low level switch ).

2N169A 34-200
15(3) 5 21.0-26.0 65 5 IF amplifiers.
2N292 8-51

8-51 15( 3) 5 23.5-28.0 65 8 IF amplifiers.

2N293
9(3) 3(0 23.0-29.0( 6) 65 9 Autodyne Converter. Mixer-oscillator.
2N1086 17-200
9(3) 3(0 23.0-27.0( 6) 65 9 Autodyne Converter. Mixer-oscillator.
2N1086A 17-200
9(3) 3(0 25.0-29.0(°) 65 9 Autodyne Converter. Mixer-oscillator.
2N1087 17-200

SNOLLVDMIDadS
20 1.5 — 75 9 Decade counter. Low level switch. Amplifiers.
2N1694 15-45( 2)

(
3) BVcsa, R— 10K. (
6) Vctsw 5 V.
(
7) Also available in military types.
NOTES: 0) lc w 8 ma., Vcs =1 V
(2) lc w 2 ma., Vcs w 1 V. (
4) M AX Vcs(say) =0.4 V. (6) Conversion Gain ® 1600 kc.

6L
continued on next page
 PNP ALLOY

6L
SNOILVDIAIDUdS
TYPICAL MINIMUM MAXIMUM

hag fete BVcga I

CB0 PT
VCE= IV @ Ic=600 ga Power
1=20 ma Raz=10K @ Vag Dissipation
Dwg.
Types No. me Volts no Volts mw Comments

2N43A( 12 ) 23 34-65 1.3 30 16 45 240 See 2N525.

2N44A( 10 23 18-43 1.0 30 16 45 240 See 2N524.
2N186A 23 19-31 0.8 25 16 25 200
2N187A 23 25-42 1.0 25 16 25 200
Not recommended
2N188A 23 34-65 1.2 25 16 25 200 for new designs.
See 2N508, 2N1175
2N189 23 25-42 0.8 25 16 25 200 and 2N1413 series.
2N190 23 34-65 1.0 25 16 25 200
2N191 23 53-121 1.2 25 16 25 200
2N192 23 72-176 1.5 25 16 25 200
2N241A 23 50-125 1.3 25 16 25 200
2N319 24 25-42 2.0 20 16 25 225
2N320 24 34-65 2.5 20 16 25 225
2N321 24 53-121 3.0 20 16 25 225
2N322 24 34-65 Audio driver and audio output.
3.0 16 16 16 200
2N323 24 53-121 3.5 16 16 16 200
2N324 24 72-198 4.0 16 16 16 200
2N394 24 20-150( 2) 7.0 15 6 10 150 Medium speed switch.
2N395 24 20-150( 2) 6.0 15 6 15 200 Medium speed switch.
2N396 24 30.150( 2) 8.0 20 6 20 200 Industrial/Military-medium beta, medium speed switch.
2N396A( 12 ) 24 30-150( 2) 8.0 20( 2) 6 20 200 Same as 2N396. Mil-S-19500/6411
2N397 24 40.150(2) 12.0 15 6 15 200 Industrial/Military-medium speed switch.
2N404( 12 ) 24 — 8.0 24(0 5 12 150 Medium speed switch—wide beta spread. MIL-T-19500/20.
2N404A 24 — 8.0 3500 5 20 150 Same as 2N404.
 24 20-100( 2) 6.0 18(0 5 12 150 General purpose medium speed switch.
2N413
24 30-1201 2) 7.0 150) 5 /2 150 Same as 2N413.
2N414
24 32-199(e) 4.0 35(0 15 45 200 General purpose.
2N461
24 100-200 4.5 16 7 16 200
2N508 High gain, low noise preamplifiers.
2N508A 24 100-200 4.5 25 7 25 200

24 25-42 2.5 30 10 30 225

2N524
Military/industrial.-Audio amplifier and medium speed switch. Spec-
2N525 24 34-65 3.0 30 10 30 225
ified lice hold-up, high temperature lc°, and low temperature lice.
3.5 30 10 30 225 Guaranteed reliability index. MIL-T-19500/60B.
2N526( 10 ) 24 53-90

2N527 24 72-121 4.0 30 10 30 225

23 34-90 1.3 30(r) 16 45 240 See 2N1924 series. Not recommended for new designs.
2N1057
2N1097 24 34-90 3.0 16 16 /6 200
Audio driver and audio output.
2N1098 24 25-90 3.0 16 16 16 200

34-90 1.3 16 16 /6 175 See 2N1097. 2N1098, or 2N1413 series. Not recommended for new
2N1144 23
designs.
23 25-90 1.3 16 16 16 175
2N1145
70-140 4.0 25 12 30 200 General purpose industrial and consumer preamplifier.
2N1175 24
General purpose industrial and consumer, high gain, low noise pre-
2N1175A 24 70-140 4.0 25 12 30 200 amplifiers. Guaranteed noise figure.

2N1303( 10 ) 24 20 Min.( 2) 7.0 25(e) 6 25 150

6 25 150 Medium speed switch. MIL-S-19500/126A.
2N1305( 10 ) 24 40-200( 2) 8.0 20(e)

2N1307(i 0) 24 60-300 (2 ) 12.0 15(0 6 25 150

2N1413 24 25-42 3.2 25 12 30 200

General purpose industrial and consumer audio amplifier and medium
2N1414 24 34-65 3.6 25 12 30 200 speed switch.

2N1415 24 53-90 4.0 25 12 30 200

1.3 40( 8) 25 65 240 See 2N1924 series. Not recommended for new designs.

SNOLLVDMIDadS
2N1614 23 18-43

2N1924 24 34-65 3.0 40 10 45 225 Military/industrial audio amplifier and medium speed switch. High
53-90 3.5 40 10 45 225 voltage, specified lice hold-up, low temperature hce, and high tern-
2N1925 24
perature !co. Guaranteed reliability index.
2N1926 24 72-121 4.0 40 10 45 225

NOTES: Test conditions in Italics. (e) Vce..5V, le-1 ma, f Kc, (

8) Var =60 V.

(I) All specs. at 25eC unless noted otherwise (

5) BVceo.
(e) K.

(
2) Vce IV, ¡c-10 Ma. (e) Var. (‘
0) Also available as military types.

(
2) Vce.25V, Is Ma. 0/ Var.= 45V.

6L
continued on next page
 HIGH FREQUENCY*— PNP Prolongated Exterior Base (PEB)

61
(See Outline Drawing No. 25)

SNOLLVDIAID3dS
MAXIMUM MAXIMUM MIN . TYPICAL 0,

VcEso ) NF at f
Vcno VI. Iic, Pc 1, so Ves fr fa,.. Ge at f Ragg=50 ohm
Typ es u,$) AT
Volts Volts Volts mw go Volts hys (' mc
) mc db me db me Comments

154T1 —12 —12 —1 80 10 —10 30 140 45 455kc Mixer-oscillator, IF amplifier in

AM receivers.
155T1 —12 —12 —1 80 10 —10 30 150 35 10.7 Mixer-oscillator, IF amplifier
(455KC and 10.7 mc).
156T1 —12 —12 —1 80 10 —10 15 150 13 100 Mixer-oscillator (100 mc) IF
amplifier.
157T1 —12 —12 —1 80 10 —10 15 160 14 100 RF amplifier (100 me).
159T1 —14 —14 —0.7 80 10 —12 15 350 800 34 44 IF amplifier (35-50 mc).
160T1 —14 —14 —0.7 80 10 —12 15 345 1000 25 100 RF amplifier, Mixer-oscillator
161T1 —14 —14 —0.7 80 10 —12 15 345 1000 19 150 6 200 RF amplifier, Mixer-oscillator.
162T1 —14 —14 —0.7 80 10 —12 15 360 1400 18 200 5 200 Low noise RF amplifier.
501T1 —20 —20 —1 80 10 —20 30 345 1000 27 100 4 100 GP= 16 db at f= 200 mc.
503T1 —20 —20 —1 80 10 —20 15 545 1000 16 200 5 200
504T1 —20 —20 —I 80 10 —20 100 300 Video frequency amplifier.
505T1 —20 —20 —1 80 10 —20 30 330 800 34 36 large output impedance.
508T1 —20 —20 —1 80 10 —20 15 330 800 28 60

°Made in France for General Electric by the Societe Europeenne des Semiconducteurs (SESGO).
(I) All specs at 25°C unless noted otherwise.
(2) Storage temperature on all types is —65 to +100°C. Operating junction temperature on all types is —65 to +85 °C.
(3) RD < 100 RE for types 154T1 through 157T1. Rs ≤50 RE for all other types.
(
4) VCE = — 6 volts, le = —1 ma for 15IT1 through 157T1. For all other types VCE = —9 volts, lc = —2 ma.
 SPECIAL SILICON PRODUCTS

REFERENCE AMPLIFIERS (See Outline Drawing No. 26)

Zener
CIRCUIT CHARACTERISTICS TRANSISTOR CHARACTERISTICS Characteristics

lye Ice° BVcEo Itt

KT ',ref GMC
Min. Max. Min. Max.
Max. I
Temperature Temperature Reference I Trans-
µa Volts Ohms
Coefficient Range Voltage Conductance
Type

TEST CONDITIONS TEST CONDITIONS

Vce=3v I
e=5 ma VcB=30v Ic=1 ma I
z=.5 ma
Vea=3v @ le=.5 ma aï Re-=1 K @ le=0

RAI .02% /°C 0°C 7.0V 3000 10 Minimum 1.0 45 200

RA1A .0054_/ °C to ± 10% µmho 120 Maximum
RAM .0027 /°C +70 °C
RAIC .001•90/°C

RA2 .02% /°C —55 °C 7.0V 6000 40 Minimum 45 200

to 0.1
RA2A .005e/°C ± 5% ambo 120 Maximum
RA213 .002%/ °C +150 °C

TEST CONDITIONS TEST CONDITIONS

Vce=3v le=.1 ma Ven=4Sv Ic=1 ma I

z=5 ma
VcB=3v @ Ic=.1 TO @ Ra=1 K @ lz=5 ma

RA 3 .02%/ °C —55 °C

SNOIIVDIAIDMIS
7.0V I 2000 30 Minimum 0.1 60 65
RA3A .005%/°C to ±5 % ambo 90 Maximum
RA3li .
002%/°C +150 °C _.....
conlinued on neil page

61
 6L
SILICON CONTROLLED SWITCHES (SCS)( 4)
Grown Diffused (See Outline Drawing No. 27)

SNOILVDIAIDadS
_ MAX . GATE RATINGS GATE INPUT TO FIRE

M ax. M ax.

Z
Ice las lose Vora lore VOFC

Vec=40v, Rac=0,

Vec=40v, Roc=0,
Roc=1 OK, 150°C

Roc.] OK, 150°C

Forward Current

Forward Current
100 µsec 100 °C
100°C Ambient

Peak Recurrent
Continuous DC
g

Rt=800 ohms

RL=800 ohms

1:21,=800 ohms
> g
C
e _e
0

Vec=d-40v

VAC=-40v
in

Peak Gate

A=50 ma
-

Vec=40v,
Roc=10K
r-i
Blocking

ó
Voltage

T;

Current
o I

.AC= an
Anode

o. e8
7, j II -

> e
i

>
o o II
à ..1 a

I
et

v
Type
o

3
°

▪
3

•
a
‘

3
o
a

MW

•
o

3
o
O

•
o
go

<
ACI ,iat

3N58(') 40 100 0.5 50 150 20 20 1.5 1.5 20 1.0 0.4 to 0.65

3N59(2) 40 100 0.5 50 150 20 1.5 1.5 20 (150°C) 1.5 —0.6 to —1.2
3N60(3) 40 100 0.5 50 150 20 20 1.5 1.5 20 0.2 (25°C) 1.5 —0.6 to —1.2 1.0 0.4 to 0.65

NOTES: (i) For this characterization GA is electrically open. This corresponds to the conventional SCR configuration. 4)See Chapter 16, G-E 7th Edition Transistor
(2) For this characterization, Ge is connected to C. This corresponds to the complementary SCR configuration. Manual,
(
3) This characterization is for SCR, complementary SCR (
6), and Binistor circuit configurations. The 31A160 () Derate at 2.4 mw per °C.
meets all specifications for the 3N58 and 3N59.
/ See General Electric Silicon Controlled Rec-
tifier Manual.
 Planar (See Outline Drawing No. 28)

MAXIMUM GATE TRIGGERING

CUTOFF CONDUCTING GATE CHARACTERISTICS
HARACTERISTICS CHARACTERISTICS

. _
C
RATINGS

I
I,TA VI.TC
Ve 111 V1.1• VGA 11,TC VI.Tt•
I
B

.
o

.
4..
c b
c0 tr,
-
Vec=409
tot,
e '
1
2
2
,è- . a Vsc=40v
12c=800(1

Dissipation
.c o Ri.=800O

Maximum
7 '5
o o s_ Rcc=10K
g. 3? . .%. ,' mo.
.*
35
1
(..4.)
o Ros=ro
ai - 0
-01- '
c.- c
;:° 2 ..,c
1,
.1 -1
il ri
T
I
3 -1
.:. l
<
e0 5 I?) e a)
C"o- > '
ei
at,

«,
2 .

<Fs> QC“..) au--

go Volts ma Volts
ma Volts Volts

o
3
o
e
ma amp ma Volts µa

3
Type Volts
5 65 1.0 .4 to .65 1.5
400 65 20 200 2.0 1.5
3N81 65 200 1.0 500
1.0 .4 to .65 1.5 -.4 to -.8
100 20 200 2.0 1.5 5 100
100 200 1.0 500 400
3N82 -
5 70 150t .4 to .80 -
200 70 20* 50 1.4 4.0t
3N83 70 50 0.1 50
10 .4 to .65 - -
20* 175 1.9 2.0 5 40
40 175 0.5 100 320 40
3N84
10 .4 to .65 - -
20* 175 1.9 2.0 5 100
100 175 0.5 100 320 100
3N85 -.4 to -.8
5 65 1.0 .4 to .65 0.1
400 65 20 200 2.0 0.2
3N£16 65 200 1.0 500

NOTES: *Measured @125 °C.

tMeasured in special test circuit (See specification sheet)

continued on next page

 UNIJUNCTIONS

61
SNOUNDLIIDHJS
TYPES Rim n I% Ip IL., Vos,

Cube Bar Bar Interbase Intrinsic M in. M ax. M ax Emitter M in.

Structure Structure Structure Resistance Standoff Volley Peak Point Reverse Current Base One
Vss=3v Ratio Current Emitter Peak Pulse
11:=0 Current
Dwg. Dwg. Dwg. Voltage
No. 29 No. 30 T3=-25 °C
No. 31 Kohms Vs6=10v ma ma tio @:: Vase Volts Comments

2N2417 2N489( ,) 12 2 60
— 2N24 I7A 2N489A 4.7-6.8 .51- 62 8 12 2 60
2N 241711 2N 489 B 6 0.2 30

2N 24 I8 2N 490(i) 12 2 60
— 2N 2418 A 2N490A 6.2-9.1 .51-.62 8 12 2 60
2N2418 I
1 2N490 B 6 0.2 30
"A" versions are guaranteed i
n rec -

2N 2419 2N491( ,) 12 2 60 ommended circuit to trigger G . E.

— 2N 2419A 2N491 A 4.7-6.8 SCB 's over range T A ss —55 °C to
.56-.68 8 12 2 60 125°C
2N 2419 B 2N491 B 6 0.2
:
SO

2N 2420 2N492(0
12 2 60
— 2N 2420A 2N492A 6.2-9.1 .56- .68 8 12 2 60

2N2420I
3
2 N 492 B 6 0.2 30

2N 2421 2N493(I) 12 2 60

2N 2421 A 2N493A 4.7-6.8 .62-.75 8 12 2 60

2N 2421 B 2N493 B 6 0.2 30

"B" versions in addition to SCR

2N 2422 2N494 12 2 60 triggering guarantees lower Inc. and
IP for long timing periods with a
2N 2422 A 2N494A 6.2-9.1 .62-.75 8 12 2 60
smaller capacitor.
2N242213 2N49413
6 0.2 30
— 2N 494C 2 .02 :10

5G 514 2N 1671 25 12 30

Types
cawI
— 5G 515 2N 1671 A 4.7-9.1 .47-.62 8 25 12 30

Ind
5G516 2N 1671 B 6 0.2 30
 .47-.80 8 25 12 30 3 Low cost UJT.
— — 2N2160 4.0-12.0

.56-.75 4 5 12 30 3 Low cost UJT.

2N2646 — — 4.7-9.1

For long timing periods and trigger

4.7-9.1 .68-.82 8 2 0.2 30 6 high current SCR'S.
2N2647 — —

Frequency Duty Cycle Multivibrators-

.62,82 360-440 12 30 45-55 guaranteed performance at 25 ° C.
5E35 — — 4.7-9.1

.62-.82 380 420 1.0 30 47-53 See specification sheet for details
5E36 — — 4.7-9.1

RBB V1 I\ Ir Max. 1E0 Max.

Vita=1.5V Viiii 1.5V Van=1.5V Van=1.5V Va2E=30V
Ic=0 Ini=0

Kohms Volts mo xa ea

.2- 7 10 1 1 — Low voltage applications.

2N2840 — — 4.7-9.1 1.3-1.5

NOTES: (I) Avai able as USAF TYPES M1L-T-19500/75.

SNOLINDLEDMS
6L
 6L
FUNCTIONAL DEVICES (ACTIVE DISCRETE)

SNOILVDIIIDgdS
CHOPPERS — NPN Five-terminal Packages Containing Two Matched Pellets
MAXIMUM MINIMUM MAXIMUM

Vo (Offset Voltage) VEEO rs

1131=1 B2=1 TO
Dwg. 1E1=1E2=0
1E1E2=1 ma 181=1 ma Icoo orI
CB02
181=1E2 Ice=0.1 ma Veal or VCB2=25V
Type No. ILvolts volts ohms no
2N2356 32 (i) 300 ® —55 °C to +125°C 20 40 10
2N2356A 32 0 50 ® —55 °C to +125°C 20 40 10
2N3082 33 (
2)350 ® —55 °C to +125 °C 20 40 10
2N3083 33 (
2) 75 ® —55°C to +125 °C 20 40 10
4JD12X013 Special Dual (Four transistor) version of 2N2356

4JDI2X070 Special Dual (Four transistor) version of 2N2356A

NOTES: ( I) .BI = 1232 = Ima (2) 1BI = 182 = 0.25ma

DARLINGTONS — NPN Four-terminal Package Containing Two Pellets Connected in Darlington Configuration
(See Outline Drawing No. 5)

VCEO heE
12212
heE Icao@PVca
MINIMUM MIN . MAX . MIN . MAX . MINIMUM MAXIMUM
Ic=30 ma Ic=100 ma I(=10 ma Ic=1 ma
Types volts
na volts
2N997 ao 7000 70,000 4000 — _ 10 el
2N998 60( 1) 2000 — 1600 8000 800 10 90
2N999 60 7000 70,000 4000 — — 10 60
2N2785 40( 1) 2000 20,000 1200 — 600 50 30
..----
. CEO at 20 ma.
 DIFFERENTIAL AMPLIFIERS — NPN Six-terminal Packages Containing Two Isolated Pellets
MAXIMUM
TYPE W EB
à VIM
Min. Icao@Yen
lirc@ 100 µa hrrn/hrer hrgeil ma hrei/hrEs
Dwg. Dwg. Dwg. Dwg. I
c=1 ma 10 isa 1 MO 110 volts
No. 36 volts Min. Max. @lc.100 µa Min. Max.
No. 21 No. 34 No. 35

30 — — — 5 2 80
— — 60(0 30 — 0.9-1.0
2N2060 —
— — — 15( 31 10 80
— 60 25 — 0.8-1.0 —
2N2223 —
30 250 0.8-1.0 — 10 50 60
— — 40 20 — 0.8-1.0
2N2480 —
200 0.8-1.0 — 5 20 60
2N3515 40 35 — 0.8-1.0 50
2N2480A 2N3513 2N3514
50 200 0.85-1.0 — 3 10 60
— — 60 35 — .85-1.0
2N2652 —
200 0.9-1.0 — 3 2 60
2N3517 2N3518 60 35 — 0.9-1.0 50
2N2652A 2N3516
— — — — 15( 11 ) 25 30
— — 30 30 — 0.6-1.0
12A8 —
600 0.9-1.0 3 5 5 30
2N3520 30 800 1 — — 150
2N2453 — 2N3519
— 0.8-1.0 10 10 — —
— 25 70 — 0.8-1.0 80
2N2910 — —
— — — — 10 45
— — 45 100 — — 150
2N2913 —
— — — — 10 45
— 45 225 — — 300
2N2914 — —
, 10 45
0.9-1.0 150 — — 5 5
— — — 45 100 —
2N2915
— — 5 5 10 45
— 45 225 — 0.9-1.0 300
2N2916 — —
— — 10 10 10 45
— — 45 100 — 0.8-1.0 150
2N2917 —
— — 10 10 10 45
— 45 225 — 0.8-1.0 300
2N2918 — —

SNOIIVDMIDadS
— — 5 5 2 45
— 60 100 — 0.9-1.0 150
2N29I9 — —
— — 5 5 2 45
— 60 225 — 0.9-1.0 300
2N2920 — —
600( 2) 0.8-1.0 5 10 10 45
2N3524 45 155( 11 500 0.8-1.0( 11 200
2N3521 2N3522 , 2N3523

See outline drawing No. 36 Network package (Matched 2N914 pellets ® Ic w 1ma. & 10 ma. hre ± 20%. Vac ± 5Inv.)
4.11112X084A

NOTES: () At Ic= 10 ma (
2) At lc = 10 ma. (
3) At 0.1 ma.

6L
 6L
SILICON DIODES

SNIOLLVDIII3adS
SIGNAL DIODES— Planar Epitaxial

MAXIMUM MAXIMUM

Reverse Recovery Time trr

Reverse Current 04' Indicated Voltage
lit

Voltage V 0 Indicated
reUenage or

v Total Capacitance @

E Dissipation @, 25 °C.
Indicated Voltage

g Noted Condition
Reverse Current

3 Forward Current
D Steady State DC
Forward

3
iA
Voltage

s
Vr(o

3 Power
o Min.
Indicated
Dwg. Fwd, Current 25°C 100 C 125 C 150°C

a
<
E
Type No. Volts µes
Fie ALO Pa Comments

0.2,-10V 10.0,- in\

1N251 37 1.0, 5 ma 30 — 150(6) 150
`'OV

1N252 37 1.0, 10 ma 0.1-5V

— 10.0,-5V — 30 — 150( 6) 150 -
2 ::2V
1N625 37 1.0, 4 ma 1,-20V 30.0,-20V — — 30 — 1000( 1) 200 20
1N626 37 1.0, 4 ma 1,-35V 30.0,-35V — — 50 — 1000( 1) 200 20
1N659 37 1.0, 6 ma 5,-50V 25.0,-50V — — 50 2.7,-10V 300( 6) 250 100
1N659A 37 1.0, 10 ma 0.025,-50V — — 5.0,-50V 75 2.7,-10V 300() 250 100
1N789 37 1.0, 10 ma 1,-20V 30,-20V — — 30 — 500( 2) 500 180
1N790 37 1.0, 10 ma 5,-20V 30,-20V — — 30 — 250( 2) 500 180
1N791 37 1.0, 50 ma 5,-20V 30,-20V — — 30 — 500( 2) 500 250
1N793 37 1.0, 10 ma 1.-50V 30,-50V — — 60 — 500( 2) 500 180
1N794 :37 1.0, 10 ma 5,-50V 30,-50V — — 60 — 250( 2) 500 180
1N795 37 1.0, 50 ma 5,-50 V 30,-50V — — 60 — 500( 2) 500 250
1N811 37 1.0, 1 ma 1.0,-10V
20.0.45 v — 10.0,-10V — 30 — 250( 6) 150 40

1N812 37 0.1-10V
2 ::20V — 10.0,-10V — 40 — 250( 2) 150 60
" 1 2 ma

1N813 37 1.0, 5 ma 0.5

— 10.0,-5V — 20 — 250(e) 150 75
2 :: 'V
lN814 37 1.0, 2 ma 0.1-20V
2 ::3v — 10.0,-20V — 50 — 250(0 150 60
 — 20 — 250( 3) 150 120
37 1.5, 100 ma :
)::':gv — 10.0,-5V
1N815 2(

— 60 — 300( 3) 200
37 1.0, 50 ma 0.1,-50V 25.0,-50V —
1N891 4.0( 8) 250 110
1N903 10.0,-40V — -- 40 1.0,-6V
37 1.0, 10 ma 0.1,-40V —

— 40 1.0,-6V 4.0( 10 250 75

1N903A 37 1.0. 20 ma 0.1,-40V 10.0,-40V —
— 30 1.0,-6V 4.0( 8) 250 110
37 1.0, 10 ma 0.1,-30V 10.0,-30V —
1N904 250 110
10.0.-30V -- — 30 1.0,-6V 4.0( 8)
1N904A 37 1.0, 20 ma 0.1,-30V
— 20 1.0,-6V 4.0M 250 110
1N905 37 1.1, 10 ma 0.1.-20V 10.0.-20V —
— 20 1.0,-6V 4.0( 11 ) 250 110
1N905A 37 • 1.0, 20 ma 0.1.-20V 10.0,-20V —
— 20 2.5,-6V 4.0( 8) 250 110
1N906 37 1.0, 10 ma 0.1,-20V 10.0,-20V —
— 20 2.5,-6V 4.0( 8) 250 110
1N906A 37 1.0. 20 ma 0.1,-20V 10.0,-20V —
— 30 2.5,-6V 4.0( 8) 250 110
1N907 37 1.0, 10 ma 0.1,-30V 10.0,-30V —
— 30 2.5,-6V 4.0( 8) 250 110
37 1.0. 20 ma 0.1,-30V 10.0,-30V —
1N907A 250 110
— — 40 2.5,-6V 4.0( 8)
1N908 37 1.0, 10 ma 0.1.-40V 10.0,-40V
— 40 2.5,-6V 4.0( 3) 250 110
1N908A 37 1.0. 20 ma 0.1.-40V 10.0,-40V —
250
1N914 37 4.0 (3) 500 110
1N4148 38 1.0. 10 ma 0.
025 ,
-20 V — — 50.0,-20V 100 4.0,-OV 500
1N4531 . 39
50.0,-20V 100 4.0,-OV 4.0( 9) 250 110
37 1.0. 20 ma 0.025,-20V 5.0,-20V —
1N914A 250 110
— 50.0.-20V 100 4.0.-OV 4.0( 3)
1N914B 37 1.0, 100 ma 0.025,-20V —
— — 75 4.0,-OV 10.0( 11 ) 250
1N915 37 1.0. 50 ma 0.025,-10V —
1N916 37 100 2.0,-OV 4.0( 3) r o
) 110
—
1.0, 10 ma 0.025.-20V — — 50.0,-20V
1N4149 38
50.0,-20V 100 2.0,-OV 4.0( 9) 250 110
1N916A 37 1.0, 20 ma 0.025,-20V — —
50.0,-20V 100 2.0,-OV 4.0( 3) 250 110
1N916B 37 1.0, 20 ma 0.025.-20V — —
— — 50 2.5.-0V 3.0( 11 ) 250 —
1N917 37 1.0, 10 ma 0.05,-10V 25.0,-20V
— — 40 4.0,-OV 150( 3) 500 180
1N925 37 1.0, 5 ma 1.0.-10V 20.0,-10V
— 40 4.0,-OV 150(s) 500 180
37 1.0. 5 ma 0.1,-10V 10.0,-10V —
1N926
0.1,-10V 10.0,-10V — — 65 4.0,-OV 150( 0 500 180
1N927 37 1.0 '10 ma 5.0,-50V 25.0,-50V
— — 40 — 150(e) 150 —
1N997 37 1.0, 10 ma 0.025,-12V —
— — 75. Spa 1.0,-OV 2.00) 250 —
37 1.0, 20 ma 0.1,-50V —
gg _
1N3062
1N3063 37 — — 100,-50V 75, Spa 2.0,-OV 2.0( 3)
0.85,10ina (cc) 0.1,-50V
1N4305 41
250
1N3064 37 4.0 (111 500
1N4454 38 1.0,10ma (cc) 0.1,-5 0 V — — 100,-50V 75, Spa 2.0,-OV 500 —
1N4532 39
— 100,-50V 75, Spa 1.5,-OV 2.0( 19 250 —
1N3065 37 1.0.20ma (cc) 0.1,-50V —
— 100,-50V 75, Spa 1.0,-OV 2.0( 3) 250 —
1N3066 37 1.0, 10 ma 0.1,-50V —
100,-20V 30, Sida 4.0,-OV 2.0( 3) 250 — m111
37 1.0, 5 ma 0.1.-20V — —
1N3067 continued on next page
,
MAXIMUM

Reverse Current @ Indicated Voltage

e Reverse Recovery Time t-r

I
R

Voltage V e Indicated
Min. SAT. Voltage or

Total Capacitance @

25 C.
Indicated Voltage
Min. Breakdown

Reverse Current

Noted Condition

3 Forward Current
Steady State DC
Forward

E Dissipation
Voltage
Vs,e

3 Power
Indicated
Dwg. Fwd, Current 25 °C 100°C 125 °C 150°C
Type No. Volts Ain

<
AO pa pa

v
Comments

0
1N3060 37 1.0, 5 ma 0.1,-20V — — 100,-20V 30, Spa 6.0,-OV 50.0( 10 ) 250 —
1N3124 37 1.0, 20 ma 0.1,-40V 10.0,-40V — — 40 2.0,-6V 4.0( 9) 125 50
1N3206 37 1.0, 10 ma 0.025,-20V
5.0.-80v — — 50,-20V 100 4.0,-OV 4.0( 11 ) 150
1N3600 37 —

1N4150 38 1.0,200ma(cc) 0.1,-50V — — 100 ,- 50V 50 2.5,-OV 6.0(12) 500 —

1N3604 37
1N4151 38 1.0, 50 ma 0.05,-50V — — 50,-50V 75, 5eat 2.0,-OV 2.0( 9) ggg 115
Very high speed, high con-
ductance, computer diode.
Subminiature package.
1N3605 37
1N4152 38 See Table 1 0.05,-30V — — 250 Controlled conductance ,
50,-30V 40, Sim 2.0,-OV 2.0( 0 500 115 ve ry hi gh speed diode. Sub-
1N4533 39
500 Submima Lure package.
1N3606 37
1N4153 38 See Table 1 0.05,-50V , 250
— — 50,-50V 75, Spa 0.0,-OV 2.04,
1N4534 39 500 115
500

1N3607 40 1.0, 50 ma 0.05,-50V — — 50,-50V Very high speed, high con -

75, 5aa 2.0,-OV 2.0( 9) 150 115 ductance diode in micro-
miniature package.
1N3608 40 See Table 1 0.05,-30V — — 50,-30V 40, 5sta 2.0,-OV 2.0( 9) 150 115

1N3609 40 See Table 1 0.05,-50V — — 50,-50V Controlled conductance, very

75, 5µa 2.0,-OV 2.0( 9) 150 115 very high speed diode in mi-
crominiature package.
1N3873 37
1N3873/HR 37 0.85,20ma (cc) 0.1,-50V — — 40,-50V 50 Very high speed, electrically
4.0,-OV 4.0( 11 ) 250 200 identical to the Polaris G-321
high reliability diode.
1N4009 37
1N4154 38 1.0, 30 ma 0.1,-25V — 250
— 100,-25V 35, 5µa 4.0,-OV 2.0 4)
1N4536 39 500 115 Economy type.
500
_
 1N4043
1N4306
40
43
1.0, 30 ma I0.1,-25V - I - 100,-25V 135, Sua
These types appear under section "Matched Pairs and Quads.
4.0,-OV 2.0 4) 150 115

1N4307 43

Kovar Tab

35 I 210
KSD101 44 1 1 @ 30 ma! 0.1,-25V 1 50-25\

Stabistors (1, 2, or 3 diode pellets in aseries)

1N4156 42 See Table 2 0.05,-20V - - 50,-20V 30, 5vat 25.0,-OV - 400 - DHD Stabistor with con-
trolled conductance and
1N4157 41 See Table 3 0.05.-20V - - 50.-20V 30, 5pa 20.0,-OV - 400 - stored charge of 50 pc
50,-20V 30, Spa 30.0,-OV 400 - Min.@I r=1 ma.
1N4453 38 See Table 4 0.05,-20V - - -

TABLE 3 TABLE 4
NOTES:
TABLE 1 TABLE 2
() Recovery to 400K, switching from 30 ma forward to -35 volts. IBM Y circuit.
I
F VF 1
F VF VF VF (
2) Recovery to 200K, switching from 5 ma forward to -40 volts. JAN 256 circut.

Min. Max. Min. Max. Min. Max. Min. Max. (

3) Recovery to 80K, switching from 5 ma forward to -40 volts. JAN 256 circuit.

MO MY MY MO MY MY MY MY MY MY (
4) Recovery to 400K, switching from 30 ma forward to -35 volts. JAN 256 circuit.

0.1 0.490 0.550 0.01 0.74 1.09 1.19 1.54 .430 .550 (
8) Recovery to 20K, switching from 5 ma forward to -10 volts. JAN 256 circuit.

(
0) Recovery to 40K, switching from 5 ma forward to -10 volts. JAN 256 circuit.
0.25 0.530 0.590 0.1 0.97 1.22 1.52 1.77 .510 .630
O) Recovery to 40K, switching from 10 ma forward to -10 volts. JAN 256 circuit.
1.0 0.590 0.670 1.0 1.21 1.41 1.85 2.05 .600 .710 (8) Recovery to 1.0 ma reverse, switching from 10 ma forward to -5.0 volts F
IL= 100 ohms.
2.0 0.620 0.700 10.0 1.38 1.58 2.12 2.32 .690 .800 (8) Recovery to 1.0 ma reverse, switching from 10 ma forward to -6.0 volts. RL= 100 ohms.

10.0 0.700 0.810 100.0 1.54 1.84 2.36 2.66 .800 .920 (10 ) Recovery to 1.0 ma reverse, switching from 30 ma forward to 30 ma reverse. RL= 150 ohms.
(11) 1,1p =10 ma, recovery to 1 ma.
20.0 0.740 0.880 - - - - - - -
(12) IF= 10 ma, In =1 ma, recovery to 0.1 ma.

SNOILVDMIDadS
Diffused Junction Diodes* (See Outline Drawing No. 37)

MAXIMUM
(2S .C. unless otherwise specified)
Forward Current Reverse Current
Continuous Peak Transient Peak ma Surge Current At P.I.V. Forward Voltage Total Capacitance
Inverse Voltage pnverse Voltage 25°C 100°C (1 Second ) 25 °C 100 °C V V=-l2 volts
Types Volts I Volts Amps uo ea Volts pf
62J2 through 66J2 200-600 I 270-720 400 150 2.5 1-0.5 65-50 1.25 at 400 ma 9

5L
4
* Made in France for General Electric by the Societe Europeenne Des Semiconducteurs (SESCO). continued on next page
 Subminiature Point Contact Diodes* (See Outline Drawing 37)

61
SNOLINDIAIDadS
MAXIMUM
Reverse Current TOTAL
MAXIMUM lit CAPACITANCE
_

Peak Inverse Average Forward Surge

Voltage Current") Currentm 25°C 150°C Va= —2 volts Vg = —40 volts
Types Volts ma ma go sza Pf Pf

121'2 through 19P2 200-10 40 120 0.5 100 0.1 0.3

23J2 through 28J2 200-10 60 120 0.2(s) 100 0.1 0.3

NOTES: *Made in France for General Electric by the Societe Europeenne Des Semiconducteurs (SESCO).
(I) For types 12P2 and 19P2 this parameter is 60 ma
(
2) For types 12P2 and 19P2 this parameter is 180 ma

(
3) For 90% of the production, the inverse current is less than 0.1 eta.

Matched Pairs and Quads (See Outline Drawing No. 43)

MAXIMUM MAX.

Reverse Current
IF Forward Voltage VF
In Typo ma Min. Max.

E,. MP-1
.100 .440 .550
IV—Max. Forward 1 .560 .670
and
Voltage 0.2 MQ-1 10 .670 .810
Forward difference between diodes
Voltage 100 .750 1.000
in pairs or quads 04
(Te=-55°C to -,125°C) ta
82
It=0.1 Ir=10
25"C 150`C to 10 mo to 50 ma
Type Volts an ua mv mv MO Comments

MP-1 (1N4306) See above* .05 (4) 50V 50 @ 50V 75 10 20 (MP-1 was formerly 1N1306)
.10 30V 100 (4) 30V 40 10 50 Matched pairs in molded package. (Silicon Signal Diodes)
MP-2 1.0 ® 10 ma

MQ-1 (1N4307) See above* .05 (41 50V 50 @ 50V 75 10 20 (MQ-1 was formerly 1N4307)
.10 (gt 30V 100 ® 30V 40 10 so Matched quads in molded package. (Silicon Signal Diodes)
MQ-2 1.0 (4) 10 ma
 Snap-off Diodes (See Outline Drawing No. 37)

MINIMUM MAXIMUM MINIMUM TYP. MAX. TYP. MAX.

Snap-off Snap-off
Peak Breakdown time time
Power Surge Voltage Capacitance Stored T8=2 nsec. Ts=2 nsec.
Dissipation Current I
R=54amps VR= OV ,f= Imc Charge I
r=20 mo Ir=100mo
25°C 1us Bi c. Qf tp tsp
Type mw amperes Volts Pf pc/ma nsec. PIS«.

SSA-550( 2)/55e) 250 2 12 1.5 20 0.3 0.5

SSA-551( 2)/555( 3) 250 2 8 4.0 20 0.3 0.5

SSA-552( 2)/556( 3) 250 2 12 1.5 1.0 0.2(') 0.4

SSA-553( 2)/557( 3) 250 2 8 4.0 1.0 0.2( 1) 0.4

NOTES: 0) Limited by resolution time of test equipment. (

2)DO-7 package. (
3)Micro Silicon Diode-see Specifications 75. 28 for outline dimensions.

Mic ophoto Diodes" )- NPN (See Outline Drawing No. 45)

MAX. TYPICAL
MAL (2) DARK CURRENT DARK CURRENT TYPICAL SENSITIVITY (3 •4) TYPICAL
PHOTOCURRENT
Bias Pc at 24 vdc at 24 vde at 250 ft. -e. at 1000 ft. --e. DECAY TIMER
Type Volts mw go go µo/ft. --e. go/ft. -e. ,sec.
31F2 40 50 0.1 0.02 0.2 0.8 I

6L sNouvamaaas
32F2 40 50 0.1 0.02 0.5 1.5 I
33F2 40 50 0.1 0.02 0.9 2.2 1
34F2 40 50 0.1 0.02 1.6 5.0 1

NOTES: *Made in France for General Electric by the Societe Europeenne Des Semiconducteurs (SESCO).
(I) All specs at 25°C unless noted otherwise.
(2) Storage temperature on all types is -65 to +125°C. Operating temperature on all types is -6 5 to + 100° C.
(3) Light source-Tungsten Filament Lamp Operated at a Color Temperature of 2870°K.

(4) Maximum Sensitivity wave length 0.9 to 1.0 microns.

 61
GERMANIUM DIODES

SNOILVDIIIDadS
SIGNAL DIODES — Point-Contactil"n (See Outline Drawing No. 37)

Maximum
Max. Forward Current — ma
- - Min. For- Maximum Reverse Current
Cont. -
Type Reverse Recurrent 1sec. ward Current
No. PRV Voltage Average Peak Surge @ ± IV ma Volts 40 Volts ma Comments

1N34 75 60 50 150 500 5.0 -10 50 - 50 800

General purpose
1N34A 75 60 50 150 500 5.0 -10 30 —50 500

1N35( 2) 75 60 50 150 500 7.5 -10 10 Matched pair of 1N34A

1N38 120 100 50 150 500 3.0 -3 6 -100 500

1N38A 120 100 50 150 500 4.0 -3 6 -100 500 High reverse voltage

1N38B 100 50 150 500 4.0 -3 6 -100 500

1N48 85 70 ao 150 400 4.0 -50 833

1N51 50 40 20 100 300 2.5 -50 1660

1N52 85 70 40 150 400 4.0 -50 150

100 General purpose detector
1N52A 50 40 150 400 5.0 -50
1N54 50 35 ao 150 500 5.0 -10 10
1N54A 75 50 40 150 500 5.0 -10 7 -50 60

1N58 120 100 40 150 500 5.0 -100 600

1N58A 120 100 40 150 500 5.0 -100 600 High reverse voltage

1N63 125 100 ao 150 400 4.0 -50 50

1N65 . 85 70 40 150 400 2.5 -50 200
1N67 100 ao 35 100 500 4.0 -5 5 -50 50 General purpose

1N67A 100 80 30 100 300 4.0 -5 s —50 50

1N68A 130 100 30 100 500 3.0 -100 625 High reverse voltage

1N69 75 60 ao 125 400 5.0 -10 50 -50 850

1N69A 75 60 40 125 400 5.0 -10 30 -50 500

1N70 125 100 30 90 350 3.0 -10 25 -50 300 General purpose

1N70A 125 100 30 90 350 3.0 -10 25 -50 300

1N75 125 100 40 150 400 2.5 -50 50

 1N8I 50 40 40 90 350 3.0 —10 10
1N81A 50 40 30 90 350 3.0 —10 10 General purpose
IN90 75 60 30 150 500 5.0 —50 500
1N116 75 60 30 250 5.0 —50 100 Low leakage
1N126 75 60 30 90 350 5.0 —50 850
General purpose
1N126A 75 60 30 90 350 5.0 —10 50 —50 300
1N127 125 100 30 90 300 3.0 —50 300
1N127A 125 100 30 90 300 3.0 —10 25 —50 200 General purpose
1N128 50 40 30 90 300 3.0 —10 10
1N19I 90 70 30 90 300 5.0 —10 25 —50 125
Computer diode
1N192 80 55 30 90 300 5.0 —10 20 —WO 100()
1N198 100 80 30 90 300 4.0 —10 10 —50 250( 6) High temp. "JAN" diode
1N198A 100 80 30 90 300 4.0 —10 10 —se) 250(0 High temp. low leakage
1N636 60 45 30 2.5 —10 10 Low leakage
1.5 mA @ IV
IP541(3) 45 30 10 100 200 .1 mA @ .3V —1 .
5 2.8 —10 18 A.M. detector

IP542( 3) The 1P542 is a matched pair of 1P541 F.M. ratio detector

NOTES: In Made in Canada by Canadian General Electric.

(2) Each diode current at +1V matched to within 10 %•
(3 ) The 1P541 and IP542 are very similar to the 1N541 and 1N542 electrically but are in a smaller case.
(4) All measurements at 25 °C unless otherwise specified.
(5) Measured at 55 °C.
(5) Measured at 65 °C.

Bonded-Junction Diodes (See Outline Drawing No. 37)

Maximum
Max. Forward Current — ma
Maximum Reverse Current

SNOLINDIAIDMS
Cont. Min. For-
Type Reverse Recurrent 1 sec. word Current
No. PRV Voltage Average Peak Surge @ ± IV ma Volts go Volts go Comments

1N56A 50 10 60 200 1.000 15 —30 300 General purpose

1N96A 75 60 70 250 400 40 —50 500
1N97A 100 80 30 250 20 —5 8 —50 100
1N98A 100 80 70 250 400 40 —5 8 —50 100 High conductance
IN99A 100 80 30 300 20 —5 5 —50 50
1N100A 100 80 70 250 400 40 —5 5 —50 50

6L
1N117A 75 60 40 300 20 —50 100 General purpose
continued on next page
Cif

61
Maximum
Ma x. Forward Current — ma
Maximum Reverse Current

SNOIIVDMIDatIS
Cont. Min. For-
Type Reverse Recurrent 1see. ward Current
No. PR V Voltage Average Peak Surge @ ± IV ma Volts go Volts AO Comments

IN118A 77 60 70 250 400 40 —50 100

1N273 35 30 80 450 100 —20 20

1N279 39 30 80 450 100 —20 200 High conductance

1N281 75 60 75 400 100 —10 30 —50 500

1N292 75 60 70 150 100 —50 200

1N298A 85 70 30 300 3.5 —5 10 —40( 2) 250(2) Computer diode

1N309 40 30 100 100 —20 100 High conductance
1N313 100 40 500 20 —20 10 —100 50 Low leakage diode
1N449 40 30 60 50 —10 10 —30 30 High conductance
1N497 30 20 60 100 —20 20 Low leakage
1N774 70 60 50 450 100 —10 15 —50 150
High conductance
IN776 30 20 45 400 50 —10 200 —30 500
1N777 70 60 50 450 100 —10 25( 3) —50(s) 1250> Switching diode

NOTES: (,)Measured at 75°C unless otherwise specified. (

2)Measured at 50 °C. M Measured at 55°C.

Video Detector Diodes** (See Outline Drawing No. 37)

Max.
Average
Maximum Rectified
Reverse Current Forward
Type Current
No. PRV Volts go ,ma )

1N60 30 —10 67 50
1N60A 40 —10 60 50
1N60C 50 —10 67 50 ** Made in Canada by
Canadian General Electric.
1N64 25 —10 100 50
1N87A 30 —1.5 30 50
IN295A in —10 200 35
1\616 SO —I
0 100 50
 TUNNEL DIODES - General Purpose

MAXIMUM Typical
Max. Resistive
Peak Point Valley Point Capaci- Peak Series Negative Cutoff
Current Current tance Voltage Resist. Conductance Frequency
Dwg. II I, C VI. R,.. G fro
Type No. ma ma pf m y Oh ms m hos • 10 1 KMC Comments

1N2939 46 1.0 ± 10% 0.14 15 65 Typ. 1.0 6.6 Typ. 2.2

1N2939A 46 1.0 ± 2.5% 0.14 10 60 ± 10 1.0 6.6 Typ. 2.6
1N2940 46 1.0 ± 10% 0.22 10 65 Typ. 4.0 6.6 Typ. 2.2
1N2940A 46 1.0 + 2.5% 0.22 7 65 ± 10 4.0 6.6 Typ. 2.6
IN2941 46 4.7 ± 10% 1.04 50 65 Typ. 2.0 30 Typ. 2.6 General purpose switching,
oscillator, amplifier and con-
IN2941A 46 4.7 ± 2.5% 1.04 30 65 ± 10 2.0 30 Typ. 3.9 verter circuits. Nominal
1N2969 46 2.2 ± 10% 0.48 25 65 Typ. series inductance, Ls, is 4nh.
3.0 16 Typ. 2.5 TO-18 package.
IN2969A 46 2.2 ± 2.5% 0.48 15 65 ± 10 3.0 16 Typ. 3.3
1N3149 46 10.0 ± 10% 2.2 90 65 Typ. 1.5 60 Typ. 2.6
1N3149A 46 10.0 + 2.5% 2.2 50 65 ± 10 1.5 60 Typ. 3.1
IN3150 46 22.0 ± 10% 4.8 150 65 Typ. 1.0 100 Typ. 2.2
IN3712 (TD-1) 47 1.0 ± 10% 0.18 10 65 Typ. 4.0 8 Typ. 2.3
1N3713 (TD-IA) 47 1.0 ± 2.5% 0.14 5 65 ± 7 4.0 8.5 ± 1 3.2
IN3714 (TD-2) 47 2.2 ± 10% 0.48 25 65 Typ. 3.0 18 Typ. 2.2
IN3715 (TD-2A) 47 2.2 ± 2.5% 0.31 10 65 ± 7 3.0 19 ± 3 3.0 General purpose switching,
IN3716 (TD-3) 47 4.7 ± 10% 1.04 50 65 Typ. 2.0 40 Typ. oscillator, amplifier and con-
1.8
IN3717 (TD-3A) verter circuits. Miniature
47 4.7 ± 2.5% 0.60 25 65 ± 7 2.0 41 + 5 3.4 axial package with series in-
IN3718 (TD-4) 47 10.0 ± 10% 2.20 90 65 Typ. ductance, Ls. of 0.5 nh. MIL
1.5 80 Typ. 1.6
qualified units available for
1N3719 (TD-4A) 47 10.0 + 2.5% 1.40 50 65 + 7 1.5 85 + 10 2.8 - A" versions.

IN3720 (TD-5) 47 22.0 ± 10% 4.80 150 65 Typ. 1.0 180 Typ. 1.6
IN3721 (TD-5A) 47 22.0 ± 2.5% 3.10 100 65 ± 7 1.0 190 ± 30 2.6
TD-9 47 0.5 ± 10% 0.10 5 60 Typ. 6.0 4.0 Typ. 1.3
 Ultra-High Speed Switching (See Outline Drawing No. 48)

MAXIMUM VOLTAGE
Typical
Valley Series Typical
Peak Point Point Coped- Peak Forward Forward Resis- Rise
Current Current tance Point le=0.25 II IF=Ir tance Time
I, I, C VP VFS Ver Rs tr
Type ma TO Pf MY IVIV TV ohms psec. Comments

TD-251 2.2 ± 10% o ;I 3.0 70 Typ. 420 Min. 500-650 5.0 430

TD-251A 2.2 ± 10% 0.31 1.0 110 Max. 420 Min. 500-650 7.0 160

TD-252 4.7 ± 10% 0.60 4.0 80 Typ. 435 Min. 500-650 3.5 320

TD-252A 4.7 ± 10% 0.60 1.0 120 Max. 435 Min. 500-650 4.0 74

TD-253 10.0 ± 10% 1.40 9.0 75 Typ. 450 Min. 500-650 1.7 350
Extremely high speed memory
TD-253A 10.0 ± 10% 1.40 5.0 80 Typ. 450 Min. 520-650 2.0 190 circuits, logic circuits, pulse gen-
1.40 2.0 120 Max. 450 Min. 550-650 2.5 68 erators and threshold detectors.
TD-253B 10.0 ± 10%
Housed in a subminiature epoxy
TD-254 22.0 ± 10% 3.80 18.0 90 Typ. 520 Typ. 600 Typ. 1.8 185 package with series conductance.
oh. Ls, of 1.5
TD-254A 22.0 ± 10% 3.80 4.0 120 Max. 460 Min. 550-650 2.0 64
TD-255 50.0 ± 10% 8.50 25.0 110 Typ. 530 Typ. 625 Typ. 1.4 100

TD-255A 50.0 ± 10% 8.50 5.0 130 Typ. 480 Min. 640 Typ. 1.5 35

TD-256 100 ± 10% 17.50 35.0 150 Typ. 530 Typ. 650 Typ. 1.1 57
TD-256A 100 ± 10% 17.50 6.0 180 Typ. 500 Min. 660 Typ. 1.2 22

Microwave (See Outline Drawing No. 49)

Typical Maximum Maximum Minimum
Peak Point Negative Junction Series Resistive Cutoff
Current Resistance Capacitance Resistance Frequency
II -R Ci Rs fro
Type ma ohms pf ohms GC Comments

TD-401 .2.0 65-75 2.60 5 5

TD-402 2.0 65-75 1.30 5 10

TD 403 2.0 65-75 0.89 5 15 High performance microwave pill pack-
TD-404 2.0 65-75 0.67 5 20 age with series inductance. Ls, of 0.1 oh
and package capacitance, di., of 0.1
TD-405 2.0 65-75 0.54 6 25 Pf. Units can be stud mounted on
TD-406 2.0 65-75 0.45 6 30 request.

TD-407 2.0 65-75 0.40 6 35

TD-408 2.0 65-75 0.35 6 40
 Back Diodes

MAXIMUM MINIMUM Forward Typical

- Reverse Voltage Current Forward
Peak Point Total Irt Voltage
Current Capacitance Vi Vas I Vel=90 V1,2
Dwg. ii' C (In=li. max) (I=I ma) ±10 my)
- 14'2=3 lei/
Type No. ma p8 my my ma my Comments

BD-1 50 1.0 20 440 440 10.0 120

BD-2 50 0.5 10 420 465 5.0 130
BD-402 49 0.5 3 420 465 5.0 130
BD-3 50 0.2 10 400 465 2.0 170
BD-1 through -7 are general pur-
BD-403 49 0.2 1 400 465 2.0 170 pose types for use in mixer,
BD-4 50 0.1 10 380 465 1.0 170 detectors and switching circuits
housed in miniature axial package.
BD-404 49 0.1 1 380 465 1.0 170 BD-400 series are microwave ver-
sions featuring low capacitance
BD-5 50 0.05 10 350 465 0.5 160 and a pill package with a series
BD-405 49 0.05 1 350 465 0.5 160 inductance Ls, of 0.1 nh.

BD-6 50 0.02 10 330 465 0.2 160

BD-406 49 0.02 2 330 465 0.2 160
BD-7 50 0.01 10 300 465 0.1 160
2.0
1N4090 48 0.2 1.5 430 500 (Vini.100 170 Low noise mixer.
± 20 111V)

GALLIUM ARSENIDE TUNNEL DIODES (See Outline Drawing No. 50)

SNOILVDIAIDacIS
MAXIMUM
Forward Max.
Peak Point Valley Point Peak Voltage Negative Series
Current Current Capacitance Voltage (lr=lp) Conductance Resist.
I.• Iv C V. VFP —G Rs
Type ma ma Pt MV MY mhos .. 10' ohms Comments

Oscillator circuits where wide volt-

age swing is required. Series in-
1N3118 10 ± 10% I10 20 Irm t>1, /WI IIIIII 10 5 ductance, Ls, is 4 oh. TO-18
package.

ed
19 SPECIFICATIONS

NOTES:

574
 TRANSISTOR OUTLINE DRAWINGS

DIMENSIONS WITHIN
JEDEC OUTLINE TO-5

NOTE I: Lead diameter is controlled in the

21 .150 MIN

Jr e
zone between 070 and 750 from the seat- NOTE 1: Lead diameter is controlled m the
ing plane. Between 250 and end of lead a (NOTE 41
lone between 050 and 250 from the seat.
max of 321 !s held mg plane. Between 250 and end of lead a .260
max of 021 is held.
127 MAX. NOTE 2: Leads having maximum dlagnete
.500 SEATING 019' measured ni gagmg bIane 054 301
.263 MAX. 000 below the seahng plane of the device
ALL OIMEN. IN INCHES AND ARE O OT MIN PLANE
"
035 e0
N
REFERENCE UNLESS TOLERANCED --à— shall be within .007 ol tgue position tela-
1 .I56R
H 050 ± .005 MAX. tige to amaximum width tab.
NOTE 3: Measured from max Marneter of
100±.005 he actual device.
.128 SEATING
.-11a
3 LEADS .116 DIA. NOTE 4: This tone is controlled for auto PLANE
.090
.017 = matis handling The variation in actual tham.
elm within this zone shall not exceed 010
(NOTE II .140 3 LEADS
Tris .156 "ll
• "
h.002

(NOTE I)
.407 MAX.

_L
.034
.028
3 LEADS .045
.500 MIN. Mi.0I7 ALL OMEN. IN INCHES AND ARE .029

SNOILVDMIDAdS
REFERENCE UNLESS TOLERANCE° (NOTE 3)
, 45 .
.050t.005

.520 MAX.

ALL »EN. IN baCHES AND ARE REFERENCE uNLESS TOLERANCED

6L
DIMENSIONS WITHIN JEDEC
OUTLINE TO-46
.230
.209

e
o 1- le et: ALL DIMEN, IN INCHES AND ARE
REFERENCE UNLESS TOLERANCED

o
NOTE I: Lead diameter is controlled in Me .215 MAO 030 MAO
Tone between 050 and 250 from the sea, J95 MIN

:3375:
mg plane Belween .250 and end ol lead a MHOS: Lead diameter n controlled In the
DIMENSIONS WITHIN zone between 050 and 250 horn the base
max of 021 is held.
JEDEC OUTLINE TO-5 .cee max t seat. Between 250 and end 01 Mad amax.
NOTE 2: Leads having maximum diameter of .021 is held.
1.515MAX .063 MIN
1.0191 measured in gaging plane .054 .001 .322
SEATING 1485 MIN T NOTE 4: 1^,e.44 mcanl ,nr; narinare
.000 below the seating plane ol the device
shall be within 007 of true position rela. PLANE w6-32 shoe,' hell* is supplied. For hds serese
toe to amaximum vadth tab. .407MAX NC DA a IV clearance hole Is recommended
-11 -
5-Or,
.1-114
- I .3801816 N.0 11 "
NOTE 3: Measured rom max diameter of 3 LEADS NOTE 1: Lead diamete, is controlled in the MAO

I
(NOTE 41
the actual device. .017 I'M now between 0)0 and 250 from the seat-
.260 TORQUE
ing Paw Between 2)0 and end ol leaf a 4IN /LOS
(NOTE II max of 021 is held .j 240
NOTE 2: LEMS having maximum diameter
10191measured in gaging Oane 054 • WI
000 below the seating plane of the device .035
shall be within 007 of true position rele -11\ 3 LEADS
MIN
live to amaximum width tab.
E. .017 f2Sf
NOTE 3: Measured from max. diameter al
.096 2 MICA MUMERS (NOTE 1)
the actual device SEATING 0.3 X .005 T141,
.048 \
e .036 NOTE 4: This LC.% is controlled for auto PL ANE
mall, handling The valiation in actual diales FLAT WASHER
ALL OMEN. IN INCHES AND ARE .026
PANEL TEFLON SPACER
eter within this gone shall not exceed .010 .31703 X.032 THK
REFERENCE UNLESS TOLF_RANCED (NOTE 3) 3 LEADS MAX. .182 0.0. X .090 TM(
.093 THIC
INT. LOCK WASHER -/
(NOTE 11 06 32 NUT
CONNECTED
INTERNALLY
TO HEADER .100 ±.010

.034 .078 TOOS

.045
ALL DIMEN. IN INCHES AND ARE .029
REFERENCE UNLESS TOLERANCED (NOTE 3)
5'
.460 MAX
.940M114

CONNECTED TO CASE
 .375 ALL DIMENSIONS IN
•4-40 NUT
MAX. INCHES ANO ARE
SA INT LW REFERENCE UNLESS 0

o
TOLERANCED
MAX TORQUE ,—.030 WIN
55 IN Lin

1
.610 DIMENSIONS *4-40 X 586

1
.590 WITHIN JEDEC SLOTTED PAN H
SCR FOR UP TO
OUTLINE TO-8 .125 Tme PANEL
262
MOUNTING MAR .330
.
•17
• 955
PLATE MAL
•4-400 5/16
SCREW .330
065
PANEL: .300

o
•31 DRILL
1.120 DIM

.000 (NOTE I)
MIN
LOCKWASHER.4.40 .360
.335 MAS
00..270 MAX NUT
.325 MIN.
3 LEADS

1.189 MAX
MAX 3LEADS
.99r MIN .017. .002
.6882.002 (NOTE II A%
Pen Is Lead dmmete is controlled In the
.2002.010 zone between .050 and .250 now the cap
.128 DIA.
or base seat Between .250 and end of Had
12 HOLES)
amax of.021 rs

inn t Clearance Is Wooded to bend all

leads for overhead country «hoot Inter.
75 ur
fenng path heat sank mounlIng on chews

GROUNDED
TO CASE 3LEADS
INSULATED MOUNTING
•2-56 X 3/8
.128 .035 MAX .017 +1 % 2

MOUNTING SCREW
12 HOLES) INSULATING TUBING
(NOTE 0 '
PLATE SHOULDER
WASHER Pili la Lead ender Is controlled nthe zone between 050 and 250 Irom the base
ALL DIMENSIONS IN INCHES .029 MIN
INSULATOR seat Between .250 and end al Had amax. of .021 rs held.
PANEL-. AND ARE REFERENCE
.42 DRILL iMh Sa All noloey metal hardwa ees slernless steel. All hardware drown wIll be L.031±.003
UNLESS TOL ERANCE0
I09351 snoped enth dence .ncludIng elecirr:al rsolaton hardware shown below
LOCXWASHER o
• 2-56NUT

6L smonvaidiaaas
INSULATED
NOTE I LEADS ARE GOLD PLATED uNLESS TINNING
MAO TORQUE SMOULDER
IS REQUESTED. INSULATED
3.2 IN LBS WASHER
*2-560 3/8 MOUNTING
NOTE 2: INSULATED HARDWARE IS PROVIDED. SLOTTED PAN
H. SCR. FOR UP
TO .160 TOS,
ALL DRAM. IN INCHES AND ARE REFERENCE
PANEL
UNLESS TOLERANCES

.
070

MICA WASHER
.003 iHn.
(SAME
CONTOUR
AS
HEATSINK

• 2-56 NUT
 61
SNOLLVDMIDadS
*— 325 mAx. •

o e
o
.
3332Vee.'
" to WASHER
10 - 32 NUT —•

horn
*
.4750 0.2.04021411
NOTE I .1Ê diameter is controlled ro the • e0-32
.335 MAO.
n .050 and 250 the cap .325 MIN.
NF 2A
TEFLON SPACER
it Between 250 and end or lead PO...1697MAX .272 00 0.050 T.
21 is held. MOTO I: All leads are Protected
'—
TORQUE
ROTE 2 le attempt to insert a .2 56 from grounding on mounting panel
12 IN 1.85
.-,ss of 045 Man torque for up to .. thick. Between .250 and
PANEL AUX.
s3.2 in lbs.
.530 end of lead amax. of 021 is held.
MAO. 7/32 TNIC
11011 2: Clearance is provided to
•52 (NOTE 21
MOTE 3: 22131. IS provided lo bend bend all leads for overhead circuitry 1:IAX.
,neter leads los overhead cir
•6.32 wrthout Interfering with heat sink 2 MICA WASHERS
ut interfering with heat sink INC 2A mounting on Chassis. .630 .40 O. X.006 TIIN.
nchassis 4 .72+
Al. NAMPA
NOTE 3: All auxiliary metal hare .510 7 —
1
.1 [I .065 4/2 IN LOS
ware is stemless steel.

tar .050 MAX ! 3 LeS

INSuLAIING

INSULATED MOUNTING
TUBING MOTO Il lead diameter is controlled in the
- 00,
(HARDWARE IS PROVIDED> INOTE 11 cone between .050 and 150 trom the cap
or base seat. Between .250 and end of lead
LEADS
a max. of 021 is held.

0
3 LEADS
017
.375 MAO. IV
200 122 -56612 .017
INOTE 1/ 1101I 2v 81.151011 rs made tor the device
(NOTE II to be electrically insulated from mounting
i.010 (NOTE 2)
surface as shown above For this service

.029 MIN. ". •6 1NT

*6-32 Nui
aclearance hole of .281 is recommended.

MOM 3: All exposed metal pads are nickel

.0310.003 437 Mao plated.
2130 4241.1,N
7.010
ALL DIMENSIONS ARE
I ALL DIMENSIONS IN REFERENCE UNLESS
aS wAs.
INCHES AND ARE TOLERENCED
2
REFERENCE UNLESS c lo Leaps eir •PARTI
ALL DIMEN, IN INCHES AND ARE TOLERANCED
REFERENCE UNLESS TOLERANCED
TOO
 •• •

.
12e.
6
.044 MIN 1.0
0626.005
2E2 LHA.
.70 . .106! 010 SO MAX

o
01A PIN CIRCLE

PIO•32 NUT —177) 1;e5 50.4

SEATING PLANE
(GROUNDED TO
HOUSING I
*10-32
TEFLON SPACER i....ConIFI-
II 1P. 0 .2269 MAXI
29
272 0 D X 050 T.( .455 .
05
n.• m6371.x
.25
1
MICA WASHERS -.860 0.0 MAX X .005 TN«.
9
TEFLON SPACER - .31S 0.0. X zoo 11019
.041 MIN 1.0.
PANEL M. 5 • E •4. I' I
I MAX. (NOTE 21
7/32 TN« .135 MAX
(NOTE 21 h._
.'
FL
,
.,,
V7 WASHER - .750 00. X 063 THIC
2 MICA wASHEPS SEATING PLANE
630 MAX 00 Id now TN« 2 1..O.
CuNrSHER

.en NOTES:
430
rOS
iDO
10•32 NF• OA (P.O.
(NOTE II
1597 MAX /

MICA WASNERS- 030 I) D. MAX X 004 TAW

3 LEADS MOTS k lead diameter is controlled in the
.017 I MAX. TORQUE TO BE APPLIED TO STUD IS 20 INCH POUNDS. 9
•.002 zone between .050 and .250 from the base TEFLON SPACER -.272 0.0 X .050 MI
2 INSULATED MOUNTING HARDWARE IS SUPPLIED.

I
seat. Between 250 and end of lead ani as FOR THIS SERVICE A .321 DIA. MAX. PANEL HOLE IS RECOMMENDED.
(NOTE II
— 4 '":ern
, — EL
of .021 is held.
1439
MOT! 2: Provision is made for the device
to be electrically insulated from mounting
surface as shown above For this service I 10 FLAT WASHER- 475 0.0 X .090 TSR
a clearance hole of 281 n recommended.
HIT LOCKWASHER
NOT! 3: All exposed metal parts are nickel
/10 -32 NUT
plated
437 M•X. NOTES:

SNOLLVDIAIDScIS
•24 MIN
ALL DIMENSIONS ARE MAX. TORQUE TO BE APPLIED TO STUD IS 12 INCH POUNDS
\ REFERENCE UNLESS
2 INSULATED MOUNTING HARDWARE IS SUPPLIED
4 ,.(\ TOLERANCED
FOR THIS SERVICE A .281 DIA. MAX PANEL HOLE IS RECOMMENDED
13 LEADS Se

61
 61
SINIOLLVDIAIDadS
t 005-.1
F- 080MA% o
o
250
MIN
.230
DIMENSIONS WITHIN
.209
JEOEC OUTLINE TO-113 .060
.r93 MAX
.178

co
250
MIN

.210 DIMENSIONS WITHIN

I;
914.•1 if E
NOTE lead diameter is controlled in the
zone between 050 and .250 Iran the seat. .170 JEDEC OUTLINE TO-18 e
.195
mg plane Between 250 and end of lead a .030 EXCEPT FOR
MAX .178 EPDXY
max of 021 is hetd. LEAD CONFIGURATION
NOTE 2: Leads having mammum diameter
1.0191 measured in gaging plane 054 • 001 .030 .006
.000 below the seating plane of the device .210 MAX /VP
NOTE I: Lead diameter is controlled in the GOLD
shall be within .007 of true position rela- lone between .000 and 250 from the seat .170 FLASH
twe to amaximum width tat red plane. Between .29) and end of Had a NOVAR
.030
NOTE 3: Measured fiat, max diameter of max. of 021 is held. Max *COMMON WITH TAB
the actual device. NOTE 2: Leads haring maximum diameter
SEATING
PLANE
tole measured in gam plane .0S4 .0)1
000 below the seating plane el he dense
shall be within .007 of true position MN
H .100 MAX
1.500
tive to amaximun width tab. 1.005.1 e
00
3 LEADS RIN
NOTE 3: Measured from max. diameter of .250
.017 I'M the actual device. MIN
(NOTE Il

CONNECTED
r
Fdi'TV
- SEATING
PLANE
INTERNALLY MA
TO HEADER 4 LEADS
250
.017 MIN
.046
(NOTE il
.048
.036
COMMON BASE I eel C.

.028 EMITTER
(NOTE 3) GROUNDED .350fillea
ALL DIMEN. IN INCHES AND ARE
TO BASE

II
REFERENCE UNLESS TOLERANCES .046

046 .036
.028 030 .006
ALL DIMEN. IN INCHES AND ARE (NOTE 31 MAX TYP
REFERENCE UNLESS TOLERANCES

O COMMON WITH TAB

NOTE: BOTH 2-LEAD AND 3-LEAD VERSIONS ARE

AVAILABLE. SUFFIX DESIGNATION DETERMINES
NUMBER OF LEADS. i.e 116554-2 (2-LEAD)
 11/

o #4..40 X PAN HO. SCR.

MAX. TORQUE - 3.2 IN.LBS

o
110
MAX. DIMENSIONS WITHIN
JEDEC OUTLINE TO-5

.060 MAX
.040MIN
.215 MAX
.205 MIN
H TO-50
OUTLINE
I475 MIN PANEL .140 MAX EXCEPT FOR
LEAD CONFIGURATION
.---404 INT. LW.
VA 4-40 NUT

NOTE I: Lead diameter is controlled in the

.01
zone between 050 and 250 Imo the seat.
ing plane. Between 250 and end of lead a
b-.0250.003 TOP 22 MAX
max. of .021 is held.
NOTE 2: Leads having maximum diameter
3 LEADS ON .100 DIA
PIN CIRCLE 0191 measured in gaging plane 054 • 001
.000 below the seating plane of the device
shall be within 007 of tow melon (Fla. .035 1.500

[JO0[1
MIN
.3513 h. In amum. 4,r1th tab.
MIN NOTE I. The specified lead
NOTE 3: Measured frorn max diameter of
diameter applies to the zone
the actual device. SEATING
between .050 and .250 from
the base of the seat. Be NOTE 4: This awe is controlled for auhe PLANE
tween 250 and end of lead matic handling. The variation in actual dram-
.440- amaximum of .021 dram. eter within this zone shall not exceed 010.
6 LEADS
635 MAO. elm is held.

(
.
.017
.035 MAX NOTES I)
.015 MIN All auxilia ymetal hardware is stainless steel. All hardware shown will be
ANO 2
shipped with device

.358 MIN -±--.358 MIN

SNOLINDLEDMS
.034
BOTTOM VIEW
ALL DIMENSIONS IN INCHES
ALL D1MEN. IN INCHES AND ARE .029
REFERENCE UNLESS TOLERANCES (NOTE 31

61
4.71
00
 o

61.
SNOLLVDMIDHJS
:ge
NOTE Ir Lead diameter is controlled m lIre
zone between 050 and 250 horn the seat.
leg plane Between 250 and end ol lead a
max. of 021 ISheld
INS
DIMENSIONS WITHIN

-e is LSEATING
JEDEC OUTLINE TO-5

MIN PLANE
3 LEADS 75 -
- 0M
1- IN
-
A36 5322 .017 NOTE I: Lead thameter ru controlled re the
(NOTE 41
I

MAS. .300 (NOTE I)

zone between 050 and 250 Urn the seat•
ing plane. Between 250 and end of lead a .260
max of 02k Is held. .I .240
NOTE 2: Leads having mammon, chameter
t-LUSE BASE 10191 measured Is gagIng plane .054 •.001
LS SEAT CONNECTED 000 below the seating plane of the device
1035 1.500
MIN
3LEADS .0I7 I
o
gg= (NOTE 1)
:
TO CASE shall be wrthin 007 of true positron ;ale
live to amaximum width lab.
NOTE 3 Measured from max diameter of
MIN

IS ALL DIMEN. IN INCHES AND ARE the actual device.

SEATING
NOTE I: Lead diameter controlled in the
zone between 050 and 250 0onf the base
REFERENCE UNLESS TOLERANCES NOTE Or This zone is controlled for anta
matit handling The variation in actual dram.
PLANE
seat Between 050 and end of lead amar of etervorthra Mrs zone shall not exceed .010
.021 sheld. 3LEADS
ALL DIMEN. IN INCHES AND ARE .017
REFERENCE UNLESS TOLERANCES (NOTE il
ALL LEADS ARE ISOLATED FROM CASE CONNECTED
INTERNALLY
TO HEADER

o .0394
.045
ALL OMEN. IN INCHES AND ARE .029
REFERENCE UNLESS TOLERANCES (NOTE 3)
x

•>
y —
.039

1.1023
.3150-41

.2126

.1000 .0197

*THIS LEAD GROUNDED TO HOUSING

 SPECIAL SILICON PRODUCT OUTLINE DRAWINGS

DIMENSIONS
JEOEC OUTLINE
WITHIN
TO-12 o DIMENSIONS
JEDEC OUTLINE 10-113
WITHIN o
EXCEPT FOR
LEAD CONFIGURATION

1
NOTE Lead Dueler is controlled in the .150 MIN

e
(NOTE 41 11011 1: Lead diameter A controlled tn the
zone between 050 and 250 front the seat-
zone between 050 and 250 from the seat-
ing plane Between 250 and end of cad a .260
ing plane Between 150 and end ot lead a .030
max of 021 is held. ==li240 max of 011 n held MAX
NOTE 2: lead having MaxiMorn diameter DIMENSIONS WITHIN NOTE 2: Leads na in‘ ma lacte
10191 measure in gaging plane 054 001
.000 below he seating plane of the device
.035
JEDEC OUTLINE TO-12 .375:
3
.335
(.0191measured in gaging plane 054 ,1st
.000 below the seating plane of the device I
shall be with, 007 of true Pee ,on tel. shall be within 007 01 Poe posilmn rele
bye to aMinimum Aldtb tab MIN tive to aMannar web tab MIN
NOTE 3: Measured from max diameter of
the actual des ce.
NOTE 3: Measured from maa diameter of
the actual device
00
NOTE 4: This zone w controlled for auto.
matie hand'', The var ilion in actual diam-
SEATING
PLANE NOTE I: Lead diameter is controlled loi the
tone behreen .050 and .250 from the seat-
.150 MIN
(NOTE 4/
EntitTEn pieo SEAT NG
PLANE
man BaSE
eter within hszone sall not exceed 010 ing plane. Between .250 and end of cad a .260
3 4 LEADS man of .021 aheld. .240 nLLECTOft
'
“
4 LEADS

Oil COLLECT. (
01 ' I'M
NOTE 2: Leads having maximum diameter
Nana BASE (NOTE 0
(NOTE 11 (0191 measured in gaging plane .054 • .001 fa. Eat
'OTTER
.000 below the seating elane of the device CONNECTED
shall be within .007 ol true position tela. 110 â INTERNALLY
five to amaximum width tab. 039 :IV TO CASE
NOTE 3: Measured from max. Demeter of .006

757.
.034 the actual device. CATIICOE
SEATING GATE .048
4 Z .045 NOTE 4: This zone is centrolled loe auto - PLANE CATHODE
.028
matie handling The va ilion in actual chain
ALL OMEN. IN INCHES AND ARE .029 ALL OHACN. IN INCHES AND ARE INOTE SI
eter within this zone shall not exceed 010.
REFERENCE UNLESS TOLERANCED (NOTE 31 REFERENCE UNLESS TOLERANCES,
4 LEADS
saIn 4
s.oca
.017

ANOOE (NOTE Il
3 GATE

SNOLLVDIEDadS
CATHOOE (GC)
GATE 2

IClôl .034
CATHODE.045 .028
ALL OMEN. IN INCHES AND ARE .029
REFERENCE UNLESS TOLERANCES (NOTE 3)
45 .

61
 61.
SNOLLVDMIDadS
o
o o
DIMENSIONS WITHIN
JEDEC OUTLINE TO-18

.;;:
EXCEPT FOR .230 DIMENSIONS WITHIN
LEAD CONFIGURATION DIMENSIONS WITHIN
.209 JEDEC OUTLINE TO-5
JEDEC OUTLINE TO-18

NOTE I: Lead diameter is controlled in the

1
.210
EXCEPT FOR
LEAD CONFIGURATION
.195
.178
EXCEPT FOR
LEAD CONFIGURATION :
.170
zone between .050 and .250 Iran the seat-
ing plane. Between .250 and end of lead a .030
MAX .210 .150 MIN
max of 021 is held NOTE I: Lead diameter is controiled in the NOTE Lead diameter is controlled in the
NOTE 2: Leads having maximum diameter .170 zone between 050 and 250 from the seat. (NOTE WI
zone between 050 and 250 from the seat
(0191 measured in gaging plane 054 •001 .030 mg plane Between .250 and end of teed a .260
ing plane Between 250 and end of lead a
.000 below the seating plane of the device max cl 021 is held MAX max. of 021 is held.
shall be within .007 of nue position rela- .500 NOTE 2: Leads having maximum diameter
NOTE 2: Leads having maximum diameter
tive to amaximum width tab MIN
(0191 measured in gaging plane 054 001 019 measured in gaging plane 054 • WI r
NOTE 3: Measured from max diameter of 000 below the sealing plane of the device .000 below the seating plane of the device
the actual device. shall be within .007 of true position rel. '
035 let
shall be within .007 of true position fete .500
SEATING five to amaximum width tab tile to amaximum width tab.

00
PLANE MIN
NOTE 3: Measured from max diameter of NOTE 3. Measured frcm max diameter of
the actual deny the actual device.
SEATING

rTie
3 LEADS
SEATING NOTE 4: This zone is controlled for auto PLANE
OIT *
-lóg PLANE matic handling The variation in actual diam-
(NOTE 11 eter within this zone shall not exceed 010.
F32 3 LEADS
LEAD 4 3 LEADS
LEAD I CONNECTED B2 .017
EMITTER.... E INTERNALLY .
(NOTEIr
017 ,ciox LEAD I LEA° 4
BASE ONE .81 B2 (NOTE 0
TO HEADER
BASE TWO. 82 LEAD 4 E
.046 LEAD I
EMITTER__ E EMITTER E
.036
81 .048 BASE ONE. BI BASE ONE __Br
LEA02 .028 BASE TWO...82 BASE TWO.-82
.046 BI .034
ALL DIMEN. IN INCHES AND ARE (NOTE 3/ LEAD 2
.036 .045 .028
REFERENCE UNLESS TOLERANCES Bi .048
LEADS .028 ALL DIMEN. IN INCHES AND ARE .029
ALL OMEN. IN INCHES AND ARE MOTE 3)
REFERENCE UNLESS TOLERANCES (NOTE 3)
REFERENCE UNLESS TOLERANCE°
 FUNCTIONAL DEVICE OUTLINE DRAWINGS

DIMENSIONS WITHIN
o DIMENSIONS
JEDEC OUTLINE
WITHIN
TO-18
I. 9
r

o
JEDEC OUTLINE TO -5 I
._ .195
EXCEPT FOR
.178
EXCEPT FOR LEAD CONFIGURATION
LEAD CONFIGURATION .230
DIMENSIONS WITHIN
- r JEDEC OUTLINE TO-18
.209
NOTE I: Lead diameter is controlled in the
.210
.170
.150 MIN .195
NOTE I: Lead diameter is controlled in the EXCEPT FOR zone between 050 and 250 from the seat-
(NOTE 4/ .176 .030
zone between 050 and 250 frcen the seat LEAD CONFIGURATION ing plant Between 250 and end of lead a
MAX
Ina plane. Between 250 and endof !ead a
_I .260
max of .021 Is held.
max of .021 is held. .240
NOTE 2, Leads having magnum Mameter
NOTE 2: Leads having maximum diameter .
210
17 0 1.0191 in gaging plane 054 - 001
NOTE lead diameter is controlled in the
(019I measured wi gaging plane 054 • WI 000 beloo the seating plane of the device
lone between OSO and 250 tan the seat-
000 below Me seating plane of the device .030 shall be "Ohm 007 of true P.M. rela 1500
-
035 1.500 ing plane Between 250 and end of lead a MN
shall be withal 007 of true posdlon rela MAX hve to amaximum width tab
MIN max of 021 is held
five to amammum width tab. NOTE 3: Measured from max diameter of
NOTE 2: Leads havIng musc mum Gamete,
NOTE 3: Measured from max diameter of the actual de«
10191 measured in gaging plane 054 •601 SEAT NG
the actual device SEATING 000 below the seating plane of the device PLANE
NOTE This 4one is controlled for auto PLANE shall be within 007 of true poem' rela- 1.500
matm handling the variation in actual diam- bye to amaximum width tab. MIN 35

00 0
6 LEADS
eter within this zone shall not exceed OIL
5 LEADS NOTE 3: Measured from mas diameter el .01T I:tc
e
the actual device
SEAT NG Oc
(N°2,.Dsz I)
'
017
(NOTE 11 PLANE
C„ Cg GROUNDED
4 5LEADS
TO HOUSING

e .017 I:gg .046

:0
03
2: .036
Cris2 .048
E g
.ICLL15 .028
ALL OMEN. IN INCHES AND ARE .029 ALL DIMEN• IN INCHES AND ARE (NOTE 31
REFERENCE UNLESS TOLERANCE() (NOTE 31 REFERENCE UNLESS TOLERANCED
.046

SNOLLVDIAIDMS
.036
.040
.026
ALL DIMEN. IN INCHES AND ARE (NOTE 3/
REFERENCE UNLESS TOLERANCE('

6L
 61.
SNOILV313IDadS
6 - LEAD FLAT PACK

.015 MAX NETWORK PACKAGE

C, c, .050 TYP
(NOTE 27 o:in ,

-r .2.0
B, (NOTE 2)
-
.100.
1
.240

.028 MAX =AM 050 0

.022 MIN .010 INDEX

.007 MAX .050 r.,..„«41

e .0013

.003 MIN MAX

.375 MIN .375 MIN

t 1.— 200 MIN ZOO MIN —.1 —n .506

NOTE 1: ALL DIMENSIONS IN INCHES AND ARE REFERENCE UNLESS TOLERANCED

* LEAD SPACING TOLERANCE IS ze5 AT THE END
NOTE 2. TOLERANCE IS ± .015 AT ENDS OF LEADS AND 0.005 ADJ. TO PKG.
AND 3.005 ADJACENT TO THE BODY
 DIODE OUTLINE DRAWINGS

1.305
1.2651 o 1.5001.000

.7501.025
o
H

CATHODE END NOTE:ALL DIMENSIONS

176 OA MAXDIA-I
320
t=13.001 ,-
.018

CATHODE _.I .DIA. .0035 j

±

MAX
.105 C601:
1 4- .035

IN INCHES
.0025

I. TOLERDIMENSIONS
ANCE°. ARE IN INCHES AND REFERENCE UNLESS
.033

ALL

o
.019 4
.155
4-1.250

o
.140

00 21
:19 MAX
180
1.250
.169
.154
1.250

.075
21 MAO
.192

DIA.
.060

.032 2.002 075

CATHODE END NOTE: DIMENSIONS REF COAT

060

IN INCHES
ALL .032

CATHODE END NOTE ALL

.DIMENSIONS
IN INCHES

SNOIIVDMIDadS
2.630
2.570

1.250
o .162 o
i=f=ti
.147

MAO
387

;L: 251 f-
.021
019
.019

CATHODE DANO .032 REF. DIA.-1

CATHODE END NOTE.ALLEIMENSeNS

6L
IN INCHES
---2
 6L
SNOLLVDIAIDadS
o ICROPHOTO DIODE

470
. :
21
3 7
55:AU
1
1.-047

.074

F.1 81 , .3574

HOBO
.55

c•
I
Tr] —Loo
T V I>
o ALL DIMENSIONS IN INCHES
AND ARE REFERENCE UNLESS TOLERANCED

o
.100 MAX --1
.230
DIMENSIONS WITHIN
.209

e
1=.1 •LL JEDEC OUTLINE TO-IN
LEADS

caTifooc END
MAX 1
.210
NOTE I: Lead diameter H controlled in the
ALL »EN ed INCHES AND ARE REFERENCE .170
zone between 050 and 250 from the see
UNLESS TOLERANCED leg plane. Between .250 and end of lead a .030
max. of 021 is held MAX

.350mIN NOTE 2: Leads having rnallmum diameter

10191 measured in gagrng plane 054 •.001
/-EPDXY .000 below the seating plane of the device
shall be within .007 of true posillon rela-
tive Va maximum width tab.
.050 006

I
MAX TYP NOD 3: Measured from mas diameter of
.'-KOVAR
i21g. the actual device.
SEATING
PLANE

(I
NOTE: BOTH I-LEAD AND 2-LEAD VERSIONS ARE PINS I AND 2 ARE POSITIVE
AVAILABLE. SUFFIX DESIGNATION DETERMINES ELECTRODES CONNECTED IN- 3 LEADS
NUMBER OF LEADS. le KSDIOI-I LEAD) TERNALLY TO REDUCE LEAD .017le
CCNINON WITH TAB
4.• LEAD DIAMETER -002
INDUCTANCE. PIN 3 IS NEGATIVE
ELECTRODE CONVECTED TO THE
(NOTE Il
HEADER CONNECTED
IN
TO HEADER
.046
.036
.048
.028
ALL OMEN. IN INCHES AND ARE IHOTE 31
REFERENCE UNLESS TOLERANCED 45T
 o DIMENSIONS WITHIN JEDEC OUTLINE DO-18

WHITE DOT INDICATES CATHODE-1 .060 MAX .on MAX

.018 M1N_I_

I S
.500 MIN .100MAx .500 MIN

.110
MAX.
.090
MAX. 11 - _.0
EPDXY-A'
0035 mAx
040 MAX 11-- 1 ALL DIMENSIONS IN INCHES AND ARE MAX MIN
-{ REFERENCE UNLESS TOLERANCED
.020
.020
5.001
5.00
l'
000 1.000
X.030 MAX.- T•
-.000 -.000

ALL OMEN. IN INCHES AND ARE REFERENCE UNLESS TOLERANCED.

o
o 032 MAX
1
3 _
I
.110 ___E] .090
MAX.

W ]- .500 MIN —
.040 MAX IT
70357.e - ----'

CATHODE0035 0035 .020 ..-.005 1 .020

INDICATOR 5.001
,095 .—+1«.%3Ó 5.001
I. ALL DIMENSIONS ARE IN INCHES AND REFERENCE UNLESS +.030
-.000 -.000
TOLER ARCED.
2. UNIT WILL BE SUPPLIED WITH LEADS WHEN SPECIFIED. WHEN LEADS
ARE SUPPLIED, THE DIMENSIONS ARE WITHIN JEDEC D0.20
ALL EHNEN IN INCHES AND ARE REFERENCE UNLESS TOLERANCED.
OUTLINE.
 REGISTERED JEDEC TRANSISTOR TYPES
For Explanation of Abbreviations, See Page 642. q,
rd)
MAXIMUM RATINGS ELECTRICAL PARAMETERS
JEDEC Pc mw BVce
9
MIN. MIN. MIN. MAX.
No. Type Closest Dwg.
Use @ 25 °C BVco* lc ma T., °C hfe-hce @ k ma Ilifb me Ge db lc° (pa) @ Vca GE No.
2N22
2N23
Pt 120 —100 —20 55 1.9a >
Pt 80 —50 —40 55 1.9a
2N24 Pt 120 —30 —25 50 2.2e o
2N25
2N26
2N27
Pt
Pt
NPN
200
90
50
—50
—30
35*
—30
—40
100
60
55
85
2.5a

100 1
e
2N28 NPN 50 30* 100 85 100 .5
2N29 NPN 50 35* 30 85 100 I 15 30
2N30 Pt Obsolete 100 30 7 ao 2.2e 2T 17T
2N31 Pt Obsolete 100 30 7 40
2N32 2.2e 2T 150 25
Pt Obsolete 50 —40 —8 ao 2.2e
2N32A 2.7 21T
Pt Obsolete 50 —40 —8 40 2.2e 2.7 21T
2N33 Pt Obsolete 30 —8.5 —7 40
2N34 PNP Obsolete 50 —25 —8 50 40 .6 40T 2N190
2N34A l'NP Obsolete 50 —25 —8 23
50 40 .6 40T 2N190
2N35 NPN 23
50 25 8 50 40 .8 40T
2N36 PNP 50 —20 2N169 22
—8 50 45T 40T
2N37 PNP 50 —20 —8 2N191 23
50 30T 36T
2N38 PNP 2NI90 23
50 —20 —8 50 15T 32T
2N38A ¡'NP 50 —20 —8 2N189 23
50 18T 34 —12 —3
2N41 PNP 50 —25 —15 2N189 23
50 40T 40T —10 —12
2N43 2N190 23
PNP AF 240 —30 —300 100 30
2N43A 1 .5 —16 — 45 2N43. 2N525 23,24
PNP AF 240 —30 —300 100 30
2N44 PNP 1 .15 —16 —45 2N43A. 2N525 23,24
AF 240 —30 —300 100 25T 1 .5 —16 — 45 2N44, 2N524 23.24
2N45 PNP Obsolete 155 —25 —10 100 25T .5 34 —16 —45 2N44
2N46 PNP 50 —25 —15 50 23
40T 4T —10 —12 2N1414
2N47 PNP 50 —35* —20 65 24
.975a —5 —12
2N48 2NI414 24
PNP 50 —35* —20 65 .970a
2N49 PNP 50 —5 —12 2NI414 24
—35* —20 65 .975
2N50 l't —5 —12 2N1414 21
50 —15 —1 50 20, 3T
2N51 Pt 100 —50 —8 50
2N52 2.2e —350 —7
l't 120 —50 —8 50
2N53 Pt —50 —8
2N54 PNP 200 —45 —10 60 .95a 40T 2N1098 16V
2N55 PNP 200 —45 —10 60 .92a 24
2N56 PNP 39T 2N1097 16V 24
200 — 45 —10 60 .90a 38T
2N59 2N320 3
PNP 180 —25* —200 85 90T*
2N59A —100 35T —15 —20 2NI415
PNP 180 —40* —200 85 90T* 24
2N59B —100 35T —15 —20 2N1415
PNP 180 —50* —200 85 90T* 24
—100 35T —15 —20
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

Pc mw BVcE MIN. MIN. MIN MAX. Closest Dwg.

JEDEC
Use @ 25 °C BVca* lc ma TJ °C fife- hFr. * ® lc ma fhfb mc G db Ico (ma) ® Ws GE No.
No. Type

PNP 180 — 60* — 200 85 90T* —100 35T —15 — 20

2N 59C 24
180 —25* — 200 85 65T* — 100 35T —15 —20 2N1415
2N60 l'N1'
180 — 40* —200 85 65T* — 100 35T —15 — 20 2N1415 24
2N60A PNP
180 — 50* — 200 85 65T* — 100 35T — IS —20 2N1925 24
2N6OB PNP
180 — 60* — 200 85 65T* 100 35T —15 —20 2N1926 24
2N60C PNP
180 —25' — 200 85 45T* 100 35T —15 —20 2N1415 24
2N61 PNP
180 — 40* —200 85 45T* 100 35T —15 —20 2N1415 24
2N61A PNP
180 — 50* —200 85 45T* 100 35T —15 —20 2N1924 24
2N61B PNP
180 — 60* — 200 85 45T* 100 35T —is —20 2N1924 24
2N61C PNP
2N62 PNP 50 _ 35* —20 .975aT
100 — 22 —10 85 22T 1 39T —6 —6 2N 1924 24
2N63 PN1'
100 —15 —10 85 45T 1 41T —6 —6 2N1415 24
2N64 PN1'
100 —12 —10 85 90T 1 92T —6 —6 2N324 3
2N65 PNP
2N66 PNP 1W — 40 .8A BO .2 — 300 — 40
2N67 PNP 2W —25* —1.5A 70 23T
2N68 PNP 2W —25' —1.5A 23 —150 ma
2N71 PNP 1W — 50 —250 60 .25 20
2N72 Pt 50 — 40 — 20 55 2.5
200 — 50 2N1614 23
2N73 PN1'
200 — 50 2N1614 23
2N74 PN1'
200 —20 2N1614 23
2N75 PN1'
Obsolete 50 —20* —10 60 .90a 1.0 34 —10 —20 2N322 3
2N76 PNP
—25' —15 85 55 .70 44T —10 —12 2N324 3
2N77 PNP
R F/IF 65 15 20 85 45* 1 5 27 3 15 2N78 22
2N78 NPN
RF/IF 65 20 20 85 45* 1 5 29 3 15 2N78A 22
2N78A NPN 3, 3
35 — 30 — 50 46 .7 44 2N321, 2N323
2N79 PNP
50 —25 —8 100 BOT — 30 —10 214508. 2N1175 24.24
2N80 PNP
Obsolete 50 — 20 —15 100 20 1 —16 — 30 2N1098 24
2N81 PNP
100 20 1 —16 — 30 2N1098 24

SNOIINDIAIDadS
2N82 PNP 35 at 71* C — 20 —15
30 20 5 75 40T 5 3T 25T 3 10 2N169A 22
2N94 NPN
30 20 5 75 40T .5 6T 25T 3 10 2N169A 22
2N94A NPN
2N95 NPN 2.5W 25* 1.5 70 40 .4T 23T
50 — 30 —20 55 35 .5 2N1414 24
2N96 PNP
30 10 75 .85a .5 38T 10 4.5 2N169 15V 22
2N97 NPN so
50 ao 10 85 .85a .5 3BT 5 30 2N169A 25V 22
2N97A NPN 22
50 40 10 75 .95a .8 47T 10 4.5 2N169A 25V
2N98 NPN
50 40 10 85 .96a .a 47T 10 4.5 2N169A 25V 22
2N98A NPN
50 40 10 75 .95a 2.0 47T 10 4.5 2N169A 25V 22
2N99 NPN 22
25 25 5 50 .99a 2.5 53T 10 4.5 2N170 6V
2N100 NPN
2N101 PNP 1W —25' —1.5 70 23T
1W 25* 1.5 70 23T

6L
2N102 NPN
50 35 10 75 .75T 33T 50 35
2N103 NPN
 61
MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pc mw BVce

SNOLLVDMIDadS
MIN. MIN. MIN. MAX. Closest Dwg,
No. Type Use @ 25 °C IIVce* lc ma TJ °C hre-hee * @ le ma fhfb me Ge db leo Wed @ Vce GE No.
2N104 PN I' 150 —30 —50 85 44 .7 33T —10 —12 2N1415, 2N1414 21,24
2N105 PNP 35 —25 —15 85 55 .7 .75 42 —5 —12 2N14I5 24
2N106 l'NP 100 —6 —10 85 25 .8 28 —12 —6 2NI097, 2N1098 24,24
2N107 PNP AF 50 —6 —10 60 20 .6
2N108 PNP —10 —12 2N107, 2NI098 23,24
50 —20 —15
2N109 PNP 150 2N322 3
—25 —70 85 75* 30T 2NI175 24
2N1I0 Pt 200 —50 —50 85 32 1.5
2NlIl PNP 150 —15 200 85 15 3T 33T —5 —12 2N394 24
2NIIIA PNP 150 —15 —200 85 15 3T 33T —5 —12 2N394 24
2N1I2 I'NP 150 —15 —200 85 15 5T 35T —5 —12 2N394 24
2N112A PNP 150 —15 —200 85 15 ST 35T —5 —12 2N394 24
2NI13 PNP 100 —6 —5 85 45T 10T 33T 2N394 24
2N114 PNP 100 —6 —5 85 65T 20T
2N117 NPN 150 2N394 24
30* 25 150 .90a 1 1 10 30
2N118 NPN 150 2N332. 2N334 3, 3
30* 25 150 .950 1 2 10 30 2N333, 2N335 3, 3
2N1I8A NPN-G 150 45 25 150J 54T 7.50
2N119 NPN 10 2N335 3
150 30* 25 150 .974« 1 2
2N120 NPN 10 30 2N335, 2N336 3, 3
150 45* 25 175 .987a 1 7T 2 30
2NI22 NPN 8.75W 140A 150 3 100
2NI23 PNP 10 me 50
Sw 150 —15 —125 85 30* —10 5
2NI24 NPN —6 —20 2N123 23
50 10* 8 75 12* 5 3 2 5 2N293 22
2NI25 NPN 50 10* a 75 24* 5 5 2 5 2NI67 22
2NI26 N1'N 50 10* a 75 48* 5
5 2 5 2NI67, 2NI69 22,22
2N127 NPN 50 10* 8 75 100* 5 5 2 5 2NI67, 2NI69 22. 22
2NI28 l'NP 30 —4.5 —5 85 .95 .5 45 fns —3 —5
2N129 PNP 30 —4.5 —5 85 .92 .5
2N130 30 rwss —3 —5
PNP 85 —22 —10 85 22T 39T 2NI413. 2N1921 24.24
2NI30A PNP 100 —40 —100 85 14 1 .7T 40T —15 —20 2NI413, 2N1924 24,24
2NI31 PNP 85 —15 —10 85 45T 41T 2NI413, 2N1415 24,24
2N131A PNP 100 —30 —100 85 27 1 .8T 42T —15 —20 2N1413, 2N1924 24.24
2NI32 PNP 85 —12 —10 85 90T
2NI32A 42'1' 2N1175 24
PNP 100 —20 —100 85 56 1 IT
2NI33 44T —15 —20 2NI415 24
PNP 85 —15 —10 85 25 36T —12 —15 2N1414 22
2N133A PNP 100 —20 —100 85 SOT 1 .8T
2NI35 38T —15 —20 2NI414, 2N1175 22,24
PNP Obsolete 100 —12 —50 85 20T 4.5T
2N136 29T 2N394 24
PNP Obsolete 100 —12 —50 85 40T 6.5T 31T 2N394 24
2N137 PNP Obsolete 100 —6 —50 85 60T
2NI38 IOT 33T 2N394 24
PNP 50 —12 —20 50 140T
2NI38A 30T 2N508 24
PNP 150 —30 —100 85 29T 2NI098 24
2NI38B PNP 100 —30 —100 85
2NI39 29T 2NI098 24
PNP 80 —16 —15 85 48 1 6.8
2NI40 30 —6 —12 2N394 24
PNP 35 —16 —15 85 45 .4 7 27 —6 —12 2N394, 2N395 24,24
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

MIN. MIN. MIN. MAX. Closest DWg.

JEDEC Pc mw BVce
fhb mc Ge db Ice (pa) @ Ves GE No.
No. Use @ 25 °C BVcs * lc ma TJ °C hfe-hFs * (4) lc mta
Type

-30 -.8A 65 .975aT 50 .4T 18T -100 -20

2N111 PNP 4W
30 .8A 65 .975aT -50 .4T 26T -100 20
2NI42 NPN 4W
-30 -.8A 65 .975aT 50 .4T 26T -100 -20
2N143 PNP 4W
30 .8A 65 .975,«T 50 .4T 26T 100 20
2N144 NPN 4W 22,22
5 75 30 30 3 9 2N293, 2NI121
2NI45 NPN 65 20 22
5 75 33 33 3 9 2NI121
2NI46 NPN 65 20
36 36 3 9 2NI121 22
2NI47 NPN 65 20 5 75
32 3 12 2N169 22
2NI48 NPN 65 16 5 75
32 3 12 2NI69 22
2N 148A NPN 65 32 5 75
35 3 12 2NI69 22
2NI49 NPN 65 16 5 75
35 3 12 2N169 22
2NI49A NPN 65 32 5 75
38 3 12 2NI69 22
2NI50 NPN 65 16 5 75
38 3 12 2NI69 22
2NI50A NPN 65 32 5 75
-30* -SA 85 .1ST 30 1 ma -30
2NI55 PNP 8.5W
-30* -3A 85 24* .5A .1ST 33 1 ma -30
2N156 PNP 8.5W
-60* -SA 85 20* .5A .1 1 ma -60
2NI57 PNP 8.5W
-3A 85 20* .5A .1 1 ma -90
2NI57A PNP 8.5W -90*
-60* -3A 85 21* .5A .15T 37 1 ma -60
2N158 PNP 8.5W
-80* -3A 85 21* .5A .15 1 ma -BO
2N158A PNP 8.5W 2N332, 2N1276 3, 3
40* 25 150 .9« 4T 34T 5 40
2NI60 NPN 150 2N332 3
40* 25 150 .9a -1 4T 34T 5 40
2NI60A NPN 150
.95a -1 5T 37T 5 40 2N333, 2N1277 3, 3
2NI61 NPN 150 40* 25 150
.95a -1 5T 37T 5 40 2N333 3
2N161A NPN 150 40* 25 150
-1 8 38T 5 40 2N335, 2N1278 3, 3
2N162 NPN 150 40* 25 150 .95a
.95a -1 8 38T 5 40 2N335 3
2NI62A NPN 150 40* 25 150 3, 3
150 .975a -1 6T 40T 5 40 2N335, 2NI278
2NI63 NPN 150 40* 25 3
25 150 .975a -1 6T 40T 5 40 2N335
2N163A NPN 150 40*
8.00 30 2NI121 22
2N164A NPN 65 1.0* 20 853 40T
26 2N169 22

SNOUNDIAIDadS
55 1.0* 20 75J 72T 5.00
2N165 PNP-M 24T 5 5 2NI70 22
Obsolete 25 6 20 50 32T 1 5T
2NI66 NPN
8 5 1.5 15 2N167 22
2NI67 NPN Sw 65 30 75 85 17*
17* 8 5 1.5 15 2N 167A 22
2N167A NPN Sw 65 30 75 85
t 6T 28 5 15 2N293 22
2N168 NPN IF 55 15 20 75 20T
23* 1 5 28 5 15 2N1086, 2N1121 22,22
2NI68A NPN Obsolete 65 15 20 BS
1 8T 27 5 15 2N169 22
2N169 NPN IF 65 15 20 85 34*
34* 1 8T 27 5 15 2N169A 22
2N169A NPN AF 65 15 20 85
1 4T 22T 5 5 2N170 22
2NI70 NPN IF 25 6 20 50 .95aT
22 3 9 2N293 22
2N172 NPN 65 16 5 75
-60 - I3A 95 85T* IA .6T 40T -.5 ma -40
2N173 PNP 40W
-80 -13A 95 40T* IA ,2T 39T -10 ma -60
2N174 PNP 40W
-8 ma -BO

6L
PNP 85W -80 -15A 95 40* 1.2A .1
2N174A 2 4.3T -12 -25 2NI175A 24
PNP 20 -10 -2 85 65 .s
2N175
:
MAXIMUM RATINGS

wouvaimaaas 61
ELECTRICAL PARAMETERS
JEDEC Pc mw BV I MIN.
No. Type MIN . MIN . MAX.
Use @ 25 °C 8V.1, * I ma Closest Dwg.
TJ°C hfe-hpe s @ lc ma fhfb mc G.• db I
mp caza) (41 VCB GE No.
2N176 PNP 3W —12 —600 80
2N178 PNP 3W 251'
2N179 —12 —600 80
PNP 29T
—20 —60 88
2N180 PNP 32'1
150 —30 —25 75
2N181 PNP 60T .7 371'
250 —30 —38 75 2N1415
2N182 NPN 60T .7 34T 24
100 25* 10 85 2N526
2N183 NPN 25T* 2.5 24
100 25* 3T 10
2N184 NPN 10 85 50T*
100 25* 5 3T 10
2N185 PNP 10 85 100T*
150 —20 10 3T 10
—150 75 35 —100
2N186 PNP Obsolete 100 26 15 —20 2N323
—25 200 85 24T* 3, 3
2N186A PNP AF Ou t 200 —25 200 85 24T* —100
—100 .8T
.8T 28
28 —16
—16 —25
2N187 PNP —25 2N186A
2N186A, 2N1413 23, 24
Obsolete 100 —25 200 85 36T* —100 IT 23
2N187A PNP AF Out 30 —16 —25
200 —25 200 85 2N187A. 2N1413 23.24
2N188 PNP Obsolete 36T* —100 1T 30
100 —25 —200 85 54T* —16 —25 2N187A
2N188A PNP AF Ou t 200 —25 —200 85 54T* 100
100 1.2T
1.2T 32
32 —16 —25 2N188A 23
—16 —25 2N188A, 2N1413 23,24
2N189 PNP AF 75 —25 —50 85 23
2N190 PNP AF 75 24T* 1 .8T 37
—25 —50 85 —16 —25 2N189, 2N1413
2N191 l'NP AF 36T* - 1 1.0T 39 23,24
75 —25 —50 85 —16 —25 2N190, 2N1114
2N192 PNP 54T* 1 1.2T 41 23,24
AF 75 —25 —16 —25 2N191, 2N1415
2N193 NPN —50 85 75T* I 23,24
50 15 I.5T 43 —16 —25
2NI94 NPN 75 3.8 1 2 2N192, 2N1175 23,24
50 15 75 40 15 2N1086
2N194A 4.8 1 2 15T 22
NPN 50 20 40 15 2N1086
2N206 PNP 100 75 5 1 22
75 —30 2 20 50 18
2N207 PNP —50 85 47T .8 2N1087 22
50 —12 —20 65 2N1414
2N207A 35 1 2T 24
PNP 50 —15 —12 2N1415, 2N323 24,3
2N207B —12 —20 65 35
PNP 50 1 2T —15
2N211 —12 —20 65 35 —12 2N1415, 2N1175A 24,24
NPN 50 1 2T —15
10 50 75 3.8 —12 2N1415, 2N1175A 24,24
2N212 NPN 1 2 20
50 10 50 10 2N293, 2N1086 22, 22
2N213 NPN 50 75 7 1 4
25 100 75 70 1 22T
39 200
20 40
10
2N169A
2N213A NPN 2N293, 2N1086 22,22
150 25 100 85 100
2N214 NPN 1 10 Kc 38 22
125 25 50 20
2N215 PNP 75 75 50 35
150 —30 .6 26 200 40
2N216 NPN —50 85 44
50 15 .7 33T —10 —12
50 75 3.5 1 2N1415 24
2N217 PNP 2 26T 40 15
150 —25 —70 85 2N292, 2N1086 22,22
2N2I8 PNP 75* 30T
80 —16 —15 85 2N321, 2N396
2N219 PNP 48 1 6.8 30 3.24
80 —16 —15 85 75 —6 —12 2N394
2N220 PNP .4 10 32 24
50 —6 —12 2N394
—10 —2 85 65 24
2N223 PNP 100 —18 —150 65 39 —2 .8
.6T 43 —20 —9 2N323
2N224 PNP 2N323, 2N1175A 3, 24
250 —25* 150 75
2N225 60* —100 .5T 3
PNP 250 —25 —12 2N321, 2N1175
2N226 —25* 150 75 60* 3,24
PNP 250 —100 .5T —25
2N227 —30* 150 75 35* —12 2N321, 2N1175 3,24
PNP 250 —100 .4T —25
—30* 150 75 35* —30 2N321, 2N1415 3,24
—100 .4T —25 —30 2N321. 2N1415 3.24
 MAXIMUM RATINGS ELECTRICAL PARAMETERS
_
MIN. MIN. MIN. MAX. Closest Dwg.
JEDEC Pc mw BVes:
ë 25 °C EVce* lc ma Ti °C hfe-hvc* @ k ma fhfb mc Ge db leo (pa) @ Vce GE No.
No. Type Use

50 75 50 :15 .6 23 200 40 2N169 22

2M:28 NPN 50 25
40 75 .9a I .55 200 5 2N169 22
2N229 NPN SO 12
9 -4.5 -3 55 19 20 fos -3 -5
2N231 PNP
2N232 PNP 9 -4.5 -3 55 9 30 1
0.
. -6 -5
10 50 75 3.0 1 100 10 2N292 22
2N233 NPN 50
2N233A NPN 50 10 50 75 3.5 1 150 15 2N292 22

25W -30 -3A 90 8 Kc 25 -1 ma T -25

2N234 PNP
25W -30 -3A 90 8 Kc 25 - Ima T -25
2N234A PNP
PNP 25W -40 -3A 90 7 Kc 30
2N235
2N235A PNP 25W -40 -3A 90 7 Kc 30
40 3.0A 85 300 3
2N235B PNP -25
PNP 25W -40 -3A 95 6 Kc 30 -1 ma
2N236
25W -40 -3A 95 6 Kc 30 -1 ma -25
2N236A PN1'
40 3.0A 95 300 2
2N2368 PNP 2N525 24
150 45 20 85 SOT .50 10
2N237 PNP
75 37 -20 -20 2N323 3
2N238 PNP 50 -20
10 -6 -15 16 30 fos -3 -5
2N240 PN1' -25 2N241A 23
Obsolete 100 -25 200 85 73T* 100 1.3T 35T -16
2N241 PNP
200 -25 200 85 73T* 100 1.3T 35T -16 -25 2N241A, 2N1415 23,24
2N241A PNP Ate Out
20W -45 -2A 85 5 Kc 30 -5 ma -45
2N242 PNP 30
750 60* 60 . 150 .9 -5 30 1
2N243 NPN
750 60* 60 150 .961 -5 30 1. 30
2N244 NPN
80 -12 -10 85 60 30 37 -20 -12
2N247 PNP
30 -25 -5 85 20T* .5 50T -10 -12
2N248 PNP
350 -25 -200 85 30 -100 -25 -25
2N249 PNP
12W -30 -2A 80 30* -.SA -1 ma -30
2N250 PNP -60
I2W -60 -2A 80 30* -.5A 30 -2 ma
2N251 PNP
30 -16 -5 55 28 -10 -12
2N252 PNP 2N293, 2NI121 22,22
65 12 5 75 32 3 9
2N253 NPN 9 2N293, 2N1121 22,22
65 20 5 75 3
2N254 NPN
PN1' I.5W -15* -3 85 .2'1' 19
2N255 5 ma 15
2N255A PNP 20W 15 4A 85 25* 450
PNP 1.5W -30* -3 85 .2T 22
2N256
20W 25 4A 85 25* 450 5 ma -25
2N256A l'NP -40
2W -40* 85 55T .5A 7 Kc 30 -2 ma
2N257 PNP -6 2N332. 2N1276 3,3
200 -10* -50 150 16T 1 1.8T 38T .001T
2N260 PNP
-30* -SO 150 16T 1 1.8T 38T .001T -6 2N332 3
2N260A PNP 200
PNP 200 -75* -50 150 10T 1 1.8T 36T .001T -6 2N332 3
2N261
2N262 PNP 200 -10* -50 150 20T 1 6T 40T .001T -6 2N333 3
-30* -50 150 20T 1 6T 40T .001T -6 2N333 3
2N262A PN1' 200
2N265 PNP 75 -25 -50 85 110T* 1 1.5T 45 -16 -25 2N265, 2N508 23,24
80 -12 -10 85 60 30 37 -20 -12
2N267 l'NP
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pc mw BVce MIN. MIN. MIN. MAX. Closest Dwg.

No. TYP. Use @ 25 °C BVca * lc ma IVC hfe-het: * Q,I. I, ma fhfl, mc Ge db leo (pa) ® Vea OE No.
2N268 PNP 2W —80* 85 6 Kc 28 —2 ma —80
2N268A PNP 2W —60 90 20* 21
2N269 PNP —2 ma —80
120 —24 —100 85 35 t —5 —12 2N404 24
2N270 PNP 150 —25 —75 85 70 I; ti 35 —10 —25 2N32I, 2NI415 3,24
2N27I PNP 150
2N271A PNP
—10 —200 85 45T I in 29T —5 —12 2N394 24
150 —10 —200 85 45T 1 IOT 39T —5 —12 2N394 24
2N272 PNP 150 —24 —100 85 60 IT I2T —6T —20 2N324 3
2N273 PNP 150 —30 —100 85 10 50
2N274 PNP 29 —6T —20 2N1098 24
80 —12 —10 85 60T 1 30T 45T —20 —12
2N277 PNP 55W —40 12A 95 85T 1.2A .5T 34T —.5 ma T —30
2N278 PNP 55W —50 12A 95 85T 1.2A .5T 34T —.5 ma T —20
2N28I PNP 165 32 250 75J 70T* .90 10 2N1415 24
2N285 PNP 25W —40 3A 95 6 Kc 38 —1 ma —25
2N285A PNP 25W —40 3A 95
2N290 6 Kc 38 —1 ma —25
PNP 55W —70 —12A 95 72T* 1.2A .4T 37T —1 ma T —60
2N291 PN1' 180 —25 —200 . 85 30* 100 31 —25 — 25 2N320, 2N1414 3,24
2N292 NPN IF 65 15 —20 85 8 1 5T
2N293 NPN 25.5 5 15 2N292 22
IF 65 15 —20 85 8 1 8T 28 5 15 2N293 22
2N297 PNP 35W —50 —5A 95 40* .5 5 Kc 3 ma —60
2N297A PNP 35W —50 —5A 95 40* .5 5 Kc 3 ma —60
2N299 PNP 20 —4.5 —5 85 90 f. 20 —3 —5
2N300 PNP 20 —4.5 —5 85 11 .5
2N301 85 f
o. —3 —5
PNP 11W —20 —1.5A 91 70T* lA
2N30IA PNP 33T —3 ma —30
11W —30 —1.5A 91 70T* IA 33T —3 ma —30
2N302 PNP 150 —10 —200 85 45T
2N303 7 —1T —.12 2N186A 23
PNP 150 —10 —200 85 75T 14 —1T —.12 2NI86A 23
2N306 NPN 50 15 75 25 1 .6 34 50 20 2N292
2N307 PNP 22
10W —35 —IA 75 20 200 3 Kc
2N307A PNP 15 ma —35
17W —35 —2A 75 20 200 3.5 Kc 22
2N308 PNP 7 ma —35
30 —20 —5 55 39 —10 —9
2N309 PNP 30 —20 —5 55
2N3I0 PNP 41 —10 —9
30 —30 —5 55 28T 37T
2N311 PNP 75 —10 —9
—15 85 25 —60 —15 2N123 23
2N3I2 NPN 75 15 85 25
2N3I3 NPN Obsolete 60 15 2N167 22
65 15 20 85 25 5 36 max
2N314 NPN Obsolete 65 15 Use 2N292 22
20 85 25 8 39 max Use 2N293 22
2N3I5 PNP 100 —15 —200 85 15 100 5T —2 —5 2N396
2N315A PNP-A 150 30 1008 35T 5 24
2N316 5.00 25 2N396 24
PNP 100 —10 —200 85 20 200 12T —2 —5 2N397 24
2N316A PNP-A 150 30 100S 35T*
2N317 12.0 25 2N397 24
PNP 100 —6 —200 85 20 400 20T —2 —5
2N3I8 PNP Photo 50 —12 —20 .75T
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pc mw BVcE MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @ 25 °C Mice * lc ma TJ °C hfe- hFE * @ lc ma fhfb mc Go db Ica (po) @ Ven GE No.

2N3I9 ¡'NP AF 225 -20 - 200 85 34T* -20 2T -16 -25 2N319, 2N14I3 3,24
2N320 PNP AF 225 -20 -200 85 50T* - 20 2.5T -16 - 25 2N320, 2NI414 3,24
2N32I ¡'NP AF 225 - 20 - 200 85 80T* - 20 3.0T -16 -25 2N32I, 2N14I5 3,24
2N322 l'NP AF 140 -16 - 100 60 45T -20 2T -16 -16 2N322 3
2N323 PNP AF 140 -16 - 100 60 68T -20 2.5E -16 -16 2N323 3
2N324 ¡'NP AF 140 -16 - 100 60 85T - 20 3.0T -16 -16 2N324 3
2N325 ¡'NP 12W -35 -2A 85 30* - 500 .15 - 500 - 30
2N326 NPN 7W 35 2A 85 30* 500 .15 500 30
2N327 l'N P 335 - 50* - 100 160 9 .1 .3T 30 - 30
2N327A PNP 350 - 50* - 100 160 9* 1 .2T -30
2N 328 ¡'NP 335 -35' - 100 160 18 1 .35T 32 - 30
2N328A l'NP 350 - 50* - 100 160 18* 1 .3T - 30
2N329 ¡'NP 335 -30' - 100 160 36 1 .6T 34 - 30
2N329A ¡'NP 350 - 50* - 100 160 36* 1 .5T - 30
2N330 ¡'NP 335 - 45* - 50 160 9 1 .5 30 -30
2N330A PNP 350 - 50* - 100 160 25T 1 .5 34T - 30
2N331 PNP 200 -30' - 200 85 50T 44T -16 - 30 2N1415 24
2N332 NPN Si AF 150 45* 25 200 9 1 10T 14T 2 30 2N332 3
2N332A NPN Si AF 500 45 25 175 9 2.5 11 .500 30 2N 332A 3
2N333 NPN Si AN'. 150 45* 25 200 18 1 12* 14T 2
2N333A 30 2N333 3
NPN Si AF 500 45 25 175 18 2.5 11 .500 30 2N333A 3
2N334 NPN Si AF 150 45* 25 200 18 1 8 13T 2 30 2N334 3
2N 334A NPN Si AF 500 45 25 175 18 8.0 12 .500 30 2N334A 3
2N335 NPN Si A F" 150 45* 25 200 37 1 14' 13T 2 30 2N335 3
2N335A NPN Si AF 500 45 25 175 37 2.5 12 .500 30 2N335 3
2N335I3 NPN Si AF 500 60 25 175 37 2.5 12T .500 30 2N335B 3
2N336 NPN Si AN' 150 45* 25 200 76 1 15* 12T 2 30 2N336 3
2N336A NPN Si Ale 500 45 25 175 76 2.5 12 .500 30 2N336A 3
2N337 N PN Si AN' 125 45* 20 200 19 1 10 I 20 2N337 3
2N337A N PN-G 500 45 20 200S 35T 30.0 .10 2N337A 3
2N338 N PN Si At 125 45* 20 200 39 1 20 I 20 2N338 3
2N338A N PN-G 500 45 20 2008 75T 45.0 .10 2N 338A 3
2N339 NPN 1W 55* 60 150 .9« -5 30 1 30 2N656A 24
2N339A NPN 1000 60 2008 53T 1.0 2N656A 24
2N340 NPN 1W 85* 60 150 .9« -5 30 1 30 2N 657 A 34
2N 340A NPN 1000 85 150J 50T 30 1.0 2N657A 24
2N341 NPN IW 125* 60 150 .9« -5 30 1 30 2N657A 24
2N341A NPN 1000 125 2008 53T 30 1.0 2N657 A 24
2N342 NPN 1W 60* 60 150 .9« -5 30 I 30 2N656A 24
2N342A NPN-G 1000 85 60 150J 20T 30 1.0 2N657A 24
2N342B GD 1000 85 60 150J 2IT 6.00 50 2N33515, 2N657A 3,24
2N343 NPN IW 60* 60 150 .966« -5 30 1 30 2N656A 24
J1

MAXIMUM RATINGS ELECTRICAL PARAMETERS

co,
Pc mw Vic>: MIN. MIN. MIN. MAX. Closest Dwg.
JEDEC
Use @ 25 °C BVes ° le ma TJ °C lee-IIFE ° ® le me fh11, mc G. db 'co (µa) @ VCB GE No.
No. Type

1000 65 60 150J 59T t, (ml 100 2N33511, 2N 656A 3,24

2N3131i GD
2N344 PNP 40 —5 —5 85 11 30 1.. —3 —5
2N345 PNP 40 —5 —5 85 25 30 L. —3 —5
2N346 l'NP 40 —5 85 10 60 l'.. —3 —5
90 50 150.1 241' 3.00 35 6.0 2N292 22
2N348
2N349
N PN-G
N PN-G
750
750 125 40 150J 19T 3.00 34 8.0 2N293 22 o
2N350 l'NP IOW — 40* —SA 90 20* — 700 5 Kc 30 — 3 ma — 30
IOW _40* —3A 90 25* —700 5 Kc 32 — 3 ma —30
2N351 PN P
PN P 25W —40_ —2A 100 30 —IA 10 Kc 30-5 ma — 1 @ 85°C
2N352
PN1' 30W — 40 —2A 100 40 —IA 7 Kc 30 — 5 ma — 1 @ 85°C
2N353
2N354 PN1' 150 —25° — 50 140 9 I 8 ro. —10
2N355 PNP 150 — 10° — 50 140
9 I 8f o. — 10
2N356 N l'N 120 18 100 85 20 100 31' 5 5
2N356A N PN-A 150 30 100S 35T* 3.00 25
120 15 100 85 20 200 6T 5 5
2N357 N PN
2N357A N PN-A 150 30 100S 40 -r* 6.00 25
120 12 100 85 20 300 9T 5 5
2N358 N PN
N PN-A 150 30 100S 40T* 9.00 25
2N358A
150 20 400 85 3001' 1.50 40 10 2N508 24
2N359 PNP-A
150 400 85 150T 1.20 37 10 2N1415 24
2N360 PN P-A
150 20 400 85 75T 1.00 34 10 2N I
413 24
2N36I PNP-A
150 18 100 85 90T 2.00 42 15 2N324 3
2N362 PN P-A
150 32 100 85 50T 1.50 39 15 2N1414 24
2N363 PN P-A
150 30* 50 85 9 —I I 10 30 2N1694 24
2N364 N PN
150 30* 50 85 19 —1 1 10 30 2NI694 2I
2N365 N PN
2N366 NPN 150 30* 50 85 49 —1 1 10 30
100 — 30* — 50 75 9 1 .3 — 30 —30 2N1413 24
2N367 N l'N
150 — 30* — 50 75 19 1 .4 — 20 — 30 2N1413 24
2N368 PNP
150 —30° — 50 75 49 1 .5 — 20 — 30 2N14I5 24
2N369 PN P
2N370 l'NP 80 —24* —20 85 60T 1 30T 31M —10 —12
PNP 80 _24* — 20 85 .984T 1 30T I7.6M —10 —12
2N371
2N372 PNP 80 —24° —20 85 60T I 30T 12.5M —10 —12
PNP 80 —24° —10 85 60T 1 30T 40T —16 —12
2N373
2N374 PN P 80 —24* —10 85 60T 1 30T 40T —16 —12
2N375 PNP 45W — 60 —3A 95 35 IA 7 Kc — 3 ma — 60
2N376 PNP IOW —40° —3k 90 60T 1A 5 Kc 35T
2N377 N PN Sw 150 20 200 100 20* 30 6T 5 1
2N377A NPN 150 40 200 100 20* 200 6T 40 40
2N378 PNP 50W — 40 —5k 100 15* 2A 5 Kc — 500 —25
2N379 PNP 50W — 80 —SA 100 20* 2A 5 Kc — 500 —25
2N380 PNP 50W — 60 —SA 100 30* 2A 7 Kc — 500 —25
200 —25 — 200 85 50T 20 1.2T 3IT — IOT —25 2N320. 2NI924 3.24
2N381 PNP
 MMIIIMIIMIMINNIM
MAXIMUM RA TI
NGS ELE CTRI CAL PA RAMET ERS

JEDEC Pc mw BV( f• MIN. M IN . M IN . MAX. Closest Dwg.

No. Type Use © 25 °C BVce * I, ma T.I °C hfe-hrE * (
L
+ h ma fut. mc G• db lc() (.ca) ê VCB GE No.

2N382 PNP 200 —25 —200 85 75T 20 I.51' 11 I — IOT —25 2N321 3
2N383 l'NP 200 —25 —200 85 100T 20 1.8T F.I —10T —25 2N321. 2N1175 3,24
2N384 PNP 120 —30 —10 85 601' 1.5 100T 13 —16 —12
2N385 NPN 150 25 200 100 30* 30 4 35 25
2N385A NPN-A 150 40 200 100J 70T 8.00 40
2N386 PNP 12.5W —60 —3A 100 20 —2.5A 7 Kc —5 ma —60
2N387 PNP 12.5W —80 —3A 100 20 —2.5A 6 Kc —5 ma — 80
2N388 NPN Sw 150 20 200 100 60* 30 5 10 25
2N388A NPN 150 ao 200 100 30* 200 5 40 40
2N389 NPN 85W 60 200 12 IA 10 ma 60 @ 100°C
2N392 PNP 70W —60* —5A 95 60 3A 6 Kc — 8 ma —60
2N393 PNP 50 —6 — 50 85 20* — 50 40 fo. —5 —5
2N394 PNP Sw 150 —10 —200 85 20* —10 4 —6 —10 2N394 24
2N394A PNP-A 150 30 200 1008 70T* 7.00 6.0 2N394A 24
2N395 PNP Sw 200 —15 —200 100 20* —10 3 —6 —15 2N395 24
2N396 l'NP Sw 200 —20 —200 100 30* —10 5 —6 —20 2N396 24
2N396A PNP Sw 200 20 200 100 30* 10 5 —6 —20 2N396A 24
2N397 PNP Sw 200 —15 —200 100 40* —10 10 —6 —15 2N397 24
2N398 PNP 50 —105 —110 85 20* —5 ma —14 —2.5 2N1614 23
2N398A PNP 150 105 100J 20T 1.00 2N1924 24
2N399 PNP 25W —40 —3A 90 8 Kc 33T —1 ma —25
2N400 PNP 25W —40 3.0A 95 1 40 -2 ma —25
2N401 PNP 25W —40 —3A 90 8 Kc 30T —1 ma —25
2N402 l'NP 180 —20 —150 85 .96aT 1 .6T 37T —15 —20 2N320, 2N1413 3, 24
2N403 PNP 180 —20 —200 85 .97aT 1 .85T 32 —15 —20 2N319, 2N 1413 3,24
2N404 PNP Sw 120 —24 —100 85 4 —5 —12 2N404 24
2N404A PNP-A F1CPS 150 40 150 100 8.00 20 2N404A 24
2N405 PNP 150 —18 —35 85 35T* 1 .65T 431' —14 —12 2N322 3
2N406 PNP 150 —18 —35 85 35T* 1 .65T 43T —14 —12 2N322 3

SNOIIVDIAIDUS
2N407 l'NP 150 —18 —70 85 65T* —50 33T —14 —12 2N323 3
2N408 PNP 150 —18 —70 85 65T* — 50 331' —14 —12 2N323 3
2N409 PNP 80 —13 —15 85 .98ceT 1 6.7T 38T —10 —13 2N394 24
2N410 PNP 80 —13 —15 85 .98aT 1 6.7T 38T —10 —13 2N394 24
2N411 l'NP 80 —13 —15 85 75T .6 32T —10 —13 2N397 24
2N412 PNP 80 —13 —15 85 75T .6 32T —10 —13 2N397 24
2N413 PNP IF Sw 150 —18 —200 30 6T —5 —12 2N413 21
2N413A l'NP 150 —15 —200 85 30T 1 2.5T 33T —5 —12 2N394 24
2N414 l'NP IF Sw 150 —15 —200 60 7T —5 —12 2N414 24
2N414A PNP 150 —15 —200 85 60T 1 7T 35T —5 —12 2N394, 2N414 24
2N415 PNP 150 —10 —200 85 80T 1 10T 30T —5 —12 2N394 24
2N415A PNP 150 —10 —200 85 80T 1 10T 39T —5 —12 2N394 24

6L
2N416 PNP 150 —12 —200 85 80T 1 10T 20T —5 —12 2N394 24
 61
MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC

SNOUNDLIIDUcIS
Pc mw BVcE MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @ 25 °C BVco ° le ma TJ °C hfe-hFE * €7.* 1c ma Dill mc Ge db leo (fia) @ Veo GE No.

2N4I7 PNP 150 —10 —200 85 140T 1 20T 27T —5 —12 2N394 24
2N4I8 l'NP 2SW 80 SA 100 40* 4A 400 Kc 15 ma —60
2N420 PNP 25W 45 5A 100 40* 4A 400 Kc 10 m 10 ma —25
2N420A PNP 25W 70 SA 100 40* 4A 400 Kc 15 ma — 60
2N422 PNP 150 —20 —100 85 SOT I .8T 38T —15 —20 2N320, 2N1175A 3,24
2N425 PNP 150 —20 — 400 85 20* I 2.5 —25 —30 2N394 24
2N426 PNP 150 —18 — 400 85 30* 1 3 —25 —30 2N395 24
2N427 l'NP 150 —15 — 400 85 40* 1 5 —25 —30 2N396 24
2N428 PN I' 150 —12 —400 85 60* 1 10 —25 — 30 2N397 21
2N438 NPN 100 25 85 20* 50 2.5 10 25
2N438A NPN 150 25 85 20* 50 2.5 10 25
2N439 NPN 100 20 85 30 50 5 10 25
2N439A NPN 150 20 85 30* 50 5 10 25
2N440 NPN 100 15 85 40* 50 10 10 25
2N440A NPN 150 15 85 40* 50 10 10 25
2N444 NPN 120 15 85 1ST .5T 2T 10
2N444A NPN-A 150 40 100S 30T .50 25
2N445 NPN 100 12 85 35T 2T 2T 10
2N445A NPN-A 150 30 100S 90T* 2.00 25
2N446 NPN 100 10 85 60T ST 2T 10
2N446A NPN-A 150 30 100S 150T* 5.00 25
2N447 NPN 100 6 85 125T 9T 2T 10
2N447A NPN-A 150 30 100S 200T* 9.00 25
2N448 NPN IF 65 15 20 85 8* 1 ST 23 5 15 2N292 22
2N449 NPN IF 65 15 20 85 34* 1 8T 24.5 5 15 2N293
2N450 PNP 22
Sw 150 —12 —125 85 30* —10 5 —6 —12 2N450, 2N394A
2N456 23,24
PNP 50 — 40 SA 95 130T* IA —2 ma — 40
2N457 l'NP 50 — 60 SA 95 130T* lA —2 ma — 60
2N458 PNP 50 —80 SA 95 I30T* lA —2 ma — 80
2N459 PNP 50 — 60 5A 100 20* 2A 5 Kc 100 ma — 60
2N460 PNP 200 —45° —400 100 .94a 1 1.2T 34T —15 — 45 2N524 24
2N461 PNP 200 — 45* — 400 100 .97a 1 1.2T 37T —15 — 45 2N461
2N462 PNP 24
150 — 40* —200 75 20* —200 .5 —35 —35 2N1614. 2N527 23,24
2N463 PNP 37.5W — 60 SA 100 20* —2A 4 mc —300 — 40
2N464 PNP 150 — 40 —100 85 14 1 .7T 40T —15 —20 2N1614. 2N527 23.24
2N465 PNP 150 —30 —100 85 27 1 .8T 42T —15 —20 2N1414, 2NI924 24,24
2N466 PNP 150 —20 —100 85 56 1 IT 44T —15 —20 2N32I, 2N1175 3,24
2N467 PNP 150 —15 —100 85 112 1 1.2T 45T —15 —20 2N508 24
2N469 PNP 50 75 10 1 IT — 50 —6
2N470 NPN-GD 200 15 175A 16T 2N335
2N471 3
NPN-GD 200 30 175A 16T 2N335
2N47IA 3
NPN-GD 200 30 175A 25T 2N335 3
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pc mw BVcE MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @ 23 °C SVcis * Ic ma T.1 °C hfe-heF: * ® Ic ma fhfb me Ge db leo (ma) @ Vre GE No.

2N472 NPN-GD 200 45 I75A 16T 2N335 3

2N472A PNP-A 200 45 100S 18T 8.00 50 2N335 3
2N473 NPN-GD 200 15 175A 30T 11.0 2N333 3
2N474 NPN-GD 200 30 I75A 30T 11.0 2N333 3
2N474A NPN-GD 200 30 175A SOT 11.0 2N333 3
2N475 NPN-GD 200 45 175A 30T 11.0 2N333 3
2N475A NPN 200 45 200S 35T 8.00 50 2N533 3
2N478 NPN-GD 200 15 175A 60T 11.0 4C30 3
2N479 NPN-GD 200 30 175A 60T 11.0 4C30 3
2N479A NPN-GD 200 30 175A 80T 2N335 3
2N480 NPN-GD 200 45 175A 60T 11.0 .50 2N335 3
2N480A NPN-GD 200 45 I75A 60T 11.0 2N335 3
2N481 PNP 150 —12 —20 85 50T 1 3T —10 —12 2N395 21
2N482 PNP 150 —12 —20 85 50T 1 3.5T —10 —12 2N395 24
2N483 PN I' 150 —12 —20 85 60T 1 5.5T —10 —12 2N394 24
2N484 PNP 150 —12 —20 85 90T 1 IOT —10 —12 2N394 24
2N485 PNP 150 —12 —10 85 50T 1 7.5T —10 —12 2N394 24
2N486 PNP 150 —12 —10 85 100T 1 12T —10 —12 2N394 24
2N489 Si Uni SEE G-E SPECIFICATIONS SECTION 2N489 31
2N489A Si Uni SEE G-E SPECIFICATIONS SECTION 2N489A 31
2N489B Si Uni SEE G-E SPECIFICATIONS SECTION 2N489B 31
2N490 Si Uni SEE G-E SPECIFICATIONS SECTION 2/%4,490 31
2N490A Si Uni SEE G-E SPECIFICATIONS SECTION 2N490A 31
2N49013 Si Uni SEE G-E SPECIFICATIONS SECTION 2N490B 31
2N491 Si Uni SEE G-E SPECIFICATIONS SECTION 2N491 31
2N491A Si Uni SEE G-E SPECIFICATIONS SECTION 2N491A 31
2N491I1 Si Uni SEE G-E SPECIFICATIONS SECTION 2N491B 31
2N492 Si Uni SEE G-E SPECIFICATIONS SECTION 2N492 31
2N492A Si Uni SEE G-E SPECIFICATIONS SECTION 2N492A 31

SNOIINDIAIDMIS
2N49211 Si Uni SEE G-E SPECIFICATIONS SECTION 2N492B 31
2N493 Si Uni SEE G-E SPECIFICATIONS SECTION 2N493 31
2N493A Si Uni SEE G-E SPECIFICATIONS SECTION 2N493A 31
2N4935 Si Uni SEE G-E SPECIFICATIONS SECTION 2N4935 31
2N494 Si Uni SEE G-E Sl'ECIFICATIONS SECTION 2N494 31
2N494A Si Uni SEE G-E SPECIFICATIONS SECTION 2N494A 31
2N494B Si Uni SEE G-E SPECIFICATIONS SECTION 2N4945 31
2N495 PNP 150 —25 —50 140 9 I 8 fo• —.1 —10
2N496 PNP 150 —10 —50 140 9 1 8 f.. —.1 —10
2N497 NPN Si AF 4W 60 500 200 12* 200 10 30 2N497 24
2N497A NPN Si AF 5W 60 500 200 12* 200 10 30 2N497A 24
2N498 NPN Si AF 4W 100 500 200 12* 200 10 30 2N498 24

6L
2N498A NPN Si AF 5W 100 500 200 12* 200 10 30 2N498A 24
E

61
MAXIMUM RATINGS ELECTRICAL PARAMETERS

SNOLLVDIMMS
JEDEC Pc mw BVce MIN. MIN. MIN. MAX. Closest Dwg.
No. TYlle Use I& 25 °C BVce* lc ma T.1 °C hfe-hFe* @ lc me fhfb mc G , db Ico (ma) @ Vce GE No.

2N499 PNP 30 @ 45°C —18 — 50 85 6 2 10 100 — 30

25500 PN I' 50 @ 45°C —15 85 100 — 20
25501 PNP 25 @ 45°C _15* — 50 85 20 —10 ' 100 —15
25501A PN1' 25 @ 45°C _15* — 50 100 20° —10 8 25 —15
25502 PNI' 25 @ 4I°C —20 85 9 2 200 a —100 —20
25502A MP 25 @ 45*c —30* 100 9 2 100 — 30
25503 l'51' 25 @ 11°C —20 — 50 85 9 2 100 11 —100 —20
25505 P51' 125 40 250 853 hOT 8.00 25396 24
25506 P51' 50 — 40* —100 85 25 — 10 .6 —15 —30 25320. 25413 3.24
25507 NPN 50 40 100 85 25 10 .6 15 30
25508 PNI' AF Out 140 —16 — 100 85 125T* —20 3.5T —16 —16 25508 24
25509 PN I' 225 —30° — 40 100 .960, 10 750T —5 — 20
25514 PN1' 110W — 10 —25A 95 12° —25 —2.0 —20
25514A PNP 80W — 60 —25A 95 12* —25 2.0 — 30
2551411 P51' 80W —80 —25A 95 12* —25 7.0T —2.0 —40
25515 NPN 50 18 10 75 4 1 2 23 50 18 25293 22
25516 NPN 50 18 10 75 4 1 2 25 50 18 25293 22
25517 NPN 50 18 10 75 4 1 2 27 50 18 251121 22
25519 l'51' 100 —15 85 15 1 .5 —2 —5 2N394 24
25519A NPN-A 150 25 100S 35T* .50 25 25394 24
25520 PNP 100 —12 85 20 1 3 —2 —5 25394 24
25520A PN P-A 150 25 100S LOOT* 3.00 25 25394 24
25521 PNP 100 — 10 85 35 1 a —2 —5 25397 24
25521A PN P-A 150 25 100S 150T* 8.00 25 25397
25522 P51' 100 —8 85 60 1 15 —2 —5
25523 PNP 100 —6 85 80 1 21 —2 —5
25524 PNP AF 225 —30 — 500 100 16 —1 .8 —10 — 30 25524 24
25525 PN1' AF 225 — 30 — 500 100 30 —1 1 —10 — 30 25525 24
25526 PN P AF 225 —30 — 500 100 44 —1 1.3 —10 — 30 25526 24
25527 P51' AF 225 —30 — 500 100 60 —1 1.5 —10 —30 25527 24
25528 PN I' 2.5W — 40 100 20* —0.5 —15 —30
25529 PNP-NPN 100 15 85 15 1 2.5T 5 5
25530 PNP-NPN 100 15 85 20 1 3T 5 5 25394 24
25531 PNP-NPN 100 15 85 25 1 3.5T 5 5 25395 24
25532 PNP-NPN 100 15 85 30 1 4T 5 5 25395 24
25533 PNP-NPN 100 15 85 35 1 4.5T 5 5
25534 PNP 25 @ 50°C — 50 —25 65 35 —1 —15 — SO 251057, 251924 23,24
25535 PN P 50 —20 —20 85 35 —1 2T —10 —12 251415, 25 I175A 24, 24
25535A PN P 50 —20 —20 85 35 —I 2T —10 —12 251415, 251175A 24, 24
25535B PNP 50 — 20 — 20 85 35 —1 2T —10 —12 25508, 251175A 24,24
25536 PNP 50 — 20 — 30 85 100* — 30 1 —10 —12 25508 24
25538 PNP IOW @ 70°C _80* 95 40 2A 8T Ke — 20 ma — 80
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pc mw BV.-E MIN. MIN. PAIN. MAX. Closest Dwg.

No. Type Use @ 25 °C BV...* I. ma T.I °C hfe-hre * @ k ma fl.fh me Ge db lc° (ma) @ Vea GE No.

2N538A PNP 10W r 70°C —80* 95 40 2A IT Kc —20 ma —80

2N539 PNP 10W @ 70°C —80* 95 27 2A 7T Kc —20 ma —80
2N539A PNP 10W Olt 70°C —80 95 27 2A 7T Kc —20 ma —80
2N540 PNP 10W @ 70°C —80 95 18 2A 6T Kc —20 —80
2N540A PNP 10W @ 70 °C —80 95 18 • 2A 6T Kc —20 —80
2N544 PNP 80 —24* —10 85 60T 1 30T 30.4 —16 —12
2N545 NPN-GD 5000 60 175A 25T* 4.00 2N497A 24
2N546 NPN-GD 5000 30 175A 25T* 4.00 2N497A 24
2N547 NPN-GD 5000 60 175A 35T* 4.00 2N656A 24
2N548 NPN-GD 5000 30 175A 35T* 4.00 2N656A 24
2N549 NPN-GD 5000 60 175A 35T* 4.00 2N656A 24
2N550 NPN-GD 5000 30 175A 35T* 4.00 2N656A 24
2N551 NPN-GD 5000 60 175A 30T* 4.00 2N656A 24
2N552 NPN-GD 5000 30 175A 30T* 4.00 2N656A 24
2N553 PNP 12W 71°C —80* —4A 95 40 —.5A 20 Kc —2 ma —60
2N554 PNP 10W @ 80 °C —40* —3A 90 30T* —.5A 8T Kc 20 —50T —2
2N555 PNP 10W @ 80 °C —30 —3A 90 20 —.5A 5 Kc 34T —7 ma —30
2N556 NPN 100 25* 200 85 35* 1
2N557 NPN 100 20* 200 85 20* 1
2N558 NPN 100 15* 200 75 60* 1
2N559 PNP 150 —15 —50 100 25* 10 —50 —5 @ 65°C
2N560 NPN .50 20* —100 .10 —20 2N1613 3
2N561 1'NP 50W —50 —5A 100 65T —1A .5 24.6 —500 —30
2N563 PNP 150 —25 —300 85 10* 1 .8T —5 —10 2N44 23
2N564 PNP 120 —25 —300 85 10* 1 .8T —5 —10 2N524 24
2N565 l'NP 150 —25 —300 85 30* I IT —5 2N43
—10 23
2N566 PNP 120 —25 —300 85 30* 1 1T —5 —10 2N525 24
2N567 PNP 150 —25 —300 85 50* 1 1.5T —5 —10 2N43. 2N526 23,24
2N568 PNP 120 —25 —300 85 50* 1 1.5T —5 2N526
—10 24
2N569 l'NP 150 —20 —300 85 70* 1 2T —5 —10 2N241A, 2N1175 23.24
2N570 PNP 120 —20 —300 85 70* 1 2T —5 —10 2N527, 2N1415 23,24
2N571 PNP 150 —10 —300 85 100* 1 3T —5 —10 2N508 24
2N572 PNP 120 —10 —300 85 100* 1 3T —5 —10 2N508 24
2N574 PNP 25W @ 75°C —60* —15A 95 10* —10A 6T Kc —7 ma —60
2N574A PNP 25W @ 75°C —80* —15A 95 10* —10A 6T Kc —20 ma —80
2N575 PNP 25W @ 75°C —60* —15A 95 19* —10A 5T Kc —7 ma —60
2N575A PNP 25W @ 75°C —80* —15A 95 19* —10A 5T Kc —20 ma —80
2N576 NPN 200 20 400 100 80T* 30 5T 20 20
2N576A NPN 200 20 400 100 20* 400 5T 40 40
2N578 PNP 120 —14 —400 85 10* 1 3 —5 —12 2N394 24

E
2N579 PNP 120 —14 —400 85 20* 1 5 —5 —12 2N396 24
2N580 l'NP 120 —14 —400 85 30* 1 10 —5 —12 2N397 24
 61
MAXIMUM RATINGS ELECTRICAL PARAMETERS

SNOIIVDIAIDadS
JEDEC Pc mw BV. i MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use ® 25 °C BV. a* lc ma T.3 °C hfe-hrE ° ® lc ma %II mc Ge db 'co (no) @ VCB GE No.

80 -15 -100 85 20* -20 4 -6 -6 2N394 24

2N581 PNP
120 -14 -100 85 40* -20 11 -5 -12 2N397 24
2N582 PNP
150 -15 -200 85 20* -20 t -6 -6 2N394 24
2N583 PNP
120 -14 -100 85 40* -20 14 -5 -12 2N397 24
2N584 l'NP
2N585 NPN 120 24 200 85 20* 20 3 8 12
PNP 250 -45* -250 85 35T* -250 -16 -45 2N525, 2NI925 24.24
2N586
2N587 NPN 150 20 200 20* 200 50 40
2N588 PNP 30 ® 45°C -15 -50 85 15 -15
2N591 PNP 50 -32 -20 100 70T 2 .7T 4IT -6.5 -10 2N324. 2N526 3,24
2N592 PNP 125 -20 85 20* 1 .4T -5 -5 2N1414 24
2N593 PNP 125 -30 85 30* .5 .6T -5 -5 2NI414 24
2N594 NPN 100 20 85 20* 1 1.5 5 5
2N595 NPN 100 15 85 35* 1 3 5 5
2N596 NPN 100 10 85 50* I 5 5 5
2N597 PNP 250 -40 -400 100 40* -100 3 -25 -45 2N526, 2N 527 24, 24
2N598 PNP 250 -20 -400 100 50* -100 5 -25 -30
2N599 PNP 250 -20 - 400 100 100* -100 12 25 -30 2N508 24
2N600 PNP 750 -20 - 400 100 50* -100 5 -25 -30
2N601 PNP 0.75 -20 -400 100 2.5 3 12 25 -30
PNP 120 -20 85 20* .5 -8 -10 2N395 24
2N602
PNP 120 -20 85 30* .5 -8 -10 2N396 24
2N603
2N604 PNP 120 -20 85 40* .5 -8 -10 2N397 24
2N605 PNP 120 -15 85 40T -1 20 -10 -12 2N394 24
2N606 PNP 120 -15 85 60T -I 25 -10 -12 2N395 24

2N607 PNP 120 -15 85 80T -1 30 -10 -12 2N396 24

2N608 PNP 120 -15 85 120T -1 35 -10 -12 2N396 24
PNP 180 -20 -200 85 90T* 100 30T -25 -20 2N32I, 2N324 3, 3
2N609
2N610 PNP 180 -20 -200 85 65T* 100 28T -25 -20 2N320, 2N323 3, 3
2N611 PNP 180 -20 -200 85 45T* 100 26T -25 -20 2N320, 2N322 3, 3
2N612 PNP 180 -20 -150 85 .96aT 1 .6T 37 -25 -20 2N319, 2N1098 3.24
2N613 PNP 180 -20 -200 85 .97aT 1 .85T 32 -25 -20 2N320, 2NI097 3,24
2N6I4 PNP 125 -15 -150 85 4.5T .5 3T 26T -6 -20 2N395 24
2N615 PNP 125 -15 -150 85 7.5T .5 5T 34T -6 -20 2N395 24
2N616 PNP 125 -12 -150 85 25T .5 9T 20T -6 -15 2N394 24
2N617 PNP 125 -12 -150 85 15T .5 7.5T 30T 6 -15 2N394 24
2N6I8 PNP 45W -80* -3A 90 60* -1A 5 Ke -3 ma -60
2N622 NPN 400 50* 50 160 25T* .5 .3 34T .1 30
2N624 PNP 100 -20 -10 100 20 2 12.5 20T -30 -30
2N625 NPN 2.5W 30 100 30* 50 100 -40
2N631 PNP 170 -20 -50 85 150T 10 1.2'1' 35T -25 -20 2N508 24
2N632 PNP 150 -24 -50 85 100T 10 IT 25T -25 -20 2N324. 2N1175 3,24
2N633 PNP 150 -30 -50 85 60T 10 .8T 25T -25 -20 2N323. 2NI415 3,24
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

MIN. MIN. MAX. Closest Dwg.

Pc mw BVce MIN.
JEDEC GE No.
lc ma TeC hfe-hFe * @ I, ma fhfb one Ge db Ico (on) Li/ Vca
No. Use @ 25 °C 131/ce *
Type

20 300 85 15* 200 5 5

2N634 NPN Sw 150 25
20 300 85 40* 10 , 6
2N634A NPN Sw 150 5
20 300 85 25* 200 10 5
2N635 NPN Sw 150
300 85 80* 10 10 6 25
2N635A NPN Sw 150 20
300 85 35* 200 15 5 5
2N636 NPN Sw 150 20
300 85 100* 10 15 6 25
2N636A NPN Sw 150 15
—5A 100 30* —3A 1ma —25
2N637 PNP 25W —40
—5A 100 30* —3A 5 ma —60
2N637A PNP 25W —70
—5A 100 30* —3A 5 ma —60
2N637B PNP 25W —80
—5A 100 20* —3A 1 ma —25
2N638 PNP 25W —40
—70 —5A 100 20* —3A 5 ma —60
2N638A PNP 25W —60
—80 —5A 100 20* —3A 5 ma
2N638B PNP 25W
—5A 100 15* —3A 1 ma —25
2N639 PNP 25W —40
—5A 100 15* —3A 5 ma —60
2N639A PNP 25W —70
—5A 100 15* — 3A 5 ma —60
2N639B PNP 25W —80
—34* —10 85 .984aT —1 42T 28T —5 —12
2N640 PNP 80 —12
—34* —10 85 .984aT —1 42T 28T —7
2N641 PNP 80 —12
—34* —10 85 .984aT —1 42T 28T —7
2N642 PNP 80
85 20* —5 20 —10 —7
2N643 PNP 120 —29 —100
—100 85 20* —5 40 —10 —7
2N644 PNP 120 —29
—100 85 20* —5 60 —10 —7
2N645 PNP 120 —29
50 85 70T* —50 54T 14 25
2N647 NPN 100 25
85 65T* —50 54T 14 12
2N649 NPN 100 18 50 24
100J 40T 2.00 42 15 2N1924
2N650 PNP-A 200 45 250
.75 50 2N1924 24
PNP-A. 200 45 500 100C 24
2N650A 75T 2.50 44 15 2N1925
PNP-A 200 45 250 100J 24
2N651 3.00 46 15 2NI925
PNP-A 200 45 250 100J 160T
2N652 2NI926 24
45 500 100C 160T 1.25 50
2N652A PNP-A 200 2N1926 24
30 250 100J 40T 2.00 42 15
2N653 PNP-A 200 15 2N1414 24
30 250 100J 75T 2.50 44
2N654 PNP-A 200
3.50 46 15 2N1175 24
PNP-A 200 30 250 100J 160T
2N655 200 10 30 2N656, 2N508 24,24
NPN Si AF 4W 60 500 200 30*
2N656 200 10 30 2N656A 24
Si AF 5W 60 500 200 30*
2N656A NPN 24
200 30* 200 10 30 2N657
2N657 NPN Si AF 4W 100 500 24
30* 200 10 30 2N657A
2N657A NPN Si AF 5W 100 500 200 24
25* —1 2.5 —6 —12 2N394
2N658 PNP 175 —16 —1A 85
—1 5.0 —25 —25 2N396 24
PNP 175 —14 —1A 85 40*
2N659 —1 10 —25 —25 2N397 24
PNP 175 —11 —1A 85 60*
2N660 —1 15 —25 —25
PNP 175 —9 —1A 85 80*
2N661 2N396 24
85 30* —1 4 —25 —25
2N662 PNP 175 —11 —1A
—80* 5A (ta) 95 40* —.5A 20 Ke —2 ma —30 (471 °C
2N665 PNP 35W 25
20 85 20* 30 2 25
2N679 NPN 150
 •

61
MAXIMUM RATINGS ELECTRICAL PARAMETERS

SNOLLVDI3ID3dS
JEDEC Pc mw BVce MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @ 25 °C BVce* lc ma T.t eC lite-lwe* @ lc ma filth mc Ge db Ice (µa) @ Vce GE No.

2N680 NPN 150 20 50 85J 35T 14 2N1113 24

2N695 PNP-M 75 15 50 100.1 40T 350
2N696 NPN-PL Sw 600 60* 175J 20* 1.0 30 2N696 3
2N696A NPN-PL Sw 800 60* 200J 45T 150 .10 2N2194A 3
2N697 NPN-PL Sw 600 60* 175J 40* 1.0 30 2N697 3
2N697A NPN-M 800 60* 200 70T 150 .10 2N2193A 3
2N698 NPN-I'L Sw 800 120* 200J 40T* 70.0 .005 75 2N698 3
2N699 NPN-PL Sw 600 120* 1751 40* 2.0 60 2N699 3
2N699A NPN-M 800 120* 200 70T 180 .10 2N1893 3
2N699B NPN-PL 870 120* 2001 80T 120 .01 2N1893 3
2N700 PNP-M 75 25 50 100J IOT 500 23
-2N702 NPN 600 25 50 175 20* 10 0.5 10 2N706 16
2N703 NPN 600 25 50 175 10* 10 . 0.5 10 2N753 16
2N705 1°N I' Sw 300 15* 50 100 25*
2N705A PN P-A 175 40 200 85J 75T 2.00 44
e
2N706 NPN-PEP Sw 300 25* 200 175.I 20 0.5 2N706 16
2N 706A NPN-PEP Sw 300 25* 1751 40T 750 0.5 2N 706A 16
2N706B NPN-M Sw 300 25* 1751 40T* 400 10 2N914 16
2N707 NPN 1W 28 9* 10 3.5 15 2N915 16
2N707A NPN-M 300 70 200 175 30T* 500 5.0 2N915 16
2N708 NPN-PEP Sw 360 40 2001 50T* 500 .025 2N708 16
2N710 PNP-M Sw 300 15 50 100 25*
2N711 PNP-M Sw 150 12 50 100J 30T* 360 22 3.0
2N711A PNP-M Sw 150 15* 100 100S 25* 1.5 5 .
2N711B PNP-M Sw 150 18* 100 100S 30* 1.5 10
2N715 NPN-M 500 50 175J 30T* 150 .01 2N915 16
2N716 NPN-M 500 70 175J 30T* 150 10 2N915 16
2N717 NPN-PL Sw 400 60 175J 40T* 150 1.0 2N717 16
2N718 NPN-PL Sw 400 60 175J 75T* 150 1.0 2N718 16
-2N718A NPN-PL Sw 500 75 200J 70T* 160 .01 2N718A 16
2N719 NPN-I'L Sw 400 120 1751 30T* 180 2.0 2N719 16
2N719A NPN-PL Sw 300 120 200J 30T* 100 .01 2N719A 16
2N720 NPN-PL Sw 400 120 175J 65T* 180 2.0 2N720 16
2N721A NPN-PL Sw 500 120 200J 65T* 110 .01 2N 720A 16
2N725 NPN-M 150 15 50 20T*
2N728 NPN-D 500 30 175 40T* 150 5.0 2N706 16
2N729 NPN-D 500 15 3.0 175 40T* 150 5.0 2N717 16
2N735 NPN-D 1000 80 50 175 40T 40.0 1.0
2N736 NPN-D 1000 80 50 175 50.0 1.0
2N741 PNP-M 150 15 100 100J 25T* 360 22
2N741A PNP-M 150 20 100 100 25T* 360 22 3.0
2N743 NPN-EM 300 25 200 300S 40T* 2N914 16
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pr mw BVcE MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use (i, 25C Mice lo ma TJ °C hfe-hee s @ It ma flab mc Ge db lea (pa) tg VCB GE No.

2N744 M'?-EM 300 25 200 300S 80T* 2N911. 16

2N753 NPN-PEP Sw 300 25 1753 80T 750 2N753 lb
2N754 N PN-M 300 60 50 1753 50T 45.0 1.0 2N915 16
2N758 NPN-M 500 45 100 200A 50T 50.0 2N759 16
2N759 NPN-PL AF 500 45 100 200A 65T 50.0 2N759 16
2N760 NPN-PL AF 500 45 100 200A 150T 50.0 2N760 16
2N761 NPN-M 500 45 100 200A 35T* 50.0 2N759 16
2N762 N PN-M 500 45 100 200A 70T 5 50.0 2N759 16
2N768 PN P-M 13 35 12 100 100 40T* 175 25
2N769 l'N P-M 35 12 100 1003 55T* 900 3.0
2N779 l'NP-MD 60 15 50 100 90T* 480 25 2N964 16
2N779A PNP-MD 60 15 100 100 60T* 450 3.0 2N994 16
2N780 NPN-M 300 45 1753 20T 30.0 2N760 16
2N78I PNP-EM 150 15 200 100 25T 3.0 2N781 16
2N782 PN P-EM 150 12 200 100 20T 3.0 2N782 16
2N783 NPN-EM 300 40 200 175 40T .25 2N914 16
2N784 NPN-EM 300 30 200 175 25T .25 2N914 16
2N796 PNP-M 150 13 100 85A 75T* 80.0 3.0
2N815 NPN-FA 75 25 200 80T* 8.00 14 10
2N816 NPN-FA 75 25 200 100J 80T* 8.00 14 10
2N818 NPN-FA 75 30 400 85J 25T 2.50 10
2N819 NPN-FA 75 30 400 853 30T 5.00 10
2N820 NPN-FA 75 30 400 85J 30T 5.00 10
2N821 NPN-FA 75 30 400 85J 70T 5 10.0 10
2N822 NPN 75 30 400 85J 70T* 10.0 10
2N823 NPN 75 25 400 85J 40T 12.0 5.0
2N824 NPN 75 25 400 853 40T 12.0 5.0
2N828 PNP-D 150 15 200 150S 40T* 400 3.0
2N834 NPN-PEP Sw 300 40 200 1753 40T* 500 .50 2N834 16

SNOLLVDIAIDadS
2N835 NPN-M 300 25 200 175 40T* 450 .50 2N834 16
2N839 NPN-M :100 45 50 1753 35T 30.0 1.0 2N759 16
2N840 NPN-M 300 45 50 175 70T 30.0 1.0 2N759 16
2N841 NPN-M 300 45 50 175 140T 40.0 1.0 2N760 16
2N844 NPN-M 300 60 50 175 80T* 50.0 14 1.0 2N718A 16
2N845 NPN-M 300 100 50 175 80T* 50.0 14 1.0 2N720A 16
2N846 PNP-MD 60 15 50 100$ 35T* 450 25
2N849 NPN-M 450 25 175J 40T* 10 2N706 16
2N850 NPN-M 450 25 1753 80T* 10 2N753 16
-2N870 NPN-PL 500 100 2003 70T* 110 .01
2N871 NPN 500 100 2003 120T* 130 .01 2N871 16
2N909 NPN-D 400 60 I75J 55T 160 1.0 2N956 16

6L
2N910 NPN-PL 500 100 2003 100T 60.0 .025
 61.
MAXIMUM RATINGS ELECTRICAL PARAMETERS

SNOLINDMIDadS
JEDEC Pc mw BVce MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @ 25 °C Mice lc ma T.1 °C hfe-hrE" @ k ma fhfb mc Ge db !co (sa) @ Ven GE No.

-2N911 NPN-PL 500 100 200J 50T 50.0 .025

2N9I2 NPN-PL 500 100 200J 30T 40.0 .025
2N9I4 NPN-PEP Sw 360 40 200J 30T 400 .025 2N9I4 16
2N9I5 NPN-PL AF 360 70 200J 40T 400 .01 2N9I5 16
2N9I6 NPN-PL AF 360 45 200J 50T 500 .01 2N9I6 16
2N929 NPN-PL 300 45 175J 40 30.0 .01 2N9I5 16
2N930 NPN-PL 300 45 175J 100 30.0 .01 2N9I5 16
•2N956 NPN-1'L 500 75 200J 100T 200 .01 2N956 16
2N960 PNP Sw 150 15 100 20T 460
2N96I PNP-EM Sw 150 12 100 20T 460
2N962 PNP-EM Sw 150 12 100 20T 460
2N964 PNP-EM Sw 150 15 100 40T* 460
2N965 ¡'NP-EM Sw 150 12 100 40T* 460
2N966 ¡'NP-EM Sw 150 12 100 40T* 460
2N968 PNP 150 15 1002 20T* 320 3.0
2N969 PNP 150 12 100 20T* 320
2N970 PNP 150 12 100 20T* 320 3.0
2N97I PNP 150 7.0 100 20T* 320 10
2N972 PNP 150 15 100 40T* 320 3.0
2N973 ¡'NP 150 12 100 40T* 320 3.0
2N974 l'NP 150 12 100 40T* 320 3.0
2N975 PNP 150 7.0 100 40T* 320 10
2N994 l'N P Sw 200 15 150 150S 75* 3.0
2NI000 NPN-A 150 40 100S 35T* 7.00 15
2N1008 l'NP-A 167 20 300 752 90T 1.00 2N1415 24
2N 1008A PNP 167 40 300 852 90T 1.00 2N526 24
2N1008B ¡'NP 167 60 300 852 90T 1.00 2NI925 24
2N1009 ¡'NP-A 150 25 20 85A 40T .50 800 2N395 24
2N1010 NPN 20 10 2 85 35T 2T 10 10 2NI694 24
2N1012 NPN-A 150 40 100S 50T 3.00 25
2N1015 NPN 150 @ 45°C 30 75A 150 10* 2A 20T Kc 20 ma 30
2NI015A NPN 150 @ 45°C 60 75A 150 10* 2A 201' Kc 20 ma 60
2N 1015B NPN 150 e 45°C 100 7.5A 150 10* 2A 20T Kc 20 ma 100
2NI015C NPN 150 @ 45°C 150 7.5A 150 10* 2A 20T Kc 20 ma 150
2N1015D NPN 150 @ 45°C 200 7.5A 150 10* 2A 20T Kc 20 ma 200
2N10I5E NPN 150 (445°C 250 7.5A 150 10* 2A 20T Kc 20 ma 250
2NI015F NPN 150 @ 45°C 300 7.5A 150 10* 2A 20T Kc 20 ma 300
2N1016 NPN 150 @ 45°C 30 7.5A 150 10* 5A 20T Kc 20 ma 30
2N1016A NPN 150 @ 45°C 60 7.5A 150 10* 5A 20T Kc 20 ma 60
2N10168 NPN 150 @ 45°C 100 7.5A 150 10* 5A 20T Kc 20 ma 100
2N 1016C NPN 150 (445°C 150 7.5A 150 10* 5A 20T Kc 20 ma 150
2N 1016D NPN 150 62/ 45°C 200 7.5A 150 10* 5A 20T Kc 20 ma 200
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

MIN. MIN. MIN. MAX. Closest Dwg.

JEDEC Pc mw BVca
` (4) lc ma
hfe- hrE ' fhfh mc Ge db lc° (µa) @ Vea GE No.
No. Type Use @ 25 °C BVce* tc ma T.r °C I

150 @ 45°C 250 7.5A 150 10* SA 20T Kc 20 ma 250

2N 1016E NPI\ 20 ma 300
150 @ 45°C 300 7.5A 150 10° SA 20T Kc
2N 1016F NPN — 25 — 30
150 —10 — 400 85 70* 1 15
2N1017 PN 1'
50W —l00 —5 95 70T* —IA — 2 ma —100
2N1021 PNP — 2 ma — 120
50W —120 —5 95 70T° —IA
2N1022 PN I' —125 .5
PNP 20W — 40 —SA 95 35° — IA
2N1038
— 60 —3k 95 35* — IA —125 .5
2N1039 PNI' 20W
— 80 —3A 95 35* —1A —125 .5
2NI040 PNP 20W
—100 —3A 95 35° —IA __ -125 .5
2N1041 PNP 20W
—a — 3A 65 70° —0.5A — 1ma — 40
2N1046 PNI' 1SW 7E1 11
80° 500 200 12* 500 IS 30
2NI047 NPN 40W @ 25°C 7E3 ' 11
120* SOO 200 12* 500 IS 30
2N1048 NPN 40W @ 25°C
200 30* 500 15 30 7E2 11
2NI049 NPN 40W @ 25°C 80* 500
200 30* 500 15 30 2N2204 11
2N1050 NPN 40W @ 25°C 120° 500
100 18° —20 .5 —25 —70 2N1614, 2N1924 23.24
2N1056 l'N1' Obsolete 240 — 50 — 300
100 34* — 20 .5 —16 — 45 2N 1057, 2N 1924 23, 24
2NI057 PNP Sw 240 —45 — 300
75 10 I 4 22.5 50 18 2N292 22
2N1058 NPN 50 20 50
IS 100 75 50° 35 10 Kc 25 50 40
2N1059 NPN 180
:10 .5A 175 15* 200 .75 500 60
2N1067 NPN 5W 60
IOW 30 1.5A 175 15° 750 .75 500
2N1068 NPN 1ma 60
50W 45 4A 175 10° 1.5A .5
2N1069 NPN
45 4A 175 10° 1.5A .5 Ima 60
2N1070 NPN 50W 2N1086 22
9 20 85 17* 1 8T 24T 3 5
2N1086 NPN Ose 65 22
9 20 85 17* 1 ST 24T 3 5 2N1086A
2N 1086A NPN Ose 65
85 17° 1 ST 26T 3 5 2NI087 22
2N1087 NPN Ose 65 9 20
15 400 85 50° 20 5 8 12
2N1090 NPN 120
12 400 85 40* 20 10 a 12
2N1091 NPN 120
30 500 175 15° 200 .75 500 60
2N1092 NPN 2W 24
30 250 85J 125T 8.00 6.0 2NI307
2NI093 l'N P-A 150 2N1097 24
—16 — 100 85 55T 1 —16 —16
2N1097 PNI' AF Out 140
85 451' I —16 —16 2N1098 24
2N1098 PNP AF Out 140 —16 — 100
30W 80° 95 35* SA 10 Kc 8 ma — 80
2N1099 PNP 8 ma — 100
30W 100* 95 25* SA 10 Kc
2N1100 PNP
180 15 100 75 25° 35 10 Kc 50 20
2NI101 NPN 50 40
180 25 100 75 25* 35 10 Kc
2N1102 NPN — 10 —12
30 16* 5 85 33 —0.5 40
2N1107 PN 1'
30 16* 5 85 30 —0.5 35 —10 —12
2N1108 PN1' —10 —12
30 16* 5 85 15 —0.5 35
2NI109 PNP —10 —12
30 16* 5 85 26 —0.5 35
2N1I10 PN I'
20* 5 85 22 —0.5 35 —10 —12
2N1111 PNP 30
150 25 200 100J 110T* 10.0 30
2N1114 NPN-A —6 — 20 2N1115, 2N396A 23.24
2N1115 PNP Sw 150 — 20 —125 85 35 — 60 5
 61
MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC

SNOLLVDIAIDadS
Pc mw IMIce MIN. MIN. MIN. MAX. Closest Dwg,
No. Type Use @ 25 °C BVca * le ma re °C hfe-hEE * @ lc ma fhfb me Ge db lco (µa) @ VCB GE No.

2N1115 ,
\ l'NP s, 150 —35 —125 85 35 —60 5 —6 —20 2N1115A, 2N65OA2.1, 21
2N1116 NPN-GO 5000 60 175A 70T* 4.00
2N1117 NPN-GI) 2N656A 24
5000 60 175A 70T* 4.00 2N656A 24
2N1118 PNP 150 —25 —50 140 9 1.0 —25
2N1118A PNP 150 —25 —50 140 15 I 0.1 —10
2NI119 PNP 150 —10 —50 140 6* —15 0.1 —10
2N1121 NPN IN' 65 15 20 85 34* 1 8 Kc 5 15 2N1121 22
2N1122 PNP —25 (§ 45°C —10 —50 85 35 1.0 5 —5
2N1122A PNP —25 (§ 45°C —50 85 35 1.0 5 —5
2N1123 PNP 750 —40 —400 100 40* —100 3 —25 —45
2NI128 PNP-A 150 25 250 85J 120T 1.25 20 2N324 3
2N1I29 PNP-A 150 25 250 851 165T* .75 25 2N508 24
2N1130 PNP-A 150 30 250 851 110T* .75 25 2N1926 24
—2N1I41 PNP 750 100 100 12 —10 750T —5 —15
2N1142 l'NP 750 100 100 10 —10 600T —5 —15
2N1I43 l'NP 750 100 100 3 —10 480T —5 —15
2N1144 PNP AF Out 140 —16 —100 85 55T I —16 —16 2N1144, 2N1097 24,24
2N1I45 l'NP AF Out 140 —16 —100 85 45T 1 —16 —16 2N1145, 2NI098 24,24
2NI149 NPN 150 45* 25 175 —0.9 —1 4T 35T 2 30 2N1276 3
2N1150 NPN 150 45* 25 175 —0.948 —I ST 39T 2 30 2N1277 3
2N1151 NPN 150 45* 25 175 —0.948 —1 8T 39T 2 30 2N1278 3
2N1152 NPN 150 45* 25 175 —0.9735 —1 6T 42T 2 30 2N1278 3
2N1153 NPN 150 45* 25 175 —0.987 —I 7T 42.5T 2 30 2N1279 3
2N1154 NPN 750 50* 60 150 —0.9 —5 30 5 50 2N333 3
2N1155 NPN 750 80* 50 150 —0.9 —5 30 6 80 2N333 3
2N1156 NPN 750 120* 40 150 —0.9 —5 30 8 120
2N1157 l'NP —60* 95 38* —10A —7.0 ma —60
2NI157A l'NP —80* 95 38* —10A —20 ma —80
2NI159 l'NP 20W (4 71°C 80* —65 —65 30* 3A IOT Kc 8 ma —80
2N1160 l'NP 20W @71 °C 80* —65 20* SA IOT Kc 8 ma —80
2N1168 l'NP 45W —50* SA (1E) 95 110T IA IOT Kc 37T —8 rna —50
2N1171 PNP —12 400 85 30* 1 10 5 —12 2N397 24
2N1172 l'NP 40* —65 30 100 34T 0.2 ma —40
2N1175 PNP-A 200 35 200 85J 90T* 4.20 12 2N1175 24
2N1175A PNP-A 200 35 200 851 90T* 4.20 12 2N11.75A 24
2N1177 PNP 80 —30* —10 71 100 110 —12 —12
2N1178 PNP 80 —30* —10 71 40 140 —12 —12
2N1179 PNP 80 —30* —10 71 80 140 —12 —12
2N1180 l'NP 80 —30* —10 71 80 100 —12 —12
2NI183 PNP 1W —20 —3.0 100 20* —400 500 Kc —250 —250 —45
2N1183A PNP 1W —30 —3.0 100 20* —400 500 Kc —250 —80
2N118311 PNP 1W —40 —3.0 100 20* —400 500 Kc —250 —80
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pc mw BVce MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @ 25 °C BVce* lc ma T.I °C hfe-her.* 1, ma fhfb mc db Ico (go) (q. VCR' GE No.

2N1Ill4 PNP 1W -20 -3.0 100 40* -400 500 Kc -250 -45
2N1184A PNP IW -30 -3.0 100 40* -400 $OO Kc -250 -BO
2N118411 PNP 1W -40 -3.0 100 40* -400 500 Kc -250 -BO
¡'NP 200 60 100.1 SOT 1.50 217
2NI186
2NI187 PNP 200 60 100.1 85T 2.00 2rl. 2t
2NI188 PNP 200 60 100.1 155T 2.50 21,.192f, 21
2NI191 l'NP-A 175 40 200 85J 40T 1.50 12 2N1414 24
2N 1192 PNP-A 175 40 200 85.1 75T 2.00 .11 2N1175 24
2N1193 l'NP-A 175 40 200 85J 160T 2.50 16 2N508 24
2N1198 NPN Sw 65 25 75 85 17* 8 5 1.5 15 2NI198, 2NI67 22,22
2N1199 NPN 100 20 100 150 12* 20 0.7 -10
2N1202 l'N1' -60 95 40* -0.5A -2.0 ma -80
2N1203 PN1' -70 95 25* -2A -2.0 ma -120
2N1213 PNP 75 -25 -100 71 -5 -12
2N12I4 l'N I' 75 -25 -100 71 -5 -12
2N1215 PN 75 -25 -100 71 --S -12
2N1216 PNP 75 -25 -100 71 -5 -12
2N1217 NPN 75 20 25 40* .5 6.0 29 15 2N1217 22
2N1224 PNP 120 -40 -10 100 20 -1.5 30 15 -12 -12
2N1225 ¡'NI' 120 -40 -10 100 20 -1.5 100 15 -12 -12
2N1226 PNI" 120 -60 -10 100 20 -1.5 30 15 -12 -12
2NI228 PNP 400 -15 160 14 I.2T -0.1 -12
2N1229 ¡'NP 400 -15 160 28 I.2T -0.1 -12
2NI230 PNP 400 -35 160 14 1.21' -0.1 -30
2NI231 l'NP 400 -35 160 28 I.2T -0.1 -30
2NI232 PNP 400 -6o 160 It 1.0T -0.1 -50
2N1233 l'NP 400 -6o 160 28 1.0T -0.1 -50
2N1234 l'N1' 400 -110 160 14 8T -0.1 -90
1W free air -15 160 14 1.2'1' -0.1 -12

6L smouvaialaaas
2NI238 PN1'
2NI239 l'N I' 1W free air -15 160 28 1.2T -0.1 -12
2NI240 PN IW free air -35 160 14 1.2T -0.1 -30
2NI241 l'N I' 1W free air -35 160 28 1.21' -0.1 -30
2NI242 PNP 1W free air -60 160 It 1.0T -0.1 -50
2NI243 PNP 1W free air -60 160 28 1.0T -0.1 -50
2NI244 PNP 1W free air -110 160 14 .8T -0.1 -90
2NI247 NPN 200 6.0 175A 25T 5.00
2NI248 NPN 200 6.0 175A 20T 5.00
2NI251 NPN 150 15 100 85 70 7.5 50 20
2NI252 NPN 2W 20 175 15* 150 10 20
2NI253 NPN 2W 20 175 40* 150 10 20
0, 2NI261 PNP -45 95 20*
2NI262 PNP -45 95 30* -2.0 -60
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pc mw BVcs MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @ 25 °C BVcs* lc ma TJ °C hre-hes* @ lc ma ihrb me G, db leo ('m) ® Ws GE No.

2N1263 PM' —45 95 45* -20 — 60

2N1264 PN I' 50 — 20* 50 75 15 1.5 50 — 20
2N1265 ¡'NP 50 —l0* 100 85 25 1 600 100 2N1097 24
2N1266 l'N1' 80 — 10* 85 10 1 100 — 10 2N1098 24
2N1273 PNP-A 150 15 150 85J 50T 2.00 2N1097 24
2N1274 ¡'NP-A 150 25 150 85J 50T 2.00 2N1414 24
2NI276 NPN Si AF 150 30 25 150 10T 10 15 37E 1 30 2N1276 3
2N1277 NPN Si AF 150 30 25 150 20T 10 15 391' 1 30 2N1277 3
2N1278 N PN Si AF 150 30 25 150 33T 10 15 UT 1 30 2NI278 3
2N 1279 N l'N Si AF 150 30 25 150 80T 10 15 i-, I I 30 2N1279 3
2N1280 PNP 200 16 400 85 40 — 20 5 —10 — 10 2N396 24
2N1281 PNP 200 12 400 85 60 — 20 7 —10 —10 2N396 24
2N1282 PN I' 200 6 400 85 70 — 20 10 —10 —10 2N397 24
2N1284 PNI 1 150 15 400 85 30 —10 5 —6 —20 2N 396 24
2N1287 PNP 165 20* 300 85 40 1.00 10 2N526 24
2N 1287A l'Nl' 165 20* 300 85 40 1.00 10 2N527 24
2N1288 NPN Obsolete 75 5 50 85 50* 10 40 5 5
2N1289 NPN Obsolete 75 .15 50 85 50* 10 40 5 15
2N1291 ¡'NI' 20W 30 3 85 40* 0.5 5 —2
2N1293 ¡'NP 20W 60 3 85 40* 0.5 5 —2
2N1295 N l'N 20W 80 3 85 40* 0.5 5 —2
2N1297 PNP 20W 100 3 85 40* 0.5 5 —2
2N1299 N PN 150 20 200 100 35* 50 4.0 100 40
2N 1300 ¡'NI' 150 — 12 —100 85 50 — 10 —3
2N1301 ¡'NP 150 —12 —100 85 50 —10 —3
2N1302 NPN 150 25* 300 100 50 3.00 6.0
2N1303 l'NP 150 30* 300 100 50 3.00 6.0 2N1303 24
2N1304 NPN Sw 300 20 300 100 40* 10 5 6 25
2N1305 ¡'NI' 150 30* 300 100 70 5.00 6.0 2N1305 24
2N1306 NPN Sw 300 15 300 100 60* 10 10 6 25
2N1307 l'N 1' 150 30* 300 100 100 10.0 6.0 2N1307 24
2N1308 NPN Sw 300 15 300 100 80* 10 15 6 25
2N1309 ¡'NP 150 30* 300 100 150 15.0 6.0 2NI309 24
2N1310 NPN 120 90 20* 5 1.5r 7 5 2N1510 22
2NI313 ¡'NI' 180 —15 400 100 40* 6 2.5 —0.5 2N396 24
2N1316 l'NP 200 15 400 85 50* 10 —5 —12 2N397 24
2N1317 l'NP 200 12 400 85 45* 10 —6 —12 2N397 24
2N1318 PNP 200 6 400 85 40* 10 —7 —10 2N397 24
2N1343 l'N P 150 16 400 85 15* — 50 4 —6 —15 2N395 24
2N1344 ¡'NP 150 10 400 85 60* —20 7 10 —15 2N397, 2N396 24,24
2N1345 l'N I' 150 8 400 85 30* — 400 10 —6 —12 2N397 24
2N1346 ¡'NP 150 10 400 85 40* —14 10 —5 —5 2N397 24
 SNOLLVDIanacIS allialfflIIMIIIII1111.1.
MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pc mw BVci": MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use ® 25 °C BVca* lc met TeC hfe-hFe s @ lc ma fhfb mc Ge db lc° (Ata) @ Vcs GE No.

2N1347 PNP 150 12 200 85 30* 10 5 -6 -12 2N396 24

2N1348 l'NP 200 40* 400 85 95* 5.0 10 2N1305 24
2N1352 PNP 150 20 200 85 40* 2.5T -5 - 30 2N526, 2NI925 24,24
2NI353 PNP 200 10 200 85 25* 10 1.5 6 10 2N394, 2N397 24,24
2N1354 l'NP 200 15 200 85 25* 10 3 6 15 2N395 24
2N1355 l'NP 200 20 200 85 30* 10 5 6 20 2N396 24
2N1356 l'NP 200 30* 200 85 80* 8.0 6.0 2N397 24
2N1357 PNP 200 15 200 85 40* 10 10 6 15 2N397 24
2N1358 PNP 80* 95 40* 1.2 100
2N1366 PNP Sw 150 20* 70* 10.0 2N397 24
2N1367 NPN Sw 150 20* 70* 10.0
2N1370 PNP 150 25* 150 100 80* 2.0 2NI415 24
2N1371 l'NP 150 45* 150 100 80 2.0 2N1415 24
2N1372 PNP 210 25* 200 100 45 2.0 2N1415 24
2N1373 PNP 250 45* 200 100 45 2.0 2N1924 24
2N1374 PNP 250 25* 200 100 70 2.0 2N1415 24
2N1375 PNP 250 45* 200 100 70 2.0 2NI925 24
2N1376 l'NP 250 25° 200 100 95 2.0 2NI175 24
2N1377 l'NP 250 45* 200 100 95 2.0 2N1926 24
2N1378 l'NP 250 12* 200 100 200 2.0 2N508 24
2NI379 PNP 250 25* 200 100 200 2.0 2N1175 24
2N1380 PNP 250 12* 200 100 100 2.0 2N1097 24
2N1381 PNP 250 25* 200 100 100 2.0 2N1414 24
2N1382 PNP 200 25* 200 85 80 2.0 2N1415 24
2N1383 l'NP 200 25° 200 85 50 2.0 2NI414 24
2N1389 NPN 250 50* 50 175 25 15 2N696 3
2N1404 PNP 150 25* 300 85 100* 4.00 5.0 2N404 24
2N1408 PNP 150 50* 100 25 2N1924 24
2N1411 PNP 25 @ 45°C -5 -50 85 20* - 50 5 -5
2N14I3 PNP AF Sw 200 -25 -200 85 25* -20 0.8 -12 -30 2N1413 24
2N1414 PNP AF Sw 200 -25 -200 85 34* -20 1.0 -12 -30 2NI414 24
2N1415 PNP AF Sw 200 -25 -200 85 53* -20 1.3 -12 -30 2NI415 24
'2N1420 NPN-M 600 60* 175 140* 250 2N1711 3
2N1420A NPN-PL 800 60* 200 120* 200 2N1711 3
2N1427 PNP 25 @ 45°C -6 -50 85 20* - 50 5 -6
2N1428 PNP 100 -6 -50 140 12* -5 0.1 -6
2N1429 PNP 100 -6 -50 140 12* -5 0.1 -6
2NI431 NPN 180 15 100 75 75* 35 50 20
2N1432 l'NP 100 - 45 10 100 30 2 15 - 45
2N1433 PNP -50 3.5 95 20* 2 5 0.1 -2
2N1434 PNP -50 3.5 95 45* 2 5 0.1 -2

6L
2N1435 PNP -50 3.5 95 30* 2 5 0.1 -2
 61
MAXIMUM RATINGS ELECTRICAL PARAMETERS

SNOLLVDIAIDScIS
JEDEC Pc mw Wee MIN. MIN. MIN. MAX. Closest Dwg,
No. Type Use @ 25 °C BVcie Ic ma T.e °C hfe-hss * 0 Ii: ma f1.11, m c G, db ¡co (i.ns) @ VCB GE No.

2N Ivsr, ¡'NP 50 - 15* - 50 100 20* - 10

27\ I1ln PNP 200 25 400 85 16* 20 .8 10 30 2N 524 2t
2IN It1.7 PNP 200 25 400 85 35* 20 1.5 10 30 2N 525 24
2N1448 PNP 200 25 400 85 50* 20 2 10 30 2N 526 24
2N1449 PNP 200 25 400 85 70* 20 2.5 10 30 2N 527 24
2NI450 PNP 120 30* 100 85 20* 10 10 7
2N1451 PNP 200 45* 400 85 45* 1.50 15 2N1413 24
2N1452 PNP 200 45* 400 85 60* 2.20 15 2N1414 24
2N1471 PNP 200 12* 200 85 160* 5.0 5.0 2N508 24
2N1472 NPN 100 25 100 150 20 10 0.5 10
2N1473 NPN 20 400 75 25* 400 4 100 40
2N1478 PNP 250 - 30* - 400 100 40* -100 3 5 1.5 2N396, 2N1415 24, 24
2N1479 NI'N 4W 60* 1.5 175 15* 200 1.5 60 10 30 2N497A 16
2N1480 NPN 4W 100* 1.5 175 15* 200 1.5 100 10 30 2N497A 16
2NI481 NPN 4W 60* 1.5 175 35* 200 1.5 60 10 30 2N656A 16
2N1482 NPN 4W 100* 1.5 175 35* 200 1.5 100 10 30 2N656A 16
2N1483 NPN 15W 60* 3 175 15* 750 1.25 15 30
2N1484 NPN 15W 100* 3 175 15* 750 1.25 15 30
2NI485 NPN 15W 60* 3 175 35* 750 1.25 15 30
2N1486 NPN 15W 100* 3 175 35* 750 1.25 15 30
2N1487 NPN 60W 60* 6 175 10* 1.5 I 25 30
2N1488 NPN 60W 100* 6 175 10* 1.5 1 25 30
2N1489 NPN 60W 60* 6 175 25* 1.5 I 25 30
2N1490 NPN 60W 100* 6 175 25* 1.5 1 25 30
2N1499 PNP 25 -25* - 50 85 20* -10 5 -5
2N1499A PNP 60 20* 50 100 50* 110 3.0
2N1500 PNP 50 -15* -50 100 20* -50 5 -5
2N1501 PNP -60* 95 25* -2A -2 -60
2N1502 PNP -40* 95 25* -2A - 9 -•40
2N1507 NPN 0.6W 60* 500 175 100* 150 I 30
2N1510 NPN Neon Indicator 75 70 20 85 8* 1 5 75 2N1510 22
2N1514 NPN 2.5 100V 8.0 Amps 175 75* 1000 Kc 25 30 2N1924 24
2N1524 PNP 80 24* 10 85 60* 33.0 16 2N1924 24
2N1525 PNP 80 24* 10 85 60* 33.0 16 2N1925 24
.2N1564 NPN 1200 80* 50 175 70 40 1.0 2N698 3
2N1565 NPN 1200 80'" 50 175 120 50 1.0 2N699 3
2N1566 NPN 1200 80* 50 175 120 50 1.0 2N699 3
2N1566A NPN 600 80 100 200 125 200 .50 2N699 3
21%11572 PNP 600 125 35 2N698 3
2N1573 PNP 600 125 70* 2N699 3
2N1574 PNP 600 125 140* 2N699 3
2N1586 NPN 150 15 25 18 4.0 2N1276 3
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pc mw BVce MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @ 25 °C BVce * lc ma te °C hfe-hee s Co I, ma fi•fl• mc Ge db 'co Wed © Vea GE No.

2N1587 NPN 150 30 25 18 1.0 2N1276 3

2N1588 NPN 150 60 25 18 to 2N332 3
2N1589 NPN 150 15 25 50 6.0 2N1277 3
2N1590 NPN 150 30 25 50 6.0 2N1277 3
2N1591 NPN 150 60 25 50 6.0 2N334 3
2N1592 NPN 150 15 25 140 7.0 2N1279 3
2N1593 NPN 150 30 25 140 7.0 2N1279 3
2N1594 NPN 150 60 25 140 7.0 2N337 3
2N1605 NPN 150 24 100 100 40* 20 4 5 12
2N1605A NPN 200 40 100 100 60* 6.0 10
2N1613 NPN-PL Sw 800 75 200 80* 160 .01 2N1613 3
2N1614 PNP Sw 240 -65* -300 85 18* -20 0.5 -25 -65 251614 23
2N1624 NPN 150 25 100 120* 8.0 10
2N1644 NPN 600 60 175 75* 150 1.0 25697 3
2N1644A NPN 600 60* 175 75* 150 1.0 2N697 3
2N1646 PNP 150 15 100S 20* 3.0
2N1671 l'N Si Uni SEE G-E SPECIFICATIONS SECTION 2N1671 31
2N1671A PN Si Uni SEE G-E SPECIFICATIONS SECTION 2N1671A 31
2N1671B PN Si Uni SEE G-E SPECIFICATIONS SECTION 2N16718 31
251672 NPN 120 40* 50 2.0 25
2N 1672A NPN 120 40* 85 20* 2.0
2N1684 PNP 100 25* 100 100 8.0 20 2N397 21
2N1694 NPN 75 20* 25 85S 30* 9.0 1.5 2N1694 24
2N1700 NPN 5000 60* 1.0 Amp 200 20 1.20 75 2N656A 24
2N1705 PNP 200 18* 400 100 110 4.0 10 2N527 24
251706 PN1' 200 25* 400 100 90 3.0 10 2N527 24
2N1707 PNP 200 30* 400 100 95 3.0 15 25527 24
•2N1711 NPN 800 30* 500 175 35 230 2N1711 3
2N1714 NPN 7.5 90 1.0 Amp 175 16 7D2 10

SNOLINDIAID3dS
251715 NPN 7.5 150 1.0 Amp 175 16 7D4 10
2N1716 NPN 7.5 90 1.0 Amp 175 16 71413 10
2N1717 NPN 7.5 150 1.0 Amp 175 16 7144 10
251718 NoN 7.5 90 1.0 Amp 175 16 7G2
2N1719 NPN 7.5 150 1.0 Amp 175 16 7G4
2N1720 NPN 7.5 90 1.0 Amp 175 16 7G13
2N1721 NPN 7.5 150 1.0 Amp 175 16 7G4
2N1726 PNP 60 20 50 100 120* 150
2N1727 PN1' 60 20 50 100 150* 150
251728 PSI' 60 20 50 100 100* 150
2N1754 PNP 50 13* 100 85 50* 75
251779 NPN 100 25* 100 100 40* 5.0 10

6L
2N1780 NPN 100 25* 100 100 40* 8.0 10
 6E
MAXIMUM RATINGS ELECTRICAL PARAMETERS

SNOIIVDIJIDadS
JEDEC Pc mw BVcE MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @ 25 °C BVcs* lc mo TJ °C hfe-hre * @ k ma fhfb mc Ge db leo (pa) @ VCB GE No.

2N1781 NPN 100 25* 100 100 60* 6.0 20

2N1785 1'N I' 45 10* 50 85 60* 125 10
2N1786 PNP 45 10* 50 85 60* 125 10
2N1787 PN I' 45 15* 50 85 60* 125 10
2N1808 NPN 150 25* 300 100S 60* 4.0 5.0
'
'2N1889
- NPN-PL 800 100* 2001 70* 110 .01
2N1890 NPN-PL 800 100* 2001 120* 130 .01
2N1893 NPN-PI, Sw 800 120* 2001 85* 110 .01 2N1893 .1
2N1924 PN I' AF 225 - 60* - 500 85 30* - 100 1.0 -10 45 2N1924 21
2N1925 PNI' AF 225 _60* -500 85 47* - 100 1.3 -10 45 2N1925 24
2N1926 PN I' ‘1,
' 225 -60' -500 85 65* - 100 1.5 -10 45 2N1926 24
2N1954 PN P 200 60* 1.0 Amp 100J 120 20 2N1926 24
2N1955 PN P 200 60* 1.0 Amp 100J 200 20 2N1926 24
2N1956 PN P 200 60* 1.0 Amp 100J 120 20 2N1926 24
2N1958 NPN 600 60* 500 175 45 .50 2N2194A 3
2N1959 NPN 600 60* 500 175 80 .50 2N2193A 3
2N1960 PNP 150 15* 200 100 25 3.0
2N1961 PN I' 150 12* 200 100 20 3.0
2N1969 PN P 150 30* 400 100 125 10 5.0 2N1307 24
2N1973 NPN 800 100* 200J 100 60 .025
2N1974 NPN 800 100* 200J 50 50 .025
2N1975 NPN 800 100* 2001 30 40 .025
•2N1986 NPN 600 50* 1501 150* 50.0 5.0 2N697 3
2N1987 NPN 600 50* 1501 50* 50.0 5.0 2N696 3
2N1997 1'N l' 250 45* 500 100S 75* 3.0 6.0 2N527 24
2N1998 PN I' 250 35* 500 100S 100* 6.50 6.0 2N527 24
2N2000 PN I' Sw 300 15 1.0A 100S 50* 100 ., 10 30
2N2001 1N1' Sw 300 15 1.0A 100S 100* 100 6 6 15
2N2002 ¡'NI' Ch 250 5 100 200S .01 4.5
2N2003 I'N P Ch 250 5 100 200S .03 4.5
2N2004 l'NP Ch 250 15 100 175S 12 1 .0015 10
2N2005 PNP Ch 250 15 100 200S 1 .05 10
2N2006 PN I' Ch 250 35 100 200S I .02 30
2N2007 PN I' Ch 250 35 100 200S 1 .05 30
2N2008 NPN Pwr 3W 110 500 200J 30* 10 .05 100
2N2009 PNPN Sw 1.0A 150S 3N84 28
2N2010 PN l'N Sw 1.0A 150S 3N 85 28
2N2011 PNPN Sw 1.0A 150S 3N85 28
2N2012 PNPN Sw 1.0A 150S
2N2013 PNPN Sw 1.0A 150S
2N2014 PNPN Sw 1.0A 150S
2N2015 NPN Pwr I 150W 50 10A 200 15* 5A 200 40
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

Pc mw BVcE MIN. MIN. MIN. MAX. Closest Dwg.

JEDEC
2.5 °C BVcs * lc me '
WC hfe.hFE @ Ic me fhb mc Ge db lc° (µa) VCB GE No.
No. Type Use

2N2016 NPN Pwr 150W 65 10A 200 15* 5A 200 40

2N2017 NPN AF SW 60 IA 200 35/20* 10/1A 10 30
2N2020 NPN Pwr 40W 150* 2A 175S 25* 100 100 100 2N21511 I-,
2N2021 NPN l'wr 40W 200* 2A 175S 25* 100 100 100 2N2150 15
2N2022 PNP 150 15* 50 100J 35 3.0
2N2032 NPN Pwr 85W 45 SA 200S 20* 2A 20ma 45
2N2033 N PN l'wr 60 3A 200 20* 500 150 80
2N2034 NPN Pwr 60 3A 200 20* 1A 150 80
2N2035 N PN Pwr 60 3A 200 20* 1.5A 150 80
2N2036 NPN Pwr 60 3A 200 20* 2A 150 80
45 500 200S 12* 200 15 30 2N497 5
2N2038 NPN AF
75 500 200S 12* 200 15 30 2N498 5
2N2039 NPN AF
45 500 200S 30* 200 15 30 2N656 5
2N2040 N l'N AF
75 500 200S 30* 200 15 30 2N657 5
2N2041 NPN AF 24
2N2042 l'N I' 200 105* 50 .50 2N1925
2N2042A 1'N I' 200 105* 200 100 50 .50 25 2N1925 24
2N2043 1'N I' 200 105* 113 .75 2N1926 24
2N2043A PN I' 200 105* 200 100 113 .75 25 2N1926 21
2N2048 I'NP Sw 150 15 100 1008 50* 10 5 5
2N2048A PNP Sw 150 20 100 100S 50* 10 3 15
---2N2049 NPN-PL 800 75* 200J 60* 50 .01
2N2059 PNP Sw 60 10* 50 100S 20* 10 5 5
2N2060 NPN-PL DIST 500 100* 200J 35* .01 .002 80 2N2060 16
2N2061 PN I' Sw 10 3A 85S 10* 500 2kc 2ma 20
2N2062 MI' Sw 10 3A 85S 20* 2A 2kc 2ma 20
2N2063 PNP Sw 15 3A 955 10* 2A 21te 400 2
2N2064 PNP Sw 15 3A 95S 20* 2A 2kc 400 2
2N2065 MP Sw 25 A 958 10* 2A 2kc 400 a
A 95S 20* 2A 2kc 400 2

SNOLINDIAIDadS
2N2066 PN I' Sw 25
2N2067 l'NP AF 25 A 955 20* 500 28 3ma 40
2N2068 PN I' AF 55 IA 95S 20* 500 28 3ma 80
2N2069 ¡'NI' AF 40* 12A 95S 30* SA 1.5kc 15ma 40
2N2070 PNP AF 80* 12A 95S 30* SA 1.5kc 15ma 80
2N2071 ¡'NI' AF 40* 12A 95S 30* SA 1.5kc 15ma 40
2N2072 PNP AF 80* 12A 95S 30* SA 1.5kc 15ma 80
2N2074 l'N PN Sw 200 50 1.0A 150S 3N85 28
2N2083 PN I' MF 100 30* 10 85S 25 12 12
2N2084 PN 1IF 125 20 10 100S 40 8 6
2N2085 NPN 150 33* SOO 100 100 8.0 5.0
600 120* 500 300S 70* 225 2.0 2N2194 3
2N2086 NPN
600 120* SOO 3008 65* 225 2.0 2N2193 3

6L
CP. 2N2087 NPN
40 :SA 2008 15* 1A 25kc 30 30 2N1724 11
2N2101 NPN Pwr
 6L
MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pc mw BVcE

SNOLINDIAIDadS
MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use 4® 25 °C BVco* lc ma WC hte-hEE ° @ lc ma flarb mc G. db leo (iJa) ® We GE No.

2N2102 NPN Sw 5W 65 lA 200J 40* 150 .002 60 2N2193A 5

2N2104 PNP Sw 35 600 200J 25* 150 .010 30
2N2105 PNP Sw 35 600 200J 15* 150 .010 30
2N2106 NI'N-M AF 125 60* 150.1 15MC .20 30 2N2I06 24
2N2107 NPN-M AF 125 60* 150J I5MC .20 30 2N2107 24
2N2108 NPN-M AF 125 60* 150J I5MC .20 30 2N2108 24
2N2I50 NPN l'wr 80 2A 2005 20* IA 10 120 2N2150 15
2N215I NPN Pwr 80 2A 200S 40* IA 10 120 2N2151 15
2N2160 Si Uni SEE G-E SPECIFICATIONS SECTION 2N2I60 31
2N216I NPN Sw 200 35 50 175S 70* 10 .01 45 2NI711 5
2N2162 PNP Ch 150 30 50 140S 3.5 1 .01 10
2N2I63 PNP Ch 150 15 50 140S 3.5 1 .01 4.5
2N2164 PNP Ch 150 8 50 140S 6 1 .02 4.5
2N2165 PNP Ch 150 30 50 140S 2.5 1 .02 10
2N2I66 PNP Ch 150 15 50 140S 2.5 1 .02 4.5
2N2167 PNP Ch 150 8 50 140S 4 1 .02 4.5
2N2168 PNP Sw 60 15 100 100S 50* 10 3 5
2N2I69 PNP 60 15* 100S 85* 3.0
2N2I70 l'NP Sw 60 10 100 100S 20* 10 5 5
2N2I71 PNP AF 500 50* 400 100S 110* 20 10 25 2N508A 24
2N2172 PNP AF 200 15 400 85S 30* 10 6 20 2N524 24
2N2I73 PN I' Sw 240 15 750 100S 30* 200 10 • 10 2N527 24
2N2I75 PNP AF 100 6 50 175S 30* .02 .001 4.5
2N2I76 PNP AF 100 6 50 175S 30* .02 .001 4.5
2N2177 PNP AF 100 6 50 160S 35* .05 .005 4.5
2N2I78 PNP AF 100 6 50 160S 35* .05 .005 4.5
2N2180 PNP Sw 50 6 50 1005 70* 50 1 5
2N2I81 PNP Ch 150 25 50 140S 10* 5 .01 10
2N2I82 PNP Ch 150 25 50 140S 10* 5 .01 10
2N2183 l'N1' Ch 150 15 50 140S 10* 5 .01 10
2N2I84 l'NP Ch 150 15 50 140S 10* .01 10
2N2185 IN I' Ch 150 30 50 140S 1 I .001 10
2N2186 PNP Ch 150 30 59 I49S .001 10
2N2I87 l'N1' Ch 150 30 50 140S .001 10
2N2192 NPN-PEP Sw BOO 60 1.0 Amp 300S 100* 150 10 'Tina 30 2N2I92 3
2N2I92A NPN-PEP Sw 800 60 1.0 Amp 300S 100* 150 10 irlpa 30 2N2I92A 3
2N2193 NPN-PEP Sw 800 80 1.0 Amp 300S 40* 150 10 mpa 30 2N2I93
2N2I93A 3
NPN-PEP Sw 800 80 1.0 Amp 300S 40* 150 10 Tuna 30 2N2I93A
2N219311 3
NPN Sw 800 80* IA 200J 40* 150 .01 60 2N219311 5
2N2194 NPN-PEP Sw 800 60 1.0 Amp 300S 20* 150 10 30 2N2I94
Mel 3
2N2I94A NPN-PEP Sw 800 60 1.0 Amp 300S 20* 150 10 30 2N2I94A
nima 3
2N219411 NPN Sw 800 60* IA 200J 20* 150 .01 30 2N2I9411 5
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

BVce MIN. MIN. MIN. MAX. Closest Dwg.

JEDEC Pc mw
[Wen * ic ma TJ °C hfe-her: * 0 I, ma f1,11. mc Ge db Ico (ma) ® We GE No.
No. Type Use (4125 0 C

45 1.0 Amp 300S 20* 17.11 100 matt 60 2N2195 3

2N2195 NPN-PEP Sw 600
45 1.0 Amp 300S 20* 17,11 100 mart 60 2N2I95A 3
2N2195A NPN-PEP Sw 600
45* IA 200J 20* 1511 .1 30 2N21958 5
2N2I9511 NPN Sw 800
80* 175 10* 15T 75 80 2N2I96 8
2N2I96 NPN Power 2W
80* 175 20* 15T 75 80 2N2I97 8
2N2I97 NPN Power 2W
80 200 200S 35 100 15 80 2N657A 5
2N2I98 NPN Pwr
120* 1753 30* I5MC 50 120 2N220I 8
-2N2201 NPN Power I5W
120* 1753 30* 15MC 50 120 2N2202 9
2N2202 NPN Power 15W
120* 1753 30* I5MC 50 120 2N2203 10
2N2203 NPN Power I5W
120* 1753 30* I5MC 50 120 2N2204 11
2N2204 NPN Power I5W
0.6W 35 500 1753 75 1 —1 —30
2N2303 l'NP IF
25WC 40 3A 200S 20* 300 100 30
2N2304 NPN Pwr
75WC 40 6A 200S 15* 800 200 30
2N2305 NPN Pwr
I3WC 50 2A 175S 12* 350 1ma 75
2N2306 NPN Sw 31
250 SFE G-E SPECIFICATION SECTION 2NI671
2N2307 Si Uni
25WC 80 3A 200S 20* IA 250 100
2N2308 NPN Pwr 5
600 30 500 1753 40 0.2 .005 4 2N2I92
2N2309 NPN AF Out 4
350 60 500 1753 12* 200 .025 60 2N2353
2N2310 NPN AF
100 500 175.1 12* 200 .025 100 2N2364 4
2N2311 NPN AF 350
60 500 1753 30* 200 .025 60 2N2351 4
2N2312 NPN AF 350
100 500 175J 30* 200 .025 100 2N2364 4
2N23I3 NPN AI, 350
60* 500 1753 20* 150 .025 30 2N2352 4
2N23I4 NPN AF 350 4
60* 500 1753 40* 150 .025 30 2N235I
2N2315 NPN AF 350
350 120* 500 175.1 40* 150 .025 60
2N23I6 NPN AF
40* 150 .010 60 2N235I 4
2N2317 NPN AF 350 75* 500 1753
360 30* 200S 40* 20 .050 20
2N2318 NPN Sw
300 30* 200S 40* 20 .050 20
2N2319 NPN Sw
600 30* 200S 40* 20 .050 20
2N2320 NPN Sw 2N2322
E. SILICON CONTROLLED RECTIFIER MANUAL

SNOUNDIAIDadS
2N2322 PNPN Sw REFER TO G.
REFER TO G. E. SILICON CONTROLLED RECTIFIER MANUAL 2N2323
2N2323 PNPN Sw
REFER TO G. E. SILICON CONTROLLED RECTIFIER MANUAL 2N2324
2N2324 PNPN Sw 2N2325
2N2325 l'NI'N Sw REFER TO G. E. SILICON CONTROLLED RECTIFIER MANUAL
REFER TO G. E. SILICON CONTROLLED RECTIFIER MANUAL 2N2326
2N2326 PNPN Sw
REFER TO G. E. SILICON CONTROLLED RECTIFIER MANUAL 2N2327
2N2327 PNPN Sw
REFER TO G. E. SILICON CONTROLLED RECTIFIER MANUAL 2N2328
2N2328 PNPN Sw 2N2329
2N2329 PNI'N Sw REFER TO G. E. SILICON CONTROLLED RECTIFIER MANUAL
800 20 500 I75S 50* 10 .001 4.5
2N2330 NPN Ch 2N929 16
500 20 500 175S 50* 10 .001 4.5
2N233I NPN Ch
150 15* 100 200S —.010 —4.5
2N2332 PNI' Ch
150 15* 100 2005 —.030 —4.5
2N2333 PNI' Ch
.010 4.5

6L
2N2334 PNP Ch 150 30* 100 2005
150 30* 100 2005 .050 4.5
2N2335 PNI' Ch
 MAXIMUM RATINGS ELECTRICAL PARAMETERS
JEDEC
Pc mw BVcE
No. Type Use MIN. MIN. MIN. MAX.
Closest Dwg.
@25 °C BVca* lc ma Ti °C hfe-hEE* @ lc ma fldb mc G,‘ db 'co (jia) Vca
GE No. Cr1
2N2336 UNI' Ch
2N2337 ¡'NI' Ch 150 50* 100 2008
150 50* 100 200S .020 30
2N2338 NUN Pwr .050 30
150WC 40 7.5A 200S 7 6A
2N2339 NI'N
2N2340 NI'Nl'wr 40WC 40 2.5A 200S 6* 1.5A
2N234I NUN l'wr 40 LOA 175S 10* 750
2N104911 6
l'wr 40 1.0A 175S 40* 750 7111 8
2N2342 NUN Pwr 60 1.0A 175S 10* 750 71
7 1
11
113 8
2N2343 NI'N 0

2N2344 PN1IN l'wr

Sw 40 1.0A 175S 40* 750 8
2N2345 PNPN Sw REFER TO G. E. SILICON CONTRO LLED crl
RECTIFIER MANUAL 71113 8
2N2344
2N2346 PNPN Sw REFER TO G. K SILICON CONTROL LED RECTIFIER MANUAL
2N2347 PNPN Sw REFER TO G. E. SILICON CONTROL LED RECTIFIER MANUAL 2N2345
REFER TO G. E. SILICON CONTRO LLED RECTIFIER MANUAL 2N2346
2N2348 PNPN Sw 2N2347
2N2349 NI'N AF 150 REFER TO G. E. SILICON CONTRO LLED RECTIFIER MANUAL

2N2350 NUN Sw 400 24 25 200S 120* 10 1 2N2348

40 lA 200J 75* 10 12
2N235I NI'N Sw 400 50 IA 200J .010 30 2N2350 4
2N2352 NUN Sw 400 40 lA 200J 30*
15* 10 .
010 60 2N235I 4
2N2353 NUN Sw 350 25 lA 200J 20* 10 .
0 10 30 2N2352 4
1
2N2354 NI'N AF 180 20* 150 85S 50 10 0 30 2N2353 4
2N2356 NI'N(2) Ch-Inv 600 25* 500 200J 50* 35 25 10 10
2.5
2N2357 PNP Sw 170WC 30 50A 110S 30* 50 .
010 20 2N2356 32
2N2358 PNP Sw 170WC 60 50A 110S 20A 50 ma 60
2N2359 MP Sw 170WC 80 50A 110S 30* 20A 50 ma 100
2N2360 UNI' VHF 60 20* 50 125J 30* 20A 50 ma 120
10* 2 14 10 10
2N2361 l'N1' VHF 60 20* 50 125J
2N2362 l'NP VHF 60 20* 50 100J 10* 2
14 10 10
2N2363 MP VIF/UHF 75 20 50 100S 10* 2 10 10
2N2364 NUN Sw 400 80 IA 200J 5 12
2N2365 NUN Sw 800 60 175J 40* 150
.010 60 2N2364
2N2368 NI'N Sw 360 15 500 200J 100* 150 4
20* 10 .010 60
2N2369 NI'N 360 15 500 200J .4 20
2N2370 PNP A; 200 15 100 200S 40 10 .4 20
2N237I PNP AF 200 15 100 200S 15* .025 .005 4
2N2372 UNI' AF 20* .025 .005 4
150 15 100 200S 15* .025
2N2373 MP AF .005 4
2N2374 MP AF 150 15 100 200S 15* .025
250 35* 500 100S 100* 100 .005 4
2N2375 PNP AF 5 2 2N508A
2N2376 ¡'NU AF 250 35* 500 »OS 35* 100 24
250 35* 500 1008 35* 100 5 2 2N526
2N2377 ¡'NP IF 24
150 25 50 1408 10* 5 5 2 2N526 24
2N2378 PNP Sw I 25
2N2379 Pwr 150 10 50 140S
150 WC 100* 15A 100S 15* 15 .1 10
2N2380 NUN Sw 25* 5A 8 ma 100
600 40 500 175J
20* 150 4 40
 MAXIMUM RATINGS ELECTRICAL PARAMETERS
-
MIN. MIN. MIN. MAX. Closest Dwg.
JEDEC Pc mw BV(.1.:
Ge db lc() (ma) (41 VCB GE No.
Use é 25 °C BVce s lc ma TJ °C hfe-hre * (9 I, ma fI
dI, m c
No. Type

40* 200 7 5
2N2381 PN l' Sw 300 15 500 100S
500 100S 40* 200 7 5
2N2382 PNP Sw 300 20
5A 200S 20* 1.5A I ma 80
2N2383 NPN 85WC 60
1 ma 80
2N2384 NPN aswc 60 5A 200S 20* 1.5A
.010 45 2N9I5 16
AF 300 45 30 1753 60 1 16
2N2387 NPN .010 45 2N929
AF 300 45 30 1753 150 1
2N2388 NPN 2N911 16
500 2003 30 1 .010 60
2N2389 NPN AF 450 75* 2N910 16
500 2003 50 1 .010 60
2N2390 NPN AF 450 75*
50 1753 15 10 10 25
2N2391 PNP AF 300 20
30 10 10 25
2N2392 PNP AF 300 20 50 1753
300 1753 15 1 1 30
2N2393 ¡'NI' AF 450 35
35 300 1753 25 1 1 30
2N2394 PNP AF 450
300 2003 20* 150 .010 30
2N2395 NPN AF 450 40
40* 150 .010 30
2N2396 NPN AF 450 40 300 200J
200 2003 25* 10 .1 15
2N2397 NPN Sw 300 15
50 1003 10* 2 16 10 10
2N2398 PN1' VHF 60 20*
50 100J 10* 2 16 10 10
2N2399 PNP VHF MXR 60 20*
30* 10 3 5
2N2400 ¡'NI' Sw 150 7 100 100S
50* 10 1.5 5
2N2401 PNP Sw 150 10 100 100S
100 1005 60* 10 1.5 5
2N2402 PNP Sw 150 12 2N2I95 5
20* 600 1 30
2N2403 NPN Sw 1W 60 IA 200S
1 30 2N2I92 5
Sw 1W 60 IA 200S 40* 600
2N2404 NPN .010 100 2N657 5
1W 90 lA 200S 60* 150
2N2405 NPN .3 30
Sw 800 30 800 2003 30* 150
2N2410 NPN
100 2003 20* 10 .010 25
2N24Il PNP Sw 300 20
100 2003 40* 10 .010 25
2N24I2 PNP Sw 300 20 20
18 200 300S 30* 10 .1
2N2413 NPN IF 300
50 5 .025 60 12A8 21
2N24I4 NPN Diff. 600 28 500 2003
20 1003 15 2 5 10
2N24I5 l'NP IF 75 10
20 1003 10 2 5 10
2N24I6 PNP IF 75 10
2N2117 30
Si Uni SEE G. F. SPECIFICATION SECTION 30
2N24I7 SEE G. F. SPECIFICATION SECTION 2N2118
2N24I8 Si Uni 2N2119 30
Si Uni SEE G. E. SPECIFICATION SECTION
2N2419 2N2420 30
Si Uni SEE G. E. SPECIFICATION SECTION
2N2420 20* 2A 5ma 100
PNP l'wr Sw 90WC 100* 5A 100S
2N2423 30* 5 0.1 30
PNP Sw 375 40* 50 160S
2N2424 30
30* 50 160S 25* 5 0.1
2N2425 PNP Sw 375 40
40* 200 100S 35 1 35 20
2N2426 NPN Lo PA 150 0.5 40 2N760 16
IF/RF 500C 40 50 200S 20* .010
2N2427 NPN
100 75S 50* 2 10 10
2N2428 PNP Lo l'wr 500 32*
100 75S 65* 2 10 10
2N2429 PNP Lo Pwr 500 32* 2N527 24
60* 100 10 10
2N2430 PNP Lo l'wr 280 32* 300 75S
 MAXIMUM RATINGS
ELECTRICAL PARAMETERS
JEDEC Pc mw 1111cie MIN. MIN. MIN. MAX. Closest
ce
No. Use Dwg.
Type @ 25 °C BVce* lc ma T.T °C hfe-hre * ® le ma fhfb mc Ge db leo (pci) ® Vea GE No el
2N2431 l'N1' Lo PO 550 10* IA 90S 60* 300 10
2N2432 NPN Ch 300 30 10
100 175 50* 1 0.01
2N2433 NPN Sw 800 25
45 IA 200 30 1
2N2434 .001 60 2N2352
NPN Sw 800 45 IA
2N2435 200 50 1 .001 60
NPN Sw 800 80 500 2N2350
200 30 1 .001 90
2N2436 NPN Sw 800 80 2N2364 4
500
2N2437 NPN Ampl 800
200 50 1 .001 90 2N2350 4 o
75 500 200 18 1
2N2438 NPN Ampl 800 .001 75 2N2353 4
75 500 200 36 1
2N2439 NPN Ampl BOO .001 75 2N2364 4
75 500 200 76 1
2N2440 .001 75 2N2350 4
NPN Sw 800 80 500 200
2N2443 NPN 50 1 .001 90 2N2353
A Pwr 4W 100 2008 30 4
2N2444 PNP 1 .0015 90 2N2243
Arte 85WC 80 10A 1108 50 0.5A 20 ma 80
2N2445 1'N1' Ampl 90WC 50 15A 100S 30 0.5A 20 ma 100
2N2446 PNP Sw 90WC 60 7A 125S 15* 5A 0.5 ma 30
2N2447 PN1' AF 75 24 100 8ss 25 1 10 20 2N1415 24
2N2448 PN1' AF 75 24 100 Bss 25 1 10 20
2N2449 PNI' AF 75 20 2NI415 24
100 85S 50 1 10
2N2450 PNP AF 75 20 20 2N527 24
100 85S 50 I 10
2N2451 PNP 20 2N527 24
Sw 5 50 858 25*
2N2453 N PN (2) 10 5 6
Diff 200 30 50 200 150*
2N2453 A NPN (2) I .005 50 2N2453
Diff 200 50 50 200 150* 21
1 .005 60 2N2453A 21
2N2454 l'NPN SCR, Sw
2N2455 PNP Sw 150 8 200 100S 40* 30 2
2N2456 PNP Sw 150 8 200 100S 40* 30 2
6
2N2459 NPN Si 6
Lo PA 400 60 50 275S 20*
2N2460 NPN Si 1 .002 80 2N2353
Lo PA 400 60 50 275S 35* 4
2N2461 NPN Si 1 .002 80 2N2353
' Lo l'A 400 60 50 2758 70* 4
1 .002 80 2N2350
2N2462 NPN Si Lo PA 400 4
60 50 275S 100* I
2N2463 NPN Si Lo PA 500 .002 80 2N2350 4
60 50 275S 20* 1
2N2464 NPN Si Lo l'A 500 .002 80 2N720 16
60 50 2758 35* 1 .002 80 2N720 16
2N2465 NPN Si Lo PA 500 60 50 275S 70* 1 .002 80
2N2466 NPN Si Lo PA 500 60 50 2N956 16
275S 100* 1 .002 80
2N2467 PNP A Pwr 5W 30 2N956 16
3A 110S 20* IA 10 ma
2N2468 60
PNP A Pwr SW 60 3A 110S 20* IA 10 ma 100
2N2469 PNP A Pwr 5W 100 3A 110S 20* IA 10 ma 200
2N2472 NPN Ampl 1W 100 IA 175S 30* 200 50 120
2N2473 NPN Ampl IW 100 IA 175S
2N2474 30* 200 50 120
PNP Lo PA 250 15 50 160 8*
2N2476 NPN 0.1 .001 30
Sw 600 20 300S 20* 150 0.2 30 2N2195
2N2477 NPN Sw 5
600 20 300S 40* 150
2N2478 NPN Sw 600 0.2 30 2N2195 5
40 500 175 30* 150
2N2479 NPN Sw 600 2 60 2N2193 5
40 500 175 30* 150 4 40 2N2193 5
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

MIN. MIN. MIN. MAX. Closest Dwg.

JEDEC Pc mw BVce
lc ma TJ °C hfe-hFF: * @ It ma flirt) me Ge db lc° (pa) @ Vce GE No.
No. Type Use @ 25 °C BVce s

300 40 500 200 30* 1 .05 60 2N2480 21

2N2480 NPN (2) Diff
300 40 500 200 50* 1 .02 60 2N2480A 21
2N2480A NPN (2) Diff
Sw 360 15 500 300S 40* 10 .05 20
2N2481 NPN
150 12 100 100S 25* 2 5 6 16L3 1
2N2482 NPN IF/RF
AS 360 60 50 200 175* 1 .001 45
2N2483 NPN
AS 360 60 50 200 250* 1 .001 45
2N2484 NPN
VHF/UHF 8.8WC 120 lA 200S 10* 500 500 120
'2N2485 NPN
VHF/UHF 8.8WC 140 IA 200S 10* 500 500 140
2N2486 NPN
Sw 60 10 100 100S 20* 10 3 5
2N2487 PNP
Sw 60 10 100 100S 20* 50 3 5
2N2488 PNI 1
Sw 60 15 100 100S 20* 10 2.5 15
2N2489 PNP
Pwr Sw 170WC 70* 12A 110S 20* 5A .2 ma 2
2N2490 PNP
Pwr Sw 170WC 60* 12A 110S 35* 5A .2 ma 2
2N2491 PNP
Pwr Sw 170WC 80* 12A 110S 25* 5A .2 ma 2
2N2492 PNP
Pwr Sw 170WC 100* 12A 110S 25* 5A .2 ma 2
2N2493 PNP
IF/SF 83 20* 10 758 25* 1 6 6
2N2494 l'NP
IF/RF 83 20* 10 75S 25* 1 6 6
2N2495 PNP
1F/RF 83 20* 10 75S 25* 1 6 6
2N2496 PNP
360 20 200 10* 10 .025 20 2N708 16
2N2501 NI'N Sw
360 80 200 3005 40* 10 .005 100 2N720A 16
2N2509 NPN Sw
Sw 360 65 200 3008 150* 10 .005 80
2N2510 NPN
Sw 360 50 200 300S 240* 10 .005 60
2N2511 NPN
Vi Amp! 150 70* 30 75S 20 1 5 6
2N2512 PNP
A 400 60 100 200S 15* 5 .005 50
2N2514 NPN
60 100 200S 30* 5 .005 50 2N2352 4
2N25I5 NPN A 400
60 100 200S 60* 5 .005 50 2N2352 a
2N2516 NPN A 400
400 80 50 200S 15* 5 .005 80 2N2364
2N2517 NPN Lo PA
Lo PA 400 80 50 200S 30* 5 .005 80 2N2364
2N2518 NPN 2N2364 4
60* 5 .005 80

SNOLLVDMIDUS
2N2519 NPN Lo PA 400 80 50 200S
Lo PA 400 60 100 2005 12.5* 1 .005 45 2N2353 _4
2N2520 NPN
60 100 200S 25* 1 .005 45 2N2353 4
2N2521 NPN Lo PA 400
400 60 100 200S 50* 1 .005 45 2N2353 4
2N2522 NPN Lo PA
Lo PA 400 45 300S 40* .010 .002 45
2N2523 NPN
Lo PA 400 45 300S 100* .010 .002 45
2N2524 NPN
VHF 80 IA 200 10* 350 5 28
—2N2525 NPN
Pwr Sw 85WC 80 10A 110S 20* 3A 150 2
2N2526 PNP
Pwr Sw 85WC 120 10A IIOS 20* 3A 150 2
2N2527 PNP
Pwr Sw 85WC 160 10A 110S 20* 3A 150 2
2N2528 PNP 2N759 16
Lo PA 150 40 25 175S 10 1 .050 30
2N2529 NPN
ao 25 1758 12 1 .050 30 2N759 16
2N2530 NPN Lo PA 150
40 25 175S 20 1 .050 30 2N759 16

61
2N2531 NPN Lo PA 150
40 25 1758 45 1 2N760 16
2N2532 NPN Lo PA 150
 MAXIMUM RATINGS
ELECTRICAL PARAMETERS
JEDEC
Pc row BVce
No. Type Use MIN. MIN. MIN.
25 °C BVcs* lc ma T.I °C MAX. Closest Dwg.
hfe-hm * le ma mc db lc° (µa) 4 Ws
2N2533 NPN Lo PA GE No.
150
2N2534 NPN Lo PA 40 25 1758 20* 10
2N2535 PNP Sw 150 40 .050 30
25 175S 45* 10 2N759 16
lOWC 30 .050 30
2N2536 PNP Sw 3A 100S 40 400 0.25 ma 60 2N759 16
2N2537 NPN Sw lOWC 40 3A 100S 40 400 0.25 ma 80
2N2538 NPN Sw 800 30 800 200 50* 150 0.25 40
800 30 800 200 100* 150 0.25 40 2N2I93 5
2N2539 NPN Sw
2N2540 NPN Sw 500 30 BOO 200 50* 150 2N2I92 5
500 60 0.25 40
2N254I PNP Sw 800 200 100* 150 0.25 40
2N2542 PNPN 2N956 16
215 30 IA 100 60* 50 5 12
2N2543 PNPN SEE G. E SILICON CONTROLLED RECTIFIER MANUAL
2N2544 PNPN SEE G. E. SILICON CONTROLLED RECTIFIER MANUAL 2N2542
2N2545 PNPN SEE G. E. SILICON CONTROLLED RECTIFIER MANUAL 2N2543
2N2546 PNPN SEE G. E. SILICON CONTROLLED RECTIFIER MANUAL 2N2544
2N2547 PNPN SEE G. E. SILICON CONTROLLED RECTIFIER MANUAL 2N2545
2N2548 PNPN SEE G. E. SILICON CONTROLLED RECTIFIER MANUAL 2N2546
2N2549 PNPN SEE G. E. SILICON CONTROLLED RECTIFIER MANUAL
2N2550 PNPN SEE G. E. SILICON CONTROLLED RECTIFIER MANUAL
2N2551 PNP AF 400 SEE G. E. SILICON CONTROLLED RECTIFIER MANUAL
2N2552 PNP Pwr 150 IA 200 15* 100
2N2553 PNP Pwr
20WC ao 3A 100 20* IA
.1
125
100
20
2N2554 PNP Pwr 20WC 60 3A 100 20* IA 125 30
2N2555 PNP Pwr 20WC 80 3A 100 20* lA
2 0WC 100 12 5 40
2N2556 PNP Pwr 3A 100 20* lA 125 50
20WC ao 3A 100 20* IA
2N2557 PNP Pwr 125 20
2 0WC 60
2N2558 PNP Pwr 3A 100 20* IA
20 WC 80
2N2559 PNP Pwr 3A 100 20* lA 125
125 ao
30
2N2560 PNP Pwr 20WC 100 3A 100 20* IA
2N256I PNP Pwr 20WC ao 3.5A 100 20* 3A 125 50
20 WC 60 12 5 20
2N2562 PNP Pwr 3.5A 100 20* 3A 125 30
20WC 80 3.5A 100 20* 3A
2N2563 PN1' Pwr 125 40
2 0WC 100
2N2564 PNP Pwr 3.5A 100 20* 3A
2 0WC 40 3.5A 100 20* 3A 12 5 50
2N2565 PNP Pwr
20WC 125 20
2N2566 PNP Pwr 60 3.5A 100 20* 3A
2 0WC 80 3.5A 100 20* 3A 125 30
2N2567 PNP Pwr
2 0WC 100 125 40
2N2568 NPN Pwr 3.5A 100 20* 3A
2N2569 NPN Ch 1WC 35 100 100 15* 40 10
12 5
2
50
15
2N2570 NPN Ch 300 20 500 200 50* 100
3 00 20 .01 0 15
2N257I NPN Ch 500 200 50* 100
2N2572 NPN Ch 300 .010 15
20 500 200 50* 100 .010 15
2N2580 NPN Pwr 3 00 20
400 500 200 50* 100 .
01 0 15
5A 200 10* 5A 30ke 5ma 400
 MAXIMUM RATINGS ELECTRICAL PARAMETERS
-
MIN. MIN. MIN. MAX. Closest Dwg.
JEDEC Pc mw B V, I

® I( ma fidl, mc Ge db Ico (µa) ® Vee GE No.

No. Type Use CO 25 °C BV, ."` b ma Ti °C hire-hre

teo 10A 200 25* 5A tOkt• 5ma 400

21N2581 NPN Pwr 5ma 500
500 5A 200 10* 5A SOkc
2N2582 NPN Pwr 5ma 500
500 10A 200 25* 5A 10kc
2N2583 NPN Pwr
5A 200 10* 5A 30kc 5ma 600
2N2584 NPN Pwr 600
600 10A 200 25* 5A 30kc 5ma 600
2N2585 NPN Pwr .002 45 2N930 16
NPN AF 300 60 30 200 120* 10pa
2N2586
30 100 100 15* 8 5 15
2N2587 PNP IF 150 12
40 30 100 50* 1.5 13 3
2N2588 PNP IF 150 150
150 7A 200 17* 7A 2ma
2N2589 NPN Pwr
2N2590 PNP Vid 400 100 50 200 ao 5 .025 80
50 200 70 5 .025 80
2N2591 PNP Vid 400 100
100 50 200 115 5 .025 80
2N2592 PNP Vid 400
100 50 200 160 5 .025 80
2N2593 PNP Vid 400 2N699 5
80 IA 200 50* 100 40 .1 60
..2N2594 NPN Pwr 1W
80 50 200 15* 5 .025 50
2N2595 PNP Vid 400
80 50 200 30* 5 .025 50
2N2596 PNP Vid 400
80 50 200 60* 5 .025 50
2N2597 PNP Vid 400
80 50 200 15* 5 .025 80
2N2598 PNP Vid 400
BO 50 200 30* 5 .025 80
2N2599 PNP Vid 400
BO 50 200 60* 5 .025 80
2N2600 PNP Vid 400 45
60 50 200 12.5* 1 .025
2N2601 PNP Vid 400
50 200 25* 1 .025 45
2N2602 PNP Vid 400 60
50 200 50* 1 .025 45
2N2603 PNP Vid 400 60
30 200 40* 100a .010 45
2N2604 PNP Vid 400 60
30 200 100* 10pa .010 45
2N2605 PNP Vid 400 60 3
150 9 1 2 30 2N332
2N2610 NPN AF 150 45 25 8
175 12* 200 50 120 2N2611
2N2611 NPN Pwr 2W 120 IA
65 15A 100 85* 10A 10ma 30
2N2612 PNP Pwr 75WC 12
5

SNOUNDIAIDMS
AF 120 30 50 100 120 .5
2N2613 PNP 5 20
AF 120 40 50 100 100 1
2N2614 PNP 17
200 20* 3 9 .001 15 2N917
2N2615 NPN Ow 300 30 17
50 200 20* 3 15 .010 15 2N918
2N2616 NPN Ow 300 30
100 150 25 1 .1 6
2N2617 PNP AF 250 25
200 25* 10 .1 25 2N696
2N2618 NPN Vid 600 60 750
2N2621 PNP 150 15 100 110 15* 1 16 12
100 110 15* 1 12 12
2N2622 PNP 150 24
100 110 20* 1 8 12
2N2623 PNP 150 32
15 100 110 15* 1 16 12
2N2624 PNP 150 12
24 100 110 15* 1 12
2N2625 PNP 150
100 110 20* 1 8 12
2N2626 PNP 150 32
12 20

6L
150 15 100 110 15* 1
2N2627 PNP 14 12
150 24 100 110 15* 1
2N2628 PNP
 61
MAXIMUM RATINGS ELECTRICAL PARAMETERS
JEDEC Pc mw 8VcE MIN. MIN.

SNOIIVDMIDadS
MIN. MAX. Closest Dwg.
No. Type Use @ 25 °C inrce * lc ma T.I °C fife- her: * ® lc me. fhfb mc Ge db lc° (Ea) @ Ws GE No.
2N2629 PNP 150 32 100 110 10* 1 10 12
2N2630 l'NP Sw 300 18 100 100 25* 100 5
2N263I NPN RF 80 15
1.5A 200 8* 200 8.7 .1 30
2N2632 NPN Pwr 90 5A 175 40* IA .1 60
2N2633 NPN Pwr 120 5A 175 10* IA .1 60
2N2634 NPN Pwr 150 5A 175 10* IA .1 60
2N2635 PNP Sw 150 30 100 100 45* 50 5 25
2N2636 PNP Pwr 100W 100 25A 110 20* 25A 10ma 100
2N2637 PNP l'wr 100W 100 25A 110 20* 25A 10ma 100
2N2638 PNP l'wr 100W 100 25A 110 20* 25A 10ma
2N2639 NPN Dill 600 45 100
30 200 50* 10pa .010 45
2N2640 NPN Dill 600 45 30 200 50* 10ust .010 15
2N2642 NPN Dill 600 45 30 200 100* 10ma .010
2N2643 NPN Dill 600 45 45
30 200 100* lOga .010
2N2644 45
2N2645 NPN AF 500 75 200 100* 150 .010 60 2N956
2N2646 PN Si Uni SEE G. E. SPECIFICATION SECTION 16
2N2647 l'N Si Uni 2N2646 29
SEE G. E. SPECIFICATION SECTION
2N2648 2N2647 29
PNP Pwr 5WC 35 IA 100 80* IA
2N2649 NPN 100 35
8.7WC 65 1A 200 10* 500
2N2650 NPN 500 65
8.7WC 140 1A 200 10* 500 500 140
2N265I NPN Sw I.2WC 40 500 200
2N2652 25* 10 .030 20
NPN Dill 600 100 500 200
2N2654 35* 100µa .010 50 2N2652
PNP 100 25 10 75 21
25* 1.0 20 8.0 10
2N2655 NPN Pwr 15WC 100V 500 200
2N2656 30* 200 4 10 100
NPN RF 360 25 200 200
2N2657 40* .1 10 .5 15 2N9I8 17
NPN Pwr I.25W 80 5A 200 40* IA .1 60 2N657 5
2N2658 NPN Pwr I.25W 100 5A 200
2N2659 40* 1A .1 60 2N657
Pwr 50* 100 5-
30-90* 500 30 20 ma 20
.-2N2660 PNP Pwr I5W 70* 3A 100 30-90* 500 30 20 ma 20
2N266I PNP Pwr 15W 90* 3A 100
2N2662 30-90* 500 30 20 ma 25
PNP Pwr 15W 50* 3A 100
2N2663 30-90* 500 30 20 ma 25
PNP Pwr 15W 70* 3A 100 30-90* 500 30 20 ma 25
2N2664 PNP Pwr I5W 90* 3A 100
2N2665 30-90* 500 30 20 ma 25
PNP Pwr 15W 50* 3A 100
2N2666 50-150* 500 30 20 ma 25
PNP Pwr 15W 70* 3A 100 50-150* 500 30 20 ma 25
2N2667 PNP Pwr I5W 90* 3A 100 50-150* 500 30 20 ma 25
2N2668 PNP Pwr 15W 50* 3A 100 50-150* 500 30 20 ma 25
2N2669 PNP Pwr 15W 70* 3A 100 50-150* 500 30 20 ma 25
2N2670 PNP Pwr I5W 90* 3A 100
2N267I 50-150* 500 30 20 ma 25
PNP AF 100 25* 10 75 40 1 12 8 6
2N2672 PNP AF 100 25* 10 75 40 1 40 8 6
 ELECTRICAL PARAMETERS
MAXIMUM RATINGS

MIN. MIN. MIN. MAX. Closest Dwg.

JEDEC Pc mw BVce GE No.
hfe-hrE * @ lc ma fhfl, mc G, db lea (pa) @ Vea
No. Type Use @ 25 °C Wks* le ma Ti °C

100 25* 10 75 10 1 00 8 6
2N2672A PNP AF 8-22* 1 2.5 .100 30 2N2673 4
2N2673 NPN AF 250 60* 25 200 2N2674 4
60* 25 200 12-40* 1 5.0 .100 30
2N2674 NPN AF 250
22-76* 1 10 .100 30 2N2575 4
2N2675 NPN AF 250 60* 25 200 2N2676 4
250 60* 25 200 45-290* 1 10 .100 30
2N2676 NPN AF 20-5P 1 10 .100 30 2N2677 4
2N2677 NPN AF 250 45* 25 200
45-150* 1 20 .100 30 2N2678 4
2N2678 NPN AF 250 4P 25 200 3N84 28
2N2679 PNPN Sw SEE G. F. SPECIFICATION SECTION 3N81 28
2N2680 PNPN Sw SEE G. E. SPECIFICATION SECTION
3N82 28
SEE G. E. SPECIFICATION SECTION
2N2681 PNPN Sw
2N2682 PNPN Sw 3N83 28
SEE G. E. SPECIFICATION SECTION
2N2683 PNPN Sw 3N81 28
SEE G. E. SPECIFICATION SECTION
2N2684 PNPN Sw
2N2685 PNPN Sw 3N84 28
SEE G. E. SPECIFICATION SECTION
2N2686 PNPN Sw 3N84 28
SEE G. E. SPECIFICATION SECTION
2N2687 PNPN Sw 3N81, 3 28
SEE G. E. SPECIFICATION SECTION
2N2688 PNPN Sw 3N82, 4 28
SEE G. E. SPECIFICATION SECTION
2N2689 PNPN Sw
2N2690 PNPN Sw 30-100* 20A 6 5 ma 100
2N2691 PNP Pwr 100W 100* 20A 110C 2N929 16
90-360* 100pa 45 10 Na 25
2N2692 NPN Amp/Sw 300 45* 50 200
60 100pa 10 Na 25 2N929 16
2N2693 NPN Sw 1000 30 50 200 2N929 16
1000 20 50 200 30 100pa 10 Na 25
2N2694 NPN Sw 30-130* 50 25 Na 10
2N2695 PNP Sw 2W 25 500 200
1.2W 25 500 200 30-130* 50 25pa 10
2N2696 PNP Sw 40-120* IA .1 60
2N2697 NPN Pwr Sw IOW 60 5A 200
10W 80 5A 200 40-120* IA .1 60
2N2698 NPN l'wr Sw
150 15* 100 100 40-200 10 3 6
2N2699 PNP Sw 80-290* 2 1.3 10 .5
2N2706 PNP A 500 32* 200 75 2N918 17
200 20 200 30-180* 2 700 15 .01 15
2N2708 NPN HF
240 35 50 200 10-22 .2 .2 1.0 30
2N2709 PNP A 40* 10 .03 20
2N2710 NPN Sw 360 20 500 200 2N2711 1
200 18 100 125 30-120 2 .5 18
2N2711 NPN A 2N27I2 1
200 18 100 125 80-300 2 .5 18
2N2712 NPN A 30-120 2 .5 18 2N27I3 1
2N2713 NPN A 200 18 200 125 2N2714 1
200 18 200 125 80-300 2 .5 18
2N2714 NPN A 2N2715 1
200 18 50 125 30-120 2 .5 18
2N2715 NPN A 80-300 2 .5 18 2N2716 1
2N2716 NPN A 200 18 50 125
100 15 30 75 50* 30 1.4 .5
2N2717 PNP Sw
25* 170 150 7 5
2N2718 PNP Sw 240 12 400 100 2N914 16
300 8 200 175 30* 60 200 100 25
2N2719 NPN Sw 30-120* .100 .010 60 2N2919 21
2N2720 NPN Duff 600 60 40 200
 MAXIMUM RATINGS ELECTRICAL PARAMETE'S

JEDEC Pc mw EWE MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use g25 °C B\fcea k ma WC hre-hpi.: * (a I, ma fId I, mc G db ko (pa) Cu \Ica GE No.

2N272I NPN Diff 600 60 40 200 30-120* .100 .010 60 2N2919 21

2N2722 NPN Diff 600 45 40 200 50-250* .00 l' .001 30 2N29I6 21
2N2726 NPN l'wr IW 200* 500 200 30-90* 200 5 1 100 2N2726 5
^2N2727 NPN Pwr IW 200* 500 200 75-150* 200 10
2N2728 1 100 2N2727 5
PNP l'wr 170W 5 50A 110 40-130* 20A
2N2729 NPN IIF 300 15 50 200 20-200 3 600 .01 15
2N2730 l'NP l'wr Sw 80W 60 65A 110 30-120* 25A 5 na 80
2N273I PNP l'wr Sw 80W 45 65A 110 30-120* 25A 5 na 60
2N2732 PN P Pwr Sw 80W 30 65A 110 30-120* 25A 5 na 40
2N2733 PNP Pwr Sw 66 60 65A 110 30-120* 25A 5 na 80
2N2734 PNP Pwr Sw 66 45 65A 110 30-120* 25A 5 na 60
2N2735 PNP l'wr Sw 66 30 65A 110 30-120* 25A 5 na 40
2N2736 PNP l'wr Sw 66 60 65A 110 30-120* 25A 5 na 80
2N2737 PNP l'wr Sw 66 45 65A 110 30-120* 25A 5 na 60
2N2738 PN l' Pwr Sw 66 30 65A 110 30-120* 25A 5 na 40
2N2739 NPN Pwr 200W 50 20A 175 10* 10A
2N2740 NPN l'wr 200W 100 20A 175 10A
2N2741 NI'N Pwr 200W 150 20A 175 10A
2N2742 NPN Pwr 200W 200 20A 175 10A
2N2743 NPN Pwr 200W 250 20A 175 10A
2N2744 NI'N Pwr 200W :100 20A 175 10A
2N2745 NPN Pwr 200W 50 20A 175 I5A
2N2746 NPN l'wr 200W 100 20A 175 I5A
2N2747 NPN l'wr 200W 150 20A 175 15A
2N2748 NPN Pwr 200W 200 20A 175 I5A
2N2749 NPN l'wr 200W 250 20A 175 15A
2N2750 NPN Pwr 200W 300 20A 175 I5A
2N275I NPN Pwr 200W 50 20A 175 20A
2N2752 NPN Pwr 200W 100 20A 175 20A
2N2753 NPN l'wr 200W 150 20A 175 20A
2N2754 NPN Pwr 200W 200 20A 175 20A
2N2755 NI'N l'wr 200W 250 20A 175 20A
2N2756 NPN l'wr 200W 300 20A 175 20A
2N2757 NPN Pwr 200W 20A 175 10*
2N2758 NPN Pwr 200W 20A 175 10*
2N2759 NI'N Pwr 200W 20A 175 10*
2N2760 NPN Pwr 200W 20A 175 10*
2N276I NPN l'wr 200W 20A 175 10*
2N2762 NPN l'wr 200W 20A 175 10*
2N2763 NPN l'wr 200W 20A 175 10*
2N2764 NPN Pwr 200W 20A 175 10*
2N2765 NPN Pwr 200W 20A 175 10*
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pc mw BVcE MIN. MIN. MIN. MAX. Closest Dwg.

No. Use @ 25 °C BVce * le 11113 T.1 °C hfe-FirE * @ I
C 11113 flab mc Ge db Ico (go) @ We GE No.
Type

2N2766 NPN Pwr 200W 20A 175 10*

2N2767 NPN Pwr 200W 20A 175 10*
2N2768 NPN Pwr 200W 20A 175 10*
2N2769 NPN Pwr 200W 20A 175 10*
2N2770 NPN l'wr 200W 20A 175 10*
2N2771 NPN Pwr 200W 20A 175 10*
2N2772 NPN l'wr 200W 20A 175 10*
2N2773 NPN l'wr 200W 20A 175 10*
2N2774 NPN l'wr 200W 20A 175 10*
2N2775 NPN l'wr 200W 20A 175 10*
2N2776 NPN l'wr 200W 20A 175 10*
2N2777 NPN l'wr 200W 20A 175 10*
2N2778 NPN l'wr 200W 20A 175 10*
2N2779 NPN Pwr 200W 20A 175 10*
2N2780 NPN Pwr 200W 20A 175 10*
2N2780 NPN Pwr Sw 200W 300* 30A 200S 10* 25A
2N2781 NPN VIIF/U1IF 2.0W 75* 2.0A 1758 7.5* 350 12.5 500 28
2N2782 NPN VIIFAIIIF 2.0W 100* 2.0A 175S 7.5* 350 12.5 500 28
2N2783 NPN VHF/UHF 2.0W 100* 2.0A 1755 7.5* 350 10 28
2N2784 NPN I,o Pwr 300 15* 200 40* 10 .005 5 2N918 17
2N2785 NPN DA 500 60* 175 2000* 100 .005 30 2N2785 5
2N2786 1'N1' I1F 260 35* 150 90S 33* 100 10 10 10
2N2786A PNP 11F 260 35* 150 90S 33* 100 10 10 10
2N2787 NPN Sw 800 75* 800 175 12* 1.0 .01 50 2N2195 5
2N2788 NPN Sw 800 75* 800 175 20* 0.1 .01 50 2N2195 5
2N2789 NPN Sw 800 75* 800 175 35* 0.1 .01 50 2N2192 5
2N2790 NPN Sw 500 75* 800 175 12* 1.0 .01 50 2N760 16
2N2791 NPN Sw 500 75* 800 175 20* 0.1 .01 50 2N760 16
2N2792 N l'N Sw 500 75* 800 175 35* 0.1 .01 50 2N760 16

SNOLINDMID3dS
2N2793 PN I' l'wr Ami 170W 75* 60A 110 I'.
»* 50A 2ke
2N2794 P-FIT A 300 200S
2N2795 PN I' Sw 75 25* 100 100S 50* 10 25 25
2N2796 PNP Sw 75 20* 100 100S 30* 10 25 20
2N2797 PNP Sw 75 40* 100 100S 50* 10 25 40
2N2798 PNP Sw 75 60* 100 100S 30* 10 25 60
2N2799 PNP Sw 75 30* 100 100S 30* 10 25 30
2N2800 PNP Sw 800 50* 800 300S 20* 0.1 10 50
2N2801 PNP Sw 800 50* 800 300S 30* 0.1 10 50
2N2802 PNP Diff 250 25* 30 200S 15* .01 .01 25
2N2803 PNP Dill* 250 25* 30 200S 15* .01 .01 25
2N2804 PNP Diff 250 25* 30 200S 15* .01 .01 25

en
2N2805 PNP Diff 250 25* 30 200S 30* .01 .01 25
 6L
MAXIMUM RATINGS ELECTRICAL PARAMETERS

MMIIMIIIMMIMIMIMMIMM SNOIIVDI3IDacIS
JEDEC Pc mw BVcE MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @ 25 °C BVe.6 9 le ma TJ °C hfe-hr h ma flab mc Ge db lee (µa) Ven GE No.

2N2806 UNI' Diff 250 25* 30 200S 30* .01 .01 25

2N2807 UNI' Diff 250 25* 30 200S 30* .01 .01 25
2N2808 NUN ‘111.7111F 200 30* 25 200 20* 2.0 20 .01 15
2N2808A NUN VIIF/111 F 200 30* 25 200 20* 2.0 22 .01 15
2N2809 N PN VIIF/411 F 200 30* 25 200 20* 2.0 17 .01 15
_2N2809A N PN \ 11F/111 F 200 30* 95 9 00 20* 2.0 no .01 15
2N2810 N I' N ‘11F/III F 200 30* 25 200 20* 2.0 17 .01 15
2N2810A NPN VIIF/1.11 F 200 30* 25 200 20* 2.0 20 .01 15
2N2811 N I' N. I'wr 40W 80* 10A 200 10* 10 0.1 60 _2N172t 14
2N2812 N I' N l'wr 40W 80* 10A 200 10* 10 0.1 60 2NI724 14
2N2813 N PN l'wr 40W 120* 10A 200 10* 10 0.1 60 2N 1724 14
2N28I4 N PN l'wr tOW 120* 10A 900 10* 10 0.1 60 2NI724 14
2N2815 NPN Sw 200W 80* 20A 200S 10* 10A
2N2816 NUN Sw 200W 100* 20A 200S 10* 10A
2N2817 NUN Sw 200W 150* 20A 200S 10* 10A
2N2818 NUN Sw 200W 200* 20A 200S 10* 10A
2N2819 NPN Sw 200W 80* 25A 200S 10* 15A
2N2820 NUN Sw 200W 100* 25A 2008 10* 15A
2N2821 NUN Sw 200W 150* 25A 200S 10* 15A
2N2822 NUN Sw 200W 200* 25A 200ti 10* 15A
2N2823 NUN Sw 200W 80* 30A 2008 10* 20A
2N2824 NUN Sw 200W 100* 30A 200S 10* 20A
2N2825 NUN Sw 200W 150* 30A 200S 10* 20A
2N2826 MP A 7.5W 15 1.0A 110S 75* 100 4
2N2827 ¡'NP A 7.5W 30 1.0A 110S 75* 100 4
2N2828 NPN Sw 40W 80* 3.0A 2005 20* 500 2N1721 It
2N2829 NUN Sw 40W 80* 3.0A 2005 20* 1.0 2N1721
_ _ _ 1t

2N2831 NUN Vid 360 40* 200 200 25* 10 .03 15 2N760 16
2N2832 UNI' Sw 80* 20A 110S 25* 10A 10 ma 80
2N2833 PN I' Sw 120* 20A 110S 25* 10A 10 ma 120
2N2834 MP Sw 140* 20A 110S 9 5* 10A 10 nia 140
2N2835 Pwr 16W 32* 1.0A 90S 30* 1.0A 0.3 25 0.5
2N2836 I'N Pwr 37.5W 55* 3.5A 100S 30* 1.0A 0.250 50 0.5
2N 2837 PNP Sw 500 50* 800 300S 20* 0.1
2N 2838 l'N I' Sw 500 50* 800 3005 30* 0.1 10 50

2N2840 Si Uni SEE G. E. SPECIFICATION SECTION 2N2840 29

2N2845 NUN Sw 360 60* 200 10* 500 30 2N 956 16
2N2846 NUN Sw 800 60* 200 10* 500 30 2N1711 1
2N2847 N l'N Sw 360 60* 200 40* 150 30 2N718 16
2N2848 NUN Sw 800 60* 200 40* 150 :10 2N 697 5
 MAXIMUM RATINGS ELECTRIC AL PARA METERS

JEDEC Pc mw BVcE MIN. MIN. MIN. MAX. Closest 'Dmg.

No. Type Use g 25 °C BVcri * Ic ma T.1 °C hfe-hel. * (g. I( ma flbfh mc G db Ico (µa) @ W I; GE No.

252849 NI'N Sw 850 100* IA 200S 100* IA

252850 N l'N Sw 850 100* IA ZOOS 40* IA 252192A 5
252851 NI'N Sw 850 100* IA 200S 40* IA 252192 A 5

252852 N l'N Sw 850 100* IA 200S 20* IA 252213A

252853 N PN Sw 850 60* SA 200S 411* 1A 252193A 5
252854 NPN Sw 850 60* IA ZOOS 100* 1A 252192A _ 5_
252855 NPN Sw 850 60* IA 2005 40* IA 252192A 5
252856 NPN Sw 850 60 IA 200S 20* IA 252193A 5
252857 NI'N 11F 200 30* 20 200S 20 2 12 .01 15_ '5918
_- 17
252858 NI'N Sw 8.75W 1110* 3A 200S 20 IA
252859 NPN Sw 8.75W 120* SA 200S 20 IA
252860 ('N1' Sw 150 18* 150 100 40 6.0 12
252861 PN I' 300 25* I00 200 50 1.0 .01
252862 1'51' :100 25* 100 200 25 .01
252863 N l'N 800 60* IA 200 30* 2110 11.5 252193 5
252864 N PN 800 60* 1A 200 20* 200 0.5 252193 5
252865 NPN 200 25* 50 200 20 4.0 .01 2N918 17
252866 NPN l'wr 20W 120* 3A 200S 15* 2.11A 25:1220 15

252867 NPN l'wr 20W 120* SA ZOOS 10* 2.0A 253221 I

5
252868 NPN Sw 800 60* IA 200 40* 150 .01 30
252869 ('NI' l'wr 30W - 60* 10A 100S 30* 5A _ 4.......
252870 ('N l' I'wr SOW - 80* 10A 1110S 30* 5A ......,
252871 PNP Ch .100 60* 200S 15* 1.0 0.5 0. I - 50
252872 PN I' Ch 1.00 110* 200S 15* 1.0 05 0. I - 90

252873 1'51' 115 35* 10 I00S 40* 1.0 3.7 - I2 - 12

252874 NPN I III: 2W 75* 2A 175S 7.5* 350 10 I0 28 25656 5
N2875 l'N1' 20W 60* 2A 2005 15* 50 25 - 40 - 30
252876 51'N \II I
, 17.5W 80* 2.5A 21/0S 5* 2.5A 7 O. I 30
252877 IN N I r 30W 80* 5A 200 15* 10 11. 1 60 25:1221 15

SNOLINDIIIDUS
252878 51'N I r 30W 80* 5A 200 30* 10 0.1 60 _ 25:1221 Is
252879 N 1' \ l'wr 30W 100* 5A 200 15* 10 0.1 60 25:1221 15 -
252880 N I' N l'wr 30W 100* SA 200 30* 10 0.1 60 25:1221 15
252881 I' N I' Pwr 8.75W 60* 1.5 A ZOOS 20* 500 25k,' 100 30
252882 1' N. I' l'wr 8.75W 100* 1.5 A 2005 20* 500 251tc 100 50
252883 N l'N 111111, 800 -10* 300 200 20* 100 0.5 20 25697 5
252884 N l'N 1111IF 800 10* 300 200 20* 100 0.5 20 25697 5

252885 51'5 Sw 150 40* 50 I75 30* III 0.025 20

252886 N PN A 800 50* 500 200 22* 5.0 0.1 30 25699 5
252887 N l'N VIIF 25W 100* 1.2A 200S 6 :150
252888 1'51'5 Sw SEE G . E. SilIMN CONTROLLED li ECTI FIERNIA NU AI. 252888
252889 1'5 l'N Sw SEE G. E. SILICON CONTROLLED R ECTI FIER NI ANU AL N2889

6L
252890 N l'N l'wr 800 100* 200 L so* LOA
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pcmw BVce MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @ 25 °C BVca* h ma TJ °C hfe-hvr: * 1 I. ma tulip mc G db I (.a) V u GE No.

252891 NI'N Pwr 800 100* 200 :10* 1.11A

252892 N l'N l'wr 30W 100* 5.0A 200 50* 1.0A 253221 15
252893 N l'N l'wr 30W 100* 5.0A 200 :10* 1.0A 25:1221 15
252894 P51' Sw 360 - 19* 200 9 00 40* 30 6
252895 N l'N 500 120* 1.0A 200S 10* .01 60
252896 51'N 500 140* 1.0A 200S 35* 1.0 60
252897 5 PN 500 60* 1.0A 200S 35* 1.0 60
252898 5 PN 500 120* 1.0A 200S 10* .01 .01)2 60 252364 4
252899 51'N 500 140* 1.0A 200S 35* 1.0 60 252:164 4
252900 5 PN Amid 1.8W C 60* 1000 200 50 60 252:153
252901 _ NPN Ch .36W C 20* 20 200 12 Iir .125 15 252:156 32
252902 NI'N Amid 240W C 120* 750 200 30 50 120 7F1 12
25290:1 NPN Dill 1.2W C 60* 50 200 60 10pa 10 na 50
252904 PN I' Sw 3W 60 600 200 40 150 20 na 50
252905 ['NI' Sw 3W 60* 600 200 75 150 20 na 50
252906 ['NI' Sw 600 60* 600 200 40 150 20 na 50
252907 ['N I' Sw 600 60* 600 200 75 150 20 na 50
252908 N l'N Amid 18W 80* 2000 200 12 1000 45
252909 5 PN Amid 100 60* 1000 200 30 150 10 na 30
252910 5 PN Diff 2W 45* 200 711 .1 10 na 20 252910 21
252911 N1'5 Sw 5W 150* 3000 200 20 I000 150
252912 1'51' Pwr 75W 15* 25A 110 100 5A 15
252913 NPN Dili 1.5W 15* 10 200 60 1giat 10 na 45 252913 21
252914 NPN Dill 1.5W 15* Nl 200 150 IOaa 10 na 15 252914 21
252915 NPN Dili I.5W 15* 10 200 60 II/ma 10 na 15 252915 21
252916 NPN Dill I.5W 15* 10 2011 150 IOma 10 tut 15 252916 21
252917 NI'N Dill I.5W 45* 10 200 60 IOita 10 na 15 252917 21
252918 N l'N Dili 1.5W 60* 10 200 150 10aa 10 na 15 252918 21
252919 NPN Dili 1.5W 60* 30 200 60 I0µa 2 na 15 252919 o
252920 51'N Dill 1.5W 60* 10 200 150 Ioaa 2 na 15 2N 2920 21
252921 N1'5 A 200 25* 100 125 :15 2 .5 25 252921
2N2922 5 PN A 200 25* 100 125 55 2 .5 •25 252922 1
252923 N l'N A 9 00 r5i,
, 100 125 90 2 .5 25 252923
252924 51'N A 200 25* 100 125 150 2 .5 25 252924 1
252925 NPN A 200 25* 100 125 235 2 .5 25 252925
252926 N l'N A 200 25* 100 125 35 2 .5 25 252926 1
252927 PN I' Sw 3W 25* 500 200 30 50 25 na I0
252928 1'51' 111IF 150 15* 100 100 10 2 5 10
252929 l'151' IF/F11, 750 25* 100 100 10 10 5 10
252930 l'N I' Sw 250 :10* 500 100 60 I0 7 15
252931 NPN A 37.5 5* 50 125 30 .2 15 na 2 1111552 18
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pc mw BVen MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @ 25 °C BVcn* h. ma 7.1 °C hfe-hrE s 4 k ma (MI mc G. db lc° (pa) @ VCB GE No.

21\12932 NPN A 7.5 5* 50 125 70 .2 15 na 2 1111555 18

2N2933 N PN A 17.5 5* 50 125 45 .2 15 na 2 1111555 18
2N2934 \I'N A 17.5 45* 50 12$ :10 .2 15 na 30 1111552 18
2N2935 ;N. I A 7.5 45* 50 125 70 .2 15 na 30 1111555 18
2N2936 'N, Dill 600 60* 175 100 10µa 10 na 60 2N2916 21
2N2937 :\ 600 60* 175 100 10ma 10 na 60 2N291t 21
2N2938 1%. PN Sw 300 25* 500 200 10 1 25 na 20
2N2939 NPN Ampl 800 75* 1000 200 60 150 10 25 na 60 2N2193 5
2N2940 NPN Amyl 800 120* 1000 200 60 150 10 25 na 90
2N2941 NPN Amyl 800 150* 1000 200 60 150 10 25 na 100
2N2942 PNI' Sw 150 50* 100 100 50 10 2 25
2N2943 PNI' Sw 150 30* 100 100 :10 10 3 15
2N2944 PN1' Ch 400 15* 100 200 80 I .1 na 15
2N2945 PN I' Ch 400 25* 100 200 40 1 ma .2 na 25
2N2946 PN I' Ch 400 40* 100 200 30 1 ma .5 na 10
2N2947 NPN Ampl 25W 60 I.5A 175 2.5 1000 I 50
2N2948 NPN Ampl 25W 40 I.5A 175 2.5 1000 1 30
2N2949 NPN Ampl 6W 60 700 175 5 400 .1 50
2N2950 NPN Ampl 6W 60 700 175 5 400 .1 50
2N2951 N l'N Ampl 3W 60 250 175 20 150 .1 50 2N2I93
2N2952 NPN Ampl I.8W 60 250 17$ 20 150 .1 50
2N2953 l'N I' A 100 30 150 100 100 50 5 20
2N2954 NPN Ampl 200 30* 500 200 25 2 15 50 pa 10 2N9I8 17
2N2955 l'N I' Sw 150 40 100 1011 20 10 10 25
2N2956 l'NP Sw 150 40 100 100 30 10 10 25
2N2957 l'NP Sw 150 40 100 100 60 10 10 95
2N2958 N l'N Sw :SW 60* 600 200 40 150 25 na 50 2N2I93 5
2N2959 NPN Sw 3W 60* 600 200 100 150 25 na 50 2N2I92 5
2N2960 N l'N Sw 3W 60* 600 200 75 10 25 na 50 2N2192 5 cé)
2N2961 NPN Sw 3W 60* 600 200 30 500 25 na 50 2N2192 $ 01:1

2N2962 PN I' Ampl :SW 141* 300 100 6 5 10 M

r)
,

2N2963 l'NP Ampl 3W 40* :100 100 5 5 10

9
2N2964 l'NP Ampl 3W 30* 300 100 6 5 10
2N2965
2N2966
l'N I'
PNP
Ampl
Ampl
3W
60
30*
20*
300
100
100
100 8 3
5 5
5
10
10
r)
2N2967 NPN Sw 300 12* 200 20 10 50 na 5 >0.
2N2968 PNP Ch 150 30* 50 140 15 .1 10 na 15 • 1:1
1

2N2968 PN I' Ch 150 30* 50 140 15 .1 10 na 15 0

2N2970 l'NP Ch 150 30* 50 140 10 .1 10 na 15 Z
cd,
2N2971 1'N I' Ch 150 :10* 50 140 10 .1 10 na 15
er. 2N2972 N l'N Dill 750 45* 30 200 60 lOna 10 na 45
C.° 2N2973 NPN Dill 750 45* 30 200 150 10pa 10 na 45
Cm
 61
MAXIMUM RATINGS ELECTRICAL PARAMETERS

SKOLLVDIAID3dS
JEDEC Pc mw BVee MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use (0) 25 °C BVc:e* le ma T.1 °C hfe-FIFF: * @ le ma fleb mc Ge db lee (pa) @ Vea GE No.

2N2974 N PN Diff 750 45* 30 200 60 lama 10 na 45

2N2975 NPN Diff 750 45* 30 200 150 10pa 10 na 45
2N2976 NPN Diff 750 45* 30 200 60 10pa 10 na_ 45
2N2977 NPN Diff 750 45* 10 200 150 lopa na 45
2N2978 NPN Diff 750 60* 10 200 60 10pa 2 na 45
2N2979 Diff 750 60* 10 200 150 10µa 2 na 45
2N2980 NPN Diff 750 100* 500 200 50 10 ma 2 na 80
2N2981 NPN Diff 750 100* 500 200 50 10 ma 10 na 80
2N2982 N l'N Diff 750 100* 500 200 50 10 ma 10 na 80
2N2983 NPN Ampl IW 155* 000 200 20 1000 150
2N2984 NPN Ampl IW 185* 3000 200 20 1000 180
2N2985 NPN Ampl IW 155* 000 200 40 1000 150
2N2986 NPN Ampl IW 185* 3000 200 40 1000 180
2N2987 NPN Ampl 15W 95* 1000 200 25 200 90 2N2203
2N2988 NPN Ampl I.5W 155* 1000 200 25 200 90 2N2203
2N2989 N l'N Ampl I.5W 95* 1000 200 60 200 150
2N2990 NPN Ampl I.5W 155* 1000 200 60 200 150
IcHo
2N2991 NPN Ampl 15000 95* 1000 200 20 500 .10pa 50 7FI
lcmo
2N2992 NPN Ampl 15000 155* 1000 200 20 500 .1 0pa 90 7F3
Ictio
2N2993 NPN Ampl 15000 95* 1000 200 40 500 .10pa 50 71,2
Iceo
2N2994 NPN Ampl 15000 155* 1000 200 40 500 .10pa 90 71,1
2N2995 NPN Ampl 15000 120* 1000 175 10 1000 50i.da 120 2N2995
2N2996 PNP Ampl 751,A 15* 50 100 25 4 Spa 10
2N2997 1'N l' Ampl 75F'A 30* 50 100 40 4 5/aa 12
2N2998 l'N P Ampl 751,A 15* 20 100 15 3 Spa 10
2N2999 l'NP Ampl 75F'A 15* 20 100 10 1 Spa 10
2N3001 PNPN Sw SEE G. I. SPECIFICATION SECTION 1N84 28
2N3002 PNPN Sw SEE G. F. SPECIFICATION SECTION 1N/13 28
2N3003 l'NPN Sw SEE G. F. SPECIFICATION SECTION 0182 28
2N3004 PNPN Sw SEE G. F. SPECIFICATION SECTION
2N3005 PNPN Sw SEE G. F. SPECIFICATION SECTION 3N84 28
2N3006 PN PN Sw SEE G. F. SPECIFICATION SECTION 3N83 28
2N3007 PN PN Sw SEE G. I... SPECIFICATION SECTION 3N 82 28
2N3008 PNPN Sw SEE G. F. SPECIFICATION SECTION
2N3009 NPN Sw 1200 40* 200 200 30 30 20
2N3010 NPN Sw 300 15* 50 200 15 30 II
2N3011 NPN Sw 1200 30* 200 200 30 10 20 2N2369
2N3012 PNP Sw 1200 12* 200 200 30 30 6
 SNOLLVDMIDadS IMMIIMMIIIMMIIIII
MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pc mw BVeF: MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use 25 °C BVee * le ma T.1 °C hfe-lwE s e
,
q le ma mc Ge db leo (µa) Vce GE No.

2N3013 NPN Sw 1200 40* 200 200 30 30 20

2N3014 NPN Sw 1200 40* 200 200 30 30 20
2N3015 N PN Sw 3000 60* 200 30 150 30 2N2193 5
2N3016 NPN Ampl 5000 100* 500 150 60 1000 .1 60
2N3017 NPN Arnpl 10000 100* 1000 ISO 60 1000 .1 60
2N3018 NPN Ampl 5000 100* 2000 150 60 1000 .1 60
2N3019 N PN Ampl 5000 140* 1000 200 100 150 10 na 90 2N21.92 5
2N3020 NPN IF/RF 5w 80 IA 200 30 1 10 na 90
2N3021 NPN Sw 25W 30 3A 175 20 IA
2N3022 NPN Sw 25W 45 3A 175 20 1A
2N3023 N PN Sw 25W 60 3A 175 20 IA
2N3024 N PN Sw 25W 30 3A 175 50 IA
2N3025 NPN Sw 25W 45 3A 175 50 IA
2N3026 NPN Sw 25W 60 3A 175 50 1A
2N3033 N l'N Sw 300 160* 200 200
2N3034 NPN Sw 300 120* 200 200
11vcaa
2N3035 NPN .Sw 300 90 200 200 5 less I5V
2N3036 NPN AF 5W 80 1200 200 50* ISO 10 na 60
2N3037 NPN AF 360 70 500 200 40* 150 10 na 60
2N3038 NPN AF 360 60 500 200 80* 150 10 na 60
2N3039 I'NP AF 360 35 500 200 20* 150 25 na 30
2N3040 l'NP AF 60 30 500 200 40* 150 25 na 30
2N3043 NPN 50 45 30 200 130* 1 10 na 45
2N3044 NPN Di IT 350 45 30 200 130* 10 na 45
2N3045 NPN AF 350 45 30 200 130* 10 na 45
2N3046 NPN Dill 350 45 30 200 65* 10 na 45
2N3047 N l'N 50 45 30 200 65* 1 10 na 45
2N3048 N l'N AF 50 45 30 200 65* 10 na 45
2N3049 PN Di IT 50 20 100 200 30* 1 10 na 25
2N3050 PN I' Di IT 150 20 100 200 30* 1 10 na 25
2N3051. PN l' AF 150 20 100 200 :so* t 10 na 25
2N3052 NPN Sw 150 15 200 200 25* 10 25 na 20
2N3053 N PN AV 5W 40 700 200 50* 150 .25 60
2N3054 ' 90* 4A 200 25* 500
2N3055 N PN AF 115W 100* 15 A 200 20* 4A .IIINIM.

2N3056 N l'N II le 5W 60 1A 200 40* 150 10 na 60 2N2364

2N3057 N PN I1F 5W 60 IA 200 100* 150 10 na 60
2N3058 PN1' AF 400 6 100 200 40* .1rat .1 na 6
2N3059 l'N I' AF 400 10 100 200 100* 10aa .1 na 6

rçr
2N3060 PNP AF 400 60 100 200 30* L 5na 60

6L
2N3061 l'N I" AF 400 60 100 200 60* 1 5 na 60
 MAXIMUM RATINGS ELECTRICAL PARA METERS

JEDEC Closest
No. @ 25 °C BVcii* ma T.P °C GE

2N:1062 PNP 400

SNOLLVDIA
2N3063 PNP AF 400 80 100 200 10 na 80
2N3064 PNII> AF 400 100 100 200 100 na 100
2N3065 PNP AF 400 100 100 200 1 100 na 100
2N3072 PNV Sw 3W 60 500 200 50
2N3073 1.2W 60 Ico
PNP Sw 500 200 50
IA MIN. MIN. MAX.
2N3076 NPN Sw 125W 50 10A 200 7A
2N3077 NPN AF 360 60 50 200 1 10 na 15
2N3078 NPN AF :160 60 50 200 1 10 na 45
2N3079 NPN Sw 150W 200 5A 200 hr1 1 1 1212e:056‘:3:25,:0233:203
5ti
7l
3
12:2
31)1
450:)- 0 0 0 050 057 0:50:50:*: :* * * .* * * * * * * * * :*
0000005000 @ I' ma fie!' mc db W I) 4
2N3080 NPN Sw
AF 150W
Pc mw BV300
I
5A 200 5A
2N3081 PNP Sw 2W 50 600 300 150
5A

2N3082 NPN Ch 1.8W 7 100 200

2N3083 NPN Ch I.8W 7 100 200 25
2 50%01
2N3108 NPN Sw 5W 60 IA 200 500 10 na 60
2N3110 NPN Sw 5W .10 lA 200 500 10 na 60
5W 65* 100
200 200
200 30 100 17 10 na
2N3114 NPN IF 150 10 na 100
2N3I17 NPN AF 1.2W 60 50 20 1 10 na 45
2N3118 NPN RF 1W 60 500 200 25 30
2N3119 NPN IF IW 80 500 200 100 5 0 na
. 60
2N3120 PNP IF 3W 45 500 200 50 10 na 30
2N3136 Type 600 300 MIN.
2N3121 PNP IF 1.2W 45 500 200 10 na 30
2N3122 NPN AF 3W 30 500 200 :10
500 2 30
2N3123 NPN Sw 3W 30 800 175 150 100 na 50
2N3124 PNP AF 90W 40* 15A 100 3A 500
20 ma 80
40
2N3125 PNP AF 90W 80* 3.3A. 100 :IA 15 ma 80
2N3126 PNP AF 25W
90W 80 15A 100 3 ma 65
2N3127 PNP 100 12
0(0
)* 50 100 5 10
2N3142 NPN AFUse
2N3128 NPN IF 150 20 100 150 10 na 16
2N3I29 NPN IF 150 45 100 150 10 na 36
2N3130 NPN IF 150 6o 100 150 10 na 18
2N3I31 NPN Sw 150 15 100 150 1013111A 20
5 5 aa 20
2N3133 PNP Sw 3W 35 600 300 150 0
2N3134 PNP Sw 3W 35 600 300 50 na 0
2N3135 PNP Sw 1.8W 35 40* 1
15(
5 0
1 50 na 10
PNP Sw 1.8W 35 600 300 100* 150 50 na 10
2N3137 NPN RF 1W 20 150 200 20* 50 50 na 20
2N3138 NPN RF 20W 65 2A 200 10* lA 500 60
2N3139 NPN RF 20W 140 2A 200 10* 110
2N3140 NPN AF 20W 65* 2A 10*
2N3141 NPN AF 20W 140* 2A 10*
10* IA
IA 500 140
65
65
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JE DEC Pc mw BVcE MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @ 25 °C BVes* le ma T.I °C hfe-hFc * I ma fh11, roc Ge db Ica (µa) @ Vt.» GE No.

2N3143 NPN Ale 25W 140* 2A 10* IA 500 110

2N3144 NPN A Fe 25W 65* 2A 10* 1A 500 65
2N3145 NPN AF 25W 140° 2A 10* 1A 500 140
2N3146 ¡'NP Pwr 150W 150* 15A 25* — 10A — 10 - 150
2N3147 ¡'NI' l'wr 150W 180* ISA 25° — 10A — 10 ma — 180
2N3148 ¡'NI' Sw 11* 50 60* — 50 5 —5
2N2149 NPN Sw 70A 10° 50A
2N3150 NPN Sw 70A 10* 50A
2N3151 NPN Sw 70A 10° SO A
SO
2N3152 NPN Sw 120° 100 40* :10 100 °C 20
2N3153 N PN Sw 15 100 200 10 nn 15 25760 16
2N3154 l'N1' Sw 17.5W IA 60* 0.5A 100 2
2N3155 l'NP Sw 17.5W IA 60° 0.5A 100 2
2N3I56 ¡'NI' Sw 17.5W IA 60° 0.5A 100 2
2N3 I57 PN I' Sw 17.5W IA 60° 0.5A 100 2
2N3158 l'N I' Sw 17.5W IA :10* 0.5A 100 2
2N3159 PN I' Sw 17.5W SA :10* 0.5A 100 '''
2N3160 ¡'NI' Sw 17.5W IA :SO° 0.5A 100 2
2N3161 ¡'NI' Sw 17.5W SA 10* 0.5A 100 2
2N3162 NPN Dill 1.5W 15* 200 15* I00pa 10 na 30 2N2015 21
2N3163 ¡'NI' Pwr 85W — IA 12° —IA
2N3164 ¡'NP Pwr 85W — SA 12* —IA
2N3I65 ¡'NI' l'wr 85W — IA 12* —IA
2N3I66 l'NP l'wr 85W — IA 12* —IA
2N3 I67 ¡'NI' l'wr 86W — IA 12° —IA
2N3 168 PNI 1 l'wr 85W — IA 12* —IA
2N3I69 ¡'NI' Pwr 85W — IA 12° —IA
2N3170 ¡'NI' AF 85W — 12* —IA

SNOLLVDIAIDadS
,2_
N3171 ¡'NI' Ale 75W — IA 12° —IA
2N3172 ¡'NI' AI, 75W — IA 12* —1A
2N3173 ¡'NI' AF 75W —1A 12* — IA
2N3174 ¡'NI' AF 75W —1A 12* —IA
2N3175 ¡'NI' 85W —5A 10*
2N3176 PNP AF 115W —5A 10* —2A

I I
2N3177 ¡'NP AF 85W —SA 10° —2A
2N3178 ¡'NI' AI , 85W —SA 10* —2k
2N3I79 ¡'NI' A le 85W —SA 10* —2A
2N3180 ¡'NI' AF 85W —SA 10* —2A
2N3181 ¡'NI' Ale 85W —SA 10* —2k
2N3182 ¡'NP AF 85W —SA 10* —2A

61,
Ce) "N:1183 ¡'NI' AI" 75W —SA 10* —2k
•••1
 MAXIMUM RATINGS ELECTRICAL PARAMETERS 10

JEDEC Pc WSW BVCE MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use 4 25 °C BVce• I. ma TJ °C hte-hrE* to fi ma fhfl, mc G. db Ica (pa) @Vas GE No.

2N3I81 ¡'NI' \le 75W —3k 10* —2A

2N3185 ¡'NI' \le 75W —5A 10* —2A
2N3186 PNP AN' 75W —5A 10* —2A
2N3187 l'N1' AF 85W —5A 10* —3A
2N3188 ¡'NI' AI? 85W —5A 10* —3A
2N3189 ¡'NI' AF 85W —SA 10* —3k
2N3190 ¡'NI' AF 85W —5A 10* —3A
2N3191 ¡'NI' AF 85W —5A 10* —3A
2N3192 ¡'NP AN' 85W —5A 10* —3A
2N3193 l'N1' A' 85W —5A 10* — IA
2N3194 ¡'NI' Ale 85W —5A 10* — IA
2N3195 ¡'NP AF 75W —5A 10* — iA
2N3I96 ¡'NP AF 75W —5k 10* —3A
2N3I97 ¡'NP AF 75W —5A 10* —3A
2N3198 ¡'NP AF 75W —5A 10* —3A
2N3199 ¡'NP AF 40W —3A 20* —1A
2N3200 ¡'NI' AF 40W —5k 20* —1A
2N3201 ¡'NP AF 40W —3A 20* —IA
2N3202 ¡'NI' AF 8.75W —3A 20* — IA
2N3203 ¡'NI' AF 8.75W —3A 20* —IA
2N3204 ¡'NP AF 8.75W —3A 20* —1A
2N3205 ¡'NP AF 40W —2A 20* — 500
2N3206 ¡'NP AF 40W —2A 20* —500
2N3207 ¡'NP AF 40W —2A 20* —500
2N3208 ¡'NP AF 8.75W —2A 20* —500
2N3209 ¡'NP Sw I.2W —20* 200 200 15* 100
2N3210 NPN Sw 1.2W 40* 500 200 30* 10 10 na 20 2N708 16
2N3211 NPN Sw 1.2W 40* 500 200 10* 500
—5A
2N3212 ¡'NP Sw 12.1W 5A 30* 3A
—SA
2N3213 ¡'NP Sw 12.IW SA 30* 3A
—5A
2N3214 ¡'NP Sw 12.1W 5A 30* 3A
—SA
2N3215 ¡'NP Sw 12.IW 5A 25* :SA
2N3217 ¡'NP Sw 100 .001 15
2N3218 ¡'NP Sw 100 .001 25
2N3219 ¡'NI' Sw 100 .001 ao
2N3220 NPN AF 2A 20* IA 2N3220 15
2N3221 NPN AF 2A 40* IA 2N322I 15
2N3222 NPN AF 2A 20* IA 2N3222 15
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pc mw Vicp: MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @ 25 °C BVc a* k ma T.1 °C hfe- @I: ma fhf b mc G db lc° (pa) @ We GE No.

IMMIMMIIMMMIIIM
2N3223 NPN AF 2A 40* 1A 2N3223 15
2N3224 PNP Vid 20* — 50 —0.1 —80
2N3225 l'NP Vid — 100* 40* —50 —91 —80
2N3227 NPN Sw 1.2W 40* 200 200 100* 10 0.1 20
2N3228 PNPN Sw 3.2A
2N3229 NPN AF 17.5W 105* 2.5A 5* 2.5A 8.75 0.1 30
2N3230 NPN Sw 25W 80* 7A 200 1000 50 2 50
2N3231 NPN Sw 25W 100* 7A 200 1000 50 2 60
2N3244 l'NP Sw 5W 40* 1A 200 25* 750 50 na 30
2N3245 l'N P Sw 5W 50* IA 200 20* 1.A 50 na 50
2N3246 NPN AF .35W 60* 50 300* 100pii .001 40 2N9311A 16
2N3247 NPN AF .1 5W 60* 50 150* I.0 /..a .001 40
2N3254 PNPN Sw SKI. G. E. SPECIFICATION SECTION 3N84 28
2N3255 PNPN Sw SKI' G. E. SPECIFICATI N SECTION 3N84 28
2N3256 l'N l'N Sw SKI' G. E. SPECI FICATION SECTION (N81. 31583 28
2N3257 l'N l'N Sw SKI' G. E. SPECIFICATION SECTION (Nat 28
2N3258 PNPN Sw SKI' G. E. SPECIFICATION SECTION INII 28
2N3259 l'N PN Sw SEI G. E. SPECIFICATION SECTION 3N81. 31583 28
2N3262 NPN Pwr 8.75W 80 1.5A 200S 40* 50 2N 1068
2N3263 N l'N Pwr 60 25A 200 20* I5A
2N3264 NPN Pwr 90 25A 200 20* I5A
2N3265 NPN Pwr 60 25A 200 20* I5A
2N3266 N l'N Pwr 90 25A .00 20* I5A
2N3267 l'NP HF/IF 75 —a 20 1005 15 —
2N3268 NPN AF 150 45 25 200S 12 10 2.5
2N3273 PNI'N Sw SEE G. E. SPECI FICATION 514 11015 31582. 3N85 28

SNOILVDMIDga
2N3305 PN I' AV 600 — 40 200S 40* —.1 — .05 — 30
2N3306 l'N I' AV 600 — 40 200S 100* — .1 — .115 — 10
2N3307 NPN HF/IF 300 35 50 200 20* 2.0 17 .111 IS 2N918 17
2N3308 NPN RF/IF 300 25 50 200 10* 2.0 17 .01 15 215917 17
2N3309 NPN Pwr 5W 50* 500 175 5* 30 0.5 25 7A30 5
2N3311 PNP Pwr 170W 20 500 110 60* 3A 5na 30
2N3312 l'NP l'wr 170W 30 500 110 60* IA 5ma 15
2N3313 PNP l'wr 170W 40 500 110 60* (A 5ma 60
2N3314 PNP Pwr 170W 20 500 110 100* IA 5ma 30
2N3315 PNP Pwr 170W 30 500 110 100* 3A 5ma 45
2N3316 PNP Pwr 170W 40 500 110 10

61.
2N3323 PN I' l'wr 150 35* 100 100 300* 3A
3 5ma
10 60
10
 6
MAXIMU M RATINGS ELECTRICAL PARAMETERS

JEDEC

SNOIIVDIAIDadS
Pe env BVce MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @ 25 °C BVce* lc ma T.1 °C hfe-hrii * I( ma fil I mc G• db 'co (Ise) @ Yee GE No.

2N3324 ¡'NI' Pwr 150 35* 100 100 :10 3 10 10

2N3325 PNP Pwr 150 35* 100 100 30* 3 10 10
2N3347 ¡'NP Diff 600 —45 200 40* —.010 —.010 —45
2N3348 ¡'NP Diff 600 —45 200 40* —.010 —.010 —45
2N3349 ¡'NI' Diff 600 —45 200 40* —.010 —.010 —45
2N3350 ¡'NP Duff 600 —45 200 100* —.010 —.010 —45
2N3351 PNI' Diff 600 —45 200 100* —.010 —.010 —45
2N3352 PNP Diff 600 —45 200 100* —.010 —.010 —45
2N337I MVP RF/F 150 —10 100 125S 25 —12 —7 —6
2N3372 NPN Obsolete 200 18 100 100 250* 2 .1 18 2N3391 1
2N3373 NPN Obsolete 200 18 100 100 250* 2 .1 18 2N339IA I
2N3390 NPN AF 200 25 100 100 400* 2 0.1 18 2N3390 1
2N3391 NPN AF 200 25 100 100 250* 2 0.1 25 2N3391 1
2N339IA NPN AF 200 25 100 100 250* 2 0.1 25 2N3391A 1
2N3392 NPN AF 200 25 100 100 150* 2 0.1 25 2N3392 1
2N3393 NPN AF 200 25 100 100 90* 2 0.1 25 2N3393 1
2N3394 NPN AF 200 25 100 100 55* 2 0.1 25 2N3394 1
2N3395 NI'N AF 200 25 100 100 150* 2 0.1 18 2N3395 1
2N3396 NPN AF 200 25 100 100 90* 2 0.1 18 2N3396 1
2N3397 N1'N AF 200 25 100 100 55* 2 0.1 18 2N3397 1
2N3398 NPN AF 200 25 100 100 55* 2 0.1 18 2N3398 1
2N3399 ¡'NP IIF 8.2
2N340I ¡'NI' Ch 250 25 100 150 4 0.1 20
2N3402 NPN AF 560 25 500 150 75 2 0.1 25 2N3402 2
2N3403 NPN AF 560 25 500 150 100 2 0.1 25 2N3403 2
2N3404 NPN AF 560 25 500 150 75 2 0.1 25 2N3404
2N3405 NPN AF 560 25 500 150 100 2 0.1 25 2N3405 2
14* 10
2N3413 l'NP AF 400 150 200 200 10* 50 8 0.1 100
2N3414 NPN AF 360 25 500 150 75 2 0.1 25 2N341t 1
2N3415 NPN AF 360 25 500 150 100 2 0.1 25 2N3415 1
2N34I6 NPN AF 360 25 500 150 75 2 0.1 25 2N34I6 1
2N3417 NPN AF 360 25 500 150 100 2 0.1 25 2N34I7 1
20* 100
2N34I8 NPN l'wr Sw 800 60 3A 175 10* SA 80
5 2
20* 100
2N3419 NPN Pwr Sw 800 80 3A 175 10* 5A 120
40* 100
2N3420 NPN Pwr Sw 800 60 3A 175 15* 5A 80
40* 100
2N3421 NPN l'wr Sw 800 80 3A 175 15* 5A
2N3449 ¡'N1' Sw 150 6 100 100 20* 10 3 120
 MAXIMUM RATINGS ELECTRICAL PARAMETERS
_

JEDEC Pc mw BVce MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @ 25 °C BVce" lc ma T.I °C We- hrE * @ le ma fldb mc Ge db leo WO @ Wes GE No.

4D20 NPN Sw 150 40* 25 1503 33* 1.0 41420 3

41421 NPN Sw 150 40* 25 1503 88* 1.0 11421 3
4D22 NPN Sw 150 40* 25 1503 185* 1.0 41422 3
41324 N l'N Sw 125 15* 25 I25J 33* 1.0 41421 3
41325 NPN Sw 125 15* 25 1253 88* 1.0 4D25 3
41426 NPN Sw 125 15* 25 1253 133* 1.0 41326 3
4C28 N l'N Sw 150 40* 25 1253 15 12.0 2.0 4C28 3
4C29 NPN Sw 150 40* 25 1253 30 12.0 2.0 4C29 3
4C30 NPN Sw 150 40* 25 I25J 55 12.0 2.0 4C30 3
4C31 NI'N Sw 150 40* 25 1253 115 12.0 2.0 4C31 3
7131 N l'N Power 15W 80* 175 12* 15T 50 80 7131 8
7C1 NPN Power 15W 80* 175 12* 15T 50 80 7C1 9

7141 NPN Power 15W 80* 175 12* 15T 50 80 7141 10

7E1 N PN Power 15W 80* 175 12* 15T 50 BO 7E1 11
N l'N Power 7W 80* 175 12* 151' 50 80 7F1 12
7Fl
N I' N Power 15W BO* 175 30* 15T 50 80 7132 a
7132
NPN Power 15W 80* 175 30* 15T 50 BO 7C2 9
7C2
7142 N l'N Power 15W 80* 175 30* 15T 50 80 7142 10
— — -
7E2 NPN Power 15W 80* 175 30* 15T 50 80 7E2 II
7F2 NPN Power 7W 80* 175 30* I5T 50 80 7F2 12
7133 NPN Power 15W 120* 175 12* 15T 50 120 7133 a
7C3 Power 15W 120* 175 12* 15T 50 120 7C:3 9
NPN
7143 NPN Power 15W 120* 175 12* 15T 50 120 7D3 10
7E3 Power 15W 120* I7S 12* 15T 50 120 7E3 11
N l'N
71,3 NPN Power 7W 120* 175 12* 15T 50 120 7F3 12

SNOIIVDMIDadS
61
 61
ABBREVIATIONS
A—Audio NPN-GD—NPN Grown Diffused

SNOLLVDIIIDMS
AF—Audio Frequency Amplifier and General Purpose NPN-M—NPN Mesa
AF Out—High Current AF Output NPN-PL—NPN Planar
AF Sw—Low Frequency Switch NPN-PEP—NPN Planar Epitaxial Passivated
Ampl—Amplifier NPN-PM—NPN Planar Epitaxial Mesa
AS—Audio Signal Osc—High Gain High Frequency 11F Oscillator
C—Case Temperature .
≤25°C PNP-A—PNP Alloyed
Ch—Chopper PNP-D—PNP Diffused
DA —Darlington Amplifier PNP-EM—PNP Epitaxial Mesa
Diff—Differential Amplifier PNP-M—PNP Mesa
GD—Grown Diffused PNP-MD—PNP Micro-Alloyed Diffused
HF—High Frequency Amplifier Pt—Point Contact Types
IF—Intermediate Frequency Amplifier Pwr—Power Output 1Watt or More
Inv—Inverter Pwr Sw—Power Switch
J—Operating Junction Temperature HF—Radio Frequency Amplifier
LoIF—Low IF (262 Kc) Amplifier S—Storage Temperature
LoPA—Low Power Audio Si—Silicon High Temp. Transistors (all others germanium )
LoPO—Low Power Output Sw—High Current, High Frequency Switch
MF --Medium Frequency Amplifier T—Typical Values
Mxr—Mixer UHF—Ultra High Frequency Amplifier
NPN-A—NPN Alloyed UNI —Unijunction Transistor
NPN-D—NPN Diffused VHF—Very High Frequency Amplifier
NPN-EM—NPN Epitaxial Mesa Vid—Video Amplifier
NPN-FA—NPN Fused Alloy W—Watts
NPN-G—NPN Grown

NOTE: Closest GE types are given only as a general guide and are facturing techniques are not identical, the General Electric
based on available published electrical specifications. However, Company makes no claim, nor does it warrant, that its tran-
General Electric Company makes no representation as to the sistors are exact equivalents or replacements for the types
accuracy and completeness of such information. Since manu- referred to.
 CC

20
APPLICATION LITERATURE -
SALES OFFICES 11

APPLICATION NOTES AND ARTICLE REPRINTS

(Atailable Upon Request From Semiconductor Products Department, Aduertis-
ing & Sales Promotion, Building 7, Electronics Park, Syracuse, New York)

PUBLICATION NO. TITLE

90.2 Transistorized Flashers

90.3 Efficient High Quality Program Amplifier Circuits Using The Industrial
Silicon Series 2N2107, 2N2108, and 2N2196

90.5 Silicon Transistor Chopper For High Impedance Sources

90.6 Use of Complementary Transistors in Switching Circuits

90.7 Silicon Transistor Chopper for Low Impedance Sources

90.8 A High Performance Portable Broadcast Receiver Using Silicon

Planar Passivated Transistors

90.9 The Use of Charge Control Parameters

90.10 Notes on the Application of the Silicon Unijunction Transistor

90.12 Unijunction Temperature Compensation

90.13 Some Large Signal Properties of Planar and Planar Epitaxial

Transistors

90.14 Tape Erase and Bias Oscillator

90.15 An Integrated Reference Amplifier For Precision Power Supplies

90.16 Silicon Controlled Switches

90.17 Understanding Snap Diodes

90.20 A Precision Current Supply Using the Reference Amplifier

90.21 How to Suppress Rate Effect in PNPN Devices

General Consideration of Tunnel Diode Amplifiers

Tunnel Diodes as Amplifiers and Switches

90.33 Tunnel Diode Sinewave Oscillators

90.34 A Survey of UHF and Microwave Tunnel Diode Applications

90.36 Predicting Reverse Recovery Time of High Speed Semiconductor

Junction Diodes

90.41 Article: Designing with Tunnel Diodes

90.42 Tunnel Diode UHF-TV Tuner

90.43 A Tunnel Diode R.F. Radiation Detector

90.44 Practical Tunnel Diode Converter Circuit Considerations

90.45 On the Subject of Tunnel Diode Sinewave Oscillators

90.46 Tunnel Diode Remote Control Transmitter

90.47 The Logarithmic and Temperature Coefficient Characteristics of the

1N3605-1N3606 Diodes

90.48 Tunnel Diodes — A Four Part Series

90.80 Microelectronics Using General Electric Emitter-coupled Logic

Operators

643
 20 APPLICATION LITERATURE — SALES OFFICES

GENERAL ELECTRIC SALES OFFICES

Semiconductor Products (transistors, diodes, rectifiers)

CALIFORNIA MICHIGAN TEXAS

Los Angeles 90064 Detroit (Southfield) 48076 Dallas 75205
11840 W. Olympic Blvd. 17220 W. Eight Mile Rd. 4447 N. Central Expressway
Area Code: 213 Area Code: 313 Area Code: 214
GRanite 9-7763 ELgin 6-1075 LA 6-0426
BRadshaw 2-8566
San Diego 92101 VIRGINIA
Room 253,121 Broadway St. MINNESOTA
Minneapolis Lynchburg
Area Code: 714 P.O. Box 4217
234-0329 7710 Computer Ave., Rm. 104
Area Code: 612 (Carroll Ave. Plant)
San Francisco 94304 Area Code: 703
927-5456
(Palo Alto) VI 6-7311
701 Welch Road
Area Code: 415 NEW JERSEY WASHINGTON
DAvenport 1-6771
Clifton (New York City) 07014 Seattle 98108
200 Main Ave. 220 S. Dawson St.
COLORADO Area Code: 201 Area Code: 206
Denver 80201 GRegory 2-8100 PArkway 5-6800
201 University Blvd. (Dial direct from New York
P.O. Box 2331 City Wisconsin 7-4065)
Area Code: 303
DUdley 8-5771
NEW YORK
CONNECTICUT Buffalo 14211 DIRECT
Bridgeport 06602 1495 Fillmore Ave.
Area Code: 716
GOVERNMENT
1285 Boston Ave.
Bldg. 21—ES TX 2-8000 Ext. 205 SALES OFFICES
Area Code: 203 Syosset, L. I., N. Y. 11791
EDison 4-1012 175 Jericho Turnpike ALABAMA
Area Code: 516 Huntsville 35801
DISTRICT OF COLUMBIA WAInut 1-8840 3322 Memorial Parkway
Washington 20005 South, Suite 13
New York City
777-14th St., N.W. Area Code: 205
(Clifton, N. J. 07014)
Area Code: 202 200 Main Ave. 881-1640
EXecutive 3-3600 Area Code: 201
GRegory 2-8100 CALIFORNIA
FLORIDA (Dial direct from New York Los Angeles 90064
Orlando 32806 City Wisconsin 7-4065) 11840 W. Olympic Blvd.
14 W. Gore St. Schenectady 12305 Area Code: 213
Area Code: 305 Building 267 GRanite 9-7763
425-8634 Area Code: 518 BRadshaw 2-8566
FRanklin 4-2211
ILLINOIS Ext. 52339 DISTRICT OF COLUMBIA
Chicago 60641 Syracuse 13201 Washington 20005
3800 N. Milwaukee Ave. Bldg. 7, Electronics Park 777-14th St., N.W.
Area Code :312 Area Code: 315 Area Code: 202
SPring 7-1600 456-2062 EXecutive 3-3600

INDIANA NEW JERSEY

Indianapolis 46200 OHIO Red Bank 07701
3750 N. Meridian St. Cleveland 44121 43 W. Front St.
Area Code: 317 211 S. Green Road Area Code: 201
WAInut 3-7221 Area Code: 216 741-8484
382-5650
Dayton 45402
KENTUCKY 118 W. First St. NEW YORK
Owensboro 42301 Syracuse, N. Y. 13201
Area Code: 513
316 E. 9th St. 223-7151 Bldg. 7, Electronics Park
Area Code: 502 Area Code: 315
683-2401 456-3063
PENNSYLVANIA
MASSACHUSETTS Philadelphia OHIO
Boston (Newtonville) 02160 (Bala Cynwyd) 19004 Dayton 45402
701 Washington St. 1 Belmont Ave., Room 1103 118 W. First St.
Area Code: 617 Area Code: 215 Area Code: 513
DEcatur 2-7120 TEnnyson 9-6075 223-7151

OUTSIDE THE CONTINENTAL Electronic Component Sales IN CANADA

UNITED STATES (EXCLUDING IGE Export Div. Canadian General
HAWAII and ALASKA) 159 Madison Ave. Electric Co.
New York, N. Y. 10016 189 Dufferin St.
Area Code: 212 Toronto, Ontario, Canada
PLaza 1-1311 Area Code: 416
534-6311

644
 APPLICATION LITERATURE - SALES OFFICES 20

AUTHORIZED FULL-LINE GENERAL ELECTRIC

SEMICONDUCTOR DISTRIBUTORS

ALABAMA DELAWARE
Electronic Wholesalers, Inc. Almo Industrial Electronics
2310 Bob Wallace Ave., S.W. 112 French Street
Huntsville, 534-2461 Wilmington, OL 6-9467

DISTRICT OF COLUMBIA
ARKANSAS Silberne Industrial Sales Corp.
Carlton-Bates Co. 3400 Georgia Avenue, N.W.
1210 E. 6th st. TU 2-5000
-ittle Rock

FLORIDA
ARIZONA Electronic Wholesalers
1301 Hibiscus Boulevard
Kierulff Electronics, Inc.
Melbourne, PA 3-1441
917 North Seventh Street
Phoenix, AL 8-6121 Hammond Electronics
911 West Central Blvd.
Orlando, 241-6601

CALIFORNIA
Brill Electronics GEORGIA
610 East Tenth Street Jackson Electronic Supply Co., Inc.
Oakland, TE 4-5888 1135 Chattahoochee Ave., N.W.
Elmar Electronics Atlanta, 355-2223
140 Eleventh Street
Oakland, TE 4-3311
Fortune Electronics ILLINOIS
2280 Palou Avenue Allied Electronics
San Francisco 24, VA 6-8811 100 North Western Avenue
Hollywood Radio & Electronics, Inc. Chicago, TA 9-9100
5250 Hollywood Boulevard Electronic Distributors, Inc.
Hollywood 27, 466-3181 4900 North Elston Avenue
Kierulff Electronics, Inc. Chicago, AV 3-4800
2585 Commerceway Melvin Electronics, Inc.
Los Angeles 22, (213) OV 5-5511 541 Madison Street
Kierulff Electronics, Inc. Oak Park, ES 8-7741
2484 Middlefield Road Newark Electronics Corp.
Mountain View, 968-6292 223 West Madison Street
Radio Products Sales Chicago 6, ST 2-2944
1501 South Hill Street
Los Angeles 15, RI 8-1271
Santa Monica-Bell Electronic Corp. INDIANA
306 E. Alondra Blvd. Brown Electronics, Inc.
Gardena, FA 1-5802 1032 Broadway
Western Radio & TV Supply Fort Wayne, 742-7331
1415 India Street Graham Electronics, Inc.
San Diego, BE 9-0361 122 South Senate Avenue
R. V. Weatherford Co. Indianapolis, ME 4-8486
6921 San Fernando Road
Glendale 1, VI 9-3451
IOWA
Deeco, Inc.
COLORADO 618 First Street, N.W.
Cedar Rapids, EM 5-7551
L. B. Walker Radio Co.
300 Bryant Street
Denver 19, WEst 5-2401
Newark-Denver Electronic Supply Corp.
KANSAS
2170 South Grape Street Interstate Electronics Supply Corp.
Denver, SK 7-3351 230 Ida Street
Wichita, AM 4-6318

CONNECTICUT KENTUCKY
Arrow Electronics P. I. Burks Co.
225 Main Street 659 South Ninth Street
Norwalk, VI 7-2423 Louisville, 583-2871
Cramer Electronics, Inc.
60 Connolly Parkway
Hamden 14, 288-3581 LOUISIANA
Hatry of Hartford Crescent Electronic Supply
100 High Street 537 South Clairborne Avenue
Hartford 3, 527-1881 New Orleans, JA 2-8726

645
 20 APPLICATION LITERATURE - SALES OFFICES

Radio Parts Company NEBRASKA

1112 Magazine St.
New Orleans, 522-0217 Radio Equipment Co.
625 North 18th Street
Omaha, 341-7700
MARYLAND Scott Electronics, Inc.
2201 "0" Street
Almo Industrial Electronics Lincoln, 432-6558
317 Park Heights Avenue
Salisbury, PI 2-1393
Kann-Ellert Electronics, Inc.
2050 Rockrose Avenue NEW JERSEY
Baltimore, TU 9-4242
Wholesale Radio Parts Almo Industrial Electronics
308 W. Redwood Street 1133 Haddon Avenue
Baltimore, MU 5-2134 Camden, EM 5-4524
Atlas Electronics, Inc.
774 Pfeiffer Boulevard
MASSACHUSETTS Perth Amboy, HI 2-8000

Cramer Electronics, Inc. Eastern Radio Corp.

312 Clifton Avenue
320 Needham Street
Newton Upper Falls, WO 9-7700 Clifton, GR 1-6600
T. F. Cushing, Inc. Federated Purchaser, Inc.
1026 Bay Street 155 U.S. Highway 22
P. 0. Box 2049 Springfield, DR 6-8900
Springfield 1, 788-7341 General Radio Supply Co., Inc.
Durrell Electronics, Inc. 600 Penn Street
922 Main Street Camden 2, WO 4-8560
Waltham, 893-7020
Gerber Radio Supply Co., Inc.
1900 Columbus Avenue
Boston, GA 7-0411 NEW MEXICO
Lafayette Industrial Electronics Corp.
Kierulff Electronics, Inc.
1400 Worcester Street
6323 Acoma Road, S.E.
Natick, 969-6100 Albuquerque, AM 8-3901
Midland Specialty Co.
1712 Lomas Blvd., N.E.
MICHIGAN Albuquerque, (505) 247-2486
Electronic Supply Corp.
P.O. Box 430
Battle Creek, Michigan
Enterprise 6379 (For Most Michigan Areas) NEW YORK
Radio Specialties Co. Arrow Electronics, Inc.
12775 Lyndon Avenue 900 Broadhollow Road., Route 110
Detroit 27, BR 2-4212 Farmingdale, L. I., MY 4-6800
Atlas-New York, Inc.
1460 Old Country Road
MINNESOTA Plainview, MY 4-6969

Admiral Distributors, Inc. Eastern Semiconductor Sales, Inc.

5333 Cedar Lake Road Pickard Building
Minneapolis, LI 5-8811 East Molloy Road
Syracuse, (315) 454-9247
Gopher Electronics Co.
2520 W. Larpenteur Ave. Harvey Radio Co., Inc.
St. Paul 13, 645-0241 103 West 43rd Street
New York 36, (212) JU 2-1500
Lew Bonn Company
1211 LaSalle Avenue Milo Electronics Corp.
Minneapolis, 339-9461 530 Canal Street
New York, BE 3-2980
Peerless Radio Distributors, Inc.
19 Wilbur Street
MISSISSIPPI Lynbrook, L. I., LY 3-2121
Ellington Radio, Inc. Rochester Radio Supply Company
824 S. Gallatin Street 140 West Main Street
Jackson, FL 3-7877 Rochester, LO 2-9900
Stack Electronics, Inc.
45 Washington Street
MISSOURI Binghamton, RA 3-6326
Electronic Components for Industry Standard Electronics, Inc.
2605 South Hanley Road 1501 Main Street
St. Louis, MI 7-5505 Buffalo, TT 3-5000
ECI Semiconductors, Inc. Terminal Hudson Electronics, Inc.
3265 Gillham Road 236 West 17th Street
Kansas City, WE 1-0829 New York, CH 3-5200
Radio Lab, Inc. Valley Industrial Electronics, Inc.
1612 Grand Avenue Truck Route 5A
Kansas City, HA 1-0171 Yorkville, RE 6-3393

646
 APPLICATION LITERATURE - SALES OFFICES 20

NORTH CAROLINA TENNESSEE

Electronic Wholesalers, Inc. Bondurant Brothers Co.
938 Burke Street 906 Sevier Avenue
Winston-Salem, 725-8711 Knoxville, 523-9144
Southeastern Radio Supply Co., Inc. Curie Radio Supply Co.
414 Hillsboro Street 439 Broad Street
Raleigh, 828-2311 Chattanooga, 266-4729
Electra Distributing Co.
1914 West End Avenue
Nashville, AL 5-8444
OHIO
Radio Electric Supply Co.
Buckeye Electronic Distributors, Inc. 961 East Sullivan Street
242 East Long Street Kingsport, CI 5-6106
Columbus, CA 8-3265
Hughes-Peters, Inc.
1128 Sycamore Street
Cincinnati, (513) 381-7625 TEXAS
Hughes-Peters, Inc. Lenert Co.
481 East 11th Avenue 1420 Hutchinson
Columbus, AX 4-5351 Houston, CA 4-2663
Newark-Herrlinger Electronics Co. McNicol, Inc.
112 East Liberty Street 811 North Estrella Street
Cincinnati, GA 1-5282 El Paso, LO 6-2936
Pioneer-Standard Electronics, Inc. Sterling Electronics
5403 Prospect Avenue 1616 McKinney Street
Cleveland, 432-0010 Houston, CA 5-1321
Srepco Electronics, Inc. Wholesale Electronic Supply
314 Leo Street 2809 Ross Avenue
Dayton, BA 4-3871 Dallas, TA 4-3001
Warren Radio Co.
1002 Adams Street
Toledo, CH 8-3364
UTAH
OKLAHOMA S. R. Ross, Inc.
1212 South State Street
Oil Capitol Electronics Corp. Salt Lake City, DA 8-0591
708 South Sheridan Street
Tulsa, TE 6-2511
Radio, Inc.
1000 South Main Street VIRGINIA
Tulsa, LU 7-9124
Meridian Electronics, Inc.
Trice Wholesale Electronics 1001 West Broad Street
800 North Hudson Street Richmond, 353-6648
Oklahoma City, JA 4-4411
Peoples Radio & TV Supply Co.
1015 Moorman Road
Roanoke, 342-8933
PENNSYLVANIA Virginia Radio Supply Co.
715 Henry Avenue
Almo Industrial Electronics, Inc. Charlottesville, 296-4184
412 North 6th Street
Philadelphia, WA 2-5918
Atlas Electronics, Inc.
125 Titus Avenue WASHINGTON
Warrington, DI 3-1860
Radio Parts Co. C&G Electronics Co.
6401 Penn Avenue 2600 2nd Avenue
Pittsburgh 6, 361-4600 Seattle, MA 4-4354
Wholesale Radio Parts
1650 Whiteford Road
York, 755-2891
WEST VIRGINIA
Mountain Electronics
708 Bigley Avenue
RHODE ISLAND Charleston, (304) 344-3411
W. H. Edwards Co.
116 Hartford Avenue
Providence, 421-6158
WISCONSIN
Electronic Expeditors, Inc.
3501 Burleigh
SOUTH CAROLINA Milwaukee, UP 1-3000
Dixie Radio Supply Co., Inc. Marsh Radio Supply Co.
1900 Barnwell Street 6047 West Beloit Road
Columbia, 253-5333 West Allis, EV 3-2590
Wholesale Radio Supply Co., Inc. Radio Parts Co.
515 Bay Street 1314 North 7th Street
Charleston, 723-3626 Milwaukee, BR 6-4160

647
20 APPLICATION LITERATURE — SALES OFFICES

OTHER GENERAL ELECTRIC PRODUCT DEPARTMENTS

Cadmium Sulfide Cells

Control Elements G. E. Receiving Tube Department
Magnetic Reed Switches Owensboro, Kentucky
Tubes

G. E. Capacitor Department
Capacitors
Hudson Falls, New York

Silicon Controlled Rectifiers

G. E. Rectifier Components Department
Rectifiers
Auburn, New York
Zener Diodes

G. E. Lamp Department
Lamps
Nela Park, Cleveland, Ohio

C. E. Meter Department
Meters
Somersworth, New Hampshire

G. E. Specialty Motor Department

Motors
Fort Wayne, Indiana

G. E. Specialty Control Department

Relays
Waynesboro, Virginia

Silicone Potting Compounds G. E. Silicone Products Department

Silicone Grease Waterford, New York

C. E. Metallurgical Products Department

Thermistors
Edmore, Michigan

G. E. Specialty Transformer Department

Transformers
Fort Wayne, Indiana

G. E. M'ire and Cable Department

Wire & Cable
Bridgeport, Connecticut

648
 APPLICATION LITERATURE - SALES OFFICES 20

General Electric Semiconductor

TYPE INDEX
TYPE PAGE TYPE PAGE TYPE PAGE TYPE PAGE
Diodes IN774 570 IN3873 564 2N293 551
IN34 568 IN776 570 1N3873/HR 564 2N319 552
1N34A 568 IN777 570 IN4009 564 2N320 552
IN35 568 1N789 562 1N4043 565 2N321 552
IN38 568 IN790 562 1N4090 573 2N322 552
1N38A 568 1N791 562 1N4148 563 2N323 552
1N38B 568 IN793 562 1N4149 563 2N324 552
IN48 568 IN794 562 IN4150 564 2N332 536
IN51 568 IN795 562 IN4151 564 2N332A 536
IN52 568 IN811 562 1N4152 564 2N333 536
1N52A 568 IN812 562 IN4153 564 oN333A 536
1N54 568 IN813 562 1N4154 564 2N334 536
1N54A 568 IN814 562 1N4156 565 2N334A 536
1N56A 569 IN815 563 1N4157 565 2N335 536
IN58 568 1N891 563 1N4305 563 2N335A 536
IN58A 568 1N903 563 IN4306 565 2N335B 536
1N60 .... 570 1N903A 563 IN4307 565 2N336 536
1N60A 570 1N904 563 1N4453 565 2N336A 536
1N60C 570 1N904A 563 IN4454 563 2N337 536
1N63 568 1N905 563 IN4531 563 2N337A 536
1N64 570 1N905A 563 1N4532 563 2N338 536
IN65 568 1N906 563 1N4533 564 2N338A .. . 536
IN67 568 1N906A 563 1N4534 564 2N394 552
1N67A 568 1N907 563 IN4536 564 2N395 552
1N68A 568 1N907A 563 IP541 569 2N396 552
IN69 568 1N908 563 1P542 569 2N396A 552
1N69A 568 1N908A 563 BD-1-7 573 2N397 552
1N70 568 IN914 563 BD-402-406 573 2N404 552
1N70A 568 1N914A 563 KSD101 565 2N404A 552
IN75 568 1N914B 563 MP -1 566 2N413 553
IN81 569 1N915 563 MP-2 566 2N414 553
1N81A 569 IN916 563 MO-! 566 2N461 553
1N90 569 IN916A 563 MQ-2 566 2N470 537
1N96A 569 1N916B 563 SSA-550-557 567 2N47I 537
1N97A 569 IN917 563 TD-1-5 571 2N471A 537
IN98A 569 IN925 563 TD-1A-5A 571 2N472 537
1N99A 569 IN926 563 TD-9 571 2N472A 537
1N100A 569 1N927 563 TD-251-256 . 572 2N473 537
1N1I6 569 IN997 563 TD-251A-256A. 572 2N474 537
1N117A 569 IN2939 571 TD-401-408 572 2N474A 537
IN118A 570 1N2939A 571 RAI 555 2N475 537
IN126 569 IN2940 571 RALA 555 2N475A 537
1N126A 569 1N2940A 571 RA1B 555 2N478 537
1N127 569 IN2941 571 RA1C 555 2N479 537
IN127A 569 1N2941A 571 RA2 555 2N479A 537
IN128 569 IN2969 571 RA2A 555 2N480 537
IN191 569 1N2969A 571 RA2B 555 2N480A 537
1N192 569 1N3062 563 RA3 555 2N489 558
IN198 569 IN3063 563 RA3A 555 2N489A 558
1N198A 569 1N3064 563 RA3B 555 2N489B 558
IN251 562 IN3065 563 2N490 558
IN252 562 1N3066 563 Transistors 2N490A 558
IN273 570 IN3067 563 2N43A 552 2N490B 558
IN279 570 IN3068 564 2N44A 552 2N49I 558
1N281 570 IN3118 573 2N78 551 2N491A 558
IN292 570 IN3124 564 2N78A 551 2N49IB 558
1N295A 570 IN3149 571 2NI67A 551 2N492 558
1N298A 570 1N3149A 571 2N169 551 2N492A 558
1N309 570 1N3150 571 2N169A 551 2N492B 558
IN313 570 IN3206 564 2N186A 552 2N493 558
1N449 570 IN3600 564 2N187A 552 2N493A 558
1N497 570 IN3604 564 2N188A 552 2N493B 558
1N616 570 IN3605 564 2N189 552 2N494 558
IN625 .. . 562 IN3606 564 2N190 552 2N494A 558
1N626 . . 562 IN3607 564 2NI91 552 2N494B 558
1N636 . . 569 1N3608 564 2N192 552 2N494C 558
IN659 . . . 562 1N3609 564 2N241A 552 2N497 539
1N659A 562 IN3712-3721 571 2N292 551 2N497A 539

649
20 APPLICATION LITERATURE - SALES OFFICES

TYPE PAGE TYPE PAGE TYPE PAGE TYPE PAGE

2N498 539 2111145 553 2N2351A 546 2N3082 560
2N498A 539 2N1175 553 2N2352 546 2N3083 560
2N508 553 2N1175A ......553 2N2352A 546 2N3220 542
2N508A 553 2N1248 537 2N2353 546 2N3221 542
2N524 553 2111276 537 2N2353A 547 2N3222 542
2N525 553 2111277 537 2N2356 560 2N3232 542
2N526 553 2N1278 538 2N2356A 560 2N3390 534
2N527 553 2/11279 538 2N2364 547 2N3391 534
2N541 537 2/11303 553 2N2364A 547 2N3391A 534
211542 537 2111305 553 2N2369 550 2N3392 534
2N542A 537 2111307 553 2N2417 558 2N3393 534
2N543 537 2N1413 553 2N2417A 558 2N3394 534
2N543A 537 2N1414 553 2N2417B 558 2N3395 534
2/1656 53 9 2N1415 553 2112418 558 2N3396 534 I
2N656A 53 9 2N1417 538 2N2418A 555r3
5 2NgZ
2N 534
2N657 53 9 2N1418 538 2N2418B 534
2N657A 539 2N1613 548 2N2419 558 2N3402 535
2N696 548 2/11614 553 2N2419A 558 2N3403 535
211697 548 2N1616 542 2N2419B 558 2N3404 535
2/1698 548 2N1617 542 2N2420 558 2N3405 535
2N699 548 2111618 542 2N2420A 558 2N3414 535
2N706 549 2N1671 558 2N2420B 558 2N3415 535
2N706A 549 2N1671A 558 2N2421 558 2113416 535
2N708 549 2N1671B 558 2N2421A 558 2N3417 535
2N709 549 2N1694 551 2N2421B 558 2N3513 561
2N717 548 2N1711 548 2N2422 558 2N3514 561
2N718 548 *N11724 542 2N2422A 558 2N3515 561
2N718A 548 2N1724A 542 2N2422B 558 2N3516 561
2N719 548 2N1725 542 2N2453 561 2N3517 561
2N719A 548 2N1837 548 2N2480 561 2N3518 561
2N720 548 2N1889 543 2N2480A 561 2N3519 561
2N720A 548 2N1890 543 2N2481 550 2N3520 561
2N753 549 2211893 548 2N2483 544 2213521 561
2N759 544 2N1724 542 2N2484 544 2N3522 561
211760 544 2N1925 553 2N2611 541 2N3523 561
2N834 550 2N1926 553 2N2646 559 2N3524 561
2N870 543 2N1972 543 2/12647 559 3N58 556
2N871 543 2N1973 543 2112652 561 3N59 556
2N910 543 *N1974 543 2N2652A 561 3N60 556
2N911 543 2N1975 543 2N2673 538 3N81 557
2N912 543 2N1983 543 2N2674 538 3N82 557
2N914 550 2N1984 543 2N2675 538 3N83 557
2N915 544 2N1985 543 2112676 539 3N84 557
2N916 544 2112017 539 2112677 539 3N85 557
2N917 545 2N2049 543 2112678 539 31186 . . ... 557
2N918 545 2N2060 561 2N2711 534 4C28-4C31 .. . 538
2N929 544 2N2106 539 2N2712 534 4D20-4D26 ... 538
2N930 544 2N2107 539 2N2713 535 4JD12X013 ... 560
2N956 548 2N2108 539 2N2714 535 4JD12X043 .... 547
211997 560 2N2150 542 2/12715 534 4JD12X047 .... 547
2N998 560 2N2151 542 2N2716 534 4JD12X070 ... . 560
2N999 560 2N2160 559 2N2726 539 4JD12X084A ... 561
2N1047 540 2112192 546 2N2727 539 5E35 559
2N1047A 540 2N2192A 546 2N2785 560 5E36 559
2N1047B 540 2N2193 546 2N2840 559 5G514 558
2N1048 540 2N2193A 546 2N2868 547 5G515 558
2N1048A 540 2N2194 546 2N2909 547 5G516 558
2N1048B 540 2N2194A 546 2N2910 561 7A30 540
2N1049 540 2112195 546 2N2913 561 7A31 540
2N1049A 540 2N2195A 547 2N2914 561 7A32 540
2N1049B 540 2N2196 540 2N2915 561 7A35 540
2N1050 540 2N2197 540 2112916 561 7B1 541
2N1050A 540 2N2201 540 2N2917 561 7B2 541
2N1050B 540 2N2202 540 2N2918 561 7B13 541
2N1057 553 2N2203 540 2N2919 561 7B33 541
2N1067 540 2N2204 540 2N2920 561 7B34 541
2N1068 540 2N2223 561 2N2921 534 7C1 541
2N1086 551 2N2239 541 2N2922 534 7C2 541
2N1086A 551 2112243 547 2N2923 534 7C3 541
2N1087 551 2N2243A 547 2N2924 534 7C13 541
2N1097 553 2N2350 546 2112925 534 7D1 541
2111098 553 2N2350A 546 2112926 534 7D2 541
2N1144 553 2N2351 546 2N2995 541 7D3 541

650
 APPLICATION LITERATURE - SALES OFFICES 20
TYPE PAGE TYPE PAGE TYPE PAGE TYPE PAGE
7DI3 541 11C5BI 546 I2P2 566 24J2 566
7D33 541 I1C5F1 546 13P2 566 25J2 566
7D34 541 I1C7B1 547 14P2 566 26J2 566
7E1 541 I1C7F1 547 15P2 566 27J2 566
7E2 541 IICIOB1 547 16GI 534 28J2 566
7E3 541 11C10F1 547 16G2 534 31F2 567
7E13 541 IICIIBI 547 16J1 535 32F2 567
7F1 541 IICIIFI 547 16J2 535 33F2 567
7F2 541 11C201B20 546 16K 535 34F2 567
7F3 541 11C203B20 546 16L2 535 62J2 565
7F4 541 11C205B20 546 16L3 535 63J2 565
7FI3 541 11C207B20 547 16L4 535 64J2 565
7G1 541 11C2I0B20 547 16L22 535 65J2 565
7G2 541 11C2I1B20 547 I6L23 535 66J2 565
7G3 541 I1B551 549 I6L24 535 154T1 554
7GI3 541 I10551 547 I6L25 535 155TI 554
7G33 541 I1B552 549 16L42 535 156T1 554
7G34 542 110553 547 I6L43 535 157TI 554
10B551 550 11B554 549 I6L44 535 159TI 554
10B553 550 11B555 549 161,62 535 160T1 554
10B555 550 1113556 549
16L63 535 16ITI 554
10B556 550 110557 547
100573 545 11B580 549 16L64 535 162TI 554
100574 545 11C702 546 16P2 566 50ITI 554
IICIBI 546 11C704 546 I7P2 566 503TI 554
IICIFI 546 I1C710 r4 7
7 18%
19 566 504TI 554
1IC3B1 546 11C1536 566 505TI 554
11C3FI 546 I2A8 561 2312 566 508TI 554

651
20 APPLICATION LITERATURE - SALES OFFICES

NOTES

652