TPS51222

www.ti.com............................................................................................................................................................................................... SLUS908 – JANUARY 2009

Fixed Frequency, 99% Duty Cycle Peak Current Mode Notebook System Power Controller
1FEATURES
• Input Voltage Range: 4.5 V to 32 V
2 APPLICATIONS
• Output Voltage Range: 1 V to 12 V • Notebook Computer System and I/O Bus
• Selectable Light Load Operation • Point of Load in LCD TV, MFP
(Continuous / Auto Skip / Out-Of-Audio™ Skip)
• Programmable Droop Compensation DESCRIPTION
• Voltage Servo Adjustable Soft Start The TPS51222 is a dual synchronous buck regulator
controller with two LDOs. It is optimized for 5-V/3.3-V
• 200-kHz to 1-MHz Fixed-Frequency PWM
system controller, enabling designers to cost
• Current Mode Architecture effectively complete 2-cell to 4-cell notebook system
• 180° Phase Shift Between Channels power supply. The TPS51222 supports high
• Resistor or Inductor DCR Current Sensing efficiency, fast transient response, and 99% duty
cycle operation. It supports supply input voltage
• Current Monitor Output for Each Channel ranging from 4.5 V to 32 V, and output voltages from
• Adaptive Zero Crossing Circuit 1 V to 12 V. Peak current mode supports stability
• Powergood Output for Each Channel operation with lower ESR capacitor and output
accuracy. The high duty cycle (99%) operation and
• OCL/OVP/UVP/UVLO Protections the wide input/output voltage range supports flexible
• Thermal Shutdown (Non-Latch) design for small mobile PCs and a wide variety of
• Output Discharge Function other applications. The fixed frequency can be
adjusted from 200 kHz to 1 MHz by a resistor, and
• Integrated Boot Strap MOSFET Switch each channel runs 180° out-of-phase. The TPS51222
• QFN-32 (RTV) Package can also synchronize to the external clock, and the
interleaving ratio can be adjusted by its duty. The
TPS51222 is available in the 32-pin 5 × 5 QFN
package and is specified from –40°C to 85°C.

VBAT VBAT
VREG5
5 V/
100 mA VO2
VO1 32 31 30 29 28 27 26 25 3.3 V
5V
DRVL1

VREG5

DRVL2
GND
SW1

VBST1

SW2
VBST

1 DRVH1 DRVH2 24

VO1 2 V5SW VIN 23 VBAT

VREG3
3 RF VREG3 22 3.3 V/
10 mA
EN1 4 EN1 EN2 21 EN2
TPS51222RTV
PGOOD1 5 PGOOD1 PGOOD2 20 PGOOD2

SKIPSEL1 6 SKIPSEL1 SKIPSEL2 19 SKIPSEL2

7 CSP1 CSP2 18
COMP1

COMP2
VREF2
IMON1

IMON2
VFB1

VFB2
EN

8 CSN1 CSN2 17

9 10 11 12 13 14 15 16
EN IMON2
IMON1
VO1 VO2

UDG-09009

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 Out-Of-Audio, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS51222
SLUS908 – JANUARY 2009............................................................................................................................................................................................... www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

EN VIN

V5SW

4.7V/ 4.5V + + 1.25V + + 4.7V/ 4.5V

EN1 OK V5SW OK
VREG5 VREG3
GND

+ V5OK

4.2V/ 3.8V
Ready GND

+
THOK VREF2
150/ 140 GND 1.25V
Deg-C

GND
CLK2
RF OSC
CLK1 GND

1V +5%/ 10% +
PGOOD1

Delay
+

1V -30% + 1V - 5%/ 10%

GND
UVP CLK1

Ready
+ OVP Fault2

1V +15% SDN2

Clamp (+) Fault1

COMP1
Ramp SDN1
Clamp (-) Comp +

+ PWM
VFB1
VREG5
1V +

EN1 VFB-AMP
Enable/ VREF2
Soft-start + VBST1

IMON1 Ramp Control

Filter Amp. Comp + Logic
Skip DRVH1

CSN1 CS-AMP
SW1
+
+ OCP XCON
CSP1
100mV VREG5

DRVL1
AZC

Discharge
Control
GND GND

100mV N-OCP
VREF2 +
OOA GND
Ctrl
SKIPSEL1 GND

Channel-1 Switcher shown

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ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
TPS51222 UNIT
VIN –0.3 to 34
VBST1, VBST2 –0.3 to 39
(3)
VBST1, VBST2 –0.3 to 7

(2)
SW1, SW2 –5 to 34
Input voltage range V
CSN1, CSN2, CSP1, CSP2 –1 to 13.5
EN, EN1, EN2, SKIPSEL1, SKIPSEL2, VFB1, VFB2 –0.3 to 7
V5SW –1 to 7
V5SW (to VREG5) (4) –7 to 7
DRVH1, DRVH2 –5 to 39 V
DRVH1, DRVH2 (3) –0.3 to 7 V
Output voltage range (2) COMP1, COMP2, DRVL1, DRVL2, IMON1, IMON2, PGOOD1,
–0.3 to 7 V
PGOOD2, RF, VREF2, VREG5
VREG3 –0.3 to 3.6 V
TJ Junction temperature 150 °C
Tstg Storage temperature –55 to 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the corresponding SW terminal.
(4) When EN is high and V5SW is grounded, or voltage is applied to V5SW when EN is low.

DISSIPATION RATINGS (2 oz. Trace and Copper Pad with Solder)

TA < 25°C DERATING FACTOR TA = 85°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING
32-pin RTV 1.7 W 17 mW/°C 0.7 W

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT
VIN 4.5 32 V
Supply voltage
V5SW –0.8 6
VBST1, VBST2 –0.1 37
DRVH1, DRVH2 –4.0 37
DRVH1, DRVH2 (wrt SW1, 2) –0.1 6
SW1, SW2 –4.0 32
I/O voltage V
CSP1, CSP2, CSN1, CSN2 –0.8 13
COMP1, COMP2, DRVL1, DRVL2, EN, EN1, EN2, IMON1, IMON2,
PGOOD1, PGOOD2, RF, SKIPSEL1, SKIPSEL2, VFB1, VFB2, –0.1 6
VREF2, VREG5
VREG3 –0.1 3.5
TA Operating free-air temperature –40 85 °C

ORDERING INFORMATION
ORDERABLE PART
TA PACKAGE (1) TRANSPORT MEDIA QUANTITY ECO PLAN
NUMBER
Plastic Quad Flat Pack TPS51222RTVT Tape and Reel 250 Green (RoHS
-40°C to 85°C
(32-Pin QFN) TPS51222RTVR Tape and Reel 3000 and no Sb/Br)

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.

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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN shutdown current, TA = 25°C,
I(VINSDN) VIN shutdown current 7 15 µA
No Load, EN = 0V, V5SW = 0 V
VIN standby current, TA = 25°C, No Load,
I(VINSTBY) VIN Standby Current 80 120 µA
EN1 = EN2 = V5SW = 0 V
Vbat standby current, TA = 25°C, No Load
I(VBATSTBY) Vbat Standby Current 500 µA
SKIPSEL2 = 2V, EN2 = open, EN1 = V5SW = 0V (1)
V5SW current, TA = 25°C, No Load,
I(V5SW) V5SW Supply Current 0.8 mA
ENx = 5V, VFBx = 1.05 V
VREF2 OUTPUT
I(VREF2) < ±10 µA, TA = 25°C 1.98 2.00 2.02
V(VREF2) VREF2 Output Voltage V
I(VREF2) < ±100 µA, 4.5V < VIN < 32 V 1.97 2.00 2.03
VREG3 OUTPUT
V5SW = 0 V, I(VREG3) = 0 mA, TA = 25°C 3.279 3.313 3.347
V(VREG3) VREG3 Output Voltage V5SW = 0 V, 0 mA < I(VREG3) < 10 mA, V
3.135 3.300 3.400
5.5 V < VIN < 32 V
I(VREG3) VREG3 Output Current VREG3 = 3 V 10 15 20 mA
VREG5 OUTPUT
V5SW = 0 V, I(VREG5) = 0 mA, TA = 25°C 4.99 5.04 5.09
V5SW = 0 V, 0 mA < I(VREG5) < 100 mA, V
4.90 5.03 5.15
V(VREG5) VREG5 Output Voltage 6 V < VIN < 32 V
V5SW = 0 V, 0 mA < I(VREG5) < 100 mA,
4.50 5.03 5.15 V
5.5 V < VIN < 32 V
V5SW = 0 V, VREG5 = 4.5 V 100 150 200
I(VREG5) VREG5 Output Current mA
V5SW = 5 V, VREG5 = 4.5 V 200 300 400
Turning on 4.55 4.7 4.8
V(THV5SW) Switchover Threshold V
Hysteresis 0.15 0.20 0.25
td(V5SW) Switchover Delay Turning on 7.7 ms
R(V5SW) 5V SW Ron I(VREG5) = 100 mA 0.5 Ω
OUTPUT

VFB Regulation Voltage TA = 25°C, No Load 0.9925 1.000 1.0075

V(VFB) V
Tolerance TA = –40°C to 85°C , No Load 0.990 1.000 1.010
I(VFB) VFB Input Current VFBx = 1.05 V, COMPx = 1.8 V, TA = 25°C –50 50 nA
R(Dischg) CSNx Discharge Resistance ENx = 0 V, CSNx = 0.5 V, TA = 25°C 20 40 Ω
VOLTAGE TRANSCONDUCTANCE AMPLIFIER
Gmv Gain TA = 25°C 500 µS
Differential Input Voltage
VID –30 30 mV
Range

COMP Maximum Sink TA = 0 to 85°C 27 33 µA

I(COMPSINK) COMPx = 1.8 V
Current TA = –40 to 85°C 22 33 µA
COMP Maximum Source
I(COMPSRC) COMPx = 1.8 V –33 –43 µA
Current
VCOMP COMP Clamp Voltage 2.18 2.22 2.26 V
COMP Negative Clamp
VCOMPN 1.73 1.77 1.81 V
Voltage

(1) Specified by design. Detail external condition follows application circuit of Figure 52.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT AMPLIFIER
GC Gain CSNx = 5V, TA = 25°C (2) 1.667
Common mode Input
VIC 0 13 V
Voltage Range
Differential Input Voltage
VID TA = 25°C –75 75 mV
Range
POWERGOOD
PG in from lower 92.5% 95% 97.5%
V(THPG) PG threshold PG in from higher 102.5% 105% 107.5%
PG hysteresis 5%
I(PG) PG sink Current PGOOD = 0.5 V 5 mA
t(PGDLY) PGOOD Delay Delay for PG in 0.8 1 1.2 ms
SOFTSTART
t(SSDYL) Soft Start Delay Delay for Soft Start, ENx = Hi to SS-ramp starts 200 µs
t(SS) Soft Start Time Internal Soft Start 960 µs
FREQUENCY AND DUTY CONTROL
f(SW) Switching Frequency Rf = 330 kΩ 273 303 333 kHz
Lo to Hi 0.7 1.3 2 V
V(THRF) RF Threshold
Hysteresis 0.2 V
Sync Input Frequency
f(SYNC) 200 1000 kHz
Range (2)
V(DRVH) = 90% to 10%, No Load, CCM/ OOA (2) 120 ns
tONmin Minimum On Time
V(DRVH) = 90% to 10%, No Load, Auto-skip 160 250 ns
tOFFmin Minimum Off Time V(DRVH) = 10% to 90%, No Load 290 400 ns
DRVH-off to DRVL-on 10 30 50 ns
tD Dead time
DRVL-off to DRVH-on 30 40 70 ns
(2)
V(DTH) DRVH-off threshold DRVH to GND 1 V
V(DTL) DRVL-off threshold DRVL to GND (2) 1 V
CURRENT SENSE
TA = 0 to 85°C 56 60 65
2 V< VCSNx < 12.6 V
TA = –40 to 85°C 55 60 68
V(OCL) Current limit threshold mV
TA = 0 to 85°C 55 60 67
0.95 V < VCSNx < 12.6 V
TA = –40 to 85°C 54 60 72

Auto-Zero cross adjustable Positive 5

VZCAJ 0.95 V < VCSNx < 12.6 V, Auto-skip mV
offset range Negative –5
Zero cross detection
V(ZC) 0.95 V < VCSNx < 12.6 V, OOA –4 0 4 mV
comparator Offset

Negative current limit TA = 0 to 85°C –50 –60 –73

V(OCLN-LV) 0.95 V < VCSNx < 12.6 V
threshold TA = –40 to 85°C –49 –60 –77

(2) Specified by design.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT DRIVERS
Source, V(VBST-DRVH) = 0.1 V 1.7 5
R(DRVH) DRVH resistance Ω
Sink, V(DRVH-SW) = 0.1 V 1 3
Source, V(VREG5-DRVL) = 0.1 V 1.3 4
R(DRVL) DRVL resistance Ω
Sink, V(DRVL-GND) = 0.1 V 0.7 2
CURRENT MONITOR
GIMON Current monitor gain 50
VCSPx–VCSNx = 60 mV, 0.95 V < VCSNx < 12.6 V,
VIMON Current monitor output 2.75 3.00 3.25 V
TA = 25°C
VCSPx–VCSNx = 0 mV, 0.95 V < VCSNx < 12.6 V,
VIMON-OFF Current monitor output offset –200 200 mV
TA = 25°C
UVP, OVP AND UVLO
V(OVP) OVP Trip Threshold OVP detect 110% 115% 120%
t(OVPDLY) OVP Prop Delay 1.5 µs
V(UVP) UVP Trip Threshold UVP detect 65% 70% 73%
t(UVPDLY) UVP Delay 0.8 1 1.2 ms
Wake up 1.7 1.8 1.9 V
V(UVREF2) VREF2 UVLO Threshold
Hysteresis 75 100 125 mV
Wake up 3 3.1 3.2
V(UVREG3) VREG3 UVLO Threshold V
Hysteresis 0.10 0.15 0.20
Wake up 4.1 4.2 4.3 V
V(UVREG5) VREG5 UVLO Threshold
Hysteresis 0.35 0.40 0.44 V
INTERFACE AND LOGIC THRESHOLD
Wake up 0.8 1 1.2
V(EN) EN Threshold V
Hysteresis 0.1 0.2 0.3
Wake up 0.45 0.50 0.55
V(EN12) EN1/EN2 Threshold V
Hysteresis 0.1 0.2 0.3
EN1/EN2 SS Start
V(EN12SS) SS-ramp start threshold at external soft start 1 V
Threshold
(3)
V(EN12SSEND) EN1/EN2 SS End Threshold SS-End threshold at external soft start 2 V
I(EN12) EN1/EN2 Source Current VEN1/EN2 = 0V 1.6 2 2.4 µA
Continuous 1.5

SKIPSEL1/SKIPSEL2 Auto Skip 1.9 2.1

V(SKIPSEL) V
Setting Voltage OOA Skip (min 1/8 Fsw) 3.2 3.4
OOA Skip (min 1/16 Fsw) 3.8
SKIPSELx = 0 V –0.5 0.5
I(SKIPSEL) SKIPSEL Input Current µA
SKIPSELx = 5 V –0.5 0.5
BOOT STRAP SW
V(FBST) Forward Voltage VVREG5-VBST, IF = 10 mA, TA = 25°C 0.10 0.20 V
I(BSTLK) VBST Leakage Current VVBST = 37 V, VSW = 32 V 0.01 1.5 µA
THERMAL SHUTDOWN
Shutdown temperature (3) 150
T(SDN) Thermal SDN Threshold °C
Hysteresis (3) 10

(3) Specified by design.

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DEVICE INFORMATION

PINOUT
RTV PACKAGE
(TOP VIEW)

VREG5
DRVL1

DRVL2
VBST1

VBST2
GND
SW1

SW2
32
31
30
29
28
27
26
25
DRVH1 1 24 DRVH2
V5SW 2 23 VIN
RF 3 22 VREG3
EN1 4 TPS51122 21 EN2
PGOOD1 5 20 PGOOD2
SKIPSEL1 6 19 SKIPSEL2
CSP1 7 18 CSP2
CSN1 8 17 CSN2
10

12
13
14
15
16
11
9
VFB1
COMP1

IMON2
VREF2

VFB2
EN

COMP2
IMON1

PIN FUNCTIONS
PIN
I/O DESCRIPTION
NAME NO.
COMP1 10 Loop compensation pin for current mode (error amplifier output). Connect R (and C if required) from this pin
I
COMP2 15 to VREF2 for proper loop compensation with current mode operation.
CSN1 8 Current sense comparator inputs (–). See the current sensing scheme section. Used as power supply for the
I
CSN2 17 current sense circuit for 5 V or higher output voltage setting. Also, used for output discharge terminal.
CSP1 7 Current sense comparator inputs (+). An RC network with high quality X5R or X7R ceramic capacitor should
I/O be used to extract voltage drop across DCR. 0.1-µF is a good value to start the design. See the current
CSP2 18 sensing scheme section for more details.
DRVH1 1 High-side MOSFET gate driver outputs. Source 1.7 Ω, sink 1.0 Ω, SW-node referenced floating driver. Drive
O
DRVH2 24 voltage corresponds to VBST to SW voltage.
DRVL1 30
O Low-side MOSFET gate driver outputs. Source 1.3 Ω, sink 0.7 Ω, and GND referenced driver.
DRVL2 27
VREF2 and VREG5 linear regulators enable pin. When turning on, apply greater than 1.2 V and less than 6
EN 12 I
V. Connect to GND to disable.
EN1 4 Channel 1 and channel 2 SMPS Enable Pins. When turning on, apply greater than 0.55 V and less than 6 V.
I
EN2 21 Connect to GND to disable. Adjustable soft-start capacitance to be attached here.
GND 28 – Ground
IMON1 11
O Current monitor outputs for channel 1 and channel 2. Adding an RC filter is recommended.
IMON2 14
PGOOD1 5 Powergood window comparator outputs for channel 1 and channel 2. The recommended applied voltage
O
PGOOD2 20 should be less than 6 V, and the recommended pull-up resistance value is from 100 kΩ to 1 MΩ.
Frequency setting pin. Connect a frequency setting resistor to (signal) GND. Connect to an external clock for
RF 3 I/O
synchronization.

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PIN FUNCTIONS (continued)

PIN
I/O DESCRIPTION
NAME NO.
SKIPSEL1 6 Skip mode selection pin.
GND: Continuous conduction mode
I VREF2: Auto Skip
SKIPSEL2 19
VREG3: OOA Auto Skip, maximum 7 skips (suitable for fsw < 400kHz)
VREG5: OOA Auto Skip, maximum 15 skips (suitable for equal to or greater than 400kHz)
SW2 25
I/O High-side MOSFET gate driver returns.
SW1 32
VREG5 switchover power supply input pin. When EN1 is high, PGOOD1 indicates GOOD and V5SW
voltage is higher than 4.8 V, switch-over function is enabled.
V5SW 2 I
Note: When switch-over is enabled, VREG5 output voltage is approximately equal to the V5SW input
voltage.
VBST1 31 Supply inputs for high-side N-channel FET driver (boot strap terminal). Connect a capacitor (0.1-µF or
I greater is recommended) from this pin to respective SW terminal. Additional SB diode from VREG5 to this
VBST2 26 pin is an optional.
VFB1 9 SMPS voltage feedback Inputs. Connect the feedback resistors divider, and should be referred to (signal)
I
VFB2 16 GND.
VIN 23 I Supply input for 5-V and 3.3-V linear regulator. Typically connected to VBAT.
VREF2 13 O 2-V reference output. Bypass to (signal) GND with 0.22-µF of ceramic capacitance.
Always alive 3.3 V, 10 mA low dropout linear regulator output. Bypass to (signal) GND with more than 1-µF
VREG3 22 O
ceramic capacitance. Runs from VIN supply or from VREG5 when it is switched over to V5SW input.
5-V, 100-mA low dropout linear regulator output. Bypass to (power) GND using a 10-µF ceramic capacitor.
Runs from VIN supply. Internally connected to VBST and DRVL. Shuts off with EN. Switches over to V5SW
VREG5 29 O when 4.8 V or above is provided.
Note: When switch-over (see above V5SW) is enabled, VREG5 output voltage is approximately equal to
V5SW input voltage.

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TYPICAL CHARACTERISTICS
INPUT VOLTAGE SHUTDOWN CURRENT INPUT VOLTAGE SHUTDOWN CURRENT
vs vs
INPUT VOLTAGE JUNCTION TEMPERATURE

15 15

TA = 25°C VI = 12 V

IVINSDN -– Shutdown Current – mA

IVINSDN -– Shutdown Current – mA

12 12

9 9

6 6

3 3

0 0
5 10 15 20 25 30 -50 0 50 100 150

VI – Input Voltage – V TJ – Junction Temperature – °C

Figure 1. Figure 2.

INPUT VOLTAGE STANDBY CURRENT INPUT VOLTAGE STANDBY CURRENT

vs vs
JUNCTION TEMPERATURE INPUT VOLTAGE

150 150

VI = 12 V TA = 25°C
IVINSTBY – Standby Current – mA

IVINSTBY – Standby Current – mA

120 120

90 90

60 60

30 30

0 0
-50 0 50 100 150 5 10 15 20 25 30

TJ – Junction Temperature – °C VI – Input Voltage – V

Figure 3. Figure 4.

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TYPICAL CHARACTERISTICS (continued)

NO LOAD BATTERY CURRENT NO LOAD BATTERY CURRENT

vs vs
INPUT VOLTAGE INPUT VOLTAGE

1.0 1.0
EN = on EN = on
0.9 0.9
EN1 = off EN1 = on
EN2 = on EN2 = on
0.8 0.8
IVBAT – Battery Current – mA

IVBAT – Battery Current – mA

0.7 0.7

0.6 0.6

0.5 0.5

0.4 0.4

0.3 0.3

0.2 0.2

0.1 0.1

0 0
5 10 15 20 25 5 10 15 20 25

VI – Input Voltage – V VI – Input Voltage – V

Figure 5. Figure 6.

BATTERY CURRENT VREF2 OUTPUT VOLTAGE

vs vs
INPUT VOLTAGE OUTPUT CURRENT

1.0 2.02
EN = on VI = 12 V
0.9
EN1 = on
VVREF2 – VREF2 Output Voltage – V

EN2 = off
0.8
IVBAT – Battery Current – mA

2.01
0.7

0.6

0.5 2.00

0.4

0.3
1.99
0.2

0.1

0 1.98
5 10 15 20 25 –100 –50 0 50 100

VI – Input Voltage – V IVREF2 – VREF2 Output Current – mA

Figure 7. Figure 8.

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TYPICAL CHARACTERISTICS (continued)

VREG3 OUTPUT VOLTAGE VREG5 OUTPUT VOLTAGE

vs vs
OUTPUT CURRENT OUTPUT CURRENT

3.40 5.10
VVREG3 – 3.3-V Linear Regulator Output Voltage – V

VVREG5 – 5-V Linear Regulator Output Voltage – V

VI = 12 V VI = 12 V

3.35 5.05

3.3 5.00

3.25 4.95

3.20 4.90
0 2 4 6 8 10 0 20 40 60 80 100

IREG3 – 3.3-V Linear Regulator Output Current – mA IREG5 – 5-V Linear Regulator Output Current – mA

Figure 9. Figure 10.

SWITCHING FREQUENCY FORWARD VOLTAGE OF BOOST SW

vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE

330 0.25
VFBST – Forward Voltage Boost Voltage – V

RRF = 330 kW
320
fSW – Switching Frequency – kHz

0.20

310
0.15

300

0.10
290

0.05
280

270 0
-50 0 50 100 150 -50 0 50 100 150

TJ – Junction Temperature – °C TJ – Junction Temperature – °C

Figure 11. Figure 12.

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TYPICAL CHARACTERISTICS (continued)

OVP/UVP THRESHOLD VOLTAGE VBST LEAKAGE CURRENT

vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE

150 1.5

OVP
UVP

IBSTLK – VBST Leakage Current – mA

Voltage Protection Threshold – %

130 1.2

110 0.9

90 0.6

70 0.3

50 0
-50 0 50 100 150 -50 0 50 100 150

TJ – Junction Temperature – °C TJ – Junction Temperature – °C

Figure 13. Figure 14.

CURRENT LIMIT THRESHOLD 5-V OUTPUT VOLTAGE

vs vs
JUNCTION TEMPERATURE INPUT VOLTAGE

66 5.2
VCSN (V) Auto-Skip Mode
5.1 fSW = 330 kHz
VOCL – Current Limit Threshold – mV

64 1
5 5.0
VO1 – 5-V Output Voltage – V

12
4.9
62
4.8

60 4.7

4.6
58
4.5
IO (A)
4.4
56 0
4
4.3
8
54 4.2
-50 0 50 100 150 4.5 5.0 5.5 6.0 6.5 7.0

TJ – Junction Temperature – °C VI – Input Voltage – V

Figure 15. Figure 16.

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TYPICAL CHARACTERISTICS (continued)

3.3-V OUTPUT VOLTAGE 5-V EFFICIENCY

vs vs
INPUT VOLTAGE OUTPUT CURRENT

3.40 100
Auto-Skip
Auto-Skip Mode
fSW = 330 kHz
80
VO2 – 3.3-V Output Voltage – V

3.35

h – Efficiency – %
60
OOA CCM
3.30

40

3.25 IO (A)
20 Current Mode
0
4 VI = 12 V
8 RGV = 18 kW

3.20 0
4.5 5.0 5.5 6.0 6.5 7.0 0.001 0.01 0.1 1 10

VI – Input Voltage – V IO1 – 5-V Output Current – A

Figure 17. Figure 18.

5-V EFFICIENCY 3.3-V EFFICIENCY

vs vs
OUTPUT CURRENT OUTPUT CURRENT

100 100
VI = 8 V
Auto-Skip

90 80
VI = 12 V
VI = 20 V
h – Efficiency – %

h – Efficiency – %

80 60 CCM

OOA
70 40

VI = 12 V
60 Auto-Skip 20 Current Mode
Current Mode RGV = 12 kW
RGV = 18 kW 5.0-V SMPS: ON

50 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10

IO1 – 5-V Output Current – A IO2 – 3.3-V Output Current – A

Figure 19. Figure 20.

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TYPICAL CHARACTERISTICS (continued)

3.3-V EFFICIENCY 5-V SWITCHING FREQUENCY

vs vs
OUTPUT CURRENT OUTPUT CURRENT

100 400
CCM
VI = 8 V
350
90

fSW – Switching Frequency – kHz

VI = 12 V VI = 20 V 300
80
h – Efficiency – %

250

70 200

150
60

VI = 12 V 100
OOA
50 Current Mode
RGV = 12 kW 50
5.0-V SMPS: ON
Auto-Skip
40 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10

IO2 – 3.3-V Output Current – A IO1 – 5-V Output Current – A

Figure 21. Figure 22.

3.3-V SWITCHING FREQUENCY 5-V OUTPUT VOLTAGE

vs vs
OUTPUT CURRENT OUTPUT CURRENT

400 5.10
CCM
5.08
350
fSW – Switching Frequency – kHz

5.06 Auto-Skip
VO1 – 5.0-V Output Voltage – V

300
5.04
250
5.02

200 5.00
OOA
4.98
150 CCM

4.96
100
OOA
4.94 VI = 12 V
50 Current Mode
4.92
RGV = 18 kW
Auto-Skip
0 4.90
0.001 0.01 0.1 1 10 0 1 2 3 4 5 6 7 8

IO2 – 3.3-V Output Current – A IO1 – 5-V Output Current – A

Figure 23. Figure 24.

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TYPICAL CHARACTERISTICS (continued)

3.3-V OUTPUT VOLTAGE 5-V OUTPUT VOLTAGE

vs vs
OUTPUT CURRENT OUTPUT CURRENT

3.40 5.10

3.38 5.08
Auto-Skip
3.36 and 5.06 Auto-Skip
VO2 – 3.3-V Output Voltage – V

VO1 – 5.0-V Output Voltage – V

OOA and
3.34 5.04 OOA

3.32 5.02

3.30 5.00

3.28 CCM 4.98

CCM

3.26 4.96 VI = 12 V
Current Mode
3.24 VI = 12 V 4.94 (Non-droop)
Current Mode RGV = 1 kW
3.22 4.92 C = 1.8 nF
RGV = 12 kW
3.20 4.90
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8

IO2 – 3.3-V Output Current – A IO1 – 5-V Output Current – A

Figure 25. Figure 26.

3.3-V OUTPUT VOLTAGE 5.0-V BODE-PLOT – GAIN AND PHASE

vs vs
OUTPUT CURRENT FREQUENCY

3.40 80 180
Phase
3.38 60 135
Auto-Skip
3.36 and
VO2 – 3.3-V Output Voltage – V

40 90
OOA
3.34
20 45
Gain – dB

Phase – °
3.32
Gain
0 0
3.30
–20 45
3.28 CCM
–40 –90
3.26 VI = 12 V VO= 5.0 V
Current Mode VI = 12 V
3.24 (Non-droop) –60 –135
IO = 8 A
RGV = 9.1 kW
3.22 C = 1.8 nF –80 –180
100 1k 10 k 100 k 1M
3.20
f – Frequency – Hz
0 1 2 3 4 5 6 7 8

IO2 – 3.3-V Output Current – A

Figure 27. Figure 28.

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TYPICAL CHARACTERISTICS (continued)

3.3-V BODE-PLOT – GAIN AND PHASE

vs
FREQUENCY 5.0-V SWITCH-OVER WAVEFORMS
80 180
Phase
60 135

40 90

20 45 VREG5 (100 mV/div)

Gain – dB

Phase – °
Gain
0 0
VO1 (100 mV/div)
–20 45

–40 –90
VO= 3.3 V
–60 VI = 12 V –135
IO = 8 A 2 ms/div

–80 –180
100 1k 10 k 100 k 1M

f – Frequency – Hz

Figure 29. Figure 30.

CURRENT MONITOR VOLTAGE

vs
OUTPUT CURRENT

3.0

2.5
VIMONx – Output Voltage – V

2.0

VIMON1
1.5

1.0
VIMON2

0.5

0
0 2 4 6 8 10 12

IOUTx – Output Current – A

Figure 31.

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TYPICAL CHARACTERISTICS
5.0-V START-UP WAVEFORMS 3.3-V START-UP WAVEFORMS

EN2 (5V/div)
EN1 (5V/div)

Vout1 (2V/div)
Vout2 (2V/div)

PGOOD2 (5V/div)

PGOOD1 (5V/div) 1msec/div

1msec/div

Figure 32. Figure 33.

5.0-V SOFT-STOP WAVEFORMS 3.3-V SOFT-STOP WAVEFORMS

EN1 (5V/div) EN2 (5V/div)

Vout1 (2V/div) Vout2 (2V/div)

PGOOD1 (5V/div) PGOOD2 (5V/div)

1msec/div 1msec/div

Figure 34. Figure 35.

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TYPICAL CHARACTERISTICS (continued)

5.0-V LOAD TRANSIENT RESPONSE 3.3-V LOAD TRANSIENT RESPONSE

VI=12V, Auto-skip VI =12V, Auto-skip

VO1 (100mV/div) VO2 (100mV/div)

SW1 (10V/div) SW2 (10V/div)

100
100 mms/div
s/div IO1 (5A/div)
100 IO2 (5A/div)
100 mms/div
s/div

Figure 36. Figure 37.

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DETAILED DESCRIPTION

ENABLE AND SOFT START

When EN is Low, the TPS51222 is in the shutdown state. Only the 3.3-V LDO stays alive, and consumes 7 µA
(typically). When EN becomes High, the TPS51222 is in the standby state. The 2-V reference and the 5-V LDO
become enabled, and consume about 80 µA with no load condition, and are ready to turn on SMPS channels.
Each SMPS channel is turned on when ENx becomes High. After ENx is set to high, the TPS51222 begins the
softstart sequence, and ramps up the output voltage from zero to the target voltage in 0.96 ms. However, if a
slower soft-start is required, an external capacitor can be tied from the ENx pin to GND. In this case, the
TPS51222 charges the external capacitor with the integrated 2-µA current source. An approximate external
soft-start time would be tEX-SS = CEX / IEN12, which means the time from ENx = 1 V to ENx = 2 V. The recommend
capacitance is more than 2.2 nF.

1) Internal
Soft-start

EN1

Vout1
200ms
960ms
EN1>1V EN1<2V
2) External
Soft-start

EN1

Vout1 External
Soft-start
time
Figure 38. Enable and Soft-start Timing

Table 1. Enable Logic States

EN EN1 EN2 VREG3 VREF2 VREG5 CH1 CH2
GND Don’t Care Don’t Care ON Off Off Off Off
Hi Lo Lo ON ON ON Off Off
Hi Hi Lo ON ON ON ON Off
Hi Lo Hi ON ON ON Off ON
Hi Hi Hi ON ON ON ON ON

3.3-V, 10-mA LDO (VREG3)

A 3.3-V, 10-mA, linear regulator is integrated in the TPS51222. This LDO services some of the analog circuit in
the device and provides a handy standby supply for 3.3-V Always On voltage in the notebook system. Apply a
2.2-µF (at least 1-µF), high quality X5R or X7R ceramic capacitor from VREG3 to (signal) GND in adjacent to the
device.

2-V, 100-µA Sink/Source Reference (VREF2)

This voltage is used for the reference of the loop compensation network. Apply a 0.22-µF (at least 0.1-µF),
high-quality X5R or X7R ceramic capacitor from VREF2 to (signal) GND in adjacent to the device.

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5.0-V, 100-mA LDO (VREG5)

A 5.0-V, 100-mA, linear regulator is integrated in the TPS51222. This LDO services the main analog supply rail
and provides the current for gate drivers until switch-over function becomes enable. Apply a 10-µF (at least
4.7-µF), high-quality X5R or X7R ceramic capacitor from VREG5 to (power) GND in adjacent to the device.

VREG5 SWITCHOVER
When EN1 is high, PGOOD1 indicates GOOD and a voltage of more than 4.8 V is applied to V5SW, the internal
5V-LDO is shut off and the VREG5 is shorted to V5SW by an internal MOSFET after an 7.7-ms delay. When the
V5SW voltage becomes lower than 4.65 V, EN1 becomes low, or PGOOD1 indicates BAD, the internal switch is
turned off, and the internal 5V-LDO resumes immediately.

BASIC PWM OPERATIONS

The main control loop of the SMPS is designed as a fixed frequency, peak current mode, pulse width modulation
(PWM) controller. It achieves stable operation with any type of output capacitors, including low ESR capacitor(s)
such as ceramic or specialty polymer capacitors.
The current mode scheme uses the output voltage information and the inductor current information to regulate
the output voltage. The output voltage information is sensed by VFBx pin. The signal is compared with the
internal 1-V reference and the voltage difference is amplified by a transconductance amplifier (VFB-AMP). The
inductor current information is sensed by CSPx and CSNx pins. The voltage difference is amplified by another
transconductance amplifier (CS-AMP). The output of the VFB-AMP indicates the target peak inductor current. If
the output voltage decreases, the TPS51222 increases the target inductor current to raise the output voltage.
Alternatively, if the output voltage rises, the TPS51222 decreases the target inductor current to reduce the output
voltage.
At the beginning of each clock cycle, the high-side MOSFET is turned on, or becomes ‘ON’ state. The high-side
MOSFET is turned off, or becomes OFF state, after the inductor current becomes the target value which is
determined by the combination value of the output of the VFB-AMP and a ramp compensation signal. The ramp
compensation signal is used to prevent sub-harmonic oscillation of the inductor current control loop. The
high-side MOSFET is turned on again at the next clock cycle. By repeating the operation in this manner, the
controller regulates the output voltage. The synchronous low-side or the rectifying MOSFET is turned on each
OFF state to keep the conduction loss minimum.

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PWM FREQUENCY CONTROL

The TPS51222 has a fixed frequency control scheme with 180° phase shift. The switching frequency can be
determined by an external resistor which is connected between RF pin and GND, and can be calculated using
Equation 1.
1 × 105
fsw éëkHz ùû =
RF éëkΩ ùû (1)
TPS51222 can also synchronize to more than 2.5 V amplitude external clock by applying the signal to the RF
pin. The set timing of channel 1 initiates at the raising edge (1.3 V typ) of the clock and channel 2 initiates at the
falling edge (1.1 V typ). Therefore, the 50% duty signal makes both channels 180° phase shift.
1000

900

800

700
fSW - Frequency - kHz

600

500

400

300

200

100

0
100 200 300 400 500
RF - Resistance - kW

Figure 39. Switching Frequency vs RF

LIGHT LOAD OPERATION

The TPS51222 automatically reduces switching frequency at light load conditions to maintain high efficiency if
Auto Skip or Out-of-Audio™ mode is selected by SKIPSELx. This reduction of frequency is achieved by skipping
pulses. As the output current decreases from heavy load condition, the inductor current is also reduced and
eventually comes to the point that its peak reaches a predetermined current, ILL(PEAK), which indicates the
boundary between heavy-load condditions and light-load conditions. Once the top MOSFET is turned on, the
TPS51222 does not allow it to be turned off until it reaches ILL(PEAK). This eventually causes an overvoltage
condition to the output and pulse skipping. From the next pulse after zero-crossing is detected, ILL(PEAK) is limited
by the ramp-down signal ILL(PEAK)RAMP, which starts from 25% of the overcurrent limit setting (IOCL(PEAK): (see the
Current Protection section) toward 5% of IOCL(PEAK) over one switching cycle to prevent causing large ripple. The
transition load point to the light load operation ILL(DC) can be calculated in Equation 2.
I LL(DC) + I LL(PEAK) * 0.5 I IND(RIPPLE)
(2)
1 (V - VOUT ) × VOUT
IIND(RIPPLE) = × IN
L × fSW VIN (3)
where
• fSW is the PWM switching frequency which is determined by RF resistor setting or external clock

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ILL(PEAK)RAMP = (0.2 - 0.13 ´ tON ´ fSW )´ t ´ IOCL(PEAK )

(4)
Switching frequency versus output current in the light load condition is a function of L, f, VIN and VOUT, but it
decreases almost proportionally to the output current from the ILL(DC), as described in Equation 2; while
maintaining the switching synchronization with the clock. Due to the synchronization, the switching waveform in
boundary load condition (close to ILL(DC)) appears as a sub-harmonic oscillation; however, it is the intended
operation.
If SKIPSELx is tied to GND, the TPS51222 works on a constant frequency of fSW regardless its load current.

Inductor
Current

ILL(PEAK)

ILL(DC) IIND(RIPPLE)

0 Time
Figure 40. Boundary Between Pulse Skipping and CCM
ILL(peak) – Inductor Current Limit – A

20% of IOCL ILL(PEAK) Ramp Signal

ILL(PEAK) at
Light Load

7% of IOCL
tON
1/fSW

t – Time

Figure 41. Inductor Current Limit at Pulse Skipping

Table 2. Skip Mode Selection

SKIPSELx GND VREF2 VREG3 VREG5
OOA Skip (maximum 7 OOA Skip (maximum 15 skips, for
OPERATING MODE Continuous Conduction Auto Skip
skips, for <400 kHz) equal to or greater than 400kHz)

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OUT OF AUDIO SKIP OPERATION

Out-Of-Audio™ (OOA) light-load mode is a unique control feature that keeps the switching frequency above
acoustic audible frequencies toward virtually no load condition while maintaining state-of-the-art high conversion
efficiency. When OOA is selected, the switching frequency is kept higher than audible frequency range in any
load condition. The TPS51222 automatically reduced switching frequency at light-load conditions. The OOA
control circuit monitors the states of both MOSFETs and forces an ON state if the predetermined number of
pulses are skipped. The high-side MOSFET is turned on before the output voltage declines down to the target
value, so that eventually an overvoltage condition is caused. The OOA control circuit detects this overvoltage
condition and begins modulating the skip-mode on time to keep the output voltage.
The TPS51222 supports a wide-switching frequency range, therefore, the OOA skip mode has two selections.
See Table 2. When the 300-kHz switching frequency is selected, a maximum of seven (7) skips (SKIPSEL=3.3
V) makes the lowest frequency at 37.5 kHz. If a 15-skip maximum is chosen, it becomes 18.8 kHz, hence the
maximum 7 skip is suitable for less than 400 kHz, and the maximum 15 skip is 400 kHz or greater.

99% DUTY CYCLE OPERATION

In a low-dropout condition such as 5-V input to 5-V output, the basic control loop attempts to maintain 100% of
the high-side MOSFET ON. However, with the N-channel MOSFET used for the top switch, it is not possible to
use the 100% on-cycle to charge the boot strap capacitor. TPS51222 detects the 100% ON condition and
asserts the OFF state at the appropriate time.

HIGH-SIDE DRIVER
The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance, which is 1.7Ω for VBSTx to DRVHx, and 1Ω for DRVHx to SWx. When
configured as a floating driver, 5 V of bias voltage is delivered from VREG5 supply. The instantaneous drive
current is supplied by the flying capacitor between VBSTx and SWx pins. The average drive current is equal to
the gate charge at Vgs = 5V times switching frequency. This gate drive current as well as the low-side gate drive
current times 5 V makes the driving power which needs to be dissipated mainly from TPS51222 package. A
dead time to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET
on, and low-side MOSFET off to high-side MOSFET on.

LOW-SIDE DRIVER
The low-side driver is designed to drive high-current low-RDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance, which are 1.3Ω for VREG5 to DRVLx and 0.7Ω for DRVLx to GND. The
5-V bias voltage is delivered from VREG5 supply. The instantaneous drive current is supplied by an input
capacitor connected between VREG5 and GND. The average drive current is also calculated by the gate charge
at Vgs = 5 V times switching frequency.

CURRENT SENSING SCHEME

In order to provide both good accuracy and cost effective solution, the TPS51222 supports external resistor
sensing and inductor DCR sensing. An RC network with high quality X5R or X7R ceramic capacitor should be
used to extract voltage drop across DCR. 0.1µF is a good value to start the design. CSPx and CSNx should be
connected to positive and negative terminal of the sensing device respectively. The output signal of the internal
current amplifier becomes 100 mV at the OCL setting point. This means that the current sensing amplifier
normalize the current information signal based on the OCL setting. Attaching a RC network recommended even
with a resistor sensing scheme to get an accurate current sensing; see the External Components Selection
session for detailed configurations.

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ADAPTIVE ZERO CROSSING

TPS51222 has an adaptive zero crossing circuit which performs optimization of the zero inductor current
detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and
compensates inherent offset voltage of the ZC comparator and delay time of the ZC detection circuit. It prevents
SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too early
detection. As a result, better light load efficiency is delivered.

CURRENT PROTECTION
TPS51222 has cycle-by-cycle overcurrent limiting control. If the inductor current becomes larger than the
overcurrent trip level, TPS51222 turns off high-side MOSFET, turns on low-side MOSFET and waits for the next
clock cycle.
IOCL(PEAK) sets peak level of the inductor current. Thus, the dc load current at overcurrent threshold, IOCL(DC), can
be calculated as follows;
I OCL(DC) + I OCL(PEAK) * 0.5 I IND(RIPPLE)
(5)
VOCL
I OCL(PEAK) +
RSENSE (6)
where
• RSENSE is resistance of current sensing device
• V(OCL) is the overcurrent trip threshold voltage
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down, and it ultimately crosses the undervoltage protection threshold and shutdown.

POWERGOOD
The TPS51222 has powergood output for both switcher channels. The powergood function is activated after
softstart has finished. If the output voltage becomes within ±5% of the target value, internal comparators detect
power good state and the powergood signal becomes high after 1ms internal delay. If the output voltage goes
outside of ±10% of the target value, the powergood signal becomes low after 1.5µs internal delay. Apply voltage
should be less than 6V and the recommended pull-up resistance value is from 100kΩ to 1MΩ.

OUTPUT DISCHARGE CONTROL

The TPS51222 discharges output when ENx is low. The TPS51222 discharges outputs using an internal
MOSFET which is connected to CSNx and GND. The current capability of these MOSFETs is limited to
discharge the output capacitor slowly. If ENx becomes high during discharge, MOSFETs are turning off, and
some output voltage remains. SMPS changes over to soft-start. The PWM initiates after the target voltage
overtakes the remaining output voltage.

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OVERVOLTAGE/UNDERVOLTAGE PROTECTION
TPS51222 monitors the output voltage to detect overvoltage and undervoltage. When the output voltage
becomes 15% higher than the target value, the OVP comparator output goes high and the circuit latches as the
high-side MOSFET driver OFF and the low-side MOSFET driver ON, and shuts off another channel.
When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After 1 ms, TPS51222 latches OFF both high-side and
low-side MOSFETs, and shuts off another channel. This UVP function is enabled after soft-start has completed.
The procedure for restarting from these protection states is:
1. toggle EN
2. toggle EN1 and EN2 or
3. once hit UVLO

UVLO PROTECTION
The TPS51222 has undervoltage lockout protections (UVLO) for VREG5, VREG3 and VREF2. When the voltage
is lower than UVLO threshold voltage, TPS51222 shuts off each output as shown inTable 3. This is non-latch
protection.

Table 3. UVLO Protection

CH1/ CH2 VREG5 VREG3 VREF2
VREG5 UVLO Off — On On
VREG3 UVLO Off Off — Off
VREF2 UVLO Off Off On —

THERMAL SHUTDOWN
The TPS51222 monitors the device temperature. If the temperature exceeds the threshold value, TPS51222
shuts off both SMPS and 5V-LDO, and decreases the VREG3 current limitation to 5 mA (typically). This is
non-latch protection.

CURRENT MONITOR
TPS51222 monitors the output current as the voltage difference between CSPx and CSNx terminal. The
transconductance amplifier (CS-AMP) amplifies this differential voltage by 50 times and sends out from IMONx
thermal. Adding RC filter is recommended.

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APPLICATION INFORMATION

EXTERNAL COMPONENTS SELECTION

A buck converter using the TPS51222 consists of linear circuits and a switching modulator. Figure 42 shows the
basic scheme.
Voltage divider

VIN
Ramp Switching Modulator
R1
comp.
DRVH
VFB Gmv Lx
PWM Rs
Control
+ logic
R2 +
&
+ + Driver DRVL
1.0V ESR

RL

COMP Co

Cc Rgv Gmc CSP

Rgc
+

VREF +
2.0V CSN

Error Amplifier

Figure 42. Simplified Current Mode Functional Blocks

The external components can be selected by following manner.

1. Determine output voltage dividing resistors (R1 and R2: shown in Figure 42) using the next equation
R1 + ǒV OUT * 1.0Ǔ R2
(7)
2. Determine switching frequency. Higher frequency allows smaller output capacitances, however, degrade
efficiency due to increase of switching loss. Frequency setting resistor for RF-pin can be calculated by;
RF[kW] + 1 10
5

ƒ sw [kHz] (8)
3. Choose the inductor. The inductance value should be determined to give the ripple current of
approximately 25% to 50% of maximum output current. Recommended ripple current rate is about 30% to
40% at the typical input voltage condition, next equation uses 33%.
1 (VIN(TYP) - VOUT ) × VOUT
L= ×
0.33 x IOUT(MAX) x fSW VIN(TYP)
(9)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation.
4. Determine the sensing resistor.
Determine the sensing resistor using next equation. IOCL(PEAK) should be approximately 1.5 × IOUT(MAX) to
1.7 × IOUT(MAX).
VOCL
R SENSE +
I OCL(PEAK)
(10)
5. Determine Rgv. Rgv should be determined from preferable droop compensation value and is given by next
equation based on the typical number of Gmv = 500µS.

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 TPS51222
www.ti.com............................................................................................................................................................................................... SLUS908 – JANUARY 2009

I OUT(MAX)
Rgv + 0.1 VOUT 1
I OCL(PEAK) Gmv Vdroop
(11)
I OUT(MAX) V OUT[V]
Rgv[kW] + 200
I OCL(PEAK) Vdroop[mV]
(12)
If no-droop is preferred, attach a series RC network circuit instead of single resistor. Series resistance is
determined using Equation 12 . Series capacitance can be arbitrarily chosen to meet the RC time constant,
but should be kept under 1/10 of fo.
6. Determine output capacitance Co to achieve a stable operation using the next equation. The 0 dB frequency,
fo, should be kept under 1/3 of the switching frequency.
Gmv Rgv ƒsw
ƒ0 + 5p I OCL(PEAK) V
1 t
OUT Co 3 (13)
Gmv Rgv
Co u 15 I OCL(PEAK) 1
p VOUT ƒsw (14)
7. Calculate Cc. The purpose of this capacitance is to cancel zero caused by ESR of the output capacitor. If
ceramic capacitor(s) is used, there is no need for Cc. If a combination of different capacitors is used, attach a
RC network circuit instead of single capacitance to cancel zeros and poles caused by the output capacitors.
With single capacitance, Cc is given in Equation 15.
Cc + Co ESR
Rgv (15)
8. Choose MOSFETs Generally, the on resistance affects efficiency at high load conditions as conduction loss.
For a low output voltage application, the duty ratio is not high enough so that the on resistance of high-side
MOSFET does not affect efficiency; however, switching speed (tr and tf) affects efficiency as switching loss.
As for low-side MOSFET, the switching loss is usually not a main portion of the total loss.

RESISTOR CURRENT SENSING

For more accurate current sensing with an external resistor, the following technique is recommended. Adding an
RC filter to cancel the parasitic inductance of resistor, this filter value is calculated using Equation 16.
Cx Rx + Lx
Rs (16)
This equation means time-constant of Cx and Rx should match the one of Lx (ESL) and Rs.
VIN

Ex-resistor
DRVH
L Lx(ESL)
Rs
Control
logic
&
Driver DRVL

Co

CSP
+
Cx Rx

CSN

Figure 43. External Resistor Current Sensing

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TPS51222
SLUS908 – JANUARY 2009............................................................................................................................................................................................... www.ti.com

INDUCTOR DCR CURRENT SENSING

To use inductor DCR as current sensing resistor (Rs), the configuration needs to change as below. However, the
equation that must be satisfied is the same as the one for the resistor sensing.
VIN

Inductor
DRVH
Lx
Rs(DCR)
Control
logic
&
Driver DRVL

Co
Rx
CSP
+
Cx

CSN

Figure 44. Inductor DCR Current Sensing

VIN

Inductor
DRVH
Lx
Rs(DCR)
Control
logic
&
Driver DRVL

Co
Rx
CSP
+
Cx Rc

CSN

Figure 45. Inductor DCR Current Sensing With Voltage Divider

TPS51222 has a fixed V(OCL) point (60 mV). In order to adjust for DCR, a voltage divider can be configured a
described in Figure 45.
For Rx, Rc and Cx can be calculated as shown below, and overcurrent limitation value can be calculated as
follows:
Lx
Cx ´ (Rx P Rc ) =
Rs (17)
I OCL(PEAK) + VOCL 1 Rx ) Rc
Rs Rc (18)
Figure 46 shows the compensation technique for the temperature drifts of the inductor DCR value. This scheme
assumes the temperature rise at the thermistor (RNTC) is directly proportional to the temperature rise at the
inductor.

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 TPS51222
www.ti.com............................................................................................................................................................................................... SLUS908 – JANUARY 2009

Inductor

Lx
Rs(DCR)

RNTC
Rx
Rc1
Rc2
CO

CSP
+
Cx
CSN

Figure 46. Inductor DCR Current Sensing With Temperature Compensate

LAYOUT CONSIDERATIONS
Certain points must be considered before starting a PCB layout work using the TPS51222.
Placement
• Place RC network for CSP1 and CSP2 close to the device pins.
• Place bypass capacitors for VREG5, VREG3 and VREF2 close to the device pins.
• Place frequency-setting resistor close to the device pin.
• Place the compensation circuits for COMP1 and COMP2 close to the device pins.
• Place the voltage setting resistors close to the device pins.
Routing (sensitive analog portion)
• Use separate traces for; see Figure 47
– Output voltage sensing from current sensing (negative-side)
– Output voltage sensing from V5SW input (when VOUT = 5V)
– Current sensing (positive-side) from switch-node

V5SW
R1
VFB
R2

H-FET Inductor
Vout
SW

L-FET
Cout

R
CSP
C

CSN

Figure 47. Sensing Trace Routings

• Use Kelvin sensing traces from the solder pads of the current sensing device (inductor or resistor) to current

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TPS51222
SLUS908 – JANUARY 2009............................................................................................................................................................................................... www.ti.com

sensing comparator inputs (CSPx and CSNx). (See Figure 48)

Current sensing
Device

RC network
next to IC

Figure 48. Current Sensing Traces

• Use small copper space for VFBx. These are short and narrow traces to avoid noise coupling
• Connect VFB resistor trace to the positive node of the output capacitor.
• Use signal GND for VREF2 and VREG3 capacitors, RF and VFB resistors, and the other sensitive analog
components. Placing a signal GND plane (underneath the IC, and fully covered peripheral components) on
the internal layer for shielding purpose is recommended. (See Figure 49)
• Use a thermal land for PowerPAD™. Five or more vias, with 0.33-mm (13-mils) diameter connected from the
thermal land to the internal GND plane, should be used to help dissipation. Do NOT connect the GND-pin to
this thermal land on the surface layer, underneath the package.
Routing (power portion)
• Use wider/shorter traces of DRVL for low-side gate drivers to reduce stray inductance.
• Use the parallel traces of SW and DRVH for high-side MOSFET gate drive, and keep them away from DRVL.
• Connect SW trace to source terminal of the high-side MOSFET.
• Use power GND for VREG5, VIN and VOUT capacitors and low-side MOSFETs. Power GND and signal GND
should be connected near the device GND terminal. (See Figure 49)

0W resistor
GND
#28
GND-pin
To inner To inner
Power-GND Signal-GND
layer plane
Inner Signal-GND plane

Figure 49. GND Layout Example

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Product Folder Link(s) :TPS51222

 VREG5
VBAT VBAT
5V/100mA
Q11
C12 Q21
C01 C22
C14 R16 10mF R26 C24
L1 L2
0.1mF 4.7W 4.7 W 0.1mF
PGND
APPLICATION CIRCUITS

PGND
VO1 VO2
Q12 PGND GND
5.0V/8A 3.3V/8A
PGND
Q22
C11

Copyright © 2009, Texas Instruments Incorporated

C21
32 31 30 29 28 27 26 25

PGND PGND PGND PGND

SW1
GND
SW2
1 24

VBST1
VBST2

DRVL1
DRVL2

VREG5
DRVH1 DRVH2
VO1 2 V5SW VIN 23 VBAT
R01
300kW
3 22 VREG3
RF VREG3 3.3V/10mA
C03
2.2mF
GND EN1 4 EN1 EN2 21 EN2
TPS51222RTV
(QFN32)
PGOOD1 5 PGOOD1 PGOOD2 20 PGOOD2
GND

SKIPSEL1 6 SKIPSEL1 SKIPSEL2 19 SKIPSEL2

R14 R24
7.5k W PowerPAD 6.8k W
7 CSP1 CSP2 18
R15 C13 C23 R25

Product Folder Link(s) :TPS51222

4.3k W 0.1 mF 0.1 mF 4.3kW
8
CSN1 CSN2 17

VFB1
COMP1
IMON1
EN
VREF2
IMON2
COMP2
VFB2

EN
R03
9 10 11 12 13 14 15 16 10kW
R02 GND
10kW IMON2
IMON1 VREF2 R21
62kW C05
C02 0.1 mF
C04 VO1 VO2
R13 0.22mF
0.1mF R11 C25
R12 18kW R23 R22
120k W C15 220p F
30kW 12kW 27kW GND
100p F
VREF2
GND GND VREF2

Figure 50. Current Mode, DCR Sensing, 5.0-V/8-A, 3.3-V/8-A, 330-kHz

GND GND

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31
TPS51222
TPS51222
SLUS908 – JANUARY 2009............................................................................................................................................................................................... www.ti.com

Table 4. Current Mode, DCR Sensing, 5.0-V/8-A, 3.3-V/8-A, 330-kHz

SYMBOL SPECIFICATION MANUFACTURER PART NUMBER
C11 2 × 330 µF, 6.3 V, 18 mΩ Sanyo 6TPE330MIL
C12 2 × 10 µF, 25 V Murata GRM32DR71E106K
C21 470 µF, 4.0V, 15 mΩ Sanyo 4TPE470MFL
C22 2 × 10 µF, 25 V Murata GRM32DR71E106K
L1 3.3 µH, 10.7 A, 10.5 mΩ TOKO FDV1040-3R3M
L2 3.3 µH, 10.7 A, 10.5 mΩ TOKO FDV1040-3R3M
Q11, Q21 30-V, 12 A, 10.5 mΩ Fairchild FDMS8692
Q12, Q22 30 V, 18 A, 5.4 mΩ Fairchild FDMS8672AS

32 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s) :TPS51222

 TPS51222
www.ti.com............................................................................................................................................................................................... SLUS908 – JANUARY 2009

3.3V/8A
VO2

3.3V/10mA
VREG3
VBAT
C21

PGND

IMON2
VBAT

L2

0.1 mF
C05

GND
C22

6.8k W
2.2mF

R24
C03
PGND

10kW
GND

R03
4.3kW

VO2
R25
Q22
Q21

SKIPSEL2
PGND

PGOOD2
EN2

0.1 mF
C23

62kW
R21

27kW
R22

GND
24

23

22

21

20

19

18

17
SKIPSEL2
0.1mF

VREG3

PGOOD2
DRVH2

CSN2
EN2

CSP2
VIN
C24

SW2
25

16

1.8nF
VFB2

C25
9.1kW
R23
4.7 W
R26

VBST2 COMP2
26

15
GND

VREF2

VREF2
0.22mF
DRVL2 IMON2
27

14

C02
TPS51222RTV
PGND

(QFN32)

GND
GND VREF2
28

13
PowerPAD
VREG5 EN
29

12

VREF2
10mF
C01

PGND

DRVL1 IMON1
30

11

10kW
R13
VBST1 COMP1
31

10
SKIPSEL1
5V/100mA

PGOOD1

1.8nF
C15
4.7W
R16

VFB1
VREG5

DRVH1

SW1
32

V5SW

CSN1
CSP1

9
EN1
RF
0.1mF
C14

30kW
1

R12
GND
0.1 mF
C13

GND
300kW

PGOOD1
R01
Q11

120k W
Q12

EN1

R11
SKIPSEL1
PGND

4.3k W
R15
GND
VO1
C12

EN

VO1
PGND

7.5k W
R14

10kW
R02

0.1mF
C04
VBAT

GND
L1

IMON1
C11

PGND
5.0V/8A
VO1

Figure 51. Current Mode (Non-Droop), DCR Sensing, 5.0-V/8-A, 3.3-V/8-A, 330-kHz

Table 5. Current Mode (Non-droop), DCR Sensing, 5.0-V/8-A, 3.3-V/8-A, 330-kHz

SYMBOL SPECIFICATION MANUFACTURER PART NUMBER
C11 2 x 330 µF, 6.3 V 18 mΩ Sanyo 6TPE330MIL

Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 33

Product Folder Link(s) :TPS51222
TPS51222
SLUS908 – JANUARY 2009............................................................................................................................................................................................... www.ti.com

Table 5. Current Mode (Non-droop), DCR Sensing, 5.0-V/8-A, 3.3-V/8-A, 330-kHz (continued)
SYMBOL SPECIFICATION MANUFACTURER PART NUMBER
C12 2 x 10 µF, 25 V Murata GRM32DR71E106K
C21 470 µF, 4.0V, 15 mΩ Sanyo 4TPE470MFL
C22 2 x 10 µF, 25 V Murata GRM32DR71E106K
L1 3.3 µH, 10.7 A, 10.5 mΩ TOKO FDV1040-3R3M
L2 3.3 µH, 10.7 A, 10.5 mΩ TOKO FDV1040-3R3M
Q11, Q21 30-V, 12-A, 10.5 mΩ Fairchild FDMS8692
Q12, Q22 30-V, 18-A, 5.4 mΩ Fairchild FDMS8672AS

34 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s) :TPS51222

 C11
SYMBOL
VREG5
VBAT VBAT
5V/100mA
Q11
C12 Q21
C01 C22
C14 R16 10mF R26 C24
L1 L2
0.1mF 4.7W 4.7 W 0.1mF
PGND PGND
VO1 VO2
Q12 PGND GND
5.0V/5A 3.3V/5A
PGND
Q22
C11

Copyright © 2009, Texas Instruments Incorporated

C21
32 31 30 29 28 27 26 25

PGND PGND PGND PGND

SW1
GND
SW2

SPECIFICATION
1 24

VBST1
VBST2

DRVL1
DRVL2

VREG5
DRVH1 DRVH2
VO1 2 V5SW VIN 23 VBAT

2 × 120 µF, 6.3V, 15 mΩ

R01
330kW
3 22 VREG3
RF VREG3 3.3V/10mA
C03
2.2mF
GND EN1 4 EN1 EN2 21 EN2
TPS51222RTV
(QFN32)
PGOOD1 5 PGOOD1 PGOOD2 20 PGOOD2
GND

SKIPSEL1 6 SKIPSEL1 SKIPSEL2 19 SKIPSEL2

R14 R24

Panasonic
6.8k W PowerPAD 6.8k W
7 CSP1 CSP2 18
R15 C13 C23 R25

Product Folder Link(s) :TPS51222

56kW 0.1 mF 0.1 mF 56kW
8
CSN1 CSN2 17

MANUFACTURER
VFB1
COMP1
IMON1
EN
VREF2
IMON2
COMP2
VFB2

EN
R03
9 10 11 12 13 14 15 16 10kW
R02 GND
10kW IMON2
IMON1 VREF2 R21
62kW C05
C02 0.1 mF
C04 VO1 VO2
R13 0.22mF
0.1mF R11 C25
R12 10kW R23 R22
120k W C15 220p F
30kW 10kW 27kW GND
100p F
VREF2
GND GND VREF2

Table 6. Current Mode, DCR Sensing, 5.0-V/5-A, 3.3-V/5-A, 300-kHz

Figure 52. Current Mode, DCR Sensing, 5.0-V/5-A, 3.3-V/5-A, 300-kHz
GND GND

EEFCX0J121R
PART NUMBER

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35
TPS51222
TPS51222
SLUS908 – JANUARY 2009............................................................................................................................................................................................... www.ti.com

Table 6. Current Mode, DCR Sensing, 5.0-V/5-A, 3.3-V/5-A, 300-kHz (continued)

SYMBOL SPECIFICATION MANUFACTURER PART NUMBER
C12 2 × 10 µF, 25 V Murata GRM32DR71E106K
C21 2 × 220 µF, 4.0 V, 15 mΩ Panasonic EEFCX0G221R
C22 2 × 10 µF, 25 V Murata GRM32DR71E106K
L1 4.0 µH, 10.3 A, 6.6 mΩ Sumida CEP125-4R0MC-H
L2 4.0 µH, 10.3 A, 6.6 mΩ Sumida CEP125-4R0MC-H
Q11, Q21 30 V, 13.6 A, 9.5 mΩ IR IRF7821
Q12, Q22 30 V, 13.8 A, 5.8 mΩ IR IRF8113

36 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s) :TPS51222

 PACKAGE MATERIALS INFORMATION

www.ti.com 4-May-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS51222RTVR WQFN RTV 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
TPS51222RTVT WQFN RTV 32 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-May-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS51222RTVR WQFN RTV 32 3000 346.0 346.0 33.0
TPS51222RTVT WQFN RTV 32 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
RTV0032E SCALE 3.000
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

5.15 B
A
4.85

PIN 1 INDEX AREA

5.15
4.85

SIDE WALL LEAD

METAL THICKNESS
0.8 DIM A
0.7 OPTION 1 OPTION 2
C 0.1 0.2

SEATING PLANE
0.05
0.00 0.08 C
2X 3.5 (DIM A) TYP
3.45 0.1 (0.2) TYP
9 16 EXPOSED
THERMAL PAD
28X 0.5
8
17

2X SYMM
33
3.5

0.30
32X
0.18
24 0.1 C A B
1
0.05 C
PIN 1 ID
(OPTIONAL) 32 25
SYMM
0.5
32X
0.3
4225196/A 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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 EXAMPLE BOARD LAYOUT
RTV0032E WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 3.45)

SYMM
32 25
32X (0.6)

1 24

32X (0.24)

(1.475)
28X (0.5)

33 SYMM

(4.8)
( 0.2) TYP
VIA

8 17
(R0.05)
TYP

9 16
(1.475)

(4.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4225196/A 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

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 EXAMPLE STENCIL DESIGN
RTV0032E WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)
(R0.05) TYP (0.845)
32 25
32X (0.6)

1 24

32X (0.24)

28X (0.5)
(0.845)
SYMM
33

(4.8)

8 17

METAL
TYP

9 16
SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4225196/A 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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