BKU / RVC / CADENCE COLLABORATION

LAB 3B – LOGIC EQUIVALENCE CHECK

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 Overview
▪ In LSI design flow, after Synthesis, we need to perform Logic Equivalence checking (LEC)
between RTL and its Netlist to ensure that the functionality of them are the same:

Phases that Logic Equivalence checking is performed

▪ This Lab will familiarize you with one of Cadence tool – Conformal-LEC, which perform LEC.

▪ This Lab will cover the following:

❑ How to use Conformal-LEC

❑ How to debug Non-equivalent points by using GUI (Graphic User Interface)

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 Advantages of Conformal-LEC
▪ Conformal-LEC has many product to adapt with your purpose:

❑ Conformal L (ASIC): Verify synthesized and place & route netlist transformation.
❑ Conformal XL (Ultra): Conformal L + Verify complex datapath.
❑ Conformal GXL (Custom) : Conformal XL + Verify custom logic and custom memories.
❑ Conformal Low Power: Conformal XL + Verify low-power logic and power domains.
▪ It’s self-contained and it not tied to any particular synthesis environment. Thus, it gives you a
higher degree of confidence than equivalence checkers integrated with a particular logic
synthesis tool.

▪ It has excellent debugging capabilities. It automatically diagnoses design mismatches and

accurately pinpoints the source of the differences.

▪ It supports Hierarchical Comparison, which speed up the compare process. Moreover,

Cadence already introduced Smart LEC with special engine, which can execute hierarchical
comparison in parallel to achieve the best run time.

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 Perform LEC with Conformal (1/4)
▪ Step 1: Change directory to “lec_env” folder. In this Lab 4, we will work at this place:
%> cd /home/vlsi_group??/vlsi/${Student_ID}/work/lec_env

▪ Step 2: Link the RTL, Netlist and Library file from “synthesis_env” into this place:
%> ln –sf ../synthesis_env/Genus_BoundFlasher/RTL/bound_flasher.v
%> ln –sf ../synthesis_env/Genus_BoundFlasher/LAB1/outputs??/bound_flasher_m.v
%> ln –sf ../synthesis_env/Genus_BoundFlasher/LIB/slow.lib

▪ Step 3: Confirm there has no broken link (link files successfully):

%> ll

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 Perform LEC with Conformal (2/4)
▪ Step 4: Prepare the setup script for Conformal as below:
%> vi ./lec.tcl

set_log_file lec.log -replace Set Log file name lec.tcl

read_library slow.lib -lib -revised Read libraries

read_design bound_flasher.v -verilog -golden Read RTL

read_design bound_flasher_m.v -verilog -revised Read Netlist

set_mapping_method -name only

set_system_mode lec Mapping process
map_key_points

add_compared_points -all Compare process

compare

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 Perform LEC with Conformal (3/4)
▪ Step 5: Prepare the execution script as below:
%> vi ./go_lec

#!/bin/bash -f go_lec

cd /home/share_file/cadence
source add_path Setting license for
source add_license using Conformal
cd -

lec -64 -dofile ./lec.tcl & Invoke Conformal

▪ Step 6: Execute %> ./go_lec

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 Perform LEC with Conformal (4/4)
▪ Step 7: It will automatically open the GUI and execute processes that we described in file “lec.tcl”

Don’t have any Non-equivalent points

=> Netlist equivalent vs RTL

Type “exit” here to exit the GUI

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 Debug Non-equivalent point (1/8)
▪ Step 1: Copy Netlist into this place:
%> rm –rf bound_flasher_m.v
%> cp –rf ../synthesis_env/Genus_BoundFlasher/LAB1/outputs??/bound_flasher_m.v ./

▪ Step 2: Confirm Netlist already copied (not link):

%> ll

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 Debug Non-equivalent point (2/8)
▪ Step 3: Modify Netlist to make a “bug” intentionally:
%> vi ./bound_flasher_m.v

Pick up 1 INV-cell
randomly and change
it to BUF-cell

▪ Step 4: Re-execute %> ./go_lec

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 Debug Non-equivalent point (3/8)
▪ Step 5: When execution is done, “Non-equivalent” points will appear:

Non-equivalent points

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 Debug Non-equivalent point (4/8)
▪ Step 6: There are many ways for debugging nonequivalent points. The following part is the
debugging example using “Diagnosis Manager” and “Schematics Viewer” in GUI:

① Click to open “Mapping Manager”

② In “Mapping Manager” window, click

“Class”, choose “Disable All” then
choose “Non-Equivalent” to display only
nonequivalent points

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 Debug Non-equivalent point (5/8)

③ Right-click to first
nonequivalent key point and
choose “Diagnose” to open
“Diagnosis Manager”

④ In “Diagnosis Manager”
window, choose “Schematics”
to open “Schematics Viewer”

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 Debug Non-equivalent point (6/8)

⑤ As you can see, on the Revised schematic (left), the end- ⑥ If you want to expand the logic cone at specific pin, right-
point simulation (pink circle) is 1, while the Golden is 0 click to this pin and choose “Fan-in Cone –> Open”

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 Debug Non-equivalent point (7/8)

⑦ Purple gate is the gate

has a corresponding
equivalent gate on the
other schematic, you can
use it for easier debugging

⑧ After trace back, you can find that the root cause is BUF-gate ⑨ When you hover your mouse over any gate, it will show the
(pink rectangle) in Revised design corresponding line number in source code

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 Debug Non-equivalent point (8/8)

⑩ Double-click to the error gate (BUF gate) in Revised design, ⑪ You can confirm and give the suitable solution such as re-
the corresponding source code will be opened synthesize, do ECO…

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 THANK YOU FOR YOUR LISTENING

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