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Key Point Mapping

Conformal Key Point Mapping

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1K views69 pages

Key Point Mapping

Conformal Key Point Mapping

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Vijay Sarathi

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Fundamentals of Key Point Mapping in

Conformal
Product Version: Conformal 16.1
August, 2016
Copyright Statement

© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are
registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective
holders.

Learn more at Cadence Online Support - http://support.cadence.com

Contents
Purpose ........................................................................................................................... 5
Audience ......................................................................................................................... 7
Overview of Key Points ................................................................................................... 7
Fundamental steps in Mapping ..................................................................................... 10
Identification of key points ......................................................................................... 11
Determining the corresponding key point .................................................................. 12
Binding corresponding key points .............................................................................. 13
Understanding the Mapping Status ........................................................................... 17
Unreachable key points ............................................................................................. 19
Not-mapped key points .............................................................................................. 22
Extra key points ......................................................................................................... 23
Diagnosing Unmapped key points ............................................................................. 24
Manual mapping of key points ................................................................................... 29
Automated mapping of key points ............................................................................. 30
Reporting the method used for mapping ................................................................... 32
Rectifying incorrect mapping ..................................................................................... 33
Reusing Mapping Information .................................................................................... 35
Phase relationship between key points ......................................................................... 37
Indicating phase at the time of mapping .................................................................... 39
Auto-inferring phase relationship ............................................................................... 41
Invert phase relationship after mapping ..................................................................... 41
Enable phase mapping at submodule level ............................................................... 42
Facilitating Name-based mapping ................................................................................. 43
Scope of built-in naming rules ................................................................................... 44
Scope of “set naming style” ....................................................................................... 44
Scope of “set naming rule”......................................................................................... 47
Using pattern based naming rules ............................................................................. 48
Using dynamic arithmetic expression in naming rules ............................................... 50
Reporting available renaming rules ........................................................................... 51
Reviewing renamed key points .................................................................................. 52
Using renaming rules with manual mapping .............................................................. 53
Use of renaming rules in module uniquification ......................................................... 54
Mapping of multiple pins or bus to a single pin in Conformal ..................................... 55
Mapping multidimensional ports and registers in RTL ............................................... 57
Importing name-change information file from third-party synthesis tool ..................... 59
Impact of register naming style on imported optimization information: ...................... 62

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Impact of Auto-modeling on Mapping ............................................................................ 64

Mapping in Hierarchical Comparison............................................................................. 65
Performance Consideration for Mapping ....................................................................... 66
Mapping in Lowpower Flow ........................................................................................... 68
Implication of Mapping in Conformal ECO .................................................................... 68
References .................................................................................................................... 69

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Purpose
Conformal Equivalence Checker (also known as Conformal LEC) uses formal proof to
verify the functional equivalence of the combinational logic of a design.

To compare two designs, Conformal LEC partitions both, the reference as well as the
Revised version of the design in terms of combinational cones, bounded by non-
combinational design objects that are known - in Conformal lexicon - as “key points”.

After the identification of key points in the two designs, Conformal LEC determines the
corresponding key point pairs and compares the functional equivalence of the
combinational logic cones that drive these key point. The reference design is called the
“Golden design” and the alternate version of the design is called the “Revised design”.

The process of determining and pairing up the corresponding key points from the
Golden and the Revised design is termed as “Mapping”.

Conformal Equivalence checker flow can be broadly described in five steps as follows:

Constraints
Design & Library + Comparison
Modeling Mapping
Setup Modeling
options

Figure 1: The basic steps of conformal equivalence check flow

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Accurate and complete mapping of the key points are crucial for a reliable comparison
outcome. If mapping of the key points lacks accuracy, the comparison outcome will be
incorrect. If mapping of the corresponding key points is incomplete, the comparison
might report false non-equivalences.

This document aims at explaining the concept of mapping of the key points in detail, the
steps to facilitate and ensure accurate mapping, and also how to diagnose and resolve
the mapping issues. It also answers a lot of frequently asked questions related to
mapping.

This document does not cover the following topics:

• Mapping of modules and module pins

• Modeling of design elements to match synthesis behavior

• How to debug miscompares

Acronyms

The following terms describe aspects of the Conformal Equivalence Checker

LEC Logic Equivalence Checker (also known as Conformal Equivalence

Checker).

EQ Indicates that the comparison outcome proved equivalent.

NEQ Indicates that the comparison outcome proved non-equivalent.

Not-compared Indicates that the comparison is pending.

Support Cone All the design logic feeds to a particular key point.

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Audience
This application note is meant for logic designers and engineers who use LEC to verify
the functional equivalence between any of the following pairs in the same design, as it
matures from RTL to placed-and-routed netlist:

• RTL versus Netlist

• Netlist versus Netlist (with more optimizations)

Readers are expected to be familiar with the basic synthesis optimization concepts.

Overview of Key Points

When performing equivalence check between two designs, LEC breaks down both the
Golden and the Revised designs in terms of combinational logic cones, bounded by
non-combinational entities called “key points”.

The corresponding combinational fan-in logic cones of identical key points are
compared for equivalence. Two key points are declared equivalent when the
corresponding fanin cones are proved to be equivalent. If a key point contains more
than one fanin cone due to multiple input pins (for example, D-flop or D-latch),
Conformal will compare the corresponding fanin cones individually for each of these
input pins.

Conformal creates a “key point” for each of the following objects:

• Flop (DFF)

• Latch (DLAT)

• Primary Input (PI)

• Primary Output (PO)

• Black box instance (BBOX)

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• TIE-Z gates formed to represent a floating net or pin, and a high-impedance state
for tri-stated gates

• CUT gates formed at the location where a combinational loop is broken

• TIE-E (error) gates formed to represent X assignments (default for Revised

netlist only)

Not all of these key points are compared. To qualify to be a valid candidate for
comparison, the key points should fulfill the following criteria:

1. One corresponding key point must be found in the other design for mapping.

2. It is the sink point of a combinational logic cone.

Any key point that does not simultaneously fulfill these two conditions are kept out of
comparison.

Primary inputs, TIE-Z and TIE-E gates, can never become the sink point of any
combinational logic cone. Therefore, by Criterion 2, these key points are not compared.

Every comparison cone is composed of the following elements:

1. Compare point

The sink point of combinational logic cones. It represents the end point of a
compare cone where data is captured. It must be a mapped key point. Unless it
is a mapped key point, it does not qualify to be a compare point.

2. Support point

The list of key points that appear in the transitive fanin cone of “compare point”
and define the structural boundary for the combinational cone driving the
compare point.

These represent the start point for the compare cone where data is launched.

3. Combinational logic cloud

The combinational logic gates that carry the data from the support points to the
compare point.

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The complete fanin logic cone consisting of the combinational logic cloud and the
support key points, is known as the “support cone” of the “compare key point”.

The following figure illustrates the compare points and support points in a typical design,
assuming the Revised design also contains the same design objects with the same
name:

Figure 2: A typical PI to PO path

In Figure 2, the paths start at the “support point”, pass through some combinational
logic, and end at the “compare point”.

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The following table lists the “support points” for each compare cone of a “compare
point”:

Compare Key point Cones Support key point

Clock cone CLK
FF1
Data cone A

Clock cone CLK

FF2
Data cone B

Clock cone CLK

FF3
Data cone C

FF4 Clock cone CLK

Data cone FF1, FF2, FF3

Q Data cone FF4

Fundamental steps in Mapping

Mapping involves three steps:

1. Identifying the key points, after analyzing both the designs.

2. Determining the corresponding key point from the other design.

3. Binding the key point to its corresponding key point.

All these steps are performed when the tool switches from Setup to LEC mode, with the
application of the set system mode lec command.

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Fundamentals of Key Point Mapping in Conformal

Identification of key points

Identification of the key points is an internal step. This is performed automatically by the
tool when it enters from SETUP mode to LEC mode.

You can use the report key point command to see the list of key points identified
in the Golden as well as in the Revised design, with the following syntax:

LEC> report key point -type BBOX PI E Z DFF DLAT CUT PO –revised

The following example shows a sample output of the command for the given types of
objects.

Figure 3: Command output

Note: LEC creates unique numerical ID, also known as “gate-ID” for every gate in the
design, including the key points. Therefore, a key point can be referred to through its
gate-ID in all commands that work on key points.

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Fundamentals of Key Point Mapping in Conformal

Determining the corresponding key point

This step is the most crucial step in mapping the key points.

LEC applies sophisticated algorithms to automatically determine, for every key point in
the Golden design, the corresponding key point in the Revised design. However, LEC
also enables the user to manually map a pair of the key points from the respective
designs.

LEC considers two key points from the two designs as corresponding key points, only
when these satisfy the following condition:

The two key points must be the same type of object as clarified in the following table:

Type of key point in Golden design Allowed type for corresponding key point

PI PI

PO PO

BBOX BBOX

DLAT DLAT

DFF DFF

CUT gate CUT gate

Z gate Z gate

E gate E gate

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Fundamentals of Key Point Mapping in Conformal

Binding corresponding key points

To map all the Golden key points with their corresponding key points in the Revised
design, use the map key points command. After mapping, LEC will print a summary
table for the Mapped and Unmapped key points.

LEC> map key points

The following example shows a typical mapping summary table after issuing the
command:

Figure 4: Sample command output

The mapping is automatically enabled whenever the tool switches from SETUP to LEC
mode using the set system mode lec command.

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Fundamentals of Key Point Mapping in Conformal

The following example shows that mapping is invoked automatically, when entering
LEC mode:

Figure 5: Automatic mapping invocation on entering LEC mode

However, you can disable automatic mapping when switching to LEC mode, by using
the -nomap option with the set system mode lec command. Then, you need to
explicitly use the map key points command later in LEC mode, to initiate mapping of
key points, as shown here:

SETUP> set system mode lec –nomap

LEC> map key points

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Fundamentals of Key Point Mapping in Conformal

The following example shows mapping invoked separately in LEC mode:

Figure 6: Decoupling mapping

To learn about one practical application of the -nomap option of set system mode
lec, refer to the Reusing Mapping Information section.

The mapping of the key points can also be scrutinized from the Mapping Manager GUI
of Conformal LEC.

To invoke the Mapping Manager window, click the Mapping Manager Icon at the top of
Conformal GUI.

Figure 7: Mapping the manager button in LEC GUI

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Fundamentals of Key Point Mapping in Conformal

The Mapping Manager pops up in a new window, with three separate panes for
Unmapped, Mapped, and Compare Points, respectively.

Figure 8: Mapping the Manager window

Note: The (?) symbol before the compared points indicate that these are yet to be
compared.

The process of mapping may require iterations or correction at times. Occasionally, the
synthesis tool might change the object names such that the default pattern matching
rules fail to determine the corresponding key point from the other design. The
unmapped key points require additional rounds of mapping, following the discovery of
the corresponding key point pair.

For iterative mapping, use the map key points command to pair the newly detected
corresponding key points.

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Fundamentals of Key Point Mapping in Conformal

Understanding the Mapping Status

After mapping the key points, Conformal LEC classifies these key points based on the
mapping status. The group of key points successfully mapped are called “Mapped Key
Points” and the group of key points that cannot be clubbed with their corresponding key
point for whatsoever reason, are called “Unmapped Key Points”.

Unmapped Key Points are further divided into three categories:

• Unreachable

• Extra

• Not-mapped

Use the report mapped points command to report all the Mapped key points, after
mapping.

Use the report unmapped points command to report all the Unmapped key points,
after mapping.

You can filter the results further to view only a specific kind of Unmapped key point, by
adding the following options to report unmapped points.

• -notmapped to view only Not-mapped key points

• -extra to view only Extra key points

• -unreachable to view only Unreachable key points

Note:

• Sequential key points that are modeled away because of optimization to a

constant, do not figure in any of the above mentioned groups.

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Fundamentals of Key Point Mapping in Conformal

• Merged sequential key points are shown under the representative key point, with
gate-id, phase, and merged register name, as shown in the following example:

LEC> report mapped point q_reg

Mapped point for
(G) + 14 DFF /q_reg
(G) + 13 DFF /q_reg1
is
(R) + 19 DFF /q_reg
(R) - 16 DFF /q1_reg
(R) + 12 DFF /q5_reg
(R) + 14 DFF /q3_reg
(R) + 13 DFF /q4_reg
(R) + 15 DFF /q2_reg

Mapped Key
Unreachable
Key Points
Points Unmapped Key
Extra
Points

Not-mapped

Figure 9: Categorization of key points after mapping

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Fundamentals of Key Point Mapping in Conformal

Unreachable key points

Unreachable key points are those key points whose effect do not reach any primary
output of the design. In other words, these no longer contribute to determine the design
functionality, and hence, cannot affect the outcome of comparison of any other key
point, in any way. As a consequence, these can be safely ignored from comparison.

A key point is declared Unreachable primarily due to one the following reasons:

1. The path starting from the key point is blocked by some other gate that masks or
disrupts its value propagation.
2. No fanout branch of the key point is structurally connected to any primary output.

There might be numerous situations that could give rise to such factors. Some of these
situations are discussed in the examples that follow.

Note: The Unreachable key points are not mapped by default. You can force their
mapping by using the set mapping method –unreach command. However, this will
increase the comparison time and can add to the list of false Non-equivalences.
Therefore, it is not recommended.

As an exception, if you want to selectively compare a handful of Unreachable key

points, use the add mapped points command to manually map and compare these
key points.

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Fundamentals of Key Point Mapping in Conformal

Examples of Unreachable key points:

Example 1

In the following example, the flop output does not propagate to the primary output,
because of the ripple effect of the constant 0 through AND gate. Conformal LEC marks
the flop FF1 as an Unreachable key point (under the Unmapped key point group).

= Blocked path

Figure 10: Unreachable due to blocked path

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Fundamentals of Key Point Mapping in Conformal

Example 2

In the following example, flop FF2 becomes an Unreachable key point, because the
MUX in its fanout cone is constrained such that the path originating from the key point is
never selected.

= Blocked path

Figure 11: Unreachable due to constraint on MUX

Note: Modeling transforms the sequential elements into alternative representation,

according to the modeling option. This might also render some sequential elements as
unreachable after modeling.

For example, clock-gate DLATs become Unreachable when modelled with the -
gated_clock modeling option.

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Fundamentals of Key Point Mapping in Conformal

Not-mapped key points

Not-mapped key points are those key points for which Conformal LEC might not
determine the corresponding key points in the other design for mapping.

Not-mapped key points might be the consequence of simple reasons, like the renaming
of design objects during synthesis. In such cases, the knowledge of name
transformation needs to be passed on to Conformal LEC, to help in the mapping. This is
discussed in the Facilitate Name-based mapping section.

Not-mapped flops or latches might also be the result of inadequate modeling options or
partial modeling or sequential redundancy. Some commonly applied sequential
optimization techniques include:

- cloning and de-cloning of registers, thus introducing additional registers or

merging of registers

- optimizing away registers that might be at a constant logic value

- optimizing away registers that are in “don’t care” state and are optimized to logic
0 or logic 1 by the synthesis tool

- replacing flop with a pair of master-slave latches

- gated clock insertion on the clock path

- removal of redundant registers that do not affect the design states anyway

Use the set flatten model command with appropriate options, to turn on modeling
of sequential elements. This helps to eliminate all Not-mapped sequential elements due
to inadequate modeling.

You can also use the set analyze option –auto command (or its equivalent the
analyze setup command) to mimic all the previous kinds of sequential optimizations.

Every modeling transforms the design and comes with a runtime cost. Complex
sequential optimizations might require higher efforts on the part of Conformal LEC. You
can increase the modeling effort with the -effort <effort level> option of the
set analyze option command (also the analyze setup command).

Yet, in some rare cases, the remodel –notmapped <modeling option> command
might be required to perform modeling of the remaining Not-mapped key points.

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Fundamentals of Key Point Mapping in Conformal

In this manner, the modeling options used can alter the count of Not-mapped key
points. Moreover, during comparison, LEC gathers more information about the Not-
mapped key points and might re-categorize these as Extra or Unreachable after
comparison.

Therefore, the Not-mapped information collected after comparison gives a more realistic
picture about the remaining Not-mapped key points.

Impact of Not-mapped key points on comparison

Not-mapped key points are not compared for functional equivalence.

In the absence of proper renaming guidance from the user, a Not-mapped key point
might remain unmapped and hence not-compared. As such, the comparison result will
be incomplete.

Not-mapped key points can also cause Non-equivalence to other key points, when
these become a support key point and influence the result of comparison.

A Not-mapped key point can be safely ignored, provided it has no corresponding key
point to map to and it does not cause Non-equivalence to other key points.

Extra key points

Unmapped Extra key points might be a Primary Input, a Primary Output, a flop, or a
latch.

Primary Inputs and Primary Outputs that are present in only one of the designs, become
Extra key points. Like Not-mapped key points, these might also arise due to name
mismatches and user guidance in mapping might help to transform these into mapped
key points.

Post-routed netlist contains extra POWER and GROUND ports like VDD and VSS that
are not present in the RTL or synthesis netlist. Use the add pin constraints
command to constrain such Primary Inputs to a constant value.

Extra Primary Outputs like DFT ports can be ignored, because these serve no purpose
in the functional mode. Ports of this kind can be altogether ignored from the list of
Primary Outputs using the add ignored outputs command. These are excluded
from the list of Extra key points as well.

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Fundamentals of Key Point Mapping in Conformal

Extra unmapped Primary Inputs can cause Non-equivalence, if – as a support key point
- these affect the functionality of other compare key points. Use the add pin
constraints command to constrain such Primary Inputs to a constant value in
accordance with the design intent.

If you would like to force Conformal LEC to discount the effect of an Extra primary input
when it does not affect any internal logic, indicate these with the add ignored
inputs command.

If an Extra primary input does not affect the functionality of any compare key point,
these can also be safely ignored.

Redundant registers (DFF and DLAT) may be reported as Extra key points in some rare
situations.

Redundant registers do not affect the downstream logic and are removed by the
synthesis tool. The same registers become unmapped key points in the reference
design. Conformal LEC is able to detect redundant registers in the design at the time of
modeling itself and model these away appropriately, most of the time. However, in some
rare situations, Conformal LEC may not be able to determine if a Not-mapped flop or
latch is a functionally redundant register, until the design comparison happens. Before
comparison, these remain as Not-mapped key points. After comparison, LEC gets more
insight about such redundant registers and re-classifies these Extra key points.

Diagnosing Unmapped key points

It may not be explicitly apparent from the mapping summary report, why a key point is
Unreachable or Not-mapped or Extra. Conformal provides commands to get closer to
that answer.

To find more information on unmapped points in the design, use the rep unmapped
points command after mapping. Use the -extra, -notmapped, or -unreachable
option with this command to restrict the report to only Extra, Not-mapped, or
Unreachable key points respectively:

LEC> rep unmapped points \

[-extra | -unreachable [-blocked | -nofanout]| -notmapped \

[-golden|-revised]

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Fundamentals of Key Point Mapping in Conformal

-blocked and -nofanout are two sub-options to -unreachable and enable further
filtering on the Unreachable key points based on the reason.

For example, the following command reports only those Unreachable key points that are
blocked by other logic gates:

LEC> rep unmapped points -unreachable -blocked

Unmapped point (unreachable: all paths to outputs are

blocked):
(G) 4 DFF /q2_reg
Unmapped point (unreachable: all paths to outputs are
blocked):
(R) 4 DFF /q3_reg
Unmapped point (unreachable: all paths to outputs are
blocked):
(G) 5 DFF /q1_reg
Further, to identify which fanout gate makes the key point Unreachable, use the
report gate command with the “-unreach” option as follows:

LEC> report gate <key point pathname> -unreach

Conformal will trace and print out the fanout paths of the Unreachable key point, up to
the point where it becomes unreachable.

Figure 12: Unreachability diagnosis using the report gate command

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Fundamentals of Key Point Mapping in Conformal

For Extra key points, check if port renaming or explicit key point mapping is required to
map these to their corresponding key point in the other design.

If the extra primary inputs are constrained to constant logic values using the add pin
constraints command, these are no longer reported as “Extra” unmapped key
points.

If the extra Primary Outputs are of no use during functional mode, consider marking
these as ignorable key points using the add ignored outputs command.

For Not-mapped key points, check for the possibility of missed opportunity for mapping
or modeling. Object renaming or explicit key point mapping might be required for these
as well. If it is showing up due to lack of optimization, use the proper modeling options
from the set flatten model command, to optimize it away.

It is recommended to use the set analyze option –auto command (or its
equivalent command analyze setup) to enable the common set of modeling options.

To restrict the modeling to the Not-mapped key points only, use the remodel –
notmapped <modeling option> command.

To identify if a Not-mapped flop or latch is a redundant register, use the analyze

redundancy command as follows:

LEC> analyze redundancy <register-name> -UNREACH

To enable remodeling of the key point if the proof is satisfied, use the -commit option
along with it.

LEC> analyze redundancy <register-name> -UNREACH –commit

The following example illustrates a circuit with functionally Unreachable flop "FF1_reg".:

Figure 13: Unreachable flop analysis

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Fundamentals of Key Point Mapping in Conformal

Use the command to perform unreachability analysis on it. Note that the tool replaces
the unreachable net with the constant 0.

Figure 14: Command output

To test if a Not-mapped key point might be a sequential constant register, use the
analyze gate command. It will report the sequential constant status for the key point
and also detect if there is any sequential constant support key point in its transitive fanin
cone.

LEC> analyze gate <register name>

In the following example, the analyze gate will report FF1_reg and FF2_reg as
sequential constant flops and FF3_reg as a non-constant flop, having a sequential
constant in support cone, as follows:

Figure 15: Diagnosing sequential constant Not-mapped flops

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Fundamentals of Key Point Mapping in Conformal

LEC> analyze gate FF2_reg -verbose

Figure 16: FF2_reg proved to be the sequential constant 0

LEC> analyze gate FF1_reg –verbose

Figure 17: FF1_reg proved to be the sequential constant 1

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Fundamentals of Key Point Mapping in Conformal

LEC> analyze gate FF3_reg –verbose

Figure 18: FF3_reg has the sequential constant flop in support cone

Manual mapping of key points

If two key points from the Golden and the Revised designs are of the same type, these
can be mapped manually or through an automated mechanism. The key points that are
already mapped are not touched by this process.

To manually map a pair of key points, use the “add mapped point” command as
follows:

LEC> add mapped points <golden key point> <revised key

point> \
-type <golden key point type> <revised key point type>

This method is tedious and requires the user to manually discover the corresponding
key points from the two designs. LEC enables a more efficient and automated approach
to deal with all available key points.

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Fundamentals of Key Point Mapping in Conformal

Automated mapping of key points

In the automated approach, LEC match two key points either by name or by function.
These two kinds of mapping methods are respectively termed as:

• Named-based mapping

• Function-based mapping

The choice of mapping method is enabled by the set mapping method command.

Name-based mapping algorithm employs string-based or pattern-based name matching

rules to determine the corresponding key point in the other design. LEC provides the
following commands for you to assist or modify the naming rules:

• set naming rule

• set naming style
• add renaming rules
• change name
• set multibit option
To learn about how to take advantage of these commands to facilitate the name-based
mapping algorithm, refer to the Facilitating Name-based mapping section.

On the other hand, function-based mapping algorithm uses heuristics to determine the
corresponding key point in the other design. Being based on heuristics, it runs slower
and it is also prone to error.

Conformal LEC enables the user to control and decide the kind of mapping method to
use. If the user wants to use both, in tandem, Conformal LEC enables the user to set
the priority between the two methods.

By default, LEC first maps the key points that have exactly the same paths, then maps
the remaining unresolved key points with a mapping algorithm. All remaining unresolved
key points become unmapped points.

To reverse the method of mapping, by first trying the function-based mapping algorithm
on key points and then applying name-based mapping on the remaining key points, use
the following setting:

SETUP> set mapping method –name guide

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Fundamentals of Key Point Mapping in Conformal

To disable function-based mapping completely, use the following setting:

SETUP> set mapping method –name only

To disable name-based mapping completely, use the following setting:

SETUP> set mapping method –noname

For more information about how to use the set mapping method command to control
various aspects of the overall mapping strategy, refer to the Conformal Command
Reference manual.

Note:

• Primary Inputs and Primary Outputs are always mapped by name. This implies
that if the port names are changed the user is required to facilitate name-based
mapping for these ports.

• Tie-E gates are always mapped by function. This implies that the user does not
have any control over it to modify mapping of the E-gates.

• Blackbox pins are always mapped by name only.

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Fundamentals of Key Point Mapping in Conformal

Reporting the method used for mapping

To diagnose the method used for mapping, use the report mapped point command
with the –method option. It will list all mapped key points along with the mapping
strategy used for it. For example:

LEC> report mapped points -method

Mapped points: SYSTEM class

1-th mapped points: mapped by Name
(G) + 1 PI /d[8]
(R) + 2 PI /d_8
2-th mapped points: mapped by Name
(G) + 2 PI /d[7]
(R) + 3 PI /d_7
. . .
. . .
28-th mapped points: mapped by Function
(G) + 28 DFF /gm_hic/gm_hic_arb/q_size_reg_reg[0]
(R) + 24 DFF
/gm_hic/gm_hic_arb/q_size_reg_reg_abc_[0]/U$1

===========================================================
Mapped points PI PO DFF Total
-----------------------------------------------------------
Golden 10 9 9 28
-----------------------------------------------------------
Revised 10 9 9 28
===========================================================
If the count of function-based mapping is high, it can have a detrimental effect on the
runtime. Study the key point names and see if some of these can be converted to
name-based mapping, using one of the strategies described in the Facilitating Name-
based mapping section.

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Fundamentals of Key Point Mapping in Conformal

To know about the strategy employed for a specific key point, use the command with
the key point gate-id or name, as shown in the following example:

LEC> report mapped points 28 -method

Mapped point for
(G) + 28 DFF /gm_hic/gm_hic_arb/q_size_reg_reg[0]
is mapped by Function to
(R) + 24 DFF
/gm_hic/gm_hic_arb/q_size_reg_reg_abc_[0]/U$1
To get a quick idea about how many key points were mapped by-name and how many
were mapped by-function, use the report mapped point command with the –
summary option.

LEC> report mapped points -method -summary

……
===========================================================
Mapping method PI PO DFF Total
-----------------------------------------------------------
Name 10 9 0 19
Function 0 0 9 9

Rectifying incorrect mapping

Sometimes key points might get incorrectly mapped due to the use of incorrect
renaming rules, incorrect functional mapping, or mistake during manual mapping.

To rectify the mapping of such key points, there are essentially two steps in the given
sequence:

1. Unmap the key point pair

2. Correctly map these to their corresponding key points

If a few key points need correction, manually delete the mapping and then remap these:

LEC> delete mapped points <gate-id> [-golden|-revised]

LEC> add mapped points <golden_key_point>
<revised_key_point>

However, if incorrect mapping affects a large number of key points, you can delete the
mapping of these key points using other options of delete mapped points that
select a group of key points.

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Fundamentals of Key Point Mapping in Conformal

Some commonly used combinations are:

delete mapped point Effects

option

-all Deletes mapping of all key points

-class user Deletes mapping of key points added by the add

mapped point command

-class system Deletes mapping of key points added by the map

key points command

Instance-pathname*/pin- Deletes mapping of all key points matching

pathname* instance- pathname/pin-pathname string. It accepts
wildcards.

-noneq Deletes mapping of all Non-equivalent key points

After deleting the group of key points, start mapping for the unmapped key points afresh
with one of the mapping methods, to remap these.

Mapping Method When to choose

set mapping method –name only To map based on name match only

set mapping method -noname To map based on function-based match

set mapping method -phase To map key points with invert-phase

add renaming rule To guide mapping based on pattern

Note: On dissolution of mapping of a key point, LEC removes the comparison results of
all the compared points associated with the deleted mapped points. You need to do a
fresh comparison of these compare points to reassess their equivalence status.

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Fundamentals of Key Point Mapping in Conformal

Reusing Mapping Information

When a large number of key points are involved, mapping of key points may cost a
significant runtime.. Conformal provides a method to save one-to-one key point
mapping information from an LEC session into an ASCII file and reuse these as it is in
subsequent sessions. This method eliminates the time and effort spent on mapping and
reduces the overall runtime.

However, the mapping file may be written out with a more liberal setting for mapping
unreachable key points and so on, while at the time of reading, a more restrictive setting
for mapping can be chosen. The result of mapping will depend on the current run
session.

To write out the mapping information into a file, use the following command in LEC
mode:

LEC> write mapped points <mapping_file> [-replace]

Mapping file format

The following example illustrates the sample content of a mapping file:

add mapped points dec_data[7] dec_data[7] \

-type PI PI -module err_detect err_detect
add mapped points dec_data[6] dec_data[6] \
-type PI PI -module err_detect err_detect
add mapped points dec_data[5] dec_data[5] \
-type PI PI -module err_detect err_detect
add mapped points dec_data[4] dec_data[4] \
-type PI PI -module err_detect err_detect

To restore the mapping information from the file in subsequent LEC sessions, prevent
automatic mapping by the tool and use:

LEC> read mapped points <mapping_file>

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Fundamentals of Key Point Mapping in Conformal

Because Conformal LEC, by default, maps the key points when entering the LEC mode,
you need to prevent this automatic mapping of key points by using the –nomap option
with the set system mode lec command:

SETUP> set system mode lec –nomap

You can also pass the mapping file with “set analyze
option” command with –mapping_file option as follows:

SETUP> set analyze option –mapping_file <mapping_file>

With this command, you can provide mapping information before entering the LEC
mode. The mapping information in this file is used on an as needed basis.

Caveat

set naming rule –register “<register name format>” can alter the
naming of flops and latches from their original RTL names and it may be difficult to
correlate these from the mapping file. To write out the mapping information in terms of
the original RTL name, add –SHOW_ORIG_RTL_NAMES to write the mapped points
command as follows:

LEC> write mapped points <mapping file> -

SHOW_ORIG_RTL_NAMES
Note: Storing the register mapping information in terms of original RTL names will not
impact importing of renaming rules in any way.

In the following example, set naming rule changed the original RTL register names
from syndram/macreg/q[1:0] to syndram/macreg/q_x_reg[1:0].

SETUP> set naming rule “%s_x_reg” –register –golden

....
LEC> write mapped points map.do
By default, map.do file will show the register mapping information as follows:

add mapped points syndram/macreg/q_regx_reg[0]

syndram/macreg/q_regx_reg[0] -type DFF DFF -module top top
add mapped points syndram/macreg/q_regx_reg[1]
syndram/macreg/q_regx_reg[1] -type DFF DFF -module top top

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Fundamentals of Key Point Mapping in Conformal

When the -SHOW_ORIG_RTL_NAMES option is used, the mapping file will store the
register mapping as follows:

LEC> write mapped points map.do –show_orig_rtl_names

Modified mapping in map.do:

add mapped points syndram/macreg/q[7]

syndram/macreg/q_regx[0] -type DFF DFF -module top top
add mapped points syndram/macreg/q[6]
syndram/macreg/q_regx[1] -type DFF DFF -module top top

Phase relationship between key points

If a pair of corresponding key points are always at opposite logic values, under identical
inputs, these are said to hold inverted-phase relationships and such key points are
called phase-inverted key points. If correct phase relationship is not taken into account
during key point mapping, the comparison will report false (in-phase) Non-equivalences.

The default behavior of Conformal LEC is to assume that the corresponding key point
pair holds in-phase relationship.

If two “compare key points” are in inverted-phase, the comparison process needs to
check for inverted-equivalence rather than in-phase equivalence.

If two “support key points” are in inverted-phase, LEC assumes opposite Boolean
values for the key point pair, for comparison of “compare key points” driven by these
two “support key points”.

In case of flops and latches except for the clock cone, all of its data input cones
including asynchronous SET and RESET cones, must have inverted-phase relationship,
to be considered phase-inverted key points.

Asynchronous SET (or PRESET) pin is functionally always in the opposite phase of the
asynchronous RESET (or CLEAR) pin of a flop. Therefore, if the support cone of an
asynchronous SET pin of the Golden flop is swapped with the support cone of an
asynchronous RESET pin of the flop in the Revised netlist, these asynchronous pins
exhibit inverted-phase relationship. If other data cones other than the clock, also exhibit
inverted phase relationship, this flop will be mapped as phase-inverted key points.

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Fundamentals of Key Point Mapping in Conformal

Primary Inputs and Primary Outputs are considered to be in-phase, and Primary
Outputs are checked for in-phase equivalence only.

For black boxes, support cone of all the input pins must be in an inverted-phase
relationship for the black box instances to be mapped as phase-inverted key points.

In the following example, flop FF1 has an inverted-phase relationship, while primary
inputs D, CK, SN, and primary output Y are in the same phase.

Figure 19: Golden design

Figure 20: Revised design

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Fundamentals of Key Point Mapping in Conformal

To include the phase relationship information during mapping, use one of the following
methods:

• Indicate phase at the time of mapping

• Auto-inferring phase relationship

• Invert phase relationship after mapping

• Use a configuration file

Indicating phase at the time of mapping

To indicate phase relationship at the time of mapping use the -invert option with the
add mapped points command.

The following example indicates phase mapping for register FF1_reg, at the time of
mapping of the key points, in the Figures 19 and 20:

SETUP> set system mode lec –nomap

LEC> add mapped points D D -type PI PI
LEC> add mapped points SN SN -type PI PI
LEC> add mapped points CK CK -type PI PI
LEC> add mapped points FF1_reg FF1_reg -invert -type DFF
DFF
LEC> add mapped points Y Y -type PO PO
LEC> map key points

Note that automatic mapping by the tool was inhibited by the -nomap option of set
system mode lec.

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Fundamentals of Key Point Mapping in Conformal

Mapping Manager GUI will display the mapped key points in the following manner.
Note that the "-" sign in front of the key points indicate inverted phase relationship, and
the “+” sign indicates same phase relationship.

Figure 21: List of Mapped key points in Mapping Manger

In this example, the same fanin cone is swapped for the asynchronous SET/RESET pin
between the two designs, thus fulfilling the inverse phase condition for the
asynchronous control pin.

Post-comparison report in Conformal LEC will show the primary output Q and FF1_reg
as inverted-equivalent, while primary output Y will be in-phase equivalent. The
comparison result pane in Mapping Manager GUI represents inverted-equivalence with
"-" sign in front of the compared key points, as follows:

Figure 22: Inverted equivalent compare points

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Fundamentals of Key Point Mapping in Conformal

Auto-inferring phase relationship

You can also use set mapping method –phase, to let Conformal LEC derive the
phase information of key points. Map these as phase-inverted key points and check for
inverted-equivalence relationship between them. This command enables additional
comparison for inverted-equivalence for key points, thus increasing the runtime.

Therefore, you can limit this phase mapping command only to the Non-equivalent key
points as follows:

LEC> compare // Non-equivalent key points exists !

LEC> delete mapped points –noneq
LEC> set mapping method –phase
LEC> map key points
LEC> add compared points –all
LEC> compare // Non-equivalent key points checked for inverted-equivalence

Caveats

• If the inverter has moved beyond one register level in a register chain, it might
require the use of set mapping method –phase from the very beginning.
Using phase-mapping on Non-equivalent key points only, may not be able to
map these with the correct phase.

• Primary Inputs and Primary Outputs cannot be automatically phase-mapped. You

need to explicitly indicate phase inversion for these using the –invert option of
the add mapped points command or the set naming rule -
inverted_pin_extension command, as applicable.

Invert phase relationship after mapping

You can also enable the in-phase mapping first, and invert the phase for key points in
LEC mode manually. Use the invert mapped points command to alter the phase
relationship.

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Fundamentals of Key Point Mapping in Conformal

In the following example, the phase of the flop FF1_reg was changed to phase-inverted
mapping with the invert mapped points command:

LEC> report mapped points -type DFF

Mapped points: SYSTEM class

Golden Revised
+ 6 DFF /FF1_reg + 6 DFF /FF1_reg

1 mapped points reported

===========================================================
Mapped points PI PO DFF Total
-----------------------------------------------------------
Golden 3 2 1 6
-----------------------------------------------------------
Revised 3 2 1 6
===========================================================
LEC> invert mapped points FF1_reg
Inverted mapping of mapped point is:
(G) + 6 DFF /FF1_reg
(R) - 6 DFF /FF1_reg
Alternately, use the –phase_mapping option of analyze setup (and also with its
equivalent set analyze option –auto), to let LEC review the mapped key points
for possible phase inversion and apply the correction automatically.

Only mapped key points are considered by this command. Unmapped key points will not
be affected by this command.

Enable phase mapping at submodule level

Applying phase mapping on the entire design may be a time consuming process. This is
because Conformal LEC will evaluate each key point pair for the possibility of inverted
mapping.

Phasing mapping might be challenging, if name correspondence is low among key

points in a design. If you know which module underwent phase inversion, use the
following command pair in SETUP mode, specifically for that module:

SETUP> add mapping model <module_name*> -inverted -revised

SETUP> set mapping method –phasemapmodel

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Fundamentals of Key Point Mapping in Conformal

In certain situations, the synthesis tool use libcells for registers with inverters before and
after the state elements, in such cases also you can enable the phase mapping only on
these cells and improve the runtime performance of LEC.

Caveat

With the -phasemodel option, LEC applies inversion to all sequential elements within
the module without any further analysis. Therefore, use it only when every sequential
element in that module undergoes inversion push or boundary optimization. This option
is more suitable for library cells with inverted input and output pins.

Facilitating Name-based mapping

After design elaboration, Conformal LEC generates design object names following
some internal naming convention for RTL and hierarchical modules. The synthesis tool
may use a different naming convention for design objects, including the hierarchy
separator, array delimiter, and parameter values.

Conformal LEC, by default, attempts to map all the key points with matching
pathnames. Depending on the degree of variation in the name change, LEC provides
different methods to help name-based mapping.

The following methods cover different aspects of changes in the name:

• Built-in naming rules

• set naming style command
• set naming rule command
• add renaming rules command
• change name command
• Mapping of single-bit registers to multibit register cell

The scope of each of these commands is described in the following sections, except for
the last one.

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Fundamentals of Key Point Mapping in Conformal

Scope of built-in naming rules: LEC built-in naming rules equate the naming
conventions for the following objects:

• Array delimiter: [ ], _ _, < >, ( )

• Hierarchical separators: _, /
• Extraneous digits: reg%d_%d
• Trailing characters for library cells: /I1/U$1
• These trailing characters are truncated automatically and are ignored.

This is controlled by the the analysis effort level used with set mapping method –
name_effort <low|medium|high>. By default, it is configured to -name_effort
high.

No extra input is required from the user to map the key points whose names differ by
one of these criteria.

For example, the flops names get mapped automatically without any additional user
inputs, though the array delimiter is different (square-bracket in Golden design and
under-score in the Revised design).

Figure 23: Mapping ignores trailing chracters

Scope of “set naming style”

The set naming style command covers the standard naming style used by the
Synthesis tool for RTL design. This eases the process of identifying the name changes
done by a synthesis tool so that Conformal LEC effectively matches the RTL key point
names with the netlist key point names with no extra effort.

set naming style <LEC | RC | DC> [-Both|-Golden|-REVised]

(Setup Mode)

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Fundamentals of Key Point Mapping in Conformal

This command will impact the following naming:

• SystemVerilog union type pin name.

• Rename register type variable name if the generated name has introduced a
name collision issue. Different tools, such as RC and DC, have their own
renaming rule.

• Convert the arithmetic operators (such as '-') to instance names.

o For RC: use "sub_xxx"

o For DC: use "minus_xxx"

• Generated parameterized module name with different parameter values. When

parameter value is negative, we should use "n%d", "n%x", or "_%d" as the string
format to compose the module name.

• Hierarchical name when an operator is used in nested if-then-else or case

statement.

• Hierarchical name when an operator is used in a (nested) function call.

With the set naming style command, LEC will generate variable, instance, and
register names similar to Genus (Cadence Synthesis tool) or Design Compiler (third-
party synthesis tool) making mapping easier.

If you are working with a third party tool for synthesis, use:

set naming style DC

Similarly, for Genus with Legacy User Interface:

set naming style RC

Note that it works only for default synthesis attributes.

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Fundamentals of Key Point Mapping in Conformal

Example

Example of set naming style DC on SV struct and union data type

Golden RTL contains:

typedef struct packed {

bit [1:10] f;
bit [1:0] s;
} struct_1;

typedef union packed {

struct_1 s1;
struct_1 s2;
} my_union_type;

module top (u1,clk,out);

input [11:0] u1;
output [11:0] out;
input clk;
my_union_type ff1;
always @(posedge clk) begin
ff1 =u1;
end
assign out = ff1 ;
endmodule
With set naming style LEC (default), the register names will be generated as:

ff1[s1][s][0],
ff1[s1][f][1],
etc.
With set naming style DC, the register names will be generated as:

ff1_reg[11],
ff1_reg[10],
etc.

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Fundamentals of Key Point Mapping in Conformal

Scope of “set naming rule”

The default synthesis naming styles for the design module, instance, variable, or port
might be overridden by the user. Use set naming rule to define the naming rules to
rename the design module, instance, variable, or port.

This command has to be specified before the read design and read library
commands.

The set naming rule command will impact the following naming conventions:

• Array delimiter
• Field delimiter for VHDL record and SystemVerilog struct type
• SystemVerilog interface delimiter
• Hierarchical separator
• Register naming
• Parameter
• Instance naming (simple and generate-loop instance names)
• Tristate instances
• Inverted Pin Extension

For example, if the register instance name in Golden Verilog was a/b/data[3:0], and
the synthesis tool generated four register names as a.b.data_3, a.b.data_2,
a.b.data_1, and a.b.data_0, the hierarchy separator, array delimiter, and register
name will be modified by the synthesis tool.

By default, LEC will generate register names differently as a/b/data_reg[0],

a/b/data_reg[0], a/b/data_reg[0], and a/b/data_reg[0].

To generate register names in the same fashion in LEC, use the following naming rules
to construct register instance names in the same manner in Conformal LEC:

SETUP> set naming rule "_" "" -Array_delimiter -golden

SETUP> set naming rule "%s" -Register -golden
SETUP> set naming rule "." -Hierarchical_separator -golden

For more examples, refer to the Conformal Command Reference Manual.

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Fundamentals of Key Point Mapping in Conformal

Using pattern based naming rules

When the modified key point names follow a regular pattern, pattern-based rules
provide a powerful mechanism to rename the key points to match its counterpart in the
other design. Use the add renaming rule command to create the PERL regular-
expression based naming rules with the following syntax:

LEC/SETUP> add renaming rule <rule_name> \

"search_string" "replace_string" -golden | -revised \
<other options> [-replace]

Note:

• Can be used in SETUP mode as well as LEC mode, enabling iterative mapping
of the Not-mapped key points

• If changes are to be applied in Golden design, use the –golden option, else
choose –revised.

• The search string and the replace string are represented as a Perl
regular expression.

• The <rule_name> should be unique.

• To overwrite an existing rule, use the -replace option.

• The rules are applied on all the Not-mapped key points. If there are multiple
rules, these are applied in the order declared.

• Renaming rules can be specified for key points, modules, and pin renaming of
blackboxes. To learn more about module renaming and pin renaming for
blackboxes, refer to the Handling Black Box During Formal Verification
application note.

• For a list of <other options> and detailed explanation of this command, refer
to the Conformal Command Reference Manual.

• If the pattern contains any of the special characters such as %, . , *, +, ^, $, |,

(,) , [,] , or \, precede these with the back-slash ‘\’ character to cancel their
special connotation. In the TCL mode of LEC, use curly braces ‘{ }’ to enclose
the entire pattern including the escape ‘\’ character.

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Fundamentals of Key Point Mapping in Conformal

• Do not mix the set mapping method –noname command with the add
renaming rule command. It will disable the renaming rules.

For example, if the register names of every bit of a bus is named as follows (changes
are highlighted in yellow), it involves a lot more changes than can be handled by the
commands described so far.

Golden instance pathname Revised instance pathname

syndrm/macreg_1/q_reg[ syndrm/macreg_03/q_reg(7)/g2/
7] i0

Name-based mapping will not be able to map these instances automatically, initially
leaving these Not-mapped in the “Unmapped Points” section of Mapping Manager
UI.

Figure 24: Not-mapped key point list dislayed in Mapping Manager window

For the previous case, two renaming rules will be required for mapping:

LEC> add renaming rule r1 "macreg_%d" "macreg_0@1" –revised

LEC> add renaming rule r2 "q_reg$%d$" "q_reg\[@1\]" –
revised
LEC> map key points

After use of the renaming rules, the registers will be shown in the “Mapped Points”
section of the Mapping Manager UI:

Figure 25: Register mapping after renaming

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Fundamentals of Key Point Mapping in Conformal

Take care of the order in which the rules are defined. An incorrect order may result in
unwanted name changes. If there are multiple rules in the script, these will be applied
serially one by one, so the second rule will be applied to the output string of the first
rule.

Note: Additionally, mapping of blackbox instances involve adjusting module and pin
names, if they differ. One typical example is replacing a RAM memory cell in the Golden
design, with a cell from a different library in the Revised design, where both the module
and pin names might differ.

To learn more about mapping intricacies of blackboxes, read the Handling Black Box
During Formal Verification application note from the Cadence Online Support.

Using dynamic arithmetic expression in naming rules

If a range of key points are renamed in the Revised design such that these represent a
dynamic arithmetic expression, containing +, -, *, or /, of the numbers used in the
Golden design, you can use a single and compact add renaming rules with the
#(expression) and perform a name-based mapping for the entire range.

The (expression) will contain the arithmetic formula.

For example, if the bit-order of a register bank is reversed as follows:

Golden instance pathname Revised instance pathname

syndrm/macreg_1/q_reg[7:0 syndrm/macreg_1/q_reg[0:7
] ]

The renaming rule might be written in a compact manner as follows:

SETUP> add renaming rule R3 "q_reg\[%d\]" "q_reg[#(7-@1)]"

-revised

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Reporting available renaming rules

To list the available renaming rules, use the report renaming rules command, as
shown in the following example:

SETUP/LEC> report renaming rule

Mapping renaming rules (in apply order):

===========================================================
Name Apply to Rename pattern Substitution pattern
-----------------------------------------------------------
R1 Golden %w\[%d\] @1_@2
R2 Revised _abc
===========================================================
To see how many key points were mapped by different renaming rules, use the set
analyze option –analyze_renaming_rules command, with the balanced
extraction of instances enabled. To enable balanced extractions, use one of the
modelling options like -seq_constant.

During the modeling of key points, LEC analyzes the renaming rules and tabulates how
may key points were mapped by each renaming rule, as shown in the following
example:

SETUP> set analyze option –analyze_renaming_rules

SETUP> set flatten model –seq_const // for balanced
extractions

...

SETUP> set sys mode lec

// Processing Golden ...
// Modeling Golden ...
// Processing Revised ...
// Modeling Revised ...
// Renaming Rule Analysis (DFF/DLATs)
===========================================================
Rule Matches(g) Matches(r) Mapped %
-----------------------------------------------------------
0 0
Rule1 9 0 0 0
Rule2 0 6 0 0

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Reviewing renamed key points

Even after renaming a key point, the report mapped points command displays the
original key point name. To see the modified name, use the –rename option with the
report mapped points command, as shown in the following example:

The first result shows the original instance names and the second result shows the
modified names, after applying the renaming rules.

LEC> report mapped points q_size_reg[8]

Mapped point for

(G) + 11 PO /q_size_reg[8]
is
(R) + 11 PO /q_size_reg_8
LEC> report mapped points q_size_reg[8] -rename

Mapped point for

(G) + 11 PO /q_size_reg_8
is
(R) + 11 PO /q_size_reg_8
In the Mapping Manager UI, if you hover the mouse over the key point (whether it is
Not-mapped, or Mapped), the original as well as the modified name of the key point are
displayed. Press CTRL+q to show it as a pop-up balloon information box or CTRL+m to
display it in the transcript window, as follows:

Figure 26: Info Box showing original and renamed strings

Learn more at Cadence Online Support - http://support.cadence.com

Using renaming rules with manual mapping

You can combine the power of the renaming rules with the add mapped point
command to extend the scope of this command to all the Not-mapped key points,
using the –rule option as follows:

LEC> add mapped points –rule <target_pattern>

<substitution_string> [-golden|-revised] [-invert|-
noinvert]

Note:

• This option can be applied for instance mapping only, and cannot be used for pin
or module renaming.
• -noinvert and –golden are default options, hence can be omitted.

After a successful mapping, the mapped key points are displayed with the gate-id and
phase information.

For example, to map a set of Not-mapped registers y_reg[3:0] of the Golden design
with the corresponding registers flop_reg[3:0] in the Revised design, use add
mapped points with renaming rules as follows:

Figure 27: Instantaneous mapping with add mapped point

This option is particularly useful to iteratively clean up Not-mapped points in LEC

mode. The advantage of this command over add renaming rules applied in LEC
mode is that it does not require an explicit call to the map key points command to
invoke mapping.

Learn more at Cadence Online Support - http://support.cadence.com

Use of renaming rules in module uniquification

When there are multiple instantiation of the same module, unique module names are
generated by Conformal with the uniquify command, to avoid ambiguity during
hierarchical comparison.

However, the instance path names in the Golden as well as the Revised design need to
match for uniquify to take effect. Therefore, the non-matching hierarchical instance
names need to be first matched through renaming rules before attempting uniquification
of their module names. At the same time, consideration of the instance renaming rules
need to be enabled through the -use_renaming_rules option of the uniquify
command.

For example, Conformal will not be able to run the uniquify command for the
following instance pairs, because the instance path names are different:

Golden instance pathname Revised instance pathname

/a/b1/c1/d[0] a1/b1.c1/d0

/a/b1/c1/d[1] a1/b1.c1/d1

/a/b1/c1/d[2] a1/b1.c1/d2

/a/b1/c1/d[3] a1/b1.c1/d3

Learn more at Cadence Online Support - http://support.cadence.com

However, if module uniquification is preceded with renaming rules to help these to

match, they will be staged for unification, as shown here:

SETUP> add renaming rule r1 "\." "/" –revised

SETUP> add renaming rule r2 "/d\[%d\]" "/d@1" -golden
SETUP> uniquify -use_renaming_rules -all
Instance '/a/b1/c1/d[3]' in Golden:
changed from module 'd' to 'd3'
Instance '/a/b1/c1/d[2]' in Golden:
changed from module 'd' to 'd2'
Instance '/a/b1/c1/d[1]' in Golden:
changed from module 'd' to 'd1'
Instance '/a/b1/c1/d[0]' in Golden:
changed from module 'd' to 'd0'
Uniquified 4 instance(s) referring to module 'd' in Golden
Uniquified 1 module(s)

Please refer to the Conformal Command Reference Manual for a detailed explanation
on the usage of the uniquify command.

Mapping of multiple pins or bus to a single pin in

Conformal
To properly balance the fanout load on a primary input, the implantation tool can create
duplicate input pins in the Revised design. LEC cannot automatically infer the duplicate
pins. Therefore, it requires an explicit association of the duplicate pins to the
representative pin.

LEC will map the Golden primary input with the representative input pin in the Revised
design. Unless the duplicate pins are linked in this manner, these will appear as Not-
mapped key points and cause false non-equivalence.

Learn more at Cadence Online Support - http://support.cadence.com

To declare a set of primary inputs as duplicates, use the add pin equivalence
command with the following syntax:

SETUP> add pin equivalences \

<representative_primary_input> <duplicate_primary_input*
..> \
[-Invert <duplicate_primary_input* ...>] \
[-ROot | -Module <module_name*> | -All] \
[-Golden | -REvised | -Both]
Prefix the duplicate primary input list with –invert, if phase inversion is involved.

Use the report pin equivalence command to check the pin association.

In the following example, during clock-tree synthesis (CTS), the implementation tool
created one extra primary input CLK_INV for the inverted clock. To declare it as an
inverted equivalent pin of the original clock input, CLK, use the following command:

SETUP> add pin equivalence CLK –invert CLK_INV –revised

Now, LEC will map the CLK pin from both the designs, using name-based mapping.

In some scenarios, the implementation tool can create multiple duplicate pins as a bus.
To map the bits of such a bus, use a wildcard for all bits or specify every bit individually
as duplicate members.

For example, if the primary input inputA in the Golden design is cloned as a bus
inputA[3:0] in the Revised design, use the following command to map the bus:

SETUP> add pin equivalence inputA[0] inputA* -revised

SETUP> add pin equivalence inputA[0] inputA[1] inputA[2]

inputA[3] -revised

Learn more at Cadence Online Support - http://support.cadence.com

Mapping multidimensional ports and registers in RTL

Synthesis tools flatten multi-dimensional ports and registers defined in RTL into single-
dimensional vector elements. In this process of degenerating the extra dimensions, the
names of the objects would become dissimilar and name-based mapping can be very
challenging for these. Function-based mapping is not recommended because, the
chance of incorrect inference is high in this case.

Use the set naming rule –mdportflatten command to flatten the

multidimensional arrays into a single-dimensional array.

However, at times, this command may not be sufficient. You may also need additional
naming rules to match the following:

• the naming style of the synthesis tool

• array delimiter
• field delimiter
• interface delimiter (for VHDL record and SystemVerilog struct and union data
type)

In some cases, renaming rules might be useful to specify the name correlation.

For example, a SystemVerilog multidimensional array might be declared with a packed

array as follows:

typedef struct packed {

bit_x [3:0] amask;
union packed {
struct packed {
bit_x [1:0] [63:0] d;
} harv;
struct packed {
bit_x [15:0] [7:0] d;
} dude;
} bus;
} mydata_t;

...
input mydata_t DATA;

Learn more at Cadence Online Support - http://support.cadence.com

On the other hand, the Revised netlist represents the same bus as a single-bit vector as
follows:

input [131:0] DATA;

By default LEC expands the SystemVerilog multidimensional port into individual bits as
follows:

DATA[bus][harv][d][0][0]
DATA[bus][harv][d][0][1]
...
DATA[bus][harv][d][0][63]
DATA[bus][harv][d][1][0]
DATA[bus][harv][d][1][1]
...
DATA[bus][harv][d][1][63]

Use the set naming rule –mdportflatten -golden command to flatten the
multidimensional array into a single-dimensional array and map these.

However, third-party synthesis tools always, by default, flatten multiple dimensions into a
single dimension when the data type involves the SystemVerilog, union.

In the previous example, it will flatten the port as 128 bit scalars as follows, flattening
the union inside the struct:

DATA[bus][127]
DATA [bus][126]
DATA [bus][125]
...
DATA [bus][0]
Therefore, if it is a third-party netlist, only use the following command, to match the
naming style. You may require to add some renaming rules to fine-tune the mapping.

set naming style DC

Similarly, Cadence Synthesis Tool RTL Compiler (RC), by default, preserves complex
port structures and expands it in the same manner as LEC. Therefore, the following would
suffice to complete the mapping:

set naming style RC

Learn more at Cadence Online Support - http://support.cadence.com

If the default bus delimiter was further changed in the synthesis tool, consider applying
the following commands to match these:

set naming style DC|RC

set naming rule -Array_delimiter <left_string>
<right_string>
set naming rule -Field_delimiter <left_string>
<right_string>
set naming rule -INTerface_delimiter <left_string>
<right_string>

If the multi-dimensional port is a blackbox pin, you can use a renaming rule as shown in
the following example. Note that the renaming rules may contain equations.

// convert black box pins bus[a][b] to bus[32*a+b]

SETUP> add renaming rule rnr1 "%s\[%d\]\[%d\]"

"@1[#(32*@2+@3)]" -pin

The key to making the right choice of commands lies in understanding how the ports were
transformed in the Revised netlist and applying the command that will help change the
structure in the RTL accordingly.

Importing name-change information file from third-

party synthesis tool
LEC supports two methods to import name modification information:

• Importing change-name text file

• Importing VSDC file from DC

Learn more at Cadence Online Support - http://support.cadence.com

Importing change-name text file

If a history of the name changes made in design ports and nets on instance names
during synthesis is recorded in the third-party synthesis tool, you can straightaway
import the information in LEC, using the change name command, with the following
syntax:

SETUP> change name <name-change filename>

If this file meets the format expected by LEC, it can be used to perform all the name
changes required to correctly map all the key points in one go.

Genus with Legacy UI and DC generate the name-change file in a format supported by
LEC. With this command, LEC is able change the names in a post synthesis netlist back
to their original, pre-synthesis forms.

Here is an excerpt of such a file:

Design Type Object New Name

----------------------------------------------------------
mod0_module port port0_input1 port0_1
mod0_module net net0_output net0_t
mod1_module port port1_input1a port_1a
mod1_module cell net1_subinstantiation net1_n
If the name changes are recorded in multiple iterations in multiple files, then you must
read the files in the reverse order to successfully change the names to their original
form.

For example:

The first name change is recorded in file1, the second in file2, and the third in file3.

Filename Old name New Name

file1 port[0]_input[0] port0_input0
file2 port0_input0 port_0_input_0
file3 port_0_input_0 port_0_0

Learn more at Cadence Online Support - http://support.cadence.com

So, to convert the name port_0_0 back to the original name port[0]_input[0],
you need to read the change name files in the following order:

SETUP> change name file3

SETUP> change name file2
SETUP> change name file1
To learn how to generate the name-change file in Genus with Legacy UI and DC in the
previous format, refer to the command reference manual of the respective synthesis
tools.

Importing VSDC file

DC records all the relevant operations, including name-change information, in an

automatically generated VSDC file, which contains a series of TCL commands stored in
ASCII text format. This VSDC file is intended for use in formal verification tools to
facilitate alignment of key points.

To import name-change information from a VSDC file, use the read setup command
with the -apply_name_change option as follows:

SETUP> read setup information \

–type VSDC <VSDC file> \
-apply_name_change
Unlike the LEC change_names command, the previous command can decipher multiple
name change operations in one go. Therefore, a single invocation of this command is
sufficient to handle multi-level name changes of design objects.

Learn more at Cadence Online Support - http://support.cadence.com

Mapping of single-bit registers to multibit register

cells
The synthesis and physical implementation tools can replace a group of single-bit
registers with multibit register cells for better optimization. The multibit instance name
can be generated using different naming styles and it can be very hard for LEC to infer
the single bit register names from it.

LEC uses different techniques to correctly map single-bit registers to the corresponding
multibit cells in the other design.

To learn more about mapping methodologies for mapping and verification of multibit
register cells, refer to the Verification of Multibit Cells application note.

Impact of register naming style on imported

optimization information
LEC can import register optimization information from the synthesis log or VSDC file
through the read setup information command. However, the information may be
overlooked, if the register names generated in LEC, do not match the register names
captured in the imported data, in case of strictly name-based mapping.

The report setup information –usage command displays how much of the
imported information is actually utilized in modeling the design.

SETUP/LEC> report setup information -usage

===========================================================
Used Unused Rejected Ignored
-----------------------------------------------------------
seq_const_0 4657 0 0 64
seq_const_1 16 0 0 0
seq_duplication 449 0 0 0
cell_name_change 1456 6057 0 0
port_name_change 3524 799 0 0
===========================================================

Learn more at Cadence Online Support - http://support.cadence.com

If all register optimization information (like declining and optimization to logic 0/1) crowd
under the Unused column, you need to check if the register names between imported
data and LEC are dissimilar. Use set naming rule –register or use add
renaming rules, to equate the register naming style.

For example, the imported data might have _foo_reg added as a suffix to all the
register names. This does not match with the default register naming style of LEC,
which adds _reg as a suffix to the register names. The mismatch in register names will
lead to skipping of the imported information.

To resolve this mismatch, use the set naming rule as follows, before reading the Golden
design:

SETUP> set naming rule “%s_foo_reg” –register –golden

…
SETUP> read setup information –type VSDC <filename>
…
LEC> read setup information -usage
If name-change file(s) from the third-party synthesis tool is available up to the point
when the VSDC file is generated, read these in LEC using the change name command
to transform the object names appearing in the VSDC file to the original names of the
Golden design.

Learn more at Cadence Online Support - http://support.cadence.com

Impact of Auto-modeling on Mapping

When the tool switches from SETUP mode to LEC mode, it performs an auto modeling
(also called balanced modeling) of instances. In auto modeling, instances are mapped
even if these are unreachable or sequential constant registers.

Figure 28: Balanced modeling message

Auto modeling is turned on by default. It can also be turned on using:

SETUP> set flatten model –auto_modeling

Auto-modeling is turned off using:

SETUP> set flatten model –noauto_modeling

If -noauto_modeling is selected, the tool will model away the sequential constant
registers as logic constants and then map the remaining key points. This is likely to
result in less number of mapped points.

Learn more at Cadence Online Support - http://support.cadence.com

Mapping in Hierarchical Comparison

In the case of hierarchical comparison, key point mapping takes place in the same
manner as in the case of flat comparison.

Some aspects worth keeping in mind during mapping are as follows:

• You do not need to worry about the design hierarchy when defining renaming
rules with the add renaming rules command. It is sufficient to declare these
based on the patterns that require alteration. LEC will try to match these for all
the key points of the hierarchical modules under comparison.

For example, if the register names changed from a/b/c/d_reg[100] to

a/b/c/d_reg_bit_100, between the Golden RTL to the Revised netlist, the
following renaming rule is adequate. There is no need to include the exact design
hierarchy. This will also act as a safeguard against the addition or removal of
levels in hierarchy, due to instance grouping or ungrouping in the Synthesis tool.

SETUP> add renaming rule “%w\[%d\]” @1_bit_@2 -golden

• If some nets are preserved during synthesis and you want to compare the cones
of the net, declare CUT gates on the preserved net without bothering about its
hierarchy, as follows:

SETUP> add cut point <net name> [-golden | -revised]

However, all path-based commands should be declared only after module

uniquification. Use the uniquify –all –nolib command to equalize any
module name difference between the Golden and Revised, before using the add
cut point point commands. LEC is smart enough to break it down to the
correct net path names, when it compares a module at a lower hierarchy.

For example, when it is comparing the adder4 module, LEC will convert the
CUT gate specification on the net enable_add, as shown here, with a clear
message about importing the constraint:

Learn more at Cadence Online Support - http://support.cadence.com

// Command: set root module adder4 -Golden

// Command: set root module adder4 -Revised
// Command: set module property -instance /proc_0/add_0 -
Golden
// Command: set module property -instance /proc_0_add_0 -
Revised
// Command: report black box -NOHidden
// Command: set system mode lec
…

Applying top-level pathname-based constraints

// Command: add cut point enable_add –Golden
End of top-level pathname-based constraints
• Mapped points written out from a flat-comparison session can be used as it is in
the hierarchical session, without any editing.

Performance Consideration for Mapping

Nowadays, it is common to come across key points to the tune of millions. Mapping of
large number of key points can take a lot of time, if the correct approach is not adopted.

Be aware of the following factors that can increase runtime exponentially.

1. Enabling phase mapping by set mapping method -phase on the entire

design may take longer for LEC to map all the key points.

Recommendation

Phase mapping should be used with caution. If phase inverted key points exist in
the design, then you can use methods explained in the sections:

• Enable phase mapping at submodule level

• Auto-inferring phase relationship

Learn more at Cadence Online Support - http://support.cadence.com

2. Enabling the mapping of Unreachable key points adds to an overhead in the

runtime. Unreachable key points do not influence the functionality of any
Primary Output of the design.

Recommendation

It is always recommended not to spend time in mapping the Unreachable key

points and use:

SETUP> set mapping method –nounreach

3. Function-based mapping requires path traversals and therefore slows the
performance. If a large number of key points are mapped by this method, it may
severely degrade the mapping run time of Conformal LEC.

To check how many key points are mapped by function-based mapping, use the
set mapping method –method –summary command.

Recommendation

Try to map the key points by name-based mapping methods as much as

possible.

To learn about various methods in name-based mapping, refer to the Facilitating

Name-based mapping section.

4. Mapping a file written out by the write mapped points” command, contains
one-to-one mapping commands in terms of the add mapped points
command. Conformal executes the add mapped points command in isolation
one by one and immediately maps it. Every execution of the add mapped
points command incur some CPU cycles.

If the mapping file contains a very large of mapping commands, importing the
data might consume much more time than using the pattern-based renaming
rules that work on key points in one go.

Learn more at Cadence Online Support - http://support.cadence.com

Mapping in Lowpower Flow

Mapping methods are no different for lowpower aware equivalence check (also known
as LP EC). Out of all the lowpower cells, only the sequential lowpower cells will
participate in mapping. Therefore, the state-retention cells and latch-based isolation
cells will be the new additions to the design.

State-retention-power-ground cells (SRPG) are registers that can be identified and

mapped in the same manner as any other register in the design.

Latch-based isolation cells inserted by Conformal will get mapped by function and runs
a minute risk of getting mapped to an incorrect latch in the Golden design. In such
cases, use manual mapping to correct it. Refer to the Rectifying incorrect mapping
section to learn the techniques to fix incorrect mapping.

Implication of Mapping in Conformal ECO

Patch generation in Conformal ECO (C-ECO) is directly related to the Not-mapped and
Extra key points. The following table enumerates the implications of the Not-mapped
and Extra key points for patch generation:

Patch affected by Golden design Revised design

Not-mapped key points Removed from design Added to the patch

Extra PI/PO Removed from design Added as ECO ports

If the hierarchical module name and instance names do not match, there is a possibility
of mis-correlation that can affect the Not-mapped key point count and cause false Non-
equivalence.

If the patch module name is different between the Golden and the Revised design, use
add renaming rule with the -module option or use the unquify –all –nolib
-golden command to level out these differences. If the key point names are
transformed beyond recognition, use add renaming rules to help map instances
correctly and prevent against false Not-mapped key points.

Learn more at Cadence Online Support - http://support.cadence.com

References
Conformal Equivalence Checker Command Reference Manual

Conformal Equivalence Checker User Guide

Handling Black Box during Formal Verification application note

Verification of Multibit Cells application note

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