Computer Architecture

Lecture 9.
. Digital Logic.

Instructors

Elena Boldyreva, Associate Professor eaboldyreva@itmo.ru

E-mail for questions itmo-hdu-np@yandex.ru

GOALS OF THIS LECTURE: PLAN:
1. get terminology about digital 1. Boolean Algebra
logical elements 2. Combinational Circuit
2. get understanding of Boolean 3. Read-Only Memory (ROM)
algebra role 4. Sequential Circuit
3. more details about its 5. Counters
hardware realization

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

©. Stallings, William. Computer organization and architecture : designing for performance 2
 Boolean Algebra

• Mathematical discipline used to design and analyze the behavior of the digital circuitry in
digital computers and other digital systems
• Named after George Boole
– English mathematician
– Proposed basic principles of the algebra in 1854
• Claude Shannon suggested Boolean algebra could be used to solve problems in relay-switching
circuit design
• Is a convenient tool:
– Analysis
• It is an economical way of describing the function of digital circuitry
– Design
• Given a desired function, Boolean algebra can be applied to develop a simplified
implementation of that function

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 Boolean Variables and Operations

• Makes use of variables and operations

– Are logical
– A variable may take on the value 1 (TRUE) or 0
(FALSE)
– Basic logical operations (Boolean basis) are AND,
OR, and NOT
• AND
– Yields true (binary value 1) if and only if both of its
operands are true
– In the absence of parentheses the AND operation
takes precedence over the OR operation
– When no ambiguity will occur the AND operation is
represented by simple concatenation instead of the
dot operator
• OR
– Yields true if either or both of its operands are true
• NOT
– Inverts the value of its operand
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 Boolean Variables and Operations

(a) Boolean Operators of Two Input Variables

(b) Boolean Operators Extended to More than Two Inputs (A, B, . . .)

Operation Expression Output = 1 if

AND A•B•… All of the set {A, B, …} are 1.
OR A+B+… Any of the set {A, B, …} are 1.
NAND A · B·… Any of the set {A, B, …} are 0.
NOR A + B+… All of the set {A, B, …} are 0.
XOR AÅBÅ… The set {A, B, …} contains an
odd number of ones.

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 Basic Identities of Boolean Algebra
Basic Postulates
A•B=B•A A+B=B+A Commutative Laws
A • (B + C) = (A • B) + (A • C) A + (B • C) = (A + B) • (A + C) Distributive Laws
1•A=A 0+A=A Identity Elements
A• A =0 A+ A =1 Inverse Elements
Other Identities
0•A=0 1+A=1
A•A=A A+A=A
A • (B • C) = (A • B) • C A + (B + C) = (A + B) + C Associative Laws
A·B= A + B A +B= A· B DeMorgan's Theorem

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Basic Logic Gates

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 Basic Logic Gates

A A
A A

A (A+B)
A A B A+B
A B B
B

A
A A
A

A+B A B

B B
B B

Figure 11.2 Some Uses of NAND Gates Figure 11.3 Some Uses of NOR Gates

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 Combinational Circuit

An interconnected set of gates whose output at any

time is a function only of the input at that time

The appearance of the input is followed

almost immediately by the appearance of
the output, with only gate delays

Consists of n binary inputs and m binary

outputs

Can be defined in three ways:

• Truth table
• For each of the 2n possible combinations of input
signals, the binary value of each of the m output
signals is listed
• Graphical symbols
• The interconnected layout of gates is depicted
• Boolean equations
• Each output signal is expressed as a Boolean function
of its input signals

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 A Boolean Function of Three Variables

Table 11.3 A B C

A B C F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
F
1 0 1 0
1 1 0 1
1 1 1 0

Figure 11.4 Sum-of-Products Implementation of Table 11.3

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 A Boolean Function of Three Variables

A
A
B C
C

A
B
C

A F
B F B
C

B
A Figure 11.6 Simplified Implementation of Table 11.3
C

A
B
C

Figure 11.5 Product-of-Sums Implementation of Table 11.3

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A Boolean Function of Three Variables

AB BC
00 01 11 10 00 01 11 10
1 1 0 1 1
A
1 1
(a) F = AB + AB
(b) F = ABC + ABC + ABC

CD
C
00 01 11 10
00 1
01
AB B
11 1
A
10 1

(c) F = ABCD + ABCD + ABCD

D
(d) Simplified Labeling of Map

Figure 11.7 The Use of Karnaugh Maps to Represent Boolean Functions

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 A Boolean Function of Three Variables
CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10
00 00 1 00
01 1 1 01 01 1 1
AB AB AB BC
11 11 11
00 01 11 10
10 10 1 10
0 1 1
(a) ABD (b) BCD (c) ABD A
1 1
CD CD CD
(a) F = AB + BC
00 01 11 10 00 01 11 10 00 01 11 10
00 1 1 1 1 00 00
01 01 1 1 01 1 1
AB AB AB CD
11 11 1 1 11 1 1
00 01 11 10
10 10 10
00
(d) AB (e) BC (f) BD

AB 01 1
CD CD CD 11 1 1
00 01 11 10 00 01 11 10 00 01 11 10
00 1 1 1 1 00 1 1 00 1 1 10 1
AB 01 1 1 1 1 AB 01 1 1 AB 01 1 1
(b) F = BCD + ACD
11 11 1 1 11 1 1
10 10 1 1 10 1 1
(g) A (h) D (i) C
Figure 11.9 Overlapping Groups
Figure 11.8 Example Use of Karnaugh Maps
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Truth Table for the One-Digit Packed
Decimal Incrementer

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 Multiplexer
A multiplexer is a digital combinational logic circuit with n inputs and one output. Its purpose is to
connect one of the inputs to the output line, depending on a control signal. The general symbol of a
multiplexer is shown below.

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2-to-1 Multiplexer

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 4-to-1 Multiplexer

4-to-1 Multiplexer Truth Table

S2 S1 F
0 0 D0
0 1 D1
1 0 D2
1 1 D3

C0 IR0 ALU0 C1 IR1 ALU1 C15 IR15 ALU15

S2 4-to-1 S2 4-to-1 S2 4-to-1

S1 MUX S1 MUX S1 MUX

PC0 PC1 PC15

Figure 11.14 Multiplexer Input to Program Counter

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 Demultiplexer

A demultiplexer is a combinational logic circuit that performs the opposite function as

that of a multiplexer.

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 Decoder
A decoder is a combinational circuit with a number of output lines, only one of which is
asserted at any time. Which output line is asserted depends on the pattern of input lines. In
general, a decoder has n inputs and 2n outputs.
A 000
D0

B
001
D1

C
010
D2

011
D3

100
D4

101
D5

110
D6

111
D7

Figure 11.15 Decoder with 3 Inputs and 2 3 = 8 Outputs

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 Address decoding

A0

A7

n-bit
256 X 8 256 X 8 256 X 8 256 X 8
destination n-to-2n
address 2n outputs
RAM RAM RAM RAM decoder
Enable

Enable

Enable

Enable
Data input
A8
2-to-4
A9 decoder

Figure 11.17 Implementation of a Demultiplexer Using a Decoder

Figure 11.16 Address Decoding

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 Read-Only Memory (ROM)

• Memory that is implemented with combinational circuits

– Combinational circuits are often referred to as “memoryless” circuits because
their output depends only on their current input and no history of prior
inputs is retained
• Memory unit that performs only the read operation
– Binary information stored in a ROM is permanent and is created during the
fabrication process
– A given input to the ROM (address lines) always produces the same output
(data lines)
– Because the outputs are a function only of the present inputs, ROM is a
combinational circuit

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 Read-Only Memory (ROM)

0000
0001
Table 11.8 0010
0011
Truth Table for a ROM 0100
0101
X1 0110
Input Output 4-input 0111
X2
X1 X2 X3 X4 Z1 Z2 Z3 Z4 16-output 1000
X3
decoder 1001
0 0 0 0 0 0 0 0 X4
1010
0 0 0 1 0 0 0 1 1011
0 0 1 0 0 0 1 1 1100
1101
0 0 1 1 0 0 1 0 1110
0 1 0 0 0 1 1 0 1111
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0 Z1 Z2 Z3 Z4
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Figure 11.18 A 64-Bit ROM

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 Adder
Table 11.9
Binary Addition Truth Tables

(a) Single-Bit Addition (b) Addition with Carry Input

A B Sum Carry Cin A B Sum Cout
0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 1 1 0
1 0 1 0 0 1 0 1 0
1 1 0 1 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
(b) Addition with Carry Input
1 1 0 0 1
rry Cin A B Sum Cout 1 1 1 1 1
A3 B3 A2 B2 A1 B1 A0 B0
0 0 0 0 0 0
0 0 0 1 1 0
0 0 1 0 1 0 Overflow
signal C3 Cin C2 Cin C1 Cin C0 Cin 0
1 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
S3 S2 S1 S0
1 1 0 0 1
1 1 1 1 1

Figure 11.19 4-Bit Adder

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 Adder

A
B
C

A
B
C
Sum
A31 B31 A31 B31 A23 B23 A16 B16 A15 B15 A 8 B8 A7 B7 A 0 B0 A
B
C

C23 C15 C7
Cout 8-bit 8-bit 8-bit 8-bit Cin A
adder adder adder adder B
C

A
S31 S24 S23 S16 S15 S8 S7 S0 B

A
Carry
C

Figure 11.21 Construction of a 32-Bit Adder Using 8-Bit Adders

B

Figure 11.20 Implementation of an Adder

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 Sequential Circuit

• 1. Current output depends not only on the current

input, but also on the past history of inputs

• 2. Makes use of combinational circuits

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 Flip-Flops

• Simplest form of sequential circuit

• There are a variety of flip-flops, all of which share two properties:

1.The flip-flop is a bistable device. It exists in one of two states and, in the absence of
input, remains in that state. Thus, the flip-flop can function as a 1-bit memory.
2.The flip-flop has two outputs, which are always the complements of each other.

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S-R Flip Flop

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Master Slave JK Flip Flop

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Delay Flip Flop / D Flip Flop

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Toggle Flip Flop / T Flip Flop

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 Basic Flip-Flops

Name Graphical Symbol Truth Table

S Q S R Qn+1
0 0 Qn
S-R Ck 0 1 0
1 0 1
R Q 1 1 –

J Q J K Qn+1
0 0 Qn
J-K Ck 0 1 0
1 0 1
K Q 1 1 Qn

D Q D Qn+1
0 0
D Ck 1 1

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 PLD Terminology
Table 11.11 PLD Terminology

Programmable Logic Device (PLD)

A general term that refers to any type of integrated circuit used for implementing digital
hardware, where the chip can be configured by the end user to realize different designs.
Programming of such a device often involves placing the chip into a special programming unit,
but some chips can also be configured “in-system”. Also referred to as a field-programmable
device (FPD).

Programmable Logic Array (PLA)

A relatively small PLD that contains two levels of logic, an AND-plane and an OR-plane,
where both levels are programmable.

Programmable Array Logic (PAL)

A relatively small PLD that has a programmable AND-plane followed by a fixed OR-
plane.

Simple PLD (SPLD)

A PLA or PAL.

Complex PLD (CPLD)

A more complex PLD that consists of an arrangement of multiple SPLD-like blocks
on a single chip.

Field-Programmable Gate Array (FPGA)

A PLD featuring a general structure that allows very high logic capacity. Whereas
CPLDs feature logic resources with a wide number of inputs (AND planes), FPGAs offer more
narrow logic resources. FPGAs also offer a higher ratio of flip-flops to logic resources than do
CPLDs.

Logic Block
A relatively small circuit block that is replicated in an array in an FPD. When a circuit is
implemented in an FPD, it is first decomposed into smaller sub-circuits that can each be mapped
into a logic block. The term logic block is mostly used in the context of FPGAs, but it could also
refer to a block of circuitry in a CPLD.

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 PLD Examples
I1 I2 I3

“OR” array

Logic
block

I/O
block

“AND” array

(a) Layout for 3-input

2-output PLA O1 O2

A B C

ABC

AB

AC

(b) Programmed PLA

ABC + AB AB + AC
Figure 11.32 An Example of a Programmable Logic Array
Figure 11.33 Structure of an FPGA

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 Simple FPGA Logic Block

A0 2-to-1
MUX

lookup table
A1

16 1
D Q
A2

A3 Ck

Clock

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 Conclusion

▪ Boolean Algebra ▪ Sequential Circuits

▪ Gates – Flip-Flops
– Registers
▪ Combinational Circuits – Counters
– Implementation of Boolean Functions
▪ Programmable Logic Devices
– Multiplexers
– Decoders – Programmable Logic Array
– Field-Programmable Gate Array
– Read-Only-Memory
– Adders

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