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UNIT-I INTRODUCTION TO 8085 ARCHITECTURE

PART - A

1. What is stack and what is the use of stack pointer? (Dec-2015)

The stack is a reserved area of the memory in the RAM where temporary
information may be stored. A 16-bit stack pointer is used to hold the address of
the most recent stack entry.

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2. Mention the use of ALE. (Dec-2015, Dec-2013, May-2010)
The ALE signal is used to demultiplex (separate) AD0 – AD7 lines to A0 – A7

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(address lines) and D0 – D7 (data lines). The separation of address lines and
data lines is achieved by connecting a external latch to AD 0 – AD7 lines and

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enabling the latch when signal is active.
3. State the functions of keyboard interrupts. (Dec-2014)

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Keyboard interrupt is special case of signal usually generated by the keyboard in
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the text user interface. This signal is used to generate a hardware interrupt when
a key is pressed or released.
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4. List the 8085 flags. (Dec-2014, Dec-2013)

Various flags are :
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S (Sign flag), Z (Zero flag), AC (Auxiliary carry flag), P (Parity flag), CY (Carry
flag).
5. What is meant by level-triggered interrupt? Which of the interrupts in 8085
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are level triggered? (May-2014)

A level triggered interrupt is an interrupt signaled by maintaining the interrupt line
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at a high or low level. A device wishing to signal a level triggered interrupt drives
the interrupt request line to its active level (high or low), and then holds it at that
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level until it is recognized by microprocessor. In 8085 microprocessor, RST 5.5,

RST 6.5, INTR, TRAP are level triggered interrupts. TRAP is both level as well as
edge triggered interrupt.

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6. What is the function of program counter in 8085

microprocessor? (May-2013)
Program counter stores the address of the next instruction to be fetched. Thus it
is used as pointer to the instruction.
7. What is trap interrupt and its significance? (May-2012)
This interrupt is a non-maskable interrupt. It is unaffected by any mask or
interrupt enable. TRAP has the highest priority. TRAP interrupt is edge and level

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triggered. This means that the TRAP must go high and remain high until it is
acknowledged. This avoids false triggering caused by noise and transients.

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8. List the control and status signals of 8085 and mention its
need. (Dec-2012)

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ALE (Address Latch Enable)
and (Read and Write)

IO/ , S0 S1 e
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READY
9. Define the function of parity flag and zero flag in 8085. (May-2012)
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Parity flag – Parity is defined by the number of one‟s present in the accumulator.
After an arithmetic or logical operation if the result has an even number of ones,
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ie., even parity, the flag is set. If the parity is odd, flag is reset.
Zero flag – the zero flag sets if the result of operation in ALU is zero and flag
resets if result is non zero. The zero flag is also is also set if a certain register
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content becomes zero following an increment or decrement operation of that

register.
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10. To obtain a 320 ns clock, what should be the input clock frequency? What
is the frequency of clock signal at CLK OUT? (May-2014)
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System clock frequency = 1/T = 1 / 320*10-9 = 3.125 MHz

Crystal clock frequency = 2* System clock frequency
= 2*3.125*106
= 6.25 MHz
The frequency of clock signal at CLK OUT= Crystal frequency/2
= 6.25/2
=3.125 MHz.

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11. List the five interrupts pins available in the 8085.

(May-2010)
The five interrupt pins are
TRAP, RST 7.5, RST 6.5, RST 5.5, INTR.
12. Specify the size of data, address, and memory word and memory capacity
of 8085 microprocessor. (May-2011)
Size of data bus = 8-bits Size Size of address bus = 16-bits

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of memory word = 8-bits Memory capacity = 64 Kbytes
13. What is interrupt? (May-2006, May-2009)

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Interrupt is an external signal that causes a microprocessor to jump to a specific
subroutine.

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14. How performance of a microprocessor is measured in terms of MIPS?
(June-2007)
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The performance of a microprocessor is measured in terms of MIPS (Million
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instructions per Second).
MIPS rate = 1/(Average time required for the execution of instruction * 106)
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15. What are the different machine cycles in 8085 microprocessor? (May-2008)
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Opcode fetch, Memory read, Memory write, I/O read, I/O write, Interrupt
acknowledge, Bus idle.
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PART B

1.Draw and explain the architecture of 8085 in detail. (Nov/Dec-2013)

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Address Bus:
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The address bus is a group of 16 lines generally identified as A0 to A15. The address
bus is unidirectional and bits flow in one direction-from the MPU to peripheral
devices.The MPU uses the address bus to identify a peripheral or a memory (2 16 =
65,536) locations

Data Bus:

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The data bus is a group of 8 lines used for data flow. These lines are bi-directional and
data flow in both directions between the MPU and memory and peripheral devices. The
MPU uses the data bus to transfer data.
Control Bus:
The control bus carries synchronization signals and providing timing signals.The MPU
generates specific control signals for every operation it performs.These signals are used
to identify a device type with which the MPU wants to communicate.

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Registers of 8085:
The 8085 have six general-purpose registers to store 8-bit data during program execution.

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These registers are identified as B, C, D, E, H, and L.They can be combined as
registerpairs-BC, DE, and HL-to perform some 16-bit operations.

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Accumulator (A):
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The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).This
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register is used to store 8-bit data and to perform arithmetic and logical operations.The
result of an operation is stored in the accumulator.
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Flags:
The microprocessor uses the 5 flags for testing the data conditions.They are Zero (Z),
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Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags.The flagsare set or reset
according to the result of an operation.The bit position for the flags in flag register is,
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Figure: Architecture of 8085 Microprocessor

1. Sign Flag (S): If D7 of the result is1, the sign flag is set. Otherwise it is
reset. D7 is reserved for indicating the sign;
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If D7 is 1, the number will be viewed as negative number.

If D7 is 0, the number will be viewed as positive number.
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2. Zero Flag (Z): If the result of arithmetic and logical operation is zero, then zero flag is
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set. Otherwise it is reset.

3. Auxiliary Carry Flag (AC): If D3 generates any carry when doing any arithmetic and
logical operation, this flag is set. Otherwise it is reset.

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4. Parity Flag (P): If the result of arithmetic and logical operation contains even number
of 1's then this flag will be set and if it is odd number of 1's it will be reset.

5. Carry Flag (CY):If any arithmetic and logical operation result any carry then carry
flag is set otherwise it is reset.

Arithmetic and Logic Unit (ALU):

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It is used to perform the arithmetic operations like addition,subtraction, multiplication,
division, increment and decrement and logical operations like AND,OR and EX-OR.

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It receives the data from accumulator and registers.According to the result the flag
register was set or reset.

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Program Counter (PC):
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This 16-bit register sequencing the execution of instructions. The function of the
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program counter is to point to the memory address of the next instruction to be
executed.When an opcode is being fetched, the program counter is incremented by one
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to point to the next memory location.

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Stack Pointer (SP):

The stack pointer is also a 16-bit register used as a memory pointer.It points to a
memory location in R/W memory, called the stack.The beginning of the stack is defined
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by loading a 16-bit address in the stack pointer.

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Temporary Register:
It is used to hold the data during the arithmetic and logical operations.
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Instruction Register:
When an instruction is fetched from the memory, it is loaded in the instruction register.

Instruction Decoder:

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It gets the instruction from the instruction register and decodes the instruction. It
identifies the instruction to be performed.

Serial I/O Control:

It has two control signals named SID and SOD for serial data transmission.

Timing and Control unit :

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It has three control signals ALE, RD (Active low) and WR (Active low) and three status
signals IO/M(Active low), S0 and S1.

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ALE is used for provide control signal to synchronize the components of

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microprocessor and timing for instruction to perform the operation.

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RD (Active low) and WR (Active low) are used to indicate whether the operation is
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eading the data from memory or writing the data into memory respectively.
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IO/M(Active low) is used to indicate whether the operation is belongs to the memory
or peripherals.
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2.Draw the signal (pin diagram) configuration of 8085 and explain the purpose of
each signals. (Dec-2012)
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8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as
follows
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Power supply and clock signals

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Address bus
Data bus
Control and status signals
Interrupts and externally initiated signals
Serial I/O ports

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Direct Memory Access (DMA):

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Fig:Pin Diagram of 8085 Microprocessor

Power supply and Clock frequency signals:

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Vcc : + 5 volt power supply

Vss : Ground
X1, X2 : Crystal or R/C network or LC network connections to set the
frequency of internal clock generator.The frequency is internally divided by

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two. Since the basic operating timing frequency is 3 MHz, a 6 MHz crystal is
connected externally.
CLK (OUT):Clock Output is used as the system clock for peripheral and
devices interfaced with the microprocessor.

Address Bus:A8 - A15 (Input)

It carries the most significant 8 bits of the memory address or the 8 bits of the I/O

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address;

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Multiplexed Address / Data Bus:AD0 - AD7 (Input/Output)
These multiplexed set of lines used to carry the lower order 8 bit address as well as

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data bus.

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During the opcode fetch operation, in the first clock cycle, the lines deliver the
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lower order address A0 - A7.
In the subsequent IO / memory, read / write clock cycle the lines are used as
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data bus.
The CPU may read or write out data through these lines.
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Control and Status signals:

Control Signals:
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ALE (output) - Address Latch Enable.

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This signal helps to capture the lower order address presented on the
multiplexed address / data bus.
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RD (output , active low) - Read

This indicates that the selected memory location or I/O device is to be read and
the data bus is ready for accepting data from the memory or I/O device.

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WR (output, active low) - Write

This indicates that the data on the data bus is to be written into the selected
memory location or I/O device.

IO/M (output) - Memory/ IO

This status signal indicates that the read / write operation relates to whether the

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memory or I/O device.
It goes high to indicate an I/O operation.

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It goes low for memory operations.

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Status Signals:S1,S0

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It is used to know the type of current operation of the microprocessor.
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S1 S0 Operation Specified
0 0 Halt
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0 1 Memory Or I/O Write

1 0 Memory Or I/O Read
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1 1 Instruction Fetch
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Interrupts and Externally initiated operations:

They are the signals initiated by an external device to request the microprocessor
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to do a particular task or work.

There are five hardware interrupts called,
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1. TRAP
2. RST 7.5
3. RST 6.5
4. RST 5.5
5. INTR

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TRAP interrupt is a nonmaskable restart interrupt. It is unaffected by any mask or

Interrupt Enable. It has the highest priority of any interrupt.

RESTART INTERRUPTS: These three inputs have the same timing as INTR. They
are RST 7.5,RST 6.5, RST 5.5

Types of Interrupts Priority

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TRAP Highest
RST 7.5

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RST 6.5
RST 5.5

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INTR Lowest

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On receipt of an interrupt, the microprocessor acknowledges the interrupt by the
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active low INTA (Interrupt Acknowledge) signal.

Reset In (input, active low)

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This signal is used to reset the microprocessor.

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The program counter inside the microprocessor is set to zero.

The buses are tri-stated.
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Fig:Signal Diagram of 8085 Miicroprocessor

Reset Out (Output)
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It indicates CPU is being reset.

Used to reset all the connected devices when the microprocessor is reset.
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Serial I/O ports:

SID (input) - Serial Input Data

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Serial input data line The data on this line is loaded into accumulator bit 7
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whenever a RIM instruction is executed.

SOD (output) - Serial Output Data
The output SOD is set or reset as specified by the SIM instruction.
These signals are used for serial communication.

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Direct Memory Access (DMA):

HOLD :HOLD signal is generated by the DMA controller circuit. The I/O device
request the processor for the address/data bus for bulk data transfer.
HLDA:(HOLD ACKNOWLEDGE) On receipt of HOLD signal, the microprocessor
acknowledges the request by sending out HLDA signal and leaves out the control
of the buses. After the HLDA signal the DMA controller starts the direct transfer

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of data.

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READY (input)

Memory and I/O devices will have slower response compared to

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microprocessors.
Before completing the present job such a slow peripheral may not be able to
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handle further data or control signal from CPU.
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The processor sets the READY signal after completing the present job to access
the data.
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The microprocessor enters into WAIT state while the READY pin is disabled.

3.Explain the interrupt structure of 8085 microprocessor. (Nov/Dec-2013)

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Interrupt is a signal send by an external device to the processor, to perform a

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particular task or work. Mainly in the microprocessor based system the interrupts are
used for data transfer between the peripheral and the microprocessor. When a
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peripheral is ready for data transfer, it interrupts the processor by sending an

appropriate signal to the interrupt pin of the processor. If the processor accepts the
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interrupt then the processor suspends its current activity and executes an interrupt
service subroutine to complete the data transfer between the peripheral and processor.
After executing the interrupt service routine the processor resumes its current activity.
This type of data transfer scheme is called interrupt driven data transfer scheme.

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Types of Interrupts :
The interrupts are classified into software interrupts and hardware interrupts.

SOFTWARE INTERRUPTS:
The software interrupts are program instructions. These instructions are inserted at
desired locations in a program. While running a program, lf a software interrupt
instruction is encountered, then the processor executes an interrupt service routine

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(ISR).
The software interrupts of 8085 are RST 0, RST 1, RST 2, RST 3, RST 4, RST 5,

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RST6 and RST7.
All software interrupts of 8085 are vectored interrupts. The software interrupts cannot be

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masked and they cannot be disabled. When the processor encounters the software
instruction, it pushes the content of PC to stack. Then loads the Vector address in PC
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and starts executing the ISR stored in this vector address. At the end of ISR, a return
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instruction – RET will be placed. When the RET instruction is executed, the processor
POP the content of stack to PC.
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Interrupt Vector address

RST 0 0000H
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RST 1 0008H
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RST 2 0010H

RST 3 0018H
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RST 4 0020H
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RST 5 0028H

RST 6 0030H

RST 7 0038H

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HARDWARE INTERRUPTS:
The hardware interrupts are initiated by an external device by placing an appropriate
signal at the interrupt pin of the processor.The processor keeps on checking the
interrupt pins at the second T-state of last machine cycle of every instruction.If the
processor finds a valid interrupt signal and if the interrupt is unmasked and enabled,
then the processor accepts the interrupt.The acceptance of the interrupt is
acknowledged by sending an INTA signal to the interrupted device. The processor

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saves the content of PC in stack and then loads the vector address of the interrupt in
PC.If the interrupt is non-vectored, then the interrupting device has to supply the

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address of ISR when it receives INTA signal. It starts executing ISR in this address.At
the end of ISR, a return instruction, RET will be placed.When the processor executes

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the RET instruction, it POP the content of top of stack to PC. Thus the processor control
returns to main program after servicing interrupt.
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The hardware interrupts of 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR
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Further the interrupts may be classified into VECTORED and NON-VECTORED
INTERRUPTS.
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VECTORED INTERRUPT:
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In vectored interrupts, the processor automatically branches to the specific address in

response to an interrupt.
The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts.
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The vector addresses of hardware interrupts are given in the table.

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Interrupt Vector address

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TRAP 0024H

RST 7.5 003CH

RST 6.5 0034H

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RST 5.5 002CH

NON-VECTORED INTERRUPT:
In non-vectored interrupts the interrupted device should give the address of the interrupt
service routine (ISR).
The INTR is a non-vectored interrupt.

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When a device interrupts through INTR, it has to supply the address of ISR after
receiving interrupt acknowledge signal.

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TRIGGERING EDGE OF 8085 INTERRUPTS:

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The TRAP interrupt is edge and level sensitive.To initiate TRAP, the interrupt signal has
to make a low to high transition and then it has to remain high until the interrupt is

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recognized.The RST 7.5 interrupt is positive edge sensitive. To initiate the RST 7.5, the
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interrupt signal has to make a low to high transition and it need not remain high until it is
recognized.The RST 6.5, RST 5.5 and INTR are level sensitive interrupts.Hence for
these interrupts the interrupting signal should remain high, until it is recognized.
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MASKABLE & NON-MASKABLE INETRRUPTS:

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The hardware vectored interrupts are classified into

Maskable Interrupts.
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Non-maskable Interrupts.
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Non-maskable Interrupts:
The interrupts which cannot be disabled are called Non-maskable Interrupts.
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TRAP is non-maskable interrupt.

Maskable Interrupts:
The interrupts which can be enabled or disabled are called Maskable Interrupts.
RST 7.5, RST 6.5, RST 5.5 and INTR are Maskable interrupt.

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Masking is preventing the interrupt from disturbing the main program.When an interrupt
is masked the processor will not accept the interrupt signal.The interrupts can be
masked by executing SIM instruction. (SIM - Set InterruptMask).The status of maskable
interrupts can be read into accumulator by executing RIM instruction (RIM - Read
Interrupt Mask).All the hardware interrupts, except TRAP are disabled, when the
processor is resetted.They can also be disabled by executing DI instruction. (Dl-Disable
Interrupt).When an interrupt is disabled, it will not be accepted by the processor.To

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enable the disabled interrupt, the processor has to execute El instruction (El-Enable
Interrupt).

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INTERRUPT PRIORITY:

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The order in which the interrupt has to be serviced is called Interrupt Priority.The priority
order of the 8085 interrupt is
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Interrupt Interrupt Priority

TRAP 1
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RST 7.5 2
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RST 6.5 3

RST 5.5 4
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INTR 5
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IMPORTANT SUMMARY ABOUT INTERRUPTS:

S.No Interrupt Vector Triggering Edge Maskable / Interrupt

Address Priority
Type Non-Maskable

1 TRAP 0024H Edge and level Non-Maskable 1

Sensitive

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2 RST 7.5 003CH Positive Edge Sensitive Maskable 2

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3 RST 6.5 0034H Level Sensitive Maskable 3

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4 RST 5.5 002CH Level Sensitive Maskable 4

5 INTR Non- Level Sensitive Maskable 5

Vectored e
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4..Draw the timing diagram for Opcode Fetch machine cycle, Memory Read
machine cycle,MemoryWrite,I/O read machine cycle and I/O write machine Cycle.
(Nov/Dec-2014)
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Instruction Cycle:
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The time required to execute an instruction is called instruction cycle.

Machine Cycle
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The time required to access the memory or input/output devices is called machine
cycle.
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T-State
A portion of an operation carried out in one system clock period is called as T-state.The
machine cycle and instruction cycle takes multiple clock periods.

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Opcode Fetch Machine Cycle:

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Fig: Timing Diagram of 8085 Microprocessor

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Opcode fetch cycle is part of any instruction execution. In this machine cycle 8085
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fetches opcode of instruction. The following are the sequence of actions that are
performed by 8085 to fetch an opcode from memory. This machine cycle consists of 4
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T-states.

8085 places 16-bit address from PC on to the address bus and issues ALE pulse in
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first T-state (T1). This is used to de-multiplex the address and data bus. It also issues
IO/M‟ signal to „0‟. This indicates that processor is performing memory related
operation. In second T-state (T2) processor issues RD‟ control signal to memory.
This enables memory to put data present at the address location given in previous T-
state on to data bus. RD‟ control signal is active for two clock pulses.

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In T3 state memory places opcode on Data bus. Processor reads opcode present on
data bus and de-asserts RD‟ signal. Thus data bus goes into high impedance state.

In T4 state processor decodes instruction and necessary actions are performed.

Memory Read machine cycle:

This machine cycle is required when an operand is present in memory. This machine

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cycle requires three T-states. The following are the sequence of actions performed by
microprocessor during this machine cycle.

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In the first T-state (T1) 8085 places address on address bus and issues ALE signal.
And also IO/M‟ signal is made low, since it is memory related operation.

In the second T-state (T2), processor issues RD‟ control signal to memory. In
response to this memory places data on data bus.

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In the third T-state (T3), processor reads data from data bus, and de-asserts RD‟
signal.

Memory Write Machine cycle:

This machine cycle is required when the results of operation needs to store in memory.
This machine cycle requires three T-states. The following are sequence of actions

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performed by processor in this machine cycle.

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In first T-state (T1), 8085 processor places 16- bit address on address bus and issues
ALE signal. And also it makes IO/M‟ signal to low, indicating it is memory related
operation.

In second T-state (T2), processor places data to be written on data bus and asserts
WR‟ signal to the memory.

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In the third T-state (T3), memory stores the data and processor de-asserts WR‟
signal.

IO read machine cycle:

This machine cycle is required, when data needs to be read from an input device. This
machine cycle requires three T-states. The following are the sequence of actions

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performed by processor during this machine cycle.

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In the first T-state (T1) 8085 places port address(for IO mapped addresses port
address is 8-bit, but for memory mapped addresses IO device address is 16-bit, but
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reading from such is performed by memory read machine cycle) on address bus and
issues ALE signal. And also IO/M‟ signal is made high, since it is IO related operation.
In the second T-state (T2), processor issues RD‟ control signal to IO peripheral.
In response to this input device places data on data bus.

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In the third T-state (T3), processor reads data from data bus, and de-asserts RD‟
signal.

IO write Machine cycle:

This machine cycle is required when data needs to be output to an output device. This
machine cycle requires three T-states. The following are the sequence of actions

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performed by processor during this machine cycle.

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In first T-state (T1), 8085 processor places 8-bit port address on address bus (for IO
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mapped addresses port address is 8-bit, but for memory mapped addresses, IO device
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address is 16-bit, but writing to such is performed by memory write machine cycle) and
issues ALE signal. And also it makes IO/M‟ signal to high, indicating it is IO related
operation.

In second T-state (T2), processor places data to be written on data bus and asserts
WR‟ signal to the peripheral.

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In the third T-state (T3), peripheral accepts the data and processor de-asserts
WR‟ signal.
5.Explain how the memory organization was done in 8085.
8085 has 16 bit address bus, hence it can access 2 16 no. of memory locations,
which is equal to 64KB memory. Memory is required to store program as well as data.
Since microprocessor doesn‟t have on-chip memory, we need to connect it

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externally.So it requires addressing mechanism.
The following are the steps involved in interfacing memory with 8085 processor.

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1. First decide the size of memory requires to be interfaced. Depending on
this we can say how many address lines are required for it. For example if you
want to interface 4KB (212) memory it requires 12 address lines. Remaining

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address lines can be used in address decoding.
2.
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Depending on the size of memory required and given address range,
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construct address decoding circuitry. This address decoding circuitry can be
implemented with NAND gates and/or decoders or using PAL.
3. Connect data bus of memory to processor data bus.
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4. Generate the control signals required for memory using IO/M‟, WR‟, RD‟
signals of 8085 processor.
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Example:
Interface 4KB memory to 8085 with starting address A000H.
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1. 4KB memory requires 12 address lines for addressing as already

mentioned. But 8085 has 16 address lines. Hence four of address lines are used
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for address decoding

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2. Given that starting address for memory is A000H. So for 4KB memory
ending address becomes A000H+0FFFH (4KB) = AFFFH.

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A0-A11 address lines are directly connected to address bus of memory chip. A12-A15
are used for generating chip select signal for memory chip.

Address decoding circuit using 3X8 decoder:

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A15 line is use for enabling 74x138 decoder chip. A12, A13, A14 lines are connected to
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74X138 chip as inputs. When theses lines are 010 output should be „0‟. This is provided
at O2 pin of 74X138 chip.
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Address decoding circuit using only NAND gates:

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A15, A14, A13, A12 inputs should be 1010, for enabling the chip. So the circuit for this
is as shown above.

Types of address decoding:

There are two types of address decoding mechanism, based on address lines used for
generating chip select signal.

.in
1. Absolute decoding
2. Partial decoding

ng
Absolute decoding:
All the higher order lines of microprocessor, left after using the required signals for

eri
memory are completely used for generating chip select signal.This type of decoding is
called absolute decoding.
Partial decoding: e
gin
Only some of the address lines of microprocessor left after using the required
signals for memory are used for generating chip select signal. Because of this multiple
En

address ranges will be formed. If total memory space is not required for the system
then, this type of address decoding can be used. The advantage of this technique is
fewer components are required for memory interfacing because of this board size
arn

reduces and in turn cost reduces.

Le
w.
ww

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UNIT-II 8085 INSTRUCTION SET AND PROGRAMMING

PART - A
1. What is indexing? NOV/DEC 2012
Indexing technique allows programmer to point or refer the data stored in sequential
memory locations one by one.
2.What are the various types of 8085 instructions?
MAY/JUNE2013,NOV/DEC2011

.in
1. Data transfer group – MOV A,B
2. Arithmetic group – ADD B

ng
3. Logical group- ANA B
4. Branch group – JMP LABEL

eri
5. Stack I/O and Machine Control group – PUSH,POP,HLT.
3. Explain the difference between a JMP instruction and CALL instruction.
MAY/JUNE2012 e
gin
A JMP instruction permanently changes the program counter.
A CALL instruction leaves information on the stack so that the original program
En

execution sequence can be resumed.

4. What is meant by lookup table? NOV/DEC 2014
arn

A lookup table is an array that replaces runtime computation with a simpler array
indexing operation.The savings in terms of processing time can be significant, since
retrieving a value from memory is often faster than undergoing an expensive
Le

computation or input/ouput operation.

5. Explain the functioning of CMP instructions? NOV/DEC 2015
w.

This instruction subtracts the contents of the specified register from contents of
the accumulator and sets the condition flags as a result of the subtraction.
ww

6. Mention the similarity and difference between compare and subtract

instructions. May/June 2014
The compare and subtract instructions both are subtract one operand from
another and sets the flag register accordingly.The subtract instruction stores the result
in the accumulator while the compare instruction does not store any result except flags.

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7. State the purpose and importance of NOP instruction. May/June 2014

The NOP instruction in CPU‟s is to insert a time delay.It may be useful to force
the CPU to wait for external (slower) devices to complete its work.
8. What are the different types of addressing modes?NOV/DEC 2013,MAY/JUNE
2012
The addressing modes specifies the location of the operand(data). The different
types are as follows

.in
1. Immediate addressing
2. Register addressing

ng
3. Direct addressing
4. Indirect addressing

eri
5. Implicit addressing
9. Define stack and stack related instructions? MAY/JUNE
2013,NOV/DEC2012 e
gin
The stack is a group of memory locations in the R/W memory that is used for the
temporary storage of binary information during the execution of the program. The stack
En

related instructions are PUSH and POP

10. State the function of given 8085 instructions:JP,JPE,JPO,JNZ
arn

JP – Jump on positive S=0

JPE- Jump on parity even P=1
JPO- Jump on parity odd P=0
Le

JNZ-Jump if no zero Z=0

11.What are subroutine?
w.

Subroutine are group of instructions stored as a separate program in memory

and it is called from the main program whenever required.
ww

12.What is a recursive procedures?

A recursive procedure is a procedure, which calls itself. Recursive procedures
are used to work with complex data structures called trees. If the procedure is called
with N=3,then the N is decremented by 1 after each procedure CALL and the procedure
is called until N=0.

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13. How to access subroutine with in the main program procedure? NOV/DEC
2013
i) Accessed by CALL & RET instruction
ii)Machine code of instruction is put only once in the
memory iii)With procedures less memory is required
iv)Parameters can be passed in registers, memory location or stack

.in
14.What are the four instructions which control the interrupt structure of the
8085 microprocessor?

ng
DI(disable interrupts)
EI(enable interrupts)

eri
RIM(read interrupt masks)
SIM(set interrupt masks)
e
15. How the microprocessor is synchronized with peripherals?
gin
The timing and control unit synchronizes all the microprocessor operations with
clock and generates control signals necessary for communication between the
En

microprocessor and peripherals.

arn

PART - B

1. What are the different addressing modes in 8085 microprocessor? Explain it

Le

with an example? NOV/DEC 2015,NOV/DEC 2014,NOV/DEC 2012,MAY/JUNE 2012

MAY/JUNE 2011
w.

Addressing mode specifies the location of operand(data).Every instruction of a

ww

program has to operate on a data. The method of specifying the data to be operated by
the instruction is called Addressing.
The 8085 has the following 5 different types of addressing.
1. Immediate Addressing
2. Direct Addressing

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3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing

1.Immediate Addressing :
In immediate addressing mode, the data is specified in the instruction itself. The data
will be a part of the program instruction.All instructions that have „I‟ in their mnemonics

.in
are of Immediate addressing type.

ng
Example: MVI A, 01H- Move the data 01H given in the instruction to A register.

eri
2.Direct Addressing :
In direct addressing mode, the address of the data is specified in the instruction.The
e
data will be in memory. In this addressing mode, the program instructions and data can
gin
be stored in different memory blocks. This type of addressing can be identified by 16-bit
address present in the instruction.
En

Example:LDA 4500H- Load the data available in memory location 4500H in A register.
arn

3.Register Addressing :
In register addressing mode, the instruction specifies the name of the register in which
Le

the data is available.This type of addressing can be identified by register names in the
instruction.
w.

Example: MOV A, B -Move the content of B register to A register.

ww

4.Register Indirect Addressing :

In register indirect addressing mode, the instruction specifies the name of the register in
which the address of the data is available. The data will be in memory and the address
will be in the register pair.

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This type of addressing can be identified by letter „M‟ present in the instruction.

Example: MOV A, M - The content of memory (data) addressed by HL pair is

moved to A register.

5.Implied Addressing :
In implied addressing mode, the instruction itself specifies the type of operation and

.in
location of data to be operated. This type of instruction does not have any address,
register name, immediate data specified along with it.

ng
Example:CMA - Complement the content of accumulator

eri
2.Explain the Different types of instruction in 8085. NOV/DEC 2013,MAY/JUNE
e
2013,NOV/DEC 2012,MAY/JUNE 2012,MAY/JUNE 2011
gin
An instruction is a command given to the microprocessor to perform specified operation
on a given data.The instruction set of a microprocessor is the collection of instructions
En

that the microprocessor is designed to execute.It is classified into

1. Data Transfer Instructions.
arn

2. Arithmetic Instructions.
3. Logical Instructions.
4. Branching / Control Transfer Instructions.
Le

5. Stack & I/O Machine Control Instructions.

w.

1.DATA TRANSFER INSTRUCTIONS:

The data transfer instructions move the data between registers or between registers
ww

and memory. It copies the data from source location to destination location.No flags will
be affected.
MOVE INSTRUCTION:

MOV Rd, Rs

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MOV M, Rs
MOV Rd, M
This instruction copies the contents of the source register into the destination register.
The contents of the source register are not altered.If one of the operands is a memory
location, its location is specified by the contents of the HL registers.
Example: MOV B, C - This instruction move the content of C register to B register.
MOV B, M -This instruction move the content of memory location pointed by HL

.in
register to B register.

ng
MOVE IMMEDIATE 8-BIT:

eri
MVI Rd, data
MVI M, data
e
The 8-bit data is stored in the destination registeror memory.If the operand is a memory
gin
location, its location is specified by the contents of the HL registers.
En

Example:MVI A,01 - The data 01 will move to A register.

MVI M, 01 – The data 01 will move to the memory location pointed by HL
arn

registers.

LOAD ACCUMULATOR:
Le

LDA 16-bit address

w.

The contents of a memory location, specified by a16-bit address in the operand, are
copied to the accumulator. The contents of the source are not altered. This is a 3-byte
ww

instruction, the second byte specifies the low-order address and the third byte specifies
the high-order address.
Example: LDA 4000 –The content of memory location 4000 is loaded into A register.

STORE ACCUMULATOR:

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STA 16-bit address

The contents of the accumulator are copied into the memory location specified by the
operand.This is a 3-byte instruction, the second byte specifies the low-order address
and the third byte specifies the high-order address.
Example: STA 4500–The content of A register is loaded into memory location 4500.

EXCHANGE:

.in
XCHG

ng
The contents of register H are exchanged with the contents of register D, and the
contents of register L are exchanged with the contents of register E.

eri
Example: XCHG :This instruction exchange the content of H and L with D and E

2.ARITHMETIC INSTRUCTIONS:
e
The arithmetic instructions includes addition, subtraction ,increment and decrement
gin
operations.
ADDITION:
En

ADD REGISTER OR MEMORY TO ACCUMULATOR

arn

ADD Rs
ADD M
The contents of the operand (register or memory) are added to the contents of the
Le

accumulator and the result is stored in the accumulator. If the operand is a memory
location, its location is specified by the contents of the HL registers. All flags are
w.

modified to reflect the result of the addition.

Example: ADD B – The content of A register is added with the content of B register and
ww

the result is stored in A register.

ADD M -The content of A register is added with the content of
memory location pointed by HL register and the result is stored in A register.

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ADD REGISTER TO ACCUMULATOR WITH CARRY:

ADC R
ADC M
The contents of the operand (register or memory) and the Carry flag are added to the
contents of the accumulator and the result is stored in the accumulator.If the operand is
a memory location, its location is specified by the contents of the HLregisters. All flags
are modified to reflect the result of the addition.

.in
Example: ADC B -The content of A register is added with the content of B register and
also Carry and the result is stored in A register.

ng
ADC M - The content of A register is added with the content of memory location
pointed by HL register and also carry and the result is stored in A register.

eri
ADD IMMEDIATE TO ACCUMULATOR

e
gin
ADI 8-bit data
The 8-bit data (operand) is added to the contents of the accumulator and the result is
En

stored in the accumulator.All flags are modified to reflect the result of the addition.
Example: ADI 45 – The data 45H is immediately added with the content of A register
and result Is stored in A register.
arn

SUBTRACTION:
Le

SUBTRACT REGISTER OR MEMORY FROM ACCUMULATOR

w.

SUBRs
SUB M
ww

The contents of the operand (register or memory) are subtracted from the contents of
the accumulator and the result is stored in the accumulator.If the operand is a memory
location, its location is specified by the contents of the HLregisters.All flags are modified
to reflect the result of the subtraction.
Example: SUB B – The content of A register is subtracted with the content of B register
and the result is stored in A register.

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SUB M -The content of A register is subtracted with the content of memory

location pointed by HL register and the result is stored in A register.

SUBTRACT SOURCE AND BORROW FROM ACCUMULATOR :

SBB R
SBB M

.in
The contents of the operand (register or memory ) and the Borrow flag are subtracted
from the contents of the accumulator and the result is placed in the accumulator. If the

ng
operand is a memory location, its location is specified by the contents of the HL
registers.All flags are modified to reflect the result in accumulator.

eri
Example: SBB B -The content of A register is subtracted with the content of B register
and also Borrow flag and the result is stored in A register.
e
SBB M - The content of A register is subtracted with the content of memory
gin
location pointed by HL register and also Borrow and the result is stored in A register.
En

SUBTRACT IMMEDIATE FROM ACCUMULATOR:

SUI 8-bit data
arn

The 8-bit data (operand) is subtracted from the contents of the accumulator and the
result is stored in the accumulator. All flags are modified to reflect the result of the
subtraction.
Le

Example: SUI 45 -The data 45H is immediately subtracted with the content of A register
and Result is stored in A register.
w.

INCREMENT REGISTER OR MEMORY

ww

INR R
INR M
The contents of the designated (register or memory) are incremented by 1 and the
result is stored in the same place.If the operand is a memory location, its location is
specified by the contents of the HL registers.

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Example:INR B – The content of B register is incremented by 1.

INR M – The content of memory location pointed by HL register is incremented by 1.
INCREMENT REGISTER PAIR:

INX R
The contents of the designated register pair are incremented by1 and the result is
stored in the same place.

.in
Example: INX H – The HL register pair is incremented by 1 and showing the next
memory location.

ng
DECREMENT REGISTER OR MEMORY

eri
DCR R
DCR M
e
The contents of the designated (register or memory) are decremented by 1 and the
gin
result is stored in the same place.If the operand is a memory location, its location is
specified by the contents of the HL registers.
En

Example:DCR B – The content of B register is decremented by 1.

DCR M –The content of memory location pointed by HL register is decremented by 1.
arn

DECREMENT REGISTER PAIR:

Le

DCX R
The contents of the designated register pair are decremented by1 and the result is
w.

stored in the same place.

Example: DCX H – The HL register pair is decremented by 1 and showing the previous
ww

Memory location.

3.LOGICALINSTRUCTIONS:

The logical instructions includes AND,OR,XOR,Complement operations.

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Logical AND :
Logical AND register or memory with accumulator

ANA R
ANA M
The contents of the accumulator are logically ANDed with the contents of the operand
(register or memory), and the result is placed in the accumulator.If the operand is a

.in
memory location, its address is specified by the contents of HL registers.S, Z, P are
modified to reflect the result of the operation. CY is reset. AC is set.

ng
Example: ANA B - The content of A register is ANDed with the content of B register
and the result is stored in A register.

eri
ANA M - The content of A register is ANDed with the content of memory
location pointed by HL register and the result is stored A register.
e
gin
LOGICAL AND IMMEDIATE WITH ACCUMULATOR
En

ANI 8-bit data

The contents of the accumulator are logically ANDed with the 8-bit data (operand) and
arn

the result is placed in the accumulator.S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.
Example: ANI 45 -The data 45H is immediately ANDed with the content of A register
Le

and result is stored in A register.

w.

EXCLUSIVE OR REGISTER OR MEMORY WITH ACCUMULATOR

ww

XRA R
XRA M
The contents of the accumulator are Exclusive ORed with the contents of the operand
(register or memory), and the result is placed in the accumulator.If the operand is a
memory location, its address is specified by the contents of HL registers.

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S, Z, P are modified to reflect the result of the operation. CY and AC are reset.
Example: XRA B -The content of A register is XORed with the content of B register and
the result is stored in A register.
XRA M -The content of A register is XORed with the content of memory
location pointed by HL register and the result is stored A register.

EXCLUSIVE OR IMMEDIATE WITH ACCUMULATOR

.in
XRI 8-bit data

ng
The contents of the accumulator are Exclusive ORed with the8-bit data (operand) and
the result is placed in the accumulator.S, Z, P are modified to reflect the result of the

eri
operation. CY and AC are reset.
Example: XRI 45 -The data 45H is immediately XORed with the content of A register
and result is stored in A register. e
gin
LOGICAL OR REGISTER OR MEMORY WITH ACCUMULATOR
En

ORA R
arn

ORA M
The contents of the accumulator are logically ORed with the contents of the operand
(register/memory), and the Result is placed in the accumulator.If the operand is a
Le

memory location, its address is specified by the contents of HL registers.

S, Z, P are modified to reflect the result of the operation. CY and AC are reset.
w.

Example: ORA B -The content of A register is ORed with the content of B register and
the result is stored in A register.
ww

ORA M- The content of A register is ORed with the content of memory

location pointed by HL register and the result is stored A register.

LOGICAL OR IMMEDIATE WITH ACCUMULATOR:

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ORI 8-bit data

The contents of the accumulator are logically ORed with the8-bit data (operand) and the
result is placed in the accumulator.S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: ORI 45 - The data 45H is immediately ORed with the content of A register
and result is stored in A register.

.in
COMPLEMENT ACCUMULATOR:

ng
CMA
The contents of the accumulator are complemented.

eri
No flags are affected.
Example: CMA
e
gin
COMPLEMENT CARRY:
En

CMC
The Carry flag is complemented.No other flags are affected.
arn

Example: CMC

SET CARRY :
Le

STC
w.

The Carry flag is set to 1.No other flags are affected.

Example: STC
ww

4. BRANCHING (CONTROL TRANSFER)INSTRUCTIONS :

The branching instructions are used to change the execution order.They are divided into
conditional jump/call or unconditional jump/call.

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JUMP UNCONDITIONALLY

JMP 16-bit address

The program sequence is transferred to the memory location specified by the 16-bit
address given in the operand.
Example: JMP 4000

.in
JUMP CONDITIONALLY
The program sequence is transferred to the memory location specified by the 16- bit

ng
address given in the operand based on the specified flag of the PSW.

eri
Example:

OPCODE DESCRIPTION e
FLAG STATUS
gin
En

JC Jump on Carry CY = 1

JNC Jump on no Carry CY = 0

arn

JP Jump on Positive S=0

Le

JM Jump on Minus S=1

JZ Jump on Zero Z =1
w.

JNZ Jump on no Zero Z=0

ww

JPE Jump on parity even P=1

JPO Jump on parity odd P=0

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UNCONDITIONAL SUBROUTINE CALL :

CALL 16-bit address

The program sequence is transferred to the memory location specified by the 16-bit
address given in the operand. Before the transfer, the address of the next instruction
after CALL the contents of the program counter is pushed onto the stack.
Example: CALL 4000

.in
CONDITIONAL SUBROUTINE CALL :

ng
The program sequence is transferred to the memory location specified by the 16-bit
address given in the operand based on specified flag of the PSW. Before the transfer,

eri
the address of the next instruction after the call the contents of the program counter is
pushed onto the stack.
e
gin
Example: CZ 4000
En

OPCODE DESCRIPTION FLAG STATUS

arn

CC Call on Carry CY = 1
Le

CNC Call on no Carry CY = 0

CP Call on Positive S=0

w.

CM Call on Minus S=1

ww

CZ Call on Zero Z =1

CNZ Call on no Zero Z=0

CPE Call on parity even P=1

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CPO Call on parity odd P=0

UNCONDITIONALRETURN FROM SUBROUTINE:

RET
The program sequence is transferred from the subroutine to the calling program. The
two bytes from the top of the stackare copied into the program counter, and program

.in
execution begins at the new address.
Example: RET

ng
CONDITIONAL RETURN FROM SUBROUTINE:

eri
The program sequence is transferred from the subroutine to the calling program based
on the specified flag of the PSW.The two bytes from the top of the stack are copied into
e
the program counter, and program execution begins at the new address.
gin
Example: RZ
En

OPCODE DESCRIPTION FLAG STATUS

arn

RC Return on Carry CY = 1
Le

RNC Return on no Carry CY = 0

w.

RP Return on Positive S=0

ww

RM Return on Minus S=1

RZ Return on Zero Z =1

RNZ Return on no Zero Z=0

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RPE Return on parity even P=1

RPO Return on parity odd P=0

5.STACK I/O,MACHINE CONTROL INSTRUCTIONS:

These instructions are used to manipulate the stack to perform the input /output and to

.in
alter the internal control flags.Unless specified the flags are not affected.

ng
STACK INSTRUCTION:

eri
PUSH :

Example: PUSH PSW e

gin
The contents of register A and the contents of condition flags which form the PSW are
pushed onto the stack.
En

POP INSTRUCTION:
arn

Example: POP PSW

The contents of register A and the contents of condition flags which form the PSW are
Le

restored from the stack.

w.

I/O INSTRUCTION :
ww

IN port
The data placed on the 8 bit bidirectional data bus by the specified port is moved to
register A.

OUT port

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The contents of register A are placed on the 8 bit data bus is transferred to the specified
port.

MACHINE CONTROL INSTRUCTION:

EI
The interrupt system is enabled.

.in
DI

ng
The interrupt system is disabled.

eri
NOP

No Operation is performed.No flags are affected.

e
gin
HLT
En

The processor is stopped.No flags are affected.

arn

3.Write an 8085 ALP to add, subtract, multiply and divide two 8 bit numbers
stored at consecutive memory locations. NOV/DEC 2015
Le

8 BIT ADDITION:
w.

ALGORITHM:
ww

1. Initialize memory pointer to data location.

2. Get the first number from memory in accumulator.
3. Get the second number and add it to the accumulator.
4. Store the answer at another memory location.

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PROGRAM:

ADDRESS LABEL MNEMONICS OPERAND COMMENT

4100 START MVI C, 00 Clear C reg.

4101

4102 LXI H, 4500 Initialize HL reg. to

.in
4103 4500

ng
4104

eri
4105 MOV A, M Transfer first data to
accumulator

4106 INX e
H Increment HL reg. to point
gin
next memory Location.

4107 ADD M Add first number to acc.

En

Content.
arn

4108 JNC L1 Jump to location if result

does not yield carry.
4109
Le

410A
w.

410B INR C Increment C reg.

410C L1 INX H Increment HL reg. to point

ww

next memory Location.

410D MOV M, A Transfer the result from acc.

to memory.

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410E INX H Increment HL reg. to point

next memory Location.

410F MOV M, C Move carry to memory

4110 HLT Stop the program

.in
8 BIT SUBTRACTION:

ng
1. Initialize memory pointer to data location.
2. Get the first number from memory in accumulator.

eri
3. Get the second number and subtract from the accumulator.
4. If the result yields a borrow, the content of the acc. is complemented and 01H is
e
added to it (2‟s complement). A register is cleared and the content of that reg. is
gin
incremented in case there is a borrow. If there is no borrow the content of the
acc. is directly taken as the result.
En

5. Store the answer at next memory location.

arn

PROGRAM:

ADDRESS LABEL MNEMONICS OPERAND COMMENT

Le

4100 START MVI C, 00 Clear C reg.

w.

4102

4102 LXI H, 4500 Initialize HL reg. to

ww

4103 4500

4104

4105 MOV A, M Transferfirstdatato

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accumulator

4106 INX H Increment HL reg. to point

next mem. Location.

4107 SUB M Subtract first number from

acc. Content.

.in
4108 JNC L1 Jump to location if result does
not yield borrow.
4109

ng
410A

eri
410B INR C Increment C reg.

410C CMA
e Complement the Acc. Content
gin
410D ADI 01H Add 01H to content of acc.
En

410E

410F L1 INX H Increment HL reg. to point

arn

next mem. Location.

4110 MOV M, A Transfer the result from acc.

Le

to memory.

4111 INX H Increment HL reg. to point

w.

next mem. Location.

ww

4112 MOV M, C Move carry to mem.

4113 HLT Stop the program

8 BIT MULTIPLICATION:

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UNIT- III INTERFACING BASICS AND ICS

PART - A

1. Bring about the features of 8259. (May/June-2014)

It is a programmable interrupt controller. It manages eight interrupt requests. 2.

The interrupt vector addresses are programmable. 3. The priorities of interrupts are

.in
programmable. 4. The interrupt can be masked or unmasked individually

2. How data is transmitted in asynchronous serial communication? (May/June-

ng
2014)

eri
In asynchronous data transfer, one character is transferred at a time. Start and
stop bits are used with each character. The transmitter and receiver use two separate
clock inputs here.
e
gin
3. What are the internal registers available in 8259 PIC? (Apr/May-2015)

Interrupt mask register (IMR), Interrupt Request register(IRR),In service

En

register(ISR) and Priority register(PR)

arn

4. Distinguish between synchronous and asynchronous transmission.

(Apr/May-2015)
Le

Asynchronous synchronous

In this,a word or character is preceeded by a In this,the transmission begins

w.

with a block header,

ww

Start bit and is followed by a stop bit. Which is a sequence of bits.

Data can be sent one character at a time used for transferring large
amount of data

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5. What are the functions of USART? (Nov/Dec-2014)

USART stands for universal Synchronous / Asynchronous Receiver /

Transmitter. It is a programmable communication interface that can communicate by

.in
using either synchronous or asynchronous serial data.

6. What is scan counter in 8279? (Nov/Dec-2012)

ng
The scan counter has two modes to scan the key matrix and refresh the display.

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In the encoded mode, the counter provides binary count that is to be externally decoded
to provide the scan linesfor keyboard and display. In the decoded scan mode, the

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counter internally decodes the least significant 2 bit and provides a decoded 1 out of 4
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scan on SL3-SL 3. The keyboard and display both are in the same mode at a time.

7. What are the basic modes of operations of 8255? (Nov/Dec-2013)

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a) I/O Mode i. Mode 0- Simple Input/Output. ii. Mode 1- Strobe Input/Output

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(handshake mode) iii. Mode 2- Strobe bi-directional mode b) Bit Set/Reset Mode.

8. List out the operating modes in 8253 Timer/Counter. (Nov/Dec-2014)

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Mode 0 : Interrupt on terminal count

MODE 1 : Hardware Retriggerable One-shot

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MODE 2 : Rate generator

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MODE 3 : Square Wave Rate Generator

MODE 4 : Software Triggered Strobe.

MODE 5 : Hardware triggered strobe (Retriggerable).

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9. Give the control word format of 8253 Timer. (May/June-2012)

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10. What is BSR mode in 8255? (Nov/Dec-2012)

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11. What are the different peripheral interfacing used with 8085 microprocessor?
(May/June-2013)

Keyboard, Memory, EPROM, LCD display, LED seven segment displays.

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12. What are the output terminals in USART 8251? (May/June-2013)

TXD (output terminal), TXRDY (output terminal), TXEMPTY (Output terminal), RXRDY
(Output terminal), DTR (Output terminal), RTS (Output terminal)

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13. What are the different types of command words used in 8259A? (Nov/Dec-

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2013)
The command words of 8259A are classified in two groups

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1. Initialization command words (ICWs)
2. Operation command words (OCWs)

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14. What are the basic modes of operation of 8255? (Nov/Dec-2013)

Mode 0: Basic Input/output

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Mode 1: Strobes Input/output

Mode 2: Bi-direction bus.

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15. How data is transmitted in asynchronous serial communication?

(May/June-2014)
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In this the data is transferred bit by bit that is used for one to one communication.
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PART - B
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1.Draw the block diagram of 8255A Programmable Peripheral Interface (PPI) and
explain each block . (May/June-2014)

The Programmable Peripheral Interface (PPI) chip is a peripheral chip.It is made in 40

pin DIP. The 8255 is used to give the CPU access to programmable parallel I/O.. The
8255 has 24 input/output pins in all.These are divided into three 8-bit ports.

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Port A and port B can be used as 8-bit input/output ports.Port C can be used as an 8-
bit input/output port or as two 4-bit input/output ports or to produce handshake signals
for ports A and B.

The three ports are further grouped as follows:

1. Group A consisting of port A and upper part of port C.

2. Group B consisting of port B and lower part of port C.

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Eight data lines (D0 - D7) are available to read/write data into the ports or control
register.The RD andWR pin , which are active low signals for read and write operations.

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The address lines A1 and A0 allow to successively access any one of the ports or the

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control register.The control signal chip select CS is used to enable the 8255 chip. when
CS = '0', the 8255 is enabled.The RESET input is connected to the RESET

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pin8085.When the system is reset, all the ports are initialized as input lines.
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The control register or the command word register is an 8-bit register used to select the
modes of operation and input/output designation of the ports.
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Operational modes of 8255

There are two basic operational modes of 8255:

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Bit set/reset Mode (BSR Mode).

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Input/Output Mode (I/O Mode).

Bit set/reset (BSR) mode

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The Bit Set/Reset (BSR) mode is applicable to port C only.Each line of port C (PC 0 -
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PC7) can be set/reset by suitably loading the control word register. BSR mode and I/O
mode are independent and selection of BSR mode does not affect the operation of
other ports in I/O mode.
A1 A0 Port Selected

0 0 Port A

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0 1 Port B

1 0 Port C

1 1 Control Word Register

BLOCK DIAGRAM OF INTEL 8255:

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CONTROL WORD FOR BSR MODE:

D7 D6 D5 D4 D3 D2 D1 D0

0 * * * B2 B1 B0 S/R

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D7 bit is always 0 for BSR mode.

Bits D6, D5 and D4 are don't care bits.
Bits D3, D2 and D1 are used to select the pin of Port C.
Bit D0 is used to set/reset the selected pin of Port C.

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Selection of port C pin is determined as follows:
B2 B1 B0 Pin of Port C Selected

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0 0 0 PC0
0 0 1 PC1

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0 1 0 PC2
0 1 1 PC3
1 0 0 PC4 e
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1 0 1 PC5
1 1 0 PC6
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1 1 1 PC7
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INPUT/OUTPUT MODE

This mode is selected when D7 bit of the Control Word Register is 1. There are three
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I/O modes
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1. Mode 0 - Simple I/O

2. Mode 1 - Strobed I/O
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3. Mode 2 - Strobed Bi-directional I/O

CONTROL WORD FORMAT FOR I/O MODE:

D7 D6 D5 D4 D3 D2 D1 D0

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Mode 0 - Simple I/O

In this mode, the ports can be used for simple I/O operations without handshaking
signals.
Port A- 8 bit port.
Port B – 8 bit port.
Port C – two 4 bit ports.(Port C upper & Port C lower)

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Mode 0 features:
Output ports are latched.Input ports are buffered, not latched.Ports do not have

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handshake or interrupt capability.With 4 ports, 16 different combinations of I/O are
possible.

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Mode 1:- Strobed I/O
Port A or Port B for handshake (strobed) input or output operation.
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Port A + Port C upper function as handshake signals.
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Port B + Port C lower function as handshake signals.
Mode 1 features:
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Two ports i.e. port A and B can be used as 8-bit i/o ports.Each port uses three lines of
port c as handshake signal and remaining two signals can be used as i/o ports.Interrupt
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logic is supported.Input and Output data are latched.

Input Handshaking signals

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1. IBF (Input Buffer Full)

2. STB (Strobed Input)
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3. INTR (Interrupt request)

4. INTE (Interrupt enable)
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Output Handshaking signals

1. OBF (Output Buffer Full)

2. ACK (Acknowledge)
3. INTR (Interrupt request)
4. INTE (Interrupt enable)

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Mode 2:Strobed Bidirectional I/O

Port A can be used for bidirectional handshake data transfer. Pins PC4 - PC7 are used
as handshake lines for port A.Acknowledgement and handshaking signals are provided
to maintain proper data flow and synchronization between the data transmitter and
receiver.

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2.Discuss the internal architecture of 8253/8254 Programmable Interval timer.
(May/June-2014)

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The Intel 8253 and 8254 are Programmable Interval Timers (PITs), which perform
timing and counting functions and has the same pinout.

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8253 8254

Operating frequency is 0-2.6 Mhz. Operating frequency is 0-10 Mhz.

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Uses N-MOS technology. Uses H-MOS technology.

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Read Back command is not available. Read Back command is available.

Reads and Writes of the same counter Reads and Writes of the same counter can
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cannot be interleaved. be interleaved.

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BLOCK DIAGRAM OF INTEL 8253/8254

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The timer has three counters.or timers which are named as "Counter 0", "Counter 1"
and "Counter 2".Each counter has 2 input pins – "CLK" (clock input) and "GATE" – and
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1-pin, "OUT", for data output. The 3 counters are 16-bit down counters independent of
each other, and can be easily read by the CPU. The first counter is used to generate
atimekeeping interrupt.The second counter is used to trigger the refresh of DRAM
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memory. The last counter is used to generate tones via the PC speaker.

Data/Bus Buffer:
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This block contains the logic to buffer the data bus to / from the microprocessor, and to
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the internal registers. It has 8 input pins, usually labelled as D7..D0, where D7 is the
MSB.

Read/Write Logic:

The Read/Write Logic block has 5 pins.

/RD: read signal

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/WR: write signal

/CS: chip select signal
A0, A1: address lines

Control Word Register:

To initialize the counters, the microprocessor must write a control word (CW) in this
register. This can be done by setting proper values for the pins of the Read/Write Logic

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block and then by sending the control word to the Data/Bus Buffer block.The control
word register contains 8 bits, labeled D7..D0 (D7 is the MSB).

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D7 D6 D5 D4 D3 D2 D1 D0

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SC1 SC2 RW1 RW0 M2 M1 M0 BCD

D0 – 1 = BCD Counter , 0 – Binary Counter e

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D3 D2 D1
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M2 M1 M0 Mode

0 0 0 Mode0
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0 0 1 Mode1

X 1 0 Mode2
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X 1 1 Mode3

1 0 0 Mode4
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1 0 1 Mode5
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D5 D4

RW1 RW0 Operation

0 0 Counter Latching Operation

0 1 Read/Write LSB only

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1 0 Read/Write MSB only

1 1 Read/Write LSB and then MSB

D7 D6

SC1 SC0 Operation

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0 0 Select Counter 0

0 1Select Counter 1

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1 0Select Counter 2

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1 1Illegal

READ BACK COMMAND (ONLY AVAILABLE IN 8254) e

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D7 D6 D5 D4 D3 D2 D1 D0
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1 1 COUNT STATUS CNT2 CNT1 CNT0 0

D5 – 0 = Latch Count of Selected Counters.

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D4 – 0 = Latch Status of Selected Counters.

D3 – 1 = Select Counter 2
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D2 – 1 = Select Counter 1
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D1 – 1 = Select Counter 0
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Operation Modes

Mode 0 : Interrupt on Terminal Count

Mode 0 is used for the generation of accurate time delay under software control. In this
mode, the counter will start counting from the initial COUNT value loaded into it, down

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to 0.Counting rate is equal to the input clock frequency.The OUT pin is set low after the
Control Word is written, and counting starts one clock cycle after the COUNT
programmed. OUT remains low until the counter reaches 0, at which point OUT will be
set high until the counter is reloaded or the Control Word is written. The Gate signal
should remain active high for normal counting. If Gate goes low counting gets
terminated and current count is latched till Gate pulse goes high again.

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Mode 1 : Programmable One Shot
In this mode 8253 can be used as MonostableMultivibrator.GATE input is used as

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trigger input.OUT will be initially high. OUT will go low on the CLK pulse following a
trigger to begin the one-shot pulse, and will remain low until the Counter reaches zero.

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OUT will then go high and remain high until the CLK pulse after the next trigger.

Mode 2: Rate Generator

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In this mode, the device acts as a divide-by-n counter, which is commonly used to
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generate a real-time clock interrupt.Counting process will start the next clock cycle after
COUNT is sent. OUT will then remain high until the counter reaches 1, and will go low
for one clock pulse.OUT will then go high again, and the whole process repeats itself.
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Mode 3 : Square Wave Generator

This mode is similar to mode 2. The duration of the high and low clock pulses of the
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output will be different from mode 2.If „N „is the number loaded into the counter , the
output will be
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High for N/2 counts and N/2 counts for Low if N is Even.
High for (N+1)/2 counts and (N-1)/2 counts for Low if N is Odd.
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Mode 4 : Software Triggered Strobe

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After Control Word and COUNT is loaded, the output will remain high until the counter
reaches zero.The counter will then generate a low pulse for 1 clock cycle (a strobe) –
after that the output will become high again.

Mode 5 : Hardware Triggered Strobe

This mode is similar to mode 4. However, the counting process is triggered by the
GATE input.After receiving the Control Word and COUNT, the output will be set high.

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When the GATE input is high , it will start counting. When the counter reaches 0, the
output will go low for one clock cycle – after that it will become high again, to repeat the
cycle.

3.Draw and explain the functional block diagram of 8259 Programmable Interrupt
Controller. (Apr/May-2015)

Functional Description:

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The 8259 A has eight interrupt request inputs, IR0- IR7.The 8259 A uses its INT output
to interrupt the 8085A via INTR pin.The 8259Areceives interrupt acknowledge pulses

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from the at its input.Vector address used by the 8085 A to transfer control to the service
subroutine of the interrupting device, is provided by the 8259 A on the data bus.

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The 8259A is a programmable device that must be initialized by command words sent
by the. After initialization the 8259A mode of operation can be changed by operation
command words.
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The descriptions of various blocks are,
Data bus buffer:
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This 3- state, bidirectional 8-bit buffer is used to interface the 8259Ato the system data
bus. Control words and status information are transferred through the data bus buffer.
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Read/Write & control logic:

The function of this block is to accept OUTPUT commands from the CPU. It contains
the initialization command word (ICW) register and operation command word OCW)
register which store the various control formats for device operation. This function block
also allows the status of 8259A to be transferred to the data bus.

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Interrupt request register (IRR):
IRR stores all the interrupt inputs that are requesting service.It keeps track of which

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interrupt inputs are asking for service. If an interrupt input is unmasked, and has an
interrupt signal on it, then the corresponding bit in the IRR will be set.

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Interrupt mask register (IMR):
The IMR is used to disable (Mask) or enable (Unmask) individual interrupt inputs.Each

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bit in this register corresponds to the interrupt input with the same number.The IMR
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operation on the IRR. Maskingof higher priority input will not affect the interrupt request
lines oflower priority.To unmask any interrupt the corresponding bit is set „0‟.
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In service register (ISR):

The in service registers keeps tracks of which interrupt inputs are currently being
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serviced.For each input that is currently being serviced the corresponding bit will be set
in the in service register.Each of these 3-reg can be read as status reg.Priority
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Resolver:
This logic block determines the priorities of the set in the IRR. The highest priority is
selected and strobed into the corresponding bit of the ISR during pulse.
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Cascade buffer/comparator:
This function blocks stores and compare the address of all 8259A‟s in the register.The
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associated 3-I/O pins (CAS0-CAS2) are outputs when8259A is used a master.As a

master, the 8259A sends the ID of the interrupting slave device onto the cas2-cas0.The
slave thus selected will send its pre-programmed subroutine address on to the data bus.
Priority Modes of 8259 :
The priority modes availaible in 8259 is

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Fully Nested Mode

Automatic Rotation Mode
Specific Rotation Mode
Fully Nested Mode:
This is a general purpose mode in which all IR‟s are arranged from highest to
lowest ie.IR0 is the highest and IR7 is the lowest one.Any IR can be assigned the

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highest priority,the priority sequence will begin at that IR.
Automatic Rotation Mode:

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In this mode, a device which one is being serviced will be considered as a lowest
priority In the next time.

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Specific Rotation Mode:
This mode is similar to the automatic rotation mode except the user can select
any IR for the lowest priority, thus fixing any other priorities.
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End of Interrupts (EOI):
After the completion of an interrupt service, the corresponding ISR bit needs to
be reset.This is called the End of Interrupt.(EOI).It can be issued in 3 formats.They are
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Non Specific EOI Command:

When the 8259 receives this command,it resets the highest priority ISR bit.
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Specific EOI Command:

It specifies which ISR bit to be reset.
Automatic EOI Command:
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When the 8259 receives the third INTA signal, the ISR bit is reset.The major
drawback of this mode is that ISR does not have information on which IR is being
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serviced.
There are four Initialization Command Word ICW1,ICW2,ICW3&ICW4 and
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three Operation Control Word OCW1,OCW2 &OCW3

Initialization Command Word 1 (ICW1)

D7 D6 D5 D4 D3 D2 D1 D0

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A7 A6 A5 1 LTIM ADI SNGL IC4

D0- 1=ICW4 is needed, 0= No ICW4 needed D1-

1=Single 8259, 0=Cascading 8259's D2- 1=Interval
of 4,0=Interval of 8 D3- 1=level triggered mode,
0=edge triggered mode D5,D6,D7 – Interrupt

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Vector Address

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Initialization Command Word 2 (ICW2)
D7 D6 D5 D4 D3 D2 D1 D0

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A15/T7 A14/T6 A13/T5 A12/T4 A11/T3 A10 A9 A8

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A15-A7 – Interrupt Vector Address (8085 mode)
T7 – T3 - Interrupt Vector Address (8086 mode)
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Operation Control Word 1 ( OCW1)

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D7 D6 D5 D4 D3 D2 D1 D0

M7 M6 M5 M4 M3 M2 M1 M0
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M7-M0 – 1 – Interrupt Mask Set

0 – Interrupt Mask Reset
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4.Draw the neat diagram ,explain the architecture and features of 8279 keyboard /
display controller. (Apr/May-2015)

Block Diagram of Keyboard/Display Controller

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The Keyboard/Display Controller 8279Intel‟s 8279 is a general purpose Keyboard

Display controller that simultaneously drives the display of a system and interfaces a
Keyboard with the CPU. The Keyboard Display interface scans the Keyboard to identify
if any key has been pressed and sends the code of the pressed key to the CPU.It also
transmits the data received from the CPU,to the display device.The Keyboard display
controllerchip8279provides1. A set of four scan lines and eight return lines for
interfacingkeyboards.2. A set of eight output lines for interfacing display.

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I/OControlandDataBuffer

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The I/O control section controls the flow of data to/from the 8279. The data buffer
interface the external bus of the system with internal bus of 8279. The pin Ao, RD and

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WR select the command, status or data read/write operations carried out by the CPU
with 8279.

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Control and Timing Register and Timing Control

These registers store the keyboard and display modes and other operating conditions
programmed by CPU.The registers are written with Ao=1 and WR =0.The timing and
control unit controls the basic timings for the operation of the circuit.Scan Counter divide
down the operating frequency of 8279 to derive scan keyboard and scan display
frequencies.

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Scan Counter
The Scan Counter has two modes to scan the key matrix and refresh the display.In the

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Encoded mode, the counter provides a binary count that is to be externally decoded to
provide the scan lines for keyboard and display.In the decoded scan mode, the counter

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internally decodes the least significant 2 bits and provides a decoded 1 out of 4 scan on
SL0-SL3.The Keyboard and Display both are in the same mode at a time.
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Return Buffers and Keyboard Debounce and Control
This section scans for a Key closure row-wise.If it is detected, the Keyboard debounce
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unit debounces the key entry.After the debounce period, if the key continues to be
detected. The code of the Key is directly transferred to the sensor RAM along with
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SHIFT and CONTROL key status.

FIFO/Sensor RAM and Status Logic

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In Keyboard or strobed input mode, this block acts as 8-byte first-in-first-out (FIFO)
RAM. Each key code of the pressed key is entered in the order of the entry, and in the
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meantime, read by the CPU, till the RAM becomes empty. The status logic generates
an interrupt request after each FIFO read operation till the FIFO is empty.In scanned
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sensor matrix mode, this unit acts as sensor RAM.Each row of the sensor RAM is
loaded with the status of the corresponding row of sensors in the matrix.If a sensor
changes its state, the IRQ line goes high to interrupt the CPU.

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Display Address Registers and Display RAM.

The Display address registers hold the addresses of the word currently being written or
read by the CPU to or from the display RAM.The contents of the registers are
automatically updated by 8279 to accept the next data entry by CPU. The 16-byte
display RAM contains the 16-byte of data to be displayed on the sixteen 7-seg displays
in the encoded scan mode.
DetailsofModesofOperation

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Keyboard Modes
Scanned Keyboard Mode with 2 Key Lockout

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In this mode of operation, when a key is pressed, a debounce logic comes into
operation. The Key code of the identified key is entered into the FIFO with SHIFT and

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CNTL status, provided the FIFO is not full.
Scanned Keyboard with N-key Rollover
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In this mode, each key depression is treated independently. When a key is pressed, the
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debounce circuit waits for 2 keyboard scans and then checks whether the key is still
depressed. If it is still depressed, the code is entered in FIFO RAM. Any number of keys
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can be pressed simultaneously and recognized in the order, the Keyboard scan record
them.
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ScannedKeyboardSpecialErrorMode
This mode is valid only under the N-Key rollover mode. This mode is programmed using
end interrupt/error mode set command. If during a single debounce period (two
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Keyboard scan) two keys are found pressed, this is considered a simultaneous
depression and an error flag is set. This flag, if set, prevents further writing in FIFO
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butallows generation of further interrupts to the CPU for FIFO read.

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SensorMatrixMode
In the Sensor Matrix mode, the debounce logic is inhibited the 8-byte memory matrix.
The status of the sensor switch matrix is fed directly to sensor RAM matrix Thus the
sensor RAM bits contains the row-wise and column-wise status of the sensors in the
sensor matrix.

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DisplayModes
There are various options of data display The first one is known as left entry mode or
type writer mode. Since in a type writer the first character typed appears at the left-most
position, while the subsequent characters appears successively to the right of the first
one.The other display format is known as right entry mode, or calculator mode, since
the calculator the first character entered appears at the right-most position and this
character is shifted one position left when the next character is entered.

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1.LeftEntryMode

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In the Left entry mode, the data is entered from the left side of the display unit.
Address0 of the display RAM contains the leftmost display character and address 15

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of the RAM contains the rightmost display character.

2.RightEntryMode
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In the right entry mode, the first entry to be displayed is entered on the rightmost
display.The next entry is also placed in the right most display but after the previous
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display is shifted left by one display position.

All the Command words or status words are written or read with Ao = 1 and CS = 0 to or
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from 8279.
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a. Keyboard/ Display mode set

The format of the command word to select different modes of operation of 8279 is given
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below with its bit definitions.

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D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 D D K K K

D4 D3 Display Modes

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0 0 8*8 Character Left Entry

0 1 16*8 Character Left Entry
1 0 8*8 Character Right Entry
1 1 16*8 Character Left Entry

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D2 D1 D0 Keyboard Modes
0 0 0 Encoded Scan 2 Key lock

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out
0 0 1 Decoded Scan 2 Key lock

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out
0 1 0 Encoded Scan N Key
rollover
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0 1 1 Decoded Scan N Key
rollover
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1 0 0 Encoded Scan Sensor

Matrix
1 0 1 Decoded Scan Sensor
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Matrix
1 1 0 Strobed Input Encoded
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Scan
1 1 1 Strobed Input Decoded
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Scan
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5.Draw the neat diagram ,explain the architecture and features of 8237Direct
Memory Access
Controller.
DMA Controller: A DMA controller is a device, usually peripheral to a CPU that is
programmed to perform a sequence of data transfers on behalf of the CPU.A DMA

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controller can directly access memory and is used to transfer data from one memory
location to another, or from an I/O device to memory and vice versa.A DMA controller
manages several DMA channels, each of which can be programmed to perform a
sequence of these DMA transfers.A DMA request signal for each channel is routed to
the DMA controller.When the DMA controller sees a DMA request, it responds by
performing one or many data transfers from that I/O device into system memory or vice
versa.Channels must be enabled by the processor for the DMA controller to respond to

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DMA requests.A DMA controller typically shares the system memory and I/O bus with
the CPU and has both bus master and slave capability. The diagram of DMA controller

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architecture and how the DMA controller interacts with the CPU.In bus master mode,
the DMA controller acquires the system bus (address, data, and control lines)from the

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CPU to perform the DMA transfers. Because the CPU releases the system bus for the
duration of the transfer, the process is sometimes referred to as cycle stealing.In bus
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slave mode, the DMA controller is accessed by the CPU, which programs the
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DMAcontroller's internal registers to set up DMA transfers.The internal registers consist
of source and destination address registers and transfer count registers for each DMA
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channel, as well as control and status registers for initiating, monitoring, and sustaining
the operation of the DMAcontroller.
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DMA Transfer Types and Modes :

DMA controllers vary as to the type of DMA transfers and the number of DMA
channels. The two types of DMA transfers are
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i) flyby DMA transfers

ii) fetch-and-deposit DMAtransfers.
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iii) The three common transfer modes are single, block, and
demand transfer modes.
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A 8237 DMA controller IC :

CLK: CLOCK INPUT:

The Clock Input is used to generate the timing signals which control82C37A
operations.

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CS: CHIP SELECT:

Chip Select is an active low input used to enable the controller onto thedata bus for
CPU communications.

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Fig:Architecture of DMA Controller

RESET:
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This is an active high input which clears the Command, Status, Request, and
Temporary registers, the First/Last Flip-Flop, and the mode register counter.The Mask
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registeris set to ignore requests.

READY:
This signal can be used to extend the memory read and write pulses from the
82C37A to accommodate slow memories or I/O devices.

HLDA: HOLD ACKNOWLEDGE:

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The active high Hold Acknowledge from the CPU indicates that it has
relinquished control of the system busses.

DREQ0-DREQ3: DMA REQUEST:

The DMA Request (DREQ) lines are individual asynchronous channel request
inputs used by peripheral circuits to obtain DMA service.In Fixed Priority, DREQ0 has
the highest priority and DREQ3 has the lowest priority.A request is generated by

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activating the DREQ line of a channel. DACK will acknowledge the recognition of a
DREQ signal.RESET initializes these lines to active high.DREQ must be maintained

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until the corresponding DACK goes active.DREQ will not be recognized while the clock
is stopped.Unused DREQ inputs should be pulled High or Low(inactive) and the

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corresponding mask bit set.

DB0-DB7: DATA BUS: e

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The Data Bus lines are bidirectional three-state signals connected to the system
data bus. The outputs are enabled in the Program condition during the I/O Read to
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output the contents of a register to the CPU.The outputs are disabled and the inputs are
read during an I/O Write cycle when the CPU is programming the 82C37A control
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registers. During DMA cycles, the most significant 8-bits of the address are output onto
the data bus to be strobed into an external latch by ADSTB. In memory-to-memory
operations, data from the memory enters the 82C37A on the data bus during the read-
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from-memory transfer, then during the write-to memory transfer, the data bus outputs
write the data into the new memory location.
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IOR: READ:
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I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an
input control signal used by the CPU to read the control registers. In the active cycle, it
is an output control signal used by the 82C37A to access data from the peripheral
during a DMAWrite transfer.

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IOW: WRITE:
I/O Write is a bidirectional active low three-state line.
In the Idle cycle, it is an input control signal used by the CPU to load information into
the 82C37A. In the active cycle, it is an output control signal used by the 82C37A to
load data to the peripheral during a DMA
Read transfer.

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EOP: END OF PROCESS:
End of Process (EOP) is an active low bidirectional signal.The 82C37A allows an

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external signal to terminate an active DMA service by pulling the EOP pin low.A pulse is
generated by the 82C37A when terminal count (TC) for any channel is reached, except

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for channel 0 in memory-to-memory mode.During memory-to-memory transfers , EOP
will be output when the TC for channel 1 occurs.The EOP pin is driven by an open drain
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transistor on-chip, and requires an external pull-up resistor to VCC. When an EOP pulse
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occurs, whether internally or externally generated, the 82C37A will terminate the
service,and if auto-initialize is enabled, the base registers will be written to the current
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registers of that channel. The mask bit and TC bit in the status word will be set for the
currently active channel by EOP unless the channel is programmed for auto initialize. In
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that case, the mask bit remains clear.

A0-A3: ADDRESS: The four least significant address lines are bidirectional three-state
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signals. In the Idle cycle, they are inputs and are used by the 82C37A to address the
control register to be loaded or read. In the Active cycle, they are outputs and provide
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the lower 4-bits of the output

address.
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A4-A7: ADDRESS: The four most significant address lines are three-state outputs and
provide 4-bits of address. These lines are enabled only during the DMA service.

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HRQ: HOLD REQUEST: The Hold Request (HRQ) output is used to request control of
the system bus. When a DREQ occurs and the corresponding mask bit is clear, or a
software DMA request is made, the 82C37A issues HRQ. The HLDA signal then
informs the controller when access to the system busses is permitted. For stand-alone
operation where the 82C37A always controls the busses, HRQ may be tied to HLDA.
This will result in one S0 state before the transfer.

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DACK0-DACK3: DMA ACKNOWLEDGE:
DMA acknowledge is used to notify the individual peripherals when one has been

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granted a DMA cycle. RESET initializes them to active low.

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AEN: ADDRESS ENABLE:
Address Enable enables the 8-bit latch containing the upper 8address bits onto the
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system address bus. AEN can also be used to disable other system busdrivers during
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DMA transfers.AEN is active high.
ADSTB: ADDRESS STROBE:
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This is an active high signal used to control latching of the upper address byte. During
block operations, ADSTB will only be issued when the upper address byte must be
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updated. ADSTB timing is referenced to the falling edge of the 82C37A clock.

MEMR: MEMORY READ:

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The Memory Read signal is an active low three-state output used to access data from
the selected memory location during a DMA Read or a memory-to-memory transfer.
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MEMW MEMORY WRITE:

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The Memory Write signal is an active low three-state output used to write data to the
selected memory location during a DMA Write or a memory-to-memory transfer.

NC: NO CONNECT: Pin 5 is open and should not be tested for continuity.

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Functional Description
The 82C37A direct memory access controller is designed to improve the data
transfer rate in systems which must transfer data from an I/O device to memory, or
move a block of memory to an I/O device. It will also perform memory-to-memory block
moves, or fill a block of memory with data from a single location. Operating modes are
provided to handle single byte transfers as well as discontinuous data streams, which
allows the 82C37A to control data movement.Memory-to-memory operations require

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temporary internal storage of the data byte between generation of the source and
destination addresses, so memory-to-memory transferstake place at less than half the

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rate of I/O operations, but still much faster than with centralprocessor techniques. The
block diagram of the 82C37A consists of timing and control block, priority block, and

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internal registers are the main components. The timing and control block derives
internal timing from clock input, and generates external control signals. The Priority
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Encoder block resolves priority contention between DMA channels requesting service
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simultaneously.
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DMA Operation:
In a system, the 82C37A address and control outputs and data bus pins are basically
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connected in parallel with the system busses. An external latch is required for the upper
address byte. While inactive, the controller‟s outputs are in a high impedance state.
When activated by a DMArequest and bus control is relinquished by the host, the
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82C37A drives the busses and generates the control signals to perform the data
transfer.The operation performed by activating one of the four DMA request inputs has
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previously been programmed into the controller via the Command,Mode, Address, and
Word Count registers.For example, if a block of data is to be transferredfrom RAM to an
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I/O device, the starting address of the data is loaded into the 82C37A Current and Base
Address registers for a particular channel, and the length of the block is loaded into the
channel‟s Word Count register. The corresponding Mode register is programmed for a
memory to-I/O operation (read transfer), and various options are selected by the
Command register and the other Mode register bits.The channel‟s mask bit is cleared to

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