Unit – I

8 Bit & 16 Bit Microprocessor

8085 Architecture

Features of 8085 Architecture

• It is an 8 bit processor
• It operates on 5V power supply
• It has on chip clock generator. This internal clock generator requires
tuned circuit like LC, RC or Crystal. Which can be used for synchronizing
external devices.
• It can operate 3-5 MHz clock frequency.
• It has 8 data lines & 16 address lines.
• It support 74 instructions with following addressing modes
a) Immediate b)Register c) Direct d)Indirect e)Implied
• The ALU Perform
a) 8-bit binary addition with or without carry.
b) 16-bit binary addition
c) 2 digit BCD addition.
d) 8-bit logical (AND,OR,EXOR….)
• It has 8-bit Accumulator, Flag Register, Instruction Register, General
purpose Register (B,C,D,E,H,L).
• Two 16-bit Register ( SP and PC)
• It provides 5 hardware interrupt
Various Functional Blocks are

• Registers
• ALU
• Instruction Decoder & Machine Cycle encoder
• Address buffer
• Address/Data buffer
• Interrupt control
• Serial I/O control
• Timing & Control circuit

Register structure

 The six eight-bit general purpose registers are (B, C, D, E, H, L) these can be
used as single eight-bit registers and in pairs as 16-bit registers like BC,
DE, HL etc.,
 HL register are also called as scratch pad registers
 One accumulator, one flag register and two 16 bit registers (SP and PC).
 The remaining registers – temporary W and Z are not accessible to the
programmers they are used by microprocessor for internal and immediate
operations.

8085 register are classified as

1. General purpose register

2. Temporary register
a) Temporary data register b) W and Z register
3. Special Purpose register
a) Accumulator b)Flag register c) Instruction register
4. Sixteen bit registers
a) Program Counter(PC) b) Stack pointer(SP)

1. General purpose registers

 The eight-bit general purpose registers are B, C, D, E, H, L and these can be used
as single eight-bit registers and in pairs as 16-bit registers like BC, DE, HL.
 HL pair also functions as data pointer or memory pointer.These are also called as
scratch pad registers as user can store data in them.
 To store and read data from these registers bus access not required, it is an
internal operation.
2. Temporary registers

a) Temporary data register:

The ALU has two inputs. One input is supplied by the accumulator and
other from temporary data register. The programmer can not access this
temporary data register. However internally used for execution of most of the
Arithmetic and logical instructions.

b) W and Z register
It is a temporary registers. These register are used to hold 8 bit data
during execution of some instruction. These register are used internal.

3. Special Function Register

a) Accumulator ( A Register)
 It is a 8 bit register.
 It is extensively used in arithmetic,logic, load and store operations
as well as I/O operations.
 Most of the times the result of arithmetic and logical operations is
stored in the register A. Hence it is also identified as accumulator.

b) Flag Register (or) Status Register (or) Program Status Word.

The group of five flip-flops which deed as status flags and in INTEL 8085 the five status
flags are:
Carry Flag (CS), Zero Flag (Z), Sign Flag (S), Parity Flag (P), and Auxillary Carry Flag
(AC) and along with these there are three undefined bits which together called as
program status word.

D7 D6 D5 D4 D3 D2 D1 D0

S Z X AC X P X CY

Sign Flag (S):

After the execution of arithmetic or logical operations, if D7 of the result is 1,
the sign flag is set.
If S=1 flag set the number will be viewed as negative number.
S=0 the number will be viewed as positive number.

Zero Flag(Z):
Z=1 the zero flag sets if the result of operation in ALU is zero
Z=0 flag resets if result is non zero.

Auxiliary Carry Flag (AC):

This flag is used for BCD operations and it is not available for programmer.
If AC =1 flag set if there is an overflow out of bit 3 i.e., carry from lower nibble
to higher nibble (D3 bit to D4 bit).

Parity Flag (P)

It is defined by the number of ones present in the accumulator. After an ALU
operation.
If the parity is even the flag is set. It shows even parity.
If the parity is odd the flag is reset. It shows odd parity.
 Carry Flag (CY)
Carry flag is set if there is an overflow out of bit 7. The carry flag also serves as
a borrow flag for subtraction.

c) Instruction Register and Decoder:

The processor first fetches the op-code of instruction from the memory and it
is stored in a register called instruction register. The stored instruction is sent to
the instruction decoder where it is decoded and according to it, the timing and
control signals are generated.

4. Sixteen bit registers:

Program Counter: Program is a collection of instructions and microprocessor

searches these instructions from memory. Well, a program counter is a unique
register which saves the address of next instruction to be searched.

Stack Pointer: Stack is a reticent part of the memory in RAM where temporary
data can be saved

Arithmetic Logic Unit (ALU):

Arithmetic logic unit carries out bitwise arithmetic operations such as addition,
subtraction. It also carries out the logical operations like AND, OR rotate and much
more

Address Buffer

It is an 8 bit unidirectional buffer. It is used to higher order address bus (A8 to A15)

Address Data Buffer

It is an 8 bit bi directional buffer. It is used to multiplexed address/data bus
lower order address bus (A0-A7) and Data bus (D0-D7).

Interrupt control
The processor fetches, decodes and executes instruction in a sequence.
The interrupt control block has five interrupt inputs RST 5.5, RST 6.5, RST 7.5, TRAP
and INTR and INTA.

Serial I/O Control:

This provides two signals namely SID and SOD which are used to receive and
transmit the information serially.

Timing and Control Unit:

The control unit is obliged for all operations and the operations occur at the
same time with the help of clock signal.
 Pin Definitions of 8085

The Signal Can be classified into seven groups according to their functions
• Power supply and frequency signals.
• Data bus and address bus
• Control and Status Signals
• Interrupt signals
• Serial I/O signals
• DMA signals
• Reset signals

Power Supply & Frequency Signals

• Vcc : It requires a single +5 V power supply.

• Vss : Ground reference
• X1 and X2 : A tuned circuit like LC, RC or crystal is connected at these two.
• The internal clock generator divides oscillator frequency by 2, therefore, to operate
a system at 3 -5 MHz.
• CLK OUT : This signal is used as a system clock for other devices.

Data Bus & Address Bus

• AD0 to AD7 : The 8 bit data bus (D0 – D7) is multiplexed with the lower half (A0 – A7)
of the 16 bit address bus these lines are used as a bi-directional data bus.
• A8 to A15 : The upper half of the 16 bit address appears on the address lines A8 to A15
these lines are used as uni directional data bus
Control & Status Signals

ALE (output) - Address Latch Enable.

• It is an output signal used to give information of AD0-AD7 contents.
• It is a positive going pulse generated when a new operation is started by uP.
• When pulse goes high it indicates that AD0-AD7 are address.
• When it is low it indicates that the contents are data.

RD (output) Read memory or IO device.

• It is an active low signal
• This indicates that the data is to be read from the selected memory or I/O device
through the data bus.
WR (output) Write memory or IO device.
• It is an active low signal
• This indicates that the data on the data bus is to be written into the selected memory
location or I/O device.

READY (input)
• This signal is used to interface slow peripheral devices with the fast
microprocessor.
• If ready is high during read or write cycle, it indicates that the memory or peripheral
is ready to send or receive data.
• If ready is low, the CPU wait for it to go high before completing the read or write
cycle.
IO/M (output) - Select memory or an IO device
• It is an output signal
• This status signal indicates that the read / write operation relates to whether the
memory or I/O device.
• It goes high to indicate an I/O operation.
• It goes low to indicate an memory operations.

S0,S1(Output)
These signals are used to indicate the kind of operation being performed

Interrupts and Externally initiated Signals

The signals initiated by an external device to request the microprocessor to do a particular task
or work.
There are five hardware interrupts called,
TRAP, RST 7.5, RST 6.5, RST 5.5, INTA
INTR (Input)
• Interrupt request is a lowest priority interrupt signal.
• It can be enable or disable by using software.
• If INTR is high, the PC will not be allowed to increment and an INTA will be issued.

INTA (Output)
• It is an active low signal used instead of RD after an interrupt request has been
accepted.
• This signal is used to read the opcode from the data bus and execute it.

RST 7.5, RST 6.5,RST 5.5 (Input)

• These three input are hardware interrupt signal similar to INTR.
• However these interrupt do not have an acknowledgement signal.

TRAP (input)
• Trap interrupt is a non maskable restart interrupt
• This can not be enabled or disabled using programs.

DMA Signals

HOLD (Input)
 It is an active high signal used in the direct transfer of data between a
peripheral device and memory locations.
 This signal indicates that another master is requesting for the use of address
bus, data bus and control bus.
HLDA(output)
• This active high signal is used to acknowledge HOLD request.

RESET SIGNAL

Reset In (input, active low)

• This signal is used to reset the microprocessor.
• The program counter inside the microprocessor is set to zero.
• The buses are tri-stated.
Reset Out (Output)
 It indicates CPU is being reset.
 Used to reset all the connected devices when the microprocessor is reset.

Serial I/O Signals

 There are two signals to implement serial transmission.
 The data bits are send over a single line, one bit at a time in serial transmission

SID (Serial I/P Data)

 This input signal is used to accept serial data bit by bit from the external device.

SOD (Serial O/P Data) :

 This is an output signal which enables the transmission of serial data bit by bit
to the external device
 Addressing Mode

 The microprocessor has different ways of specifying the data or operand for the
instruction.

 The various formats of specifying operands are called addressing modes

The 8085 has Five addressing modes:

 Register Addressing Mode

 Immediate Addressing Mode
 Direct Addressing Mode
 Indirect Addressing Mode
 Implicit Addressing Mode

Register Addressing Mode

The register addressing mode specifies the source operand, destination operand or
both to be contained in an registers.
Example
MOV A, B ; SPHL ; ADD C

Immediate Addressing Mode

In an immediate addressing mode 8 or 16 bit data can be specified as a part of
instruction. The instructions having ‘I’ letter indicates Immediate addressing mode.
Example
MVI A, 05H
MVI M, 08H
LXI SP, 2700H
LXI D, 1000H

Direct Addressing Mode

It specifies 16 bit address of the operand within the instruction itself.
In this type of addressing mode, the 16bit memory address is directly provided with
the instruction.
Example
LDA 2000H
STA 2000H
SHLD 2500H

Indirect Addressing Mode

In this type of addressing mode, the 16bit memory address is indirectly provided
with the instruction using a register pair.

Example
INR M H L
MOV M,A
MOV B, M
A 30H 20H 50H 2050H 30H
MOV M, C

Implicit Addressing Mode

In this type of addressing mode, No operand (register or data) is specified in the
instruction.
The opcode specifies the address of the operands.
Example
CMA
HLT
NOP
STC
 Instruction Classification

8085 Instruction set can be classified according to size (in bytes) as

1. 1-byte Instructions
2. 2-byte Instructions
3. 3-byte Instructions

One Byte Instruction

Includes Opcode and Operand in the same byte

Example : MOV A, M, CMA, DAA etc

Two Byte Instruction

First byte specifies Operation Code Second byte specifies Operand

Example : MVI A, 08, IN 02, CPI 03 etc

Three Byte Instruction

First byte specifies Operation Code Second & Third byte specifies Operand

Example : LXI H, 4500, STA 4600, LDA 4200

INSTRUCTION SET

 Consists of
 74 operation codes, e.g. MOV, MVI
 246 Instructions, e.g. MOV A,B, MVI A,03

 8085 instructions can be classified as

 Data Transfer instruction
 Arithmetic instruction
 Logical and Bit manipulation
 Branching instruction
 Machine Control instruction

Data Transfer Instruction

(Refer Class Note for Detailed Specification)

 MOV Move
 MVI Move Immediate
 LDA Load Accumulator Directly from Memory
 STA Store Accumulator Directly in Memory
 LHLD Load Hand L Registers Directly from Memory
 SHLD Store Hand L Registers Directly in Memory
 LXI Load register pair Immediate
 LDAX Load accumulator indirect
 STAX Store Accumulator In direct
 XCHG Exchange DE pair and HL pair
 XTHL Exchange between HL pair and stack
  IN portaddr
i.e. IN 00 ( Reads data from the Input Switch, 0 0represents the
port address of the input switch)
 OUT portaddr
i.e. OUT 00 ( Writes data to the Display device where 00 represents
the Port address of the display)

Arithmetic Instruction
(Refer Class Note for Detailed Specification)

 ADD Add to Accumulator

 ADI Add Immediate Data to Accumulator
 ADC Add to Accumulator Using Carry Flag
 ACI Add Immediate Data to Accumulator Using Carry Flag
 SUB Subtract from Accumulator
 SUI Subtract Immediate Data from Accumulator
 SBB Subtract from Accumulator Using Borrow ((:Carry) Flag
 SBI Subtract I mmediate from Accumulator Using Borrow
 INR Increment Specified Byte by One
 DCR Decrement Specified Byte by One
 INX Increment Register Pair by One
 DCX Decrement Register Pair by One
 DAA Decimal Adjust Accumulator ( BCD Operation)

Logical Instruction
(Refer Class Note for Detailed Specification)

 ANA Logical AND with Accumulator

 ANI Logical AND with Accumulator Using Immediate Data
 ORA Logical OR with Accumulator
 ORI Logical OR with Accumulator Using Immediate Data
 XRA Exclusive Logical OR with Accumulator
 XRI Exclusive OR Using Immediate Data
 CMP Compare
 CPI Compare Using Immediate Data
 RLC Rotate Accumulator Left
 RRC Rotate Accumulator Right
 RAL Rotate Left Through Carry
 RAR Rotate Right Through Carry
 CMA Complement Accumulator
 CMC Complement Carry Flag
 STC Set Carry Flag

Branching Instruction
(Refer Class Note for Detailed Specification)

The unconditional branching instructions are as follows:

 JMP Jump
 CALL Call
 RET Return
Conditional branching instructions
 jumps Calls Returns
 JC CC RC (Carry)
 JNC CNC RNC (No Carry)
 JZ CZ RZ (Zero)
 JNZ CNZ RNZ (Not Zero)
 JP CP RP (Plus)
 JM CM RM (Minus)
 JPE CPE RPE (Parity Even)
 JPO CPO RPO (Parity Odd)
 PCHL Move Hand L to Program Counter
 RST Special Restart Instruction Used with Interrupts

Stack, I/O, and Machine Control Instructions

(Refer Class Note for Detailed Specification)

 PUSH Push Two Bytes of Data onto the Stack

 POP Pop Two Bytes of Data off the Stack
 XTHL Exchange Top of Stack with Hand L
 SPHL Move contents of Hand L to Stack Pointer
The I/O instructions are as follows:
 IN Initiate Input Operation
 OUT Initiate Output Operation
The machine control instructions are as follows:
 EI Enable Interrupt System
 DI Disable Interrupt System
 HLT Halt
 NOP No Operation

Serial Control Instruction

RIM SIM
Interrupts

• Interrupt Types
– Hardware Interrupts: External event
– Software Interrupts: Internal event (Software generated)
– Maskable and non-maskable interrupts
– Interrupt priority
• Maskable
– INTR
– RST vectored
• Non-Maskable
– TRAP
• Vectored
– RST5.5, RST6.5, RST7.5, TRAP
( Refer Class Notes)

Beyond the Topic

1. Write an assembly program to add two numbers

MVI D, 02BH
MVI C, 06FH
MOV A, C
ADD D
STA 4500
HLT

2. Write an assembly program to add two numbers

LXI H, 4500
MOV A, M
INX H
ADD M
STA 4500
HLT
 8086 Architecture

Features of 8086 Architecture

• It is a 16-bit µp.
• 8086 has a 20 bit address bus can access up to 220 memory locations (1
MB).
• It can support up to 64K I/O ports.
• It provides 14, 16 -bit registers.
• It has multiplexed address and data bus AD0- AD15 and A16 – A19.
• It requires single phase clock with 33% duty cycle to provide internal
timing. (5 MHz)
• 8086 is designed to operate in two modes, Minimum and Maximum.
• It can prefetches upto 6 instruction bytes from memory and queues them
in order to speed up instruction execution.
• It requires +5V power supply.
• It supports multiprogramming.
• A 40 pin dual in line package Minimum and Maximum Modes

• The minimum mode is selected by applying logic 1 to the MN / MX input

pin. This is a single microprocessor configuration.

• The maximum mode is selected by applying logic 0 to the MN / MX input

pin. This is a multi micro processors configuration.
 There are two functional units
– Bus Interfacing Unit (BIU)
– Execution Unit (EU)

Bus Interfacing Unit (BIU)

• It sends address of the memory or I/O

• It fetches instruction from memory.
• It reads data from memory and I/O ports.
• It writes data to memory and I/ O ports.
• It supports instruction queuing.
• It provides the address relocation facility.
• It contains Instruction Queue, Segment registers, instruction pointer,
address summer and bus control logic.

Execution Unit contains:

• General Purposes Registers
• Stack Pointer
• Base Pointer
• Index Registers
• ALU
• Flag Register
• Instruction Decoder
• Timing & Control Unit

Functions of Execution Unit

• It receives opcode of an instruction from the QUEUE.

• It decodes it and then executes it.
• It tells BIU where to fetch the instructions or data from.
• It contains the control circuitry to perform various internal operations.
• It has 16-bit ALU, which can perform arithmetic and logical operations on
8-bit as well as 16-bit data

Instruction Queue

• To increase the execution speed, BIU fetches as many as six instruction

bytes ahead to time from memory.
• All six bytes are then held in FIFO 6-byte register called instruction
queue.
• Then all bytes are given to EU one by one.
• This pre-fetching operation of BIU may be in parallel with execution
operation of EU, which improves the execution speed of the instruction.
Pipelining

• While EU executes instructions, BIU fetches instructions from memory

and stores them in the QUEUE.
• BIU and EU operate in parallel independent of each other.
• This type of overlapped operation of the functional units of a MP is called
Pipelining

Registers
• General Purpose Registers
• Pointer and Index Registers
• Segment Registers
• Instruction Pointer
• Status Flags

General Purpose Registers

• There are four 16-bit general purpose registers:

– AX : AH AL
– BX : BH BL
– CX : CH CL
– DX : DH DL
• AX Register: AX register is also known as accumulator register that
stores operands for arithmetic operation like divided, rotate.
• BX Register: This register is mainly used as a base register. It holds
the starting base location of a memory region within a data segment.
• CX Register: It is defined as a counter. It is primarily used in loop
instruction to store loop counter.
• DX Register: DX register is used to contain I/O port address for I/O
instruction.

Segment Registers
• A segment register points to the starting address of a memory
segment.
• The maximum capacity of a segment may be up to 64 KB.
• The instructions of 8086 specify 16-bit address.
• But the actual physical addresses are of 20-bit.
• 1 MB Memory can be divided into 16 parts which are called segments.

There are four segment registers

• Code Segment Register (CS)
• Data Segment Register (DS)
• Stack Segment Register (SS)
• Extra Segment Register (ES)

Code Segment (CS)

• The CS register is used for addressing a memory location in the Code
Segment of the memory, where the executable program is stored.
Data Segment (DS)
• The DS contains most data used by program. Data are accessed in the
Data Segment by an offset address or the content of other register that
holds the offset address.
Stack Segment (SS)
SS defined the area of memory used for the stack.
Extra Segment (ES)
ES is additional data segment that is used by some of the string to hold the
destination data.

Pointer and Index Register

• Stack Pointer (SP)

• Base Pointer (BP)
• Source Index (SI)
• Destination Index (DI)
Stack Pointer (SP)
• The function of SP is same as the function of SP in Intel 8085.
• It stores the address of top element in the stack.
BP, SI & DI are used in memory address computation.

Base Pointer (BP)

It is used to hold the offset address of the data to be read from or written
into the stack segment.

Source Index(SI)
It is used to hold the offset address of the source data in the data
segment, while executing string instruction.
Destination Index(DI)
It is used to hold the offset address of the destination data in the extra
segment, while executing string instruction.

Instruction Pointer

• The Instruction Pointer (IP) acts as a Program Counter.

• It points to the address of the next instruction to be executed.
• Its content is automatically incremented when the execution of a
program proceeds further.
• The contents of the IP and Code Segment Register are used to compute
the memory address of the instruction code to be fetched.
• This is done during the Fetch Cycle.

Status Register (or) Program Status Word (PSW)

• 16-bit status register.

• It is also called Flag Register or Program Status Word (PSW).
• There are nine status flags and seven bit positions remain unused.

9 flags and they are divided into two categories

• Condition Flags
• Control Flags
Control Flags

Trap Flag (TP)

 It is used for single step control.
 It allows user to execute one instruction of a program at a time for
debugging.
 When trap flag is set, program can be run in single step mode.

Interrupt Flag (IF)

 It is an interrupt enable/disable flag.
 If it is set, the maskable interrupt of 8086 is enabled and if it is
reset, the interrupt is disabled.
 It can be set by executing instruction set and can be cleared by
executing CLI instruction.

Direction Flag (DF)

 It is used in string operation.
 If it is set, string bytes are accessed from higher memory address
to lower memory address.
 When it is reset, the string bytes are accessed from lower memory
address to higher memory address.
 Pin Diagram of 8086

Address/Data bus

AD0-AD15 (Bidirectional)

Low order address bus; these are multiplexed with data.

When AD lines are used to transmit memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines the symbol D is used in place of AD,
for example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are multiplexed with status signals.

ALE =1 pin carry Address ALE-0 Carry status

 S4 S3 Segment Accessed
0 0 ES
0 1 SS
1 0 CS
1 1 DS

Bus High Enable/Status

BHE (Active Low)/S7 (Output)

* It is used to enable most significant data bus, D8-D15 during read/write

operation.
* It is multiplexed with status signal S7 is always logic 1

MINIMUM / MAXIMUM ( MN / MX)

This pin signal indicates what mode the processor is to operate in.
MN/MX is 5V (Minimum Mode)
MN/MX is GND (Maximum Mode)

RD (Read) (Active Low)

The signal is used for read data from memory or I/O device through data bus.

TEST

• It is a input pin tested by WAIT instruction.

• If Logic 0 it become No Operation
• If Logic 1 it will WAIT instruction wait for TEST become logic 0.
• This offen used for floating point operations

READY
The signal is active high.
• If Logic 1 No operation in Microprocessor.
• If Logic 0 8086 enter WAIT states and remain idle.
• It is used to interface slow operating peripherals.

RESET (Input)
The signal must be active HIGH for at least four clock cycles.
Causes the processor to immediately terminate its present activity.
CS & IP are initialized to 0000H and FFFFH.

CLK
*The clock input provides the basic timing for processor operation and bus
control activity.
• Its an 33% duty cycle .
• It Max Frequency 5 MHz
INTR Interrupt Request

• This signal is active high and internally synchronized.

• IF=1 if INTR is held high (logic 1)
• IF=0 if INTR is disabled. (logic 0)

NMI (Non Maskable Interrupt)

It is an hardware interrupt. It cannot be disabled by software.

Minimum Maximum Mode Operation

The 8086 microprocessor can work in two modes of operations : Minimum

mode and Maximum mode.

In the minimum mode of operation the microprocessor do not associate with

any co-processors and can not be used for multiprocessor systems.

In the maximum mode the 8086 can work in multi-processor or co-processor

configuration.

Minimum or maximum mode operations are decided by the pin MN/ MX(Active
low).

When this pin is high 8086 operates in minimum mode otherwise it operates in
Maximum mode.

Minimum Mode Operation

For Minimum mode operation the MN/MX is tied to VCC ( Logic High)

DT/R : (Data Transmit/Receive)

Used to indicate Transmitting data.
DT/R =1 Transmit Data , DT/R=0 Receive Data
DEN (Data Enable)
Used to indicate Data bus signal.
DEN =1 Transmit Data through data bus,
DEN=0 No Data in Data Bus
ALE (Address Latch Enable)
Used to demultiplex the address and data lines using external latches
M/IO (Memory read/write operation)
M/IO=1 indicate Memory read/write operation.
M/IO =0 indicate I/O read/write operation.
WR : ( Write )
Write control signal asserted low whenever processor writes data to
memory or I/O Port

ALE (Address Latch Enable)

When the interrupt request is accepted by the processor, the output is
low on this line.
HOLD
Input signal to the processor form the bus masters as a request to grant
the control of the bus.
Logic =1 complete the execution of current instruction and place it
Address, Data and Control bus in High impedance state.
Logic==0 Execute instruction Normally.

HLDA (Hold Acknowledge)

Acknowledge signal by the processor to the bus master requesting the
control of the bus through HOLD.

The acknowledge is asserted high, when the processor accepts HOLD.

Maximum Mode Operation

For Minimum mode operation the MN/MX is tied to Ground ( Logic Low)

S0,S1,S2 (Status Signals)

To generate bus timing and control signals. These are decoded as shown

QS0,QS1 (Queue Status)

The processor provides the status of queue in these lines.

The queue status can be used by external device to track the internal status of
the queue in 8086.
The output on QS0 and QS1 can be interpreted as shown in table
 Access Memory Location

Each address in physical memory(ROM/EPROM) is called physical address.

Segment Register Default Offset Register

CS IP
DS BX,SI,DI 8 or 16 bit displacement.
SS SP,BP
ES DI for string operation
 Addressing Mode

Every instruction of a program has to operate on a data.

The different ways in which a source operand is denoted in an instruction
are known as addressing modes

1. Register Addressing Group I : Addressing modes for

2. Immediate Addressing register and immediate data

3. Direct Addressing
4. Register Indirect Addressing Group II : Addressing modes for
5. Based Addressing memory data
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing

9. Direct I/O port Addressing Group III : Addressing modes for

10. Indirect I/O port Addressing I/O ports

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing mode

Register Addressing Mode

The instruction will specify the name of the register which holds the data to be
operated by the instruction.

Example:

MOV CL, DH

The content of 8-bit register DH is moved to another 8-bit register CL

(CL)  (DH)

Immediate Addressing Mode

In immediate addressing mode, an 8-bit or 16-bit data is specified as part of the

instruction

Example:

MOV DL, 08H

The 8-bit data (08H) given in the instruction is moved to DL
(DL)  08H
MOV AX, 0A9FH
The 16-bit data (0A9FH) given in the instruction is moved to AX register
(AX)  0A9FH

Addressing Mode for Accessing Memory

20 Address lines  8086 can address up to 220 = 1M bytes of memory

However, the largest register is only 16 bits

Physical Address will have to be calculated Physical Address : Actual address

of a byte in memory. i.e. the value which goes out onto the address bus.

Memory Address represented in the form – Seg : Offset (Eg -

89AB:F012)

Each time the processor wants to access memory, it takes the contents of a
segment register, shifts it one hexadecimal place to the left (same as
multiplying by 1610), then add the required offset to form the 20- bit address

89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

F012  0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
To access memory we use these four registers: BX, SI, DI, BP
Combining these registers inside [ ] symbols, we can get different memory
locations (Effective Address, EA)

[SI]
[BX + SI] [BX + SI + d8]
[DI]
[BX + DI] [BX + DI + d8]
d16 (variable offset
[BP + SI] [BP + SI + d8]
only)
[BP + DI] [BP + DI + d8]
[BX]
[SI + d16]
[SI + d8] [BX + SI + d16]
[DI + d16]
[DI + d8] [BX + DI + d16]
[BP + d16]
[BP + d8] [BP + SI + d16]
[BX + d16]
[BX + d8] [BP + DI + d16]

Direct Addressing
Here, the effective address of the memory location at which the data operand is stored is given
in the instruction.

The effective address is just a 16-bit number written directly in the instruction.

Example:

MOV BX, [1354H]

MOV BL, [0400H]

The square brackets around the 1354H denotes the contents of the memory location. When
executed, this instruction will copy the contents of the memory location into BX register.

This addressing mode is called direct because the displacement of the operand from the
segment base is specified directly in the instruction.
Register Indirect Addressing

In Register indirect addressing, name of the register which holds the effective address (EA) will
be specified in the instruction.

Registers used to hold EA are any of the following registers:

BX, BP, DI and SI.

Content of the DS register is used for base address calculation.

Example:

MOV CX, [BX]

Operations:

EA = (BX)
BA = (DS) x 1610
MA = BA + EA

(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA +1)

Based Addressing Mode

In Based Addressing, BX or BP is used to hold the base value for effective address and a signed
8-bit or unsigned 16-bit displacement will be specified in the instruction.

In case of 8-bit displacement, it is sign extended to 16-bit before adding to the base value.

When BX holds the base value of EA, 20-bit physical address is calculated from BX and DS.

When BP holds the base value of EA, BP and SS is used.

Example:

MOV AX, [BX + 08H]

Operations:

0008H  08H (Sign extended)

EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA

(AX)  (MA) or,

(AL)  (MA)
(AH)  (MA + 1)

Indexed Addressing Mode

SI or DI register is used to hold an index value for memory data and a signed 8-bit or
unsigned 16-bit displacement will be specified in the instruction.

Displacement is added to the index value in SI or DI register to obtain the EA.

In case of 8-bit displacement, it is sign extended to 16-bit before adding to the base
value.

Example:

MOV CX, [SI + 0A2H]

Operations:

FFA2H  A2H (Sign extended)

EA = (SI) + FFA2H
BA = (DS) x 1610
MA = BA + EA

(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)

Based Indexed Addressing Mode

In Based Index Addressing, the effective address is computed from the sum of a base register
(BX or BP), an index register (SI or DI) and a displacement.

Example:

MOV DX, [BX + SI + 0AH]

Operations:

000AH  0AH (Sign extended)

EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
MA = BA + EA

(DX)  (MA) or,

(DL)  (MA)
(DH)  (MA + 1)

String Addressing Mode

Employed in string operations to operate on string data.

The effective address (EA) of source data is stored in SI register and the EA of destination is
stored in DI register.

Segment register for calculating base address of

source data is DS and that of the destination data is ES

Example: MOVS BYTE

Operations:

Calculation of source memory location:

EA = (SI) BA = (DS) x 1610 MA = BA + EA

Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
Direct and Indirect Port Addressing Mode

These addressing modes are used to access data from standard I/O mapped devices or ports.

In direct port addressing mode, an 8-bit port address is directly specified in the instruction.

Example: IN AL, [09H]

Operations: PORTaddr = 09H

(AL)  (PORT)

Content of port with address 09H is moved to AL register

In indirect port addressing mode, the instruction will specify the name of the register which
holds the port address. In 8086, the 16-bit port address is stored in the DX register.

Example: OUT [DX], AX

Operations: PORTaddr = (DX)

(PORT)  (AX)
Content of AX is moved to port whose address is specified by DX register.

Relative Addressing Mode

In this addressing mode, the effective address of a program instruction is specified relative to
Instruction Pointer (IP) by an 8-bit signed displacement.

Example: JZ 0AH

Operations:

000AH  0AH (sign extend)

If ZF = 1, then

EA = (IP) + 000AH
BA = (CS) x 1610
MA = BA + EA

If ZF = 1, then the program control jumps to new address calculated above.

If ZF = 0, then next instruction of the program is executed.

Implied Addressing Mode

Instructions using this mode have no operands. The instruction itself will specify
the data to be operated by the instruction.

Example: CLC

This clears the carry flag to zero.

 INSTRUCTION SET

8086 has 6 types of instruction set

1. Data Transfer Instructions

2. Arithmetic Instructions
3. Logical Instructions
4. String manipulation Instructions
5. Process Control Instructions
6. Control Transfer Instructions

Data Transfer Instruction

Instructions that are used to transfer data/ address in to registers, memory locations and I/O
ports.

Generally involve two operands: Source operand and Destination operand of the same size.

Source : Register or a memory location or an immediate data

Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory and a 16-bit data can be moved to
16-bit register/ memory.
 Memory Segmentation

Memory Segmentation in 8086 Microprocessor

Segmentation is the process in which the main memory of the computer is divided into
different segments and each segment has its own base address. It is basically used to enhance
the speed of execution of the computer system, so that processor is able to fetch and execute
the data from the memory easily and fast.

Need for Segmentation –

The Base Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below)
called as Segment Registers.

Code segment register (CS): is used fro addressing memory location in the code segment of
the memory, where the executable program is stored.

Data segment register (DS): points to the data segment of the memory where the data is
stored.

Extra Segment Register (ES): also refers to a segment in the memory which is another data
segment in the memory.

Stack Segment Register (SS): is used fro addressing stack segment of the memory. The
stack segment is that segment of memory which is used to store stack data.

The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to
access one of the 1MB memory locations.
The four segment registers actually contain the upper 16 bits of the starting addresses of the
four memory segments of 64 KB each with which the 8086 is working at that instant of time. A
segment is a logical unit of memory that may be up to 64 kilobytes long.
Each segment is made up of contiguous memory locations. It is independent, separately
addressable unit. Starting address will always be changing. It will not be fixed.

Note that the 8086 does not work the whole 1MB memory at any given time. However it works only
with four 64KB segments within the whole 1MB memory.
Bellow is the one way of positioning four 64 kilobyte segments within the 1M byte memory space of
an 8086.

Overlapping Segment – A segment starts at a particular address and its maximum size can
go up to 64kilobytes. But if another segment starts along this 64kilobytes location of the first
segment, then the two are said to be Overlapping Segment.

Non-Overlapped Segment – A segment starts at a particular address and its maximum size
can go up to 64kilobytes. But if another segment starts before this 64kilobytes location of the
first segment, then the two segments are said to be Non-Overlapped Segment.

Advantages of the Segmentation

 It provides a powerful memory management mechanism.

 Data related or stack related operations can be performed in different segments.
 Code related operation can be done in separate code segments.
 It allows to processes to easily share data.
 It allows to extend the address ability of the processor, i.e. segmentation allows the
use of 16 bit registers to give an addressing capability of 1 Megabytes. Without
segmentation, it would require 20 bit registers.
 It is possible to enhance the memory size of code data or stack segments beyond 64
KB by allotting more than one segment for each area.