DF WINTER 2021 SOLUTION

Q1 (A) Implement EX – NOR using NAND Gate (3M)

ANS

Q1 (B) Convert decimal number 225.225 to octal & hexadecimal (4M)

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(i) Octal aa
8 225 1
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8 28 4
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3 3
Fractional part : 0.225
0.225 × 8 = 1.8 = 1
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0.8 × 8 = 6.4 = 6
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0.4 × 8 = 3.2 = 3
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0.2 × 8 = 1.6 = 1
0.6 × 8 = 4.8 = 4
0.8 × 8 = 6.4 = 6
0.4 × 8 = 3.2 = 3
= 341.1631463
(ii) Hexadecimal
16 225 1
14 14

Fractional part : 0.225

0.225 × 16 = 3.6 = 3
0.6 × 16 = 9.6 = 9
0.6 × 16 = 9.6 = 9
= E1.399A

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Q1 (C) Give classification of Logic Families & compare CMOS & TTL(7M)

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TTL CMOS
TTL stands for Transistor Transistor CMOS stands for
Logic. The name is derived from use complementary metal oxide
of two bipolar junction transistor or semiconductor
BJTs in design of each logic gate
TTL is classification of integrated CMOS is another classification
circuits of ICs that uses field affect
transistors in design
TTL produces more noise CMOS produces less noise
TTL units are less efficient than CMOS CMOS units are more efficient
unit than TTL units

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 Q2(A) Convert F(A, B, C) = BC + A into standard minterm form (3M)

ANS

F(A, B, C) = BC + A
̅ ) BC + A (B + 𝑩
= (A + 𝑨 ̅ ) (C + 𝑪
̅)
= ABC + 𝑨 ̅ BC + A(BC + B𝑪 ̅+𝑩 ̅C + 𝑩
̅𝑪̅)
= ABC + 𝑨 ̅ BC + ABC + AB𝑪 ̅ + 𝑨𝑩̅C + A 𝑩
̅𝑪̅
= 111 + 011 + 101 + 110
= ∑(𝟕, 𝟑, 𝟓, 𝟒)
F = ∑ 𝒎(𝟑, 𝟒, 𝟓, 𝟕)

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Q2(B) With logic diagram & truth table, explain working of 3 line to 8 line
decoder (4M) aa
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 The combinational circuit that change binary information into 2n

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output lines is known as Decoder

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3 × 8 Decoder
 The 3 to 8 line decoder is also known as binary to octal decoder
 In a 3 to 8 line decoder, there is total eight outputs i.e Y0, Y1,Y2, Y3, Y4,
Y5, Y6, Y7 and three inputs A0, A1 and A2
 The circuit has an enable input ‘E’ when enable E is set to 1, one of
these eight output will be 1

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 Truth Table

 Logic expression of term

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Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
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Y2=A0'.A1.A2'
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Y3=A0.A1.A2'
Y4=A0'.A1'.A2
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Y5=A0.A1'.A2
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Y6=A0'.A1.A2
Y7=A0.A1.A2
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 Logic Circuit

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Q2(C) Explain Successive Approximation A/D Converter in detail(7M)

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Successive Approximation A/D Converter

 In this type of A/D converter, voltage comparator logic programmer,
clock, D/A Converter are used circuit as shown in figure

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 Analog voltage to be converted in a digital voltage to the non
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inverting input of the comparator

 Output of the D/A converter is given to the input of the comparator
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 Output bit of logic programmer is set up by the comparator output of

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the logic program is in the binary form. It is converted into analog

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form with the help of D/A Converter. This analog signal is given to the
inverting input of the voltage comparator
 Clock pulses are given to logic programmer output of the
programmer can change only when the clock pulse is present
 Output of the programmer is given to decoder & display. This
decodes binary output used & energies display
 Suppose analog voltage Va is given to comparator programmer sets
MSB to 1 & other bits to 0. This is converted into analog signal V by
by D/A Converter
 Comparator compares signal with analog input signal V a. If Va > Vi
then output voltage V0 of comparator becomes HIGH(1). So when
second clock pulse comes programmer sets bit ahead of MSB to logic
1

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  But if Va < Vi, output of comparator becomes LOW(0) which resets
MSB & sets bit ahead of 1. Similarly each bit is tried one by one until
binary equivalent of analog signal is obtained
 Output of programmer is stored in digital register & it is decoded &
display
 To reduce the quantizing error offset voltage is subtracted from Vi.
This is not show
 N Clock pulse are needed for ‘N – bit comparator’. This process is
slower than parallel comparator type A/D Converter

OR
Q2(C) A combinational logic is defined by function (7M)
F1(A, B, C) = ∑ 𝒎(𝟑, 𝟓, 𝟔, 𝟕) F2(A, B, C) = ∑ 𝒎(𝟎, 𝟏, 𝟑, 𝟒, 𝟓, 𝟕)
Implement circuit with PLA having 3 inputs, 4 product terms & 2 outputs

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ANS
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F1 = BC + AC + AB F2 = BICI + AICI + ABC

F1I = BICI + AICI + AIBI F2I = BC + AC + AIBICI

 If F1 & F2 are selected for implementation total number of distinct

product terms need to be realized is six which is not possible for
specified 3 * 4 * 2 PLA
 If F1I & F2I are selected then total number of distinct product terms
reduces to four which is more possible to be implemented by
specified PLA

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Q3(A) Simplify Boolean Expression : F(x, y, z) = ∑ 𝒎(𝟎, 𝟏, 𝟑, 𝟒, 𝟓, 𝟕) (3M)

u

ANS
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F(x, y, z) = ∑ 𝒎(𝟎, 𝟏, 𝟑, 𝟒, 𝟓, 𝟕)
F(x, y, z) = 000 + 001 + 011 + 100 + 101 + 111
F(x, y, z) = AIBICI + AIBIC + AIBC + ABICI + ABICI + ABC
F(x, y, z) = AIBI(CI + C) + BC (AI + A) + ABI (C + CI)
F(x, y, z) = AIBI + BC + ABI
F(x, y, z) = BI + BC
F(x, y, z) = (BI + B) (BI + C)
F(x, y, z) = BI + C

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Q3(B) Explain S – R clocked Flip Flop (4M)

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 The clocked SR Flip Flop consists of 4 NAND gate, 2 inputs (S & R) & 2
outputs (Q & Q I). The clock pulse is given at the inputs of gate A & B
 If the clock pulse input is replaced by an enable input, then it is said to
be SR latch. Let us assume that this flip flop works under positive edge
triggering. The following figure shows the block diagram and the logic
circuit of a clocked SR flip flop

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 No change state [S = 0, R = 0]
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 When the clock pulse is applied, output of NAND gates A & B will
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be SI = 1 and R I = 1
 For this case, if Q = 0, QI = 1 then both inputs form NAND gate C
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are 1 & output thus produces by gate C is Q n+1 = 0. The present

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state output is Q = 0 and next state output is Q I = 0. Thus state has

no change
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 For same SR inputs if Q = 1, QI = 0 inputs for NAND gate C will be 0

and 1. For these inputs, output produced by NAND gate is a = 1,
hence there is no change in state
 Reset state [S = 0, R = 1]
 Upon the application of the clock pulse, the output of NAND gate
A & B are SI = 1, RI = 0. Let the present state output be Q = 0 or Q
= 1. For next state output produced is QI = 1. Now 2 inputs for
NAND gate C are SI = 1, QI = 1 will produces output at next stage
as Qn+1= 0
 Set state [S = 1 , R = 0]
 When clock pulse is applied, output from NAND gate A & B are S I
= 0 , RI = 1

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  For this condition, irrespective of present state input Q Inext state
output produced by NAND gate C is Q n+1 = 1. Thus two inputs of
NAND gate D are RI = 1 and Q = 1 which produces an Q n+1 = 0
 Invalid state [S = 1, R = 1]
 For inputs S = 1 & R = 1, NAND gates A & B produces output of S I =
0, RI = 0
 Now if Q = 0 and Q I = 1, inputs for NAND C will be SI = 0 and QI = 1.
Output produced from NAND gate C is Q n+1. Similarly two inputs
for NAND gate 0 will be R I = 0 and Q = 0. Output produced from
NAND gate D is QI = 1. This is invalid state
 Truth Table

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Q3(C) Design Full Adder circuit using decoder & multiplexer (7M)

ANS

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Sum = ∑ 𝒎(𝟏, 𝟐, 𝟒, 𝟕)
Carry = ∑ 𝒎(𝟑, 𝟓, 𝟔, 𝟕)

Using Decoder

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Using Multiplexer
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Sum
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Carry
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Logic Circuit

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OR
Q3(A)Generate AND & EX – OR gate using NOR gate (3M)

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AND gate using NOR gate

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EX – OR gate using NOR gate

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OR
Q3(B) Implement D Flip Flop using JK Flip Flop (4M)

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We first write present state, next state table for D FF. Along that we write
excitation inputs for JK FF
Excitation Table
Qn D Qn+1 J K
0 0 0 0 X
0 1 1 1 X
1 0 0 X 1
1 1 1 X 0

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From excitation table we can draw K – maps for J & K
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J=D ̅
K=𝑫
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OR
Q3(C) Design counter to generate repetitive sequence 0, 4, 2, 1,6 (7M)

ANS
‘
State Diagram

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Excitation Table

Q2
Present State
Q1 Q0 Q*2
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Next State
Q*1 Q*0
Inputs
DC DB
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0 0 0 1 0 0 1 0
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1 0 0 0 1 0 0 1
0 1 0 0 0 1 0 0
0 0 1 1 1 0 1 1
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1 1 0 0 0 0 0 0
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K maps :

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 DA = Q2IQ1
DB = Q2Q1I + Q2Q1I
DC = Q1I QI2

Counter

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Q4(A) What is Race Condition in J – K Flip Flop (3M)
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Race – Around Condition

 For J – K Flip Flop, if J = K = 1 and if clk = 1 for long period of time
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then output Q will toggle as long as the clock remains high which
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makes the output unstable or uncertain

 This is called a race around condition in JK flip flop
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 We can overcome this problem by making clock = 1 for very less

duration
 The circuit used to overcome race around condition is called Master
Slave J – K Flip Flop

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Q4(B) Construct a ring counter with five timing signals (4M)

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Q4(C) Design BCD to Excess – 3 code converter using minimum number

of NAND gates (7M)

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ANS
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Implementation for Simplification function using K – map

W = BD + BC + AD + ABI X = BCIDI + BID + BIC

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Y = CID + CD Z = DI

W = BD + AD + ABI + BC
Through complementing twice we find
W = ((BD + AD + ABI + BC)I)I

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W = ((BD)I (AD)I (ABI)I (BC)I)I
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X = BCID + BID + BIC
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X = ((BCID)I + (BID)I + (BIC)I)I
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Y = ((CIDI)I (CDI)I
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Z=0
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Circuit

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OR : Q4(A) Explain 2 – bit comparator circuit (3M)

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2 – bit comparator circuit

 A comparator used to compare two binary number each of two bits is
called 2 – bit magnitude comparator
 It consists of four input & three output to generate less than, equal to
and greater than between two binary numbers
 Figure

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 Truth Table
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For Y1 (A > B) :

Y1 = A1A0 ̅̅̅̅
𝑩𝟎 + A0̅̅̅̅
𝑩𝟏 ̅̅̅̅
𝑩𝟎 + A1 ̅̅̅̅
𝑩𝟏

For Y2 (A = B) :

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For Y3 (A < B)

Y3 = ̅𝑨̅̅𝟎̅ B1 B0 + ̅𝑨̅̅𝟏̅ B1 + ̅𝑨̅̅𝟏̅ ̅𝑨̅̅𝟎̅B0

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OR : Q4(B) Write short note on FPGA (4M)

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 Field programmable Gate arrays (FPGA) are semiconductor devices that

are based around of configurable logic blocks (CLBs) connected via
programmable interconnects
 FPGAs can be reprogrammed to desire app on or functionality
requirements after manufacture
 This feature distinguishes FPGAs from application specific integrated
circuits which are custom many tured for specific design tasks
 Although one time programmable (OTP) FPGAs are available,
dominants types are SRAM based which can be reprogrammed as
design evolves

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  FPGA Applications
 Aerospace & Defense
 ASIC prototyping
 Automotive
 Broadcast & pro AV
 Consumer Electronics
 Data Center

OR : Q4(C) What is digital to analog converter? Draw & explain R – 2R

DAC? (7M)

ANS
 A digital to analog convertor (DAC) converts digital input signal into
analog output signal
 The digital signal is represented with binary code which is

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combination of bits 0 and 1
 Diagram
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 A digital to analog (DAC) consists of number of binary inputs and

single output
 In general, number of binary inputs of DAC will be power of two
 Types of DACs
1) Weighted Resistor DAC
2) R – 2R ladder DAC

R – 2R ladder DAC
 The R – 2R ladder DAC overcomes disadvantages of binary weighted
resistor DAC. As name suggest R – 2R ladder DAC produces an analog
output which is almost equal to digital input by using a R – 2R ladder
network in inverting adder circuit
 The circuit diagram of 3 – bits R – 2R ladder DAC is shown in figure

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  Recall that the bits of binary number can have only one of two values
i.e either 0 or 1. Let 3 – bit binary input is b2b1b0. Here the bits b2 &
b0 denote most significant bits(MSB) and least significant bits (LSB)
respectively
 The digital switch is shown in the above figure will be connected to
ground, when the corresponding input bits are equal to 0. Similarly,
digital switches shown in figure will be connected to the negative

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reference voltage – VR when corresponding input bits are equal to ‘1’
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 It is difficult to get the generalised output voltage equation of R – 2R
ladder DAC. But we can find the analog output values of R – 2R
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ladder DAC for individual binary input combinations early
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 Advantages of R – 2R ladder
 R – 2R ladder DAC contains only 2 values of resistors R & 2R so
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it is easy to select & design more accurate resistors

 If more number of bits are present in digital input, then we
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have to include required number of R – 2R reactions

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additionally
Q5(A) Perform following operation using 2s complement method
(11010)2 – (1000)2 (3M)

ANS
 1s complement of 1000 is 0 1 1 1
+ 1
10 0 0
 Adding
1 1 0 1 0
+ 1 0 0 0
1 1 0 1 0
Avoiding carry, answer is (10010) 2

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Q5(B) Write short note on Read Only Memory (ROM) (4M)

ANS

ROM
 ROM stands for Read – Only Memory. It is non volatile memory that
is used to store important information which is used to operate
system
 As its name refers to read only memory we can only read programs &
data stored on it
 It is also primary memory unit of computer system
 It contains some electronic fuses that can be programmed for piece
of specific information
 The information stored in ROM in binary format. It is also known as

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permanent memory
 Block Diagram aa
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 Classification
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 Features
 ROM is non volatile memory
 Information stored in ROM is permanent
 Information & programs stored on it we can only read
 Information & programs are stored on ROM in binary format
 It is used in start – up process of computer
 Types of ROM
1) PROM : Programmable Read Only Memory
2) EPROM : Erasable Programmable Read Only Memory
3) EEPROM : Electrically Erasable Programmable Read Only
Memory
4) MROM : Masked Read Only Memory

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Q5(C) Explain working of 4 bit binary ripple counter (7M)

ANS
 A binary ripple counter consists of series connection of
complementing flip flop with output of each flip flop connected to
clock pulse input of next high – order flip – flop
 Flip – flop holding least significant bit receives incoming count pulses.
Diagram

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 Small circle in Cp input indicates that flip flop complements during
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negative going transition or when output to which it connected goes
from 1 to 0
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 The lower – order bit Q must be complemented with each count
pulse. Every time Q0 goes from 1 to it complements Q 1 every time Q1
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goes from 1 to it complements Q2 & so on

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MSB LSB Decimal

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Q3 Q2 Q1 Q0 Value
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0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14

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 1 1 1 1 15
0 0 0 0 Full Reset

Timing Diagram

 In timing diagram Q0 is changing as soon as negative edge of clock is

encountered, Q1 is changing when negative edge of Q 0 is
encountered & so on

OR Q5(A) Obtain truth table of function : F = xy + yz + zx (3M)

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ANS
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F = xy + yz + zx
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F = xy(z + 𝑧̅) + yz(x + 𝑥̅ ) + zx (y + 𝑦̅)

F = xyz + xy𝑧̅ + xyz + 𝑥̅ yz + xyz + x𝑦̅z
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F = xyz + xy𝑧̅ +𝑥̅ yz + x𝑦̅z

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F = 111 + 110 + 011 + 101

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Truth Table
x y z F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

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OR Q5(B) Implement following function using ROM
F1 = ∑ 𝒎(𝟏, 𝟑, 𝟒, 𝟔) and F2 = ∑ 𝒎(𝟎, 𝟏, 𝟓, 𝟕) (7M)

ANS
F1 = ∑ 𝒎(𝟏, 𝟑, 𝟒, 𝟔)
F2 = ∑ 𝒎(𝟎, 𝟏, 𝟓, 𝟕)

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OR Q5(C) Explain in detail Dual Slope A/D Converter (7M)

ANS

 The dual slope integration type of A/D Converter is a very popular

method for digital voltmeter application. This type of converter is also
one type of voltage to time converter
 In this a capacitor is charged for fixed time by analog voltage to be
converted into digital
 The magnitude of the voltage to which the capacitor is charge
depends upon the magnitude of analog voltage
 When the capacitor is charged it is charged in the negative direction
by the fixed negative value

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 Pulses of the counter are counted during discharged period which is
proportional to voltage
 If the magnitude of the analog voltage is more, capacitor is charged
to high voltage and time required to discharge increases so counts of
counter increase. Arrangement of this type of A/D

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 In this circuit an integrator capacitor, AND gate, clock, counter, flip
flop, electronic switch are used
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 There are 2 inputs of the electric switch in position A of analog
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voltage V0 to be converted into digital is applied to integrator. In
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position B fixed negative voltage -VR is available to integrator

 High gain of op – amp works as the integrator output V0 of integrator
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is given to inverting input of comparator

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 Output of comparator is given to one in of AND gate

 Clock pulse are given to other input of AND gate output of AND gate
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is given to counter, overflow of counter is given to flip flop which

controls electronic switch

 Advantages
1) Accuracy is more typical value is 0.05%
2) It is less costly
3) Effect of Temperature & weather condition is less
4) Noise rejection is good due to the dual slope technique
5) There is no effect of drift of the clock on the accuracy

 Disadvantages : Conversion time is comparatively more

 Application
 It is used in digital voltmeter and digital multimeter

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