UNIT I BASIC CONCEPTS

1. ProblemsonNumber Systems. (Refer Page No. 1- 4 inUnit-1 Hand written material)

2. ProblemsonSOP & POS. (Refer Page No. 11 - 14inUnit-1material)
3. Problemson3 variable & 4 variable K-Map. (Refer Page No. 15-22 inUnit-1material)
4. NANDand NOR Implementation. (Refer Page No. 27 - 30 inUnit-1material)
5. Quine McCluskey/ TabulationMethod. (Refer Page No. 31- 36 inUnit-1material)

UNITII COMBINATIONALLOGICCIRCUITS
1. Designof Half and Full adder. (Refer Page No. 2- 4in Unit-2Handwrittenmaterial)
2. Designof Code converters-------- Binaryto gray, Grayto Binary, BCDtoExcess-3, Excess-3 to
BCD.
(Refer Page No. 13 – 19 inUnit-2 material)
3. ProblemsonMultiplexer and Demultiplexer. (Refer Page No. 25- 33 inUnit-2 material)
4. ProblemsonEncoder and Decoder. (Refer Page No. 34- 47 inUnit-2
material)
5. Magnitude Comparatorand Priority Encoder. (Refer Page No. 48- 52in Unit-2 material)
6. Paritychecker and Generator. (Refer Page No. 53 - 56in Unit-2 material)
7. Sevensegment displaydecoder. (Refer Page No. 57 - 61inUnit-2 material)

UNIT III SYNCHRONOUSSEQUENTIALCIRCUITS

1. Master/ slaveFlip flop& TriggeringofFlipFlop. (Refer Page No2-3 & 10-11 inUnit-3 material)
2. Moore andMealymodel problems. (Refer Page No. 30 - 43 inUnit-3
material)
3. Shift registers and Universal shift register. (Refer Page No. 44- 51in Unit-3material)
4. Ring counterand twisted ringcounter. (Refer Page No. 52-55inUnit-3 material)
5. ProblemsonCounterandRipple counter. (Refer Page No. 19- 29 inUnit-3
material)
UNITIV ASYNCHRONOUSSEQUENTIALCIRCUITS
1. Race free state Assignment (ReferPageNo. 02 - 07 in Unit-4Hand writtenmaterial)
2. Hazards and itstypes. (Refer Page No. 08-10 in Unit-4material)
3. Designof Hazard free circuits. (ReferPageNo. 11 inUnit-4 material)
4. Asynchronous circuits problems. (Refer Page No. 28- 30 inUnit-4 material)
UNITV LOGICFAMILIESANDPROGRAMMABLELOGICDEVICES
Page1of23
1. Basic SemiconductorMemories. Static ROM,PROM,EPROM,EEPROM EAPROM.
(Refer Page No. 01- 07 inUnit-5Hand writtenmaterial)
2. Classificationof logic familiesand its characteristics.(ReferPageNo. 15- 17 in Unit-5material)
3. Working principle of TTL. (Refer Page No. 20-23in Unit-5 material)
4. Working principle of CMOS. (Refer Page No. 24-27 inUnit-5 material)
5. Comparisonof Logic Families. (Refer Page No. 34- 35inUnit-5 material)
6. ProblemsonPLA& PAL. (Refer Page No. 38-54 inUnit-5 material)

1 (i)Find the MSOP representation for the following function using K-Map. F(A,B,C,D)=
Σm(1,3, 4, 6,10,11,12,13,14) + Σd (0,8,15).

(ii)Simplify thefollowing functionusing K-Map andrealize theminimum expression

usingbasic logic gates.
f (A,B,C, D)= π M(0,1,5, 7, 9, 10, 12, 15)+ ∑d (6, 14)

2 Minimize thefollowing expressionusing QuineMc-Cluskey method. Y(A,B,C,D)= ∑

m(0,2,3,6, 7,8,10, 12, 13)

Page2of23
Page3of23
3 Design a2 bit magnitudecomparator with threeoutputs: A>B, A=B and A< B.

Page4of23
Page5of23
LOGIC DIAGRAM:

Page6of23
4 DesignaGray codeto binary code converter anddrawthe logic diagram.
TRUTHTABLE:

Page7of23
Page8of23
Page9of23
5 (i) Designa MOD-5counter using T flip flop anddrawthe logic diagram.
Present State Next State Flip FlopInput
A B C A+1 B+1 C+1 TA TB TC
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 0 0 0 1 0 0
1 0 1 X X X X X X
1 1 0 X X X X X X
1 1 1 X X X X X X
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0

Page10of23
(ii)Explaintheoperationof Masterslaveflip flop.

Page11 of23
6 (i) Designa 3bit synchronous counterforthe givensequence using D flipflop.
000 , 001, 010, 011, 100, 101, 111
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
Present State Next State Flip FlopInput
A B C A+1 B+1 C+1 DA DB DC
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0
0 1 0 0 1 1 0 1 1
0 1 1 1 0 0 1 0 0
1 0 0 1 0 1 1 0 1
1 0 1 1 1 1 1 1 1
1 1 0 X X X X X X
1 1 1 0 0 0 0 0 0

(ii)Design a4 bit serialin parallel out shift register.

Thebasic operationof aSIPOshiftregister involves thesequential transferofdatabitsthrougha
series offlip-flops. Theregister hasoneinput linecalledtheserial input (SI)and parallel output lines
(Q0, Q1,Q2,etc.)correspondingtoeachflip-flop. Theclocksignal (CLK) controls theshifting ofdata.

Page12of23
 Theinitialstateoftheregister is0000, and wewant to performa serial data input of 1011.Assume
thattheclocksignalis rising-edgetriggered.
Solution:
Initialize theSIPO shiftregister withtheinitial state0000.
On the first clock pulse, the first bit of the serial input (1) enters the first flip-flop and the existing
data in the register shifts by one position. The state of the shift register after the first clock pulse
is 0001.
Onthesecondclockpulse,the state oftheshift registerafterthesecondclockpulseis 0010.
Onthethird clockpulse, thestateoftheshiftregister after thethirdclockpulseis 0101.
Onthefourth clockpulse,thestateof theshiftregister after thefourthclockpulseis 1011.
Thefinalstateoftheshift registerafterallfour clockpulses is 1011.
7 What is ahazardin asynchronoussequential circuits? Definestatic hazard, dynamic
hazardand essentialhazard.
Givethe hazard free realization fortheBooleanfunction.
f(A,B,C,D)=m(0,2,6,7,8,10,12).

Page13of23
Page14of23
f(A,B,C,D)=m(0,2,6,7,8,10,12).

LogicDiagram:

Page15of23
8 Critically examine theconcept of cycles and racesinasynchronous sequentialcircuits
and explainin detail about theracefreestateassignment.
Races: When 2 or more binary state variables change their value in response to a
change in an input variable, race condition occurs inan asynchronous sequential circuit.
In case of unequal delays, a race condition may cause the state variables to change in
anunpredictable manner.
Cycles: A cycle occurs when an asynchronous circuit makes a transition through a
series of unstable states. If a cycle does not contain a stable state, the circuit will go
from one unstable to stable to another, until the inputs are changed.
Racefreestateassignment:
Once a reduced flow table has been derived for an asynchronous sequential circuit, the next
step in the design is to assign binary variables to each stable state. This assignment results in
the transformationof the flow table intoits equivalent transitiontable. The primary objective in
choosinga properbinarystate assignment is the preventionof critical races. Critical racescan
be avoided by making a binary state assignment in such a way that onlyone variable changes
at anygiventime whena state transition occurs inthe flowtable.
Three-RowFlow-TableExample

To avoid critical races, we must find a binary state assignment such that only one binary
variable changes during eachstate transition.

Page16of23
9 (i) Implement thefollowing switchingfunctionusing 5*8*4PLA.
Z1 = ab’d’e+ a’b’c’e’ + bc + de ; Z2 = a’c’e ;
Z3 = bc + de+ c’d’e’ + bd ; and Z4 = a’c’e+ ce

(ii) Summarizethe concept of CMOS logic and basic CMOS invertercircuit withrelevant
diagrams.
The logic gates are the basic building blocks of all digital circuits and computers. These
Page17of23
 logic gates are implemented using transistors called MOSFETs. A MOSFET transistor is
a voltage-controlled switch.
The MOSFET acts as a switch and turns on or off depending on whether the voltage on
it iseitherhigh or low.
There are twotypes of MOSFETs: NMOS and PMOS.
The NMOS turns onwhenthe voltage is high and off whenthe voltage islow.
The PMOS, onthe otherhand, turns on whenever the voltage is low and goes off as the
voltage goes high. When the two are used together to realize the logic gates, they are
calledCMOS (Complementary MOS).
The reason they are called complementary is that NMOS and PMOS work in a
complementaryfashion.
Whenthe NMOS switchturns on, the PMOS gets off, and vice-versa.
It consists of two MOSFETs in series in such a
way that the P-channel device has its source
connected to+VDD(a positive voltage) and the
N-channel device has its source connected to
ground. The gates of the two devices are
connected together as the common input and
the drains are connected together as the
commonoutput
10 (i) Implement thefollowing functionusingsuitablePLA.
F1(x, y, z)= Σm (1, 2, 4, 6)
F2(x, y, z)= Σm (0, 1, 6, 7)
F3(x, y, z)= Σm ( 2, 6)

Page18of23
 (ii)Explainthe2 input TTLNAND gatewithaneat sketch.

a) A and B both low: both B-E junctions of Q1 are forward biased. Hence D1 and D2 will
conduct to force the voltage at point C to 0.7V. This voltage is insufficient to forward bias B-E
junctionof Q2. Hence Q2 remains OFF. Therefore its collectorvoltage rises to VCCVCC. As Q3
is operatinginemitterfollower mode, output Y will be pulled up tohigh voltage Y= 1.
b) Either A or B low: If any one input is connected to ground with other left open or connected
to VCC. VCC the corresponding diode (D1 or D2) will conduct. This will pull down voltage at C
o 0.7V. This voltage is insufficient to turn on Q2 so it remains OFF. So collector voltage of Q2
will be equal to VCC. This voltage acts as base voltage for Q3. As Q3 acts as an emitter
follower, output Y will be pulled toVCCVCC. Y= 1
c) A and B both high: If both A and B are connected to then both diodes D1 and D2 will be
reverse biased and do not conduct. Therefore D3 is forward biased and base current is
supplied to transistor Q2 via R1 and D3. As Q2 conducts, the voltage at X will drop down and
Q3 will be OFF, whereas voltage at Z will increase to turn ON Q4. As Q4 goes into saturation,
the output voltage Y will be pulled downto low. Y = 0
11 Design anasynchronous sequentialcircuit that has two inputsX andY and one output Z.
WheneverY is 1, Input X is transferred to Z. WhenY is 0, the output doesnot change for
any change inX.

Page19of23
Page20of23
12 Designasynchronous sequentialcircuit forthegivenstatediagram using JK flipflop.
(15)

Page21of23
Statetable:
Present State Input Next State FlipFlop Input Output
A B X A+1 B+1 JA KA JB KB Y
0 0 0 0 1 0 X 1 X 0
0 0 1 1 0 1 X 0 X 0
0 1 0 1 1 1 X X 0 1
0 1 1 1 0 1 X X 1 0
1 0 0 1 0 X 0 0 X 0
1 0 1 1 1 X 0 1 X 1
1 1 0 0 0 X 1 X 1 0
1 1 1 1 1 X 0 X 0 1
ExcitationTable
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
K-MapSimplification

Logic Diagram:

Page22of23
***********************************************

Page23of23