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Lecture 10

The document covers key concepts in digital electronic circuits, focusing on combinational and sequential logic. It explains three-state gates, decimal adders, binary multipliers, and types of sequential circuits, including synchronous and asynchronous circuits. Additionally, it details storage elements like latches and flip-flops, highlighting their functions and differences.

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12 views23 pages

Lecture 10

The document covers key concepts in digital electronic circuits, focusing on combinational and sequential logic. It explains three-state gates, decimal adders, binary multipliers, and types of sequential circuits, including synchronous and asynchronous circuits. Additionally, it details storage elements like latches and flip-flops, highlighting their functions and differences.

Uploaded by

prasanthtaddi005
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Electronic Circuits

(EC2L004)

Lecture 10: Combinational Logic-III & Sequential Logic


Three-State Gates
• A three-state gate is a digital circuit that exhibits three states:
0, 1 and a high-impedance (high z state).

• The high impedance state the logic behaves like


• an open circuit, which means that the output appears to be
disconnected
• the circuit has no logic significance,

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 2


Multiplexers with three-state gates

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 3


Decimal Adder
• Computers or calculators that perform arithmetic operations
directly in the decimal number system represent decimal
numbers in binary coded form.

• An adder for such a computer must employ arithmetic circuits


that accept coded decimal numbers and present results in the
same code.

• For binary addition, it is sufficient to consider a pair of


significant bits together with a previous carry.

• A decimal adder requires a minimum of nine inputs and five


outputs, since four bits are required to code each decimal
digit and the circuit must have an input and output carry.
[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 4
Decimal Adder: BCD Adder

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 5


Decimal Adder: BCD Adder

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 6


Binary Multiplier
• Multiplication of binary numbers is performed in the same way
as multiplication of decimal numbers.

• The multiplicand is multiplied by each bit of the multiplier,


starting from the least significant bit. Each such multiplication
forms a partial product.

• Successive partial products are shifted one position to the


left.

• The final product is obtained from the sum of the partial


products.

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 7


Two-bit by two-bit binary multiplier

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 8


Four-bit by three-bit binary multiplier

[3:0] [3:0]

sum
carry [3:0]

carry sum
[3:0]

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 9


Synchronous Sequential Logic

10
Sequential Circuits
• A digital system has combinational logic as well as sequential
logic. The latter includes storage elements.

• The binary information stored in these elements at any given


time defines the state of the sequential circuit at that time.

• The sequential circuit receives binary information from


external inputs that, together with the present state of the
storage elements, determine the binary value of the outputs.
[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 11
Sequential Circuits
• These external inputs also determine the condition for
changing the state in the storage elements.

• The block diagram demonstrates that


• the outputs in a sequential circuit are a function not only of the
inputs, but also of the present state of the storage elements.
• The next state of the storage elements is also a function of
external inputs and the present state.

• Thus, a sequential circuit is specified by a time sequence


of inputs, outputs, and internal states .

• In contrast, the outputs of combinational logic depend only on


the present values of the inputs.
[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 12
Types of Sequential Circuits

• There are two main types of sequential circuits, and their


classification is a function of the timing of their signals.

• A synchronous sequential circuit is a system whose behavior


can be defined from the knowledge of its signals at discrete
instants of time.

• The behavior of an asynchronous sequential circuit depends


upon the input signals at any instant of time and the order in
which the inputs change.

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 13


Synchronous Sequential Logic
• A synchronous sequential circuit employs signals that affect
the storage elements at only discrete instants of time.
• Synchronization is achieved by a timing device called a clock
generator, which provides a clock signal having the form of a
periodic train of clock pulses .
• The clock signal is commonly denoted by the identifiers clock
and clk .
• Synchronous sequential circuits that use clock pulses to
control storage elements are called clocked sequential
circuits and are the type most frequently encountered in
practice.
• They are called synchronous circuits because the activity within
the circuit and the resulting updating of stored values is
synchronized to the occurrence of clock pulses.

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 14


Synchronous Sequential Logic (Contd.)
• The storage elements (memory) used in clocked sequential
circuits are called flip-flops.
• A flip-flop is a binary storage device capable of storing one bit
of information.
• In a stable state, the output of a flip-flop is either 0 or 1.

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 15


Storage Elements: Latches
• A storage element in a digital circuit can maintain a binary
state indefinitely (as long as power is delivered to the circuit),
until directed by an input signal to switch states.
• The major differences among various types of storage
elements are in the number of inputs they possess and in the
manner in which the inputs affect the binary state.
• Storage elements that operate with signal levels (rather than
signal transitions) are referred to as latches; those controlled
by a clock transition are flip-flops.
• Latches are said to be level sensitive devices; flip-flops are
edge-sensitive devices.
• The two types of storage elements are related because
latches are the basic circuits from which all flip-flops are
constructed.

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 16


SR Latch

• Under normal conditions, both inputs of the latch remain at 0


unless the state has to be changed.
• The application of a momentary 1 to the S input causes the
latch to go to the set state.
• The S input must go back to 0 before any other changes take
place.

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 17


SR Latch

• After both inputs return to 0, it is then possible to shift to the


reset state by momentary applying a 1 to the R input. The 1
can then be removed from R, where upon the circuit remains
in the reset state.
• Thus, when both inputs S and R are equal to 0, the latch can
be in either the set or the reset state, depending on which
input was most recently a 1.

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 18


SR Latch / S’R’ Latch

• SR latch with NAND gates requires a 0 signal to change its


state.

• The inputs signals for the NAND-latch are the complement


values used for the NOR latch.

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 19


SR Latch with control input

• The outputs of the NAND gates stay at the logic-1 level as


long as the enable signal remains at 0.

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 20


D Latch (Transparent Latch)

• How is D-latch structurally different than the SR latch?


• D latch eliminates the undesirable condition of the
indeterminate state that occurs in the SR latch (Q = Q’ = 1).

If D = 1, Q = 1 -> ‘set’ state


If D = 0, Q = 0 -> ‘reset’ state
[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 21
D Latch (Contd.)

• The D latch receives that designation from its ability to hold data in
its internal storage.
• The output follows changes in the data input as long as the enable
input is asserted. This situation provides a path from input D to the
output, and for this reason, the circuit is often called a transparent
latch.
• When the enable input signal is de-asserted, the binary information
that was present at the data input at the time the transition occurred
is retained (i.e., stored) at the Q output until the enable input is
asserted again.
[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 22
Graphic Symbols for Latches

[06/02/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 23

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