Sequential Logic Circuits
Sequential Logic Circuits
Chamira U. S. Edussooriya
B.Sc.Eng. (Moratuwa) M.A.Sc., Ph.D. (UVic)
The undesirable condition that may occur with the SR latch can be
eliminated by adding a NOT gate.
This modified SR latch is called the D latch.
The value at the output of the flip-flop is the value that was stored in
the master stage immediately before the negative edge occurred.
Two SR latches respond to the D and the Clk inputs while the third
SR latch provides the output of the flip-flop.
The value of D is transferred to Q during the positive edge of the
clock.
Chamira Edussooriya (ENTC, UoM) Mar. 04, 2016 8 / 10
Storage Elements: Flip-Flops cont’d
Other types of flip-flops:
JK flip-flop
T (toggle) flip-flop