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8051 memory interface

The document outlines the interfacing of external ROM and RAM with the 8051 microcontroller. It details the use of various ports for address and data lines, the role of the EA, PSEN, and ALE pins, and the requirements for memory size and address lines. Additionally, it specifies how to select external memory based on address line conditions.

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Hariram S
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24 views4 pages

8051 memory interface

The document outlines the interfacing of external ROM and RAM with the 8051 microcontroller. It details the use of various ports for address and data lines, the role of the EA, PSEN, and ALE pins, and the requirements for memory size and address lines. Additionally, it specifies how to select external memory based on address line conditions.

Uploaded by

Hariram S
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EXTERNAL MEMORY INTERFACE

EXTERNAL ROM (PROGRAM MEMORY) INTERFACING

Interfacing of ROM/EPROM to 8051

Figure shows how to access or interface ROM to 8051.

 Port 0 is used as multiplexed data & address lines. It gives lower order (A7-A0) 8bit address in
initial T cycle & higher order (A8-A15) used as data bus.

 8 bit address is latched using external latch & ALE signal from 8051.

 Port 2 provides higher order (A15-A8) 8 bit address.

 PSEN is used to activate the output enable signal of external ROM/EPROM.
EA Pin
 EA, "external access", is an input pin and must be connected to Vcc or GND

 The 8051 family members all come with on-chip ROM to store programs
 The 8031 and 8032 family members do no have on-chip ROM, so code is stored on an
external ROM and is fetched by 8031/32

 EA pin must be connected to GND to indicate that the code is stored externally

PSEN
PSEN, "program store enable", is an output pin
This pin is connected to the OE pin of the ROM

ALE

 ALE, "address latch enable”, is an output pin and is active high


 Port O provides both address and data The 8031 multiplexes address and data through Port O to
save pins
 ALE pin is used for demultiplexing the address and data by connecting to the G pin of the
74LS373 chip
μController system using 8051 to interface the eexternal
xternal ROM of size 4k x 8.
Given, Memory size: 4k
n
i.e we require 2 =4k :: n address lines
 Here n=12 :: A0 to A11 address lines are required.

 Remaining lines A0, A0, A0, A0 & PSEN are connected though OR gate to CS &RD
of external ROM.

When A00 to A0 are low (logic ‘0’), only then external ROM is selected
selected.
EXTERNAL RAM (DATA MEMORY) INTERFACING

Interfacing of RAM to 8051

Above figure shows how to connect or interface external RAM (data memory) to 8051.

 Port 0 is used as multiplexed data & address lines.


 Address lines are decoded using external latch & ALE signal from 8051 to provide lower
order (A7-A0) address lines.
 Port 2 gives higher order address lines.
 RD & WR signals from 8051 selects the memory read & memory write operations
respectively
 RD & WR signals: generally P3.6 & P3.7 pins of port 3 are used to generate memory read and
memory write signals. Remaining pins of port 3 i.e. P3.0-P3.5 can be used for other functions.

EA Pin
 EA, "external access", is an input pin and must be connected to Vcc or GND
 The 8051 family members all come with on-chip ROM to store programs
 The 8031 and 8032 family members do no have on-chip ROM, so code is stored on an
external ROM and is fetched by 8031/32
 EA pin must be connected to GND to indicate that the code is stored externally

ALE

 ALE, "address latch enable”, is an output pin and is active high


 Port O provides both address and data The 8031 multiplexes address and data through Port O to
save pins
 ALE pin is used for demultiplexing the address and data by connecting to the G pin of the
74LS373 chip
μController system using 8051 to Interface the external RAM of size 16k x 8
Given, Memory size: 16k
n
Which means, we require 2 =16k: n address lines
 Here n=14: A0 to A13 address lines are required.

 A14 and A15 are connected through OR gate to CS pin of external RAM.

 When A14 and A15 both are low (logic ‘0’), external data memory (RAM) is
selected.














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