A Laboratory Manual for

Digital Electronics (3131704)

B.E. Semester 3
(INSTRUMENATION & CONTROL)

GOVERNMENT ENGINEERIG COLLEGE

GANDHINAGAR

Directorate of Technical Education, Gandhinagar,

Gujarat
 GOVERNMENT ENGINEERIG COLLEGE
GANDHINAGAR

Certificate
This is to certify that Mr./Ms. ___________________________________
________ Enrollment No. _______________ of B.E. Semester _____
Instrumentation & Control Engineering of this Institute (GTU Code: _028_
) has satisfactorily completed the Practical / Tutorial work for the subject
Digital Electronics (3131704) for the academic year 2023-24.

Place: __________
Date: __________

Name and Sign of Faculty member

Head of the Department

Digital Electronics (3131704)

Preface

The main motto of any laboratory/practical/field work is to enhance required skills as well as
create ability amongst students to solve real-time problems by developing relevant competencies
in the psychomotor domain. By keeping this in view, GTU has designed a competency-focused
outcome-based curriculum for engineering degree programs where sufficient weightage is given
to practical work. It shows the importance of enhancement of skills amongst the students and it
pays attention to utilizing every second of time allotted for practical amongst students, instructors
and faculty members to achieve relevant outcomes by performing the experiments rather than
having merely study-type experiments. It is a must for effective implementation of competency-
focused outcome-based curriculum that every practical is keenly designed to serve as a tool to
develop and enhance relevant competency required by the various industry among every student.
These psychomotor skills are very difficult to develop through the traditional chalk-and-board
content delivery method in the classroom. Accordingly, this lab manual is designed to focus on
the industry defined relevant outcomes, rather than the old practice of conducting practical to
prove concepts and the theory.

By using this lab manual, students can go through the relevant theory and procedure in advance
before the actual performance which creates an interest and students can have a basic idea prior
to the performance. This, in turn, enhances pre-determined outcomes amongst students. Each
experiment in this manual begins with competency, industry-relevant skills, course outcomes as
well as practical outcomes (objectives). The students will also achieve safety and necessary
precautions to be taken while performing practical.

This manual also provides guidelines to faculty members to facilitate student-centric lab activities
through each experiment by arranging and managing necessary resources in order that the
students follow the procedures with required safety and necessary precautions to achieve the
outcomes. It also gives an idea of how students will be assessed by providing rubrics.

Digital Electronics is the fundamental course which deals with various digital signals and the
engineering of devices that use or produce them. Digital electronic circuits are usually made from
large assemblies of logic gates, often packaged in integrated circuits. There are two types of
Digital Circuits: Combinational Digital circuits and Sequential Digital Circuits. The course will
help in the design and analysis of the digital circuit and system.

Utmost care has been taken while preparing this lab manual. However, there are always chances
for improvement. Therefore, we welcome constructive suggestions for improvement and removal
of errors if any.
 Digital Electronics (3131704)

Practical – Course Outcome matrix

Course Outcomes (COs):
After learning the course, the students should be able to:
CO1 Apply knowledge of Boolean algebra and other minimization techniques for digital circuit design.
CO2 Identify, formulate and solve a problem based on combinational circuits.
CO3 Identify, formulate and solve a problem based on sequential circuits.
CO4 Design complex digital systems with basic building blocks like registers, counters, Memory units.
CO5 Describe Transfer logic and micro-operation and types of Digital logic families.
Sr. CO
Objective(s) of Experiment CO2 CO3 CO4 CO5
No. 1
To verify and interpret the logic and truth table for AND, OR, NOT,
1. √
NAND, NOR, Ex-OR, Ex-NOR gates.
To Realization of logic functions with the help of universal gates
2. √
NAND and NOR Gate

3. To Verify De-Morgan's laws √

To analyze the truth table of binary to gray and gray to binary
4. √ √
converter

5. To design and verify operation of Half adder and Full adder. √

6. To design and verify operation of Half Subtractor and Full Subtractor. √

7. To design and verify operation of 4-bit full adder using IC 7483. √

8. To design and verify operation of Encoder. √

9. To design and verify operation of Decoder. √

To design and implementation of 2-Bit Magnitude Comparator using
10. √
logic gates and 4-Bit Magnitude Comparator using IC 7485.
Implementation of 4 X 1 Multiplexer using Logic gates and study of
11. √
IC74151.
Implementation of 1X 4 Demultiplexer using Logic gates and study
12. √
of IC 74154.
To verify the truth table of RS, JK, T and D flip-flops by using NAND
13. √
& NOR gates ICs.
To analyze the circuit and truth table of 4-bit Bidirectional Universal
14 √ √
shift register by using IC 74194.

15. Design and verify the BCD counter using IC7490. √ √

16. Simulation of Logic circuits using Multisim simulator √ √ √ √ √

Digital Electronics (3131704)

Industry Relevant Skills

The following industry-relevant competencies are expected to be developed in the student by

undertaking the practical work of this laboratory.
1. Able to demonstrate the truth table of various expressions and combinational circuits
using logic gates.
2. Able to design, test and evaluate various combinational circuits such as adders,
subtractors, comparators, multiplexers and de-multiplexers.
3. Able to design various sequential circuits like flip-flops, counters and shift registers.

Guidelines for Faculty members

1. Teacher should provide the guideline with a demonstration of the practical to the
students with all features.
2. Teacher shall explain basic concepts/theory related to the experiment to the students before
starting each practical.
3. Involve all the students in the performance of each experiment.
4. Teacher is expected to share the skills and competencies to be developed in the
students and ensure that the respective skills and competencies are developed in the
students after the completion of the experimentation.
5. Teachers should give an opportunity to students for hands-on experience after the
demonstration.
6. Teacher may provide additional knowledge and skills to the students even though not
covered in the manual but are expected from the students by the concerned industry.
7. Give practical assignments and assess the performance of students based on the task
assigned to check whether it is as per the instructions or not.
8. Teacher is expected to refer complete curriculum of the course and follow the
guidelines for implementation.

Instructions for Students

1. Students are expected to carefully listen to all the theory classes delivered by the faculty
members and understand the COs, content of the course, teaching and examination scheme,
skill set to be developed etc.
2. Students shall organize the work in the group and make a record of all observations.
3. Students shall develop maintenance skills as expected by industries.
4. Students shall attempt to develop related hands-on skills and build confidence.
5. Students shall develop the habits of evolving more ideas, innovations, skills etc., apart from
those included in the scope of the manual.
6. Students shall refer to technical magazines and data books.
7. Students should develop a habit of submitting the experimentation work as per the schedule
and s/he should be well prepared for the same.

Common Safety Instructions

1. Students are expected to carefully handle computers and trainer kits.
 Digital Electronics (3131704)

Index
(Progressive Assessment Sheet)

Sr. Objective(s) of Experiment Page Date of Date of Assess Sign. of Remar

No. No. perform submiss ment Teacher ks
ance ion Marks with date
1 To verify and interpret the logic and truth table for AND, OR,
NOT, NAND, NOR, Ex-OR, Ex-NOR gates.
2 To Realization of logic functions with the help of universal
gates NAND and NOR Gate
3 To Verify De-Morgan's laws
4 To analyze the truth table of binary to gray and gray to binary
converter
5 To design and verify operation of Half adder and Full adder.
6 To design and verify operation of Half Subtractor and Full
Subtractor.
7 To design and verify operation of 4-bit full adder using IC
7483.
8 To design and verify operation of Encoder.

9 To design and verify operation of Decoder.

10 To design and implementation of 2-Bit Magnitude
Comparator using logic gates and 4-Bit Magnitude
Comparator using IC 7485.
11 Implementation of 4 X 1 Multiplexer using Logic gates and
study of IC74151.
12 Implementation of 1X 4 Demultiplexer using Logic gates and
study of IC 74154.
13 To verify the truth table of RS, JK, T and D flip-flops by using
NAND & NOR gates ICs.
14 To analyze the circuit and truth table of 4-bit Bidirectional
Universal shift register by using IC 74194.
15 Design and verify the BCD counter using IC7490.

16 Simulation of Logic circuits using Multisim simulator.

Total
 Experiment No: 1
To verify and interpret the logic and truth table for AND, OR, NOT, NAND,
NOR, Ex-OR, Ex-NOR gates.

Date:

Competency and Practical Skills: To develop digital circuit building and troubleshooting
skills

Relevant CO: CO1

Objectives: (a) To verify the truth table of Logic gates.

Equipment/Instruments: TTL family ICs (7408,7406,7432,7400,7402,7486 and 74266),

LEDs, Wires, 5-volt DC supply, Breadboard, Multimeter.

Theory:
1) AND gate

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A
dot (.) is used to show the AND operation i.e. A.B or can be written as AB.

Y=A.B

Figure 1 (A)Logic symbol (B) Truth Table (C) Pin diagram of AND gate

2) OR gate

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high.
A plus (+) is used to show the OR operation.

Y=A+B
 Figure 2 (A)Logic symbol (B) Truth Table (C) Pin diagram of OR gate.

3) NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It
is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This
is also shown as A' or A with a bar over the top, as shown at the outputs.

Figure 3 (A)Logic symbol (B) Truth Table (C) Pin diagram of NOT gate.

4) NAND gate

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of
all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle
on the output. The small circle represents inversion.
 Figure 4 (A)Logic symbol (B) Truth Table (C) Pin diagram of NAND gate

5) NOR gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all
NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on
the output. The small circle represents inversion.

Figure 5 (A)Logic symbol (B) Truth Table (C) Pin diagram of NOR gate
6) Ex-OR gate

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both of its two
inputs are high. An encircled plus sign (⊕) is used to show the Ex-OR operation.

Figure 6 (A)Logic symbol (B) Truth Table (C) Pin diagram of Ex-OR gate

7) Ex-NOR gate

The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low output if
either, but not both of its two inputs are high. The symbol is an EX-OR gate with a small circle on
the output. The small circle represents inversion.

Figure 7 (A)Logic symbol (B) Truth Table (C) Pin diagram of Ex-NOR gate
Procedure:

(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 14 & -ve to pin 7.
(c) Give input at pin 1, 2 & take output from pin 3. It is same for all except for NOT & NOR IC.
(d) For NOR gate IC, pin 1 is output & pin 2 & 3 are inputs.
(e) For NOT gate IC, pin 1 is input & pin 2 is output.
(f) Note the values of output for different combinations of inputs & draw the TRUTH TABLE.

OBSERVATION TABLE:

RESULT:
Truth tables of various logic functions (OR, NOR, NOT, AND, NAND, EX-OR and EX-NOR
GATE) are verified.

PRECAUTIONS:
1) All connections should be according to the circuit diagram.
2) All connections should be right and tight.
3) Readings should be taken carefully.
4) Switch off the power supply after completing the Experiment.

Quiz:
1. Define positive logic and negative logic?
2. Explain Propagation delay of digital IC.
3. Explain Power dissipation of digital IC.
4. Why logic gates are called basic gates?

Suggested Reference: VLab

https://de-iitr.vlabs.ac.in/exp/truth-table-gates/index.html
References used by the students: (Sufficient space to be provided)
Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit.
5. Quiz answers and submission in time.
 Experiment No: 2
To Realization of logic functions with the help of universal gates NAND and
NOR Gate

Date:

Competency and Practical Skills: To develop digital circuit building and troubleshooting
skills

Relevant CO: CO1

Objectives: (a) To verify the truth table of Logic gates.

(b) To convert a logic function into a NOR and a NAND implementation.

Equipment/Instruments: TTL family ICs (7402 and 7400), LEDs, Wires, 5-volt DC supply,
Breadboard, Multimeter.

Theory:

Introduction
Logic gates are electronic circuits which perform logical functions on one or more inputs to produce
one output. There are seven logic gates. When all the input combinations of a logic gate are written
in a series and their corresponding outputs are written along them, then this input/ output
combination is called Truth Table.

1)NAND gate as Universal gate

A NAND gate is actually a combination of two logic gates i.e. AND gate followed by a NOT gate.
So, its output is the complement of the output of an AND gate. This gate can have minimum two
inputs. By using only NAND gates, we can realize all the logic functions: AND, OR, NOT, Ex-OR,
Ex-NOR, NOR. So, this gate is also called as universal gate.

1.1 NAND gate as NOT gate

Figure 1 NAND as a NOT gate

1.2 NAND gate as AND gate

A NAND gate produces the complement of an AND gate. So, if the output of a
NAND gate is inverted, the overall output will be that of an AND gate.
 Figure 2 NAND as an AND gate

1.3 NAND gate as an OR gate From De Morgan’s theorems:

(A.B)’ = A’ + B’
(A’.B’)’ = A’’ + B’’ = A + B
So, give the inverted inputs to a NAND gate to obtain OR operation at the output.

Figure 3 NAND as a OR gate

1.4 NAND gate as Ex-OR gate

The output of a two input Ex-OR gate is shown by: Y = A’B + AB’. This can be
achieved with the logic diagram shown on the left side.

Figure 4 NAND as an Ex-OR gate

 1.5 NAND gate as Ex-NOR gate
Ex-NOR gate is actually an Ex-OR gate followed by a NOT gate. So, when the output
of an Ex-OR gate is given to a NOT gate, the overall output is that of an Ex-NOR
gate.

Figure 5 NAND as an Ex-NOR gate

Procedure:

(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 14 & -ve to pin 7.
(c) Connect the NAND gates for any of the logic functions to be realized.
(d) Connect the inputs of the first stage to the logic sources and the output of the last gate to the
logic indicator.
(e) Apply various input combinations and observe the output for each one.
(f) Verify the truth table for each input/ output combination.
(g) Repeat the process for all logic functions.

2)NOR gate as Universal gate

2.1 NOR gates as OR gate

A NOR produces complement of OR gate. So, if the output of a NOR gate is inverted,
overall output will be that of an OR gate.

Y = ((A+B)’)’
Y = (A+B)

Figure 6 NOR as a OR gate

2.2 NOR gates as AND gate
From DeMorgan’s theorems:
(A+B)’ = A’B’
(A’+B’)’ = A’’B’’ = AB
So, give the inverted inputs to a NOR gate, obtain AND operation at output.

Figure 7 NOR as a AND gate

2.3 NOR gates as Ex-OR gate

Ex-OR gate is actually Ex-NOR gate followed by NOT gate. So, give the output of
Ex-NOR gate to a NOT gate, overall output is that of an Ex-OR gate.
Y = A’B+ AB’

Figure 8 NOR as an Ex-OR gate

2.4 NOR gates as Ex-NOR gate

The output of a two input Ex-NOR gate is shown by: Y = AB + A’B’. This can be
achieved with the logic diagram shown in the left side.
Y = AB + A’B’

Figure 9 NOR as an Ex-NOR gate.

Procedure:

(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 14 & -ve to pin 7.
(c) Connect the NOR gates for any of the logic functions to be realized.
(d) Connect the inputs of the first stage to logic sources and the output of the last gate to logic
indicator.
(e) Apply various input combinations and observe output for each one.
(f) Verify the truth table for each input/ output combination.
(g) Repeat the process for all logic functions.

Result :
NAND & NOR are verified as universal gates successfully.

PRECAUTIONS:
1) All connections should be according to the circuit diagram.
2) All connections should be right and tight.
3) Readings should be taken carefully.
4) Switch off the power supply after completing the Experiment.

Quiz:

1. Why universal gates are called universal?

2. Where are universal gates used?
3. What are the advantages of universal gate?

Suggested Reference: VLab

https://de-iitr.vlabs.ac.in/exp/realization-of-logic-functions/index.html

References used by the students: (Sufficient space to be provided)

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit.
5. Quiz answers and submission in time.
 Experiment No: 3
To Verify De-Morgan's laws
Date:

Competency and Practical Skills: To develop digital circuit building and troubleshooting
skills

Relevant CO: CO1

Objectives: To Verify De-Morgan's laws

Equipment/Instruments: IC numbers 7400, 7402, 7404, 7408, 7432, Breadboard, Connecting

Wires, 5-volt DC supply, Multimeter.

Theory:

De-Morgan's Laws:
Boolean algebra has postulates and identities. We can often use these laws to reduce expressions or
put expressions into a more desirable form. One of these laws is the De-Morgan's law. De-Morgan's
law has two conditions, or conversely, there are two laws called De-Morgan's Laws.

First Condition or First law:

The compliment of the product of two variables is equal to the sum of the compliment of each
variable. Thus, according to De-Morgan's laws or De-Morgan's theorem. If A and B are the two
variables or Boolean numbers. Then accordingly

Second Condition or Second law:

The compliment of the sum of two variables is equal to the product of the compliment of each
variable. Thus, according to De Morgan’s theorem if A and B are the two variables then

Logic Diagram:
First Condition:

Second Condition:

Procedure:
(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 14 & -ve to pin 7.
(c) Patch the left-hand side circuit for the first condition of De-Morgan's Law on the Digital
electronics trainer.
(d) Connect the inputs to the input switches and output to the LED and verify the truth table
for all the combinations.
(e) Similarly, patch the right-hand side circuit for the first condition of De-Morgan's Law on
the Digital electronics trainer. Connect the inputs to the input switches and output to the
LED and verify the truth table for all the combinations. Both the truth tables should be
similar.
(f) Repeat steps 1 and 2 for the second condition of De-Morgan's Law.

Truth table for the first condition:

Truth table for the Second condition:

Result:
De-morgan’s law was verified successfully.

PRECAUTIONS:
1) All connections should be according to the circuit diagram.
2) All connections should be right and tight.
3) Readings should be taken carefully.
4) Switch off the power supply after completing the Experiment

Quiz:

1. According to De-Morgan’s theorem, an inverted AND gate operation result is similar to which
type of logic gate operation?
2. Mention the applications of De-Morgan’s theorem.
3. Simplify the Boolean equation M = W’XY’ + WXY’ + XY’Z using Boolean identities and
theorems to show that M = XY’

Suggested Reference: VLab

https://de-iitr.vlabs.ac.in/exp/realization-of-logic-functions/index.html

References used by the students: (Sufficient space to be provided)

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit.
5. Quiz answers and submission in time.
 Experiment No: 4
To analyze the truth table of binary to gray and gray to binary converter

Date:

Competency and Practical Skills: To develop digital circuit building and troubleshooting
skills

Relevant CO: CO1 and CO2

Objectives: (a) To understand the operation of binary to gray and gray to binary conversion
(b) To use Boolean simplification methods to reduce the number of gates in the
design
(c) To develop digital circuit building and troubleshooting skills

Equipment/Instruments: TTL family ICs Ex-OR gate 7486, LEDs, Wires, 5-volt DC supply,
Bread Board, Multimeter.

Theory:

Binary Numbers are a default way to store numbers, but in many applications binary numbers are
difficult to use and a variation of binary numbers is needed. Gray code is an ordering of the binary
numeral system such that two successive values differ in only one bit (binary digit). Gray codes are
very useful in the normal sequence of binary numbers generated by the hardware that may cause an
error or ambiguity during the transition from one number to the next. So, the Gray code can
eliminate this problem easily since only one bit changes its value during any transition between two
numbers.

Gray code has the property that two successive numbers differ in only one bit. Because of this
property, gray code does the cycling through various states with minimal effort and used in K-maps,
error correction, communication etc.

In computer science, many a times we need to convert binary code to gray code and vice versa. This
conversion can be done by applying following rules:

1) Binary to Gray conversion:

1. The Most Significant Bit (MSB) of the Gray code is always equal to the MSB of the given binary
code.
2. Other bits of the output Gray code can be obtained by Ex-ORing the binary code bit at that index
and previous index.
3. There are four inputs and four outputs. The input variables are defined as B3, B2, B1, B0 and the
output variables are defined as G3, G2, G1, G0. From the truth table, combinational circuit is
designed. The logical expressions are defined as :
 Figure-1: Binary to Gray Code Converter Circuit

2) Gray to binary conversion:

1. The Most Significant Bit (MSB) of the binary code is always equal to the MSB of the
given binary number.

2. Other bits of the output binary code can be obtained by checking Gray code bit at that
index. If current Gray code bit is 0, then copy previous binary code bit, else copy invert of
previous binary code bit.

3. There are four inputs and four outputs. The input variable are defined as G3, G2, G1,
G0 and the output variables are defined as B3, B2, B1, B0. From the truth table,
combinational circuit is designed. The logical expressions are defined as :
 Figure-2: Gray to Binary Code Converter Circuit

Procedure:
(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 14 & -ve to pin 7.
(c) Apply different combinations of inputs to the input terminals.
(d) Note the output.
(e) The results should be in accordance with the truth table.

Observation table:
(1) Binary to Gray Code converter

Binary Code Gray Code

B3 B2 B1 B0 G3 G2 G1 G0
(2) Gray to Binary code converter

Gray Code Binary Code

G3 G2 G1 G0 B3 B2 B1 B0

Result:

PRECAUTIONS:
1) All connections should be according to the circuit diagram.
2) All connections should be right and tight.
3) Readings should be taken carefully.
4) Switch off the power supply after completing the Experiment.
Quiz:
1. How do you convert gray to binary and binary to gray?
2. What are the applications of binary to gray code converter?
3. Why is gray code used instead of binary?
4. Why is gray code called reflected code?

Suggested Reference: VLab

https://de-iitr.vlabs.ac.in/exp/binary-conversion/theory.html

References used by the students: (Sufficient space to be provided)

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit.
5. Quiz answers and submission in time.
 Experiment No: 5
To design and verify operation of Half adder and Full adder

Date:

Competency and Practical Skills: To develop digital circuit building and troubleshooting
skills

Relevant CO: CO2

Objectives: (a) To understand the operation of half-adders

(b) To understand the operation of full-adders
(c) To use Boolean simplification methods to reduce the number of gates in the
design
(d) To develop digital circuit building and troubleshooting skills

Equipment/Instruments: TTL family ICs (7408,7432 and 7486), LEDs, Wires, 5-volt DC
supply, Breadboard, Multimeter.

Theory:
This experiment will examine a method to add two binary numbers. The technique uses two circuits,
a half-adder and a full adder, to accomplish the addition. When two (A and B) numbers (decimal,
binary or any other number base) are added, the result is a SUM (S) and possibly a CARRY (C).
The half-adder performs this function at the bit level with two inputs (Ax and Bx) and two outputs
(SUMx and CARRYx) where x is the bit number. The full-adder needs to be used when there is a
carry bit since the half-adder only has two inputs. The carry bit would be the third input.

1.1 Half adder

It is a logic circuit that adds two bits. It produces the output sum and carry. The Boolean equation
for sum and carry are,

If we assume A and B as the two bits whose addition is to be performed, a truth table for half adder
with A, B as inputs and Sum, Carry as outputs can be tabulated as follows:

Figure 1 Block diagram and truth table of Half adder

 Figure 2 Half adder circuit diagram
Procedure:
(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 14 & -ve to pin 7.
(c) Apply different combinations of inputs to the input terminals.
(d) Note the output for Half adder.
(e) The results should be in accordance with the truth table.

Observation table:

1.2 Full adder

It is a logic circuit that can add three bits. It produces the output sum and carry. The Boolean
equation for sum and carry are,
If we assume A, B and Cin as the three bits whose addition is to be performed, a truth table for a
Full adder with A, B and Cin as inputs and Sum, Carry as outputs can be tabulated as follows:

Figure 3 Block diagram and truth table of Full adder

Figure 4 Full adder circuit diagram

Procedure:
(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 14 & -ve to pin 7.
(c) Apply different combinations of inputs to the input terminals.
(d) Note the output for Full adder.
(e) The results should be in accordance with truth table.
Observation table:

Result:
The Half adder and Full adder circuits are verified.

PRECAUTIONS:
1) All connections should be according to the circuit diagram.
2) All connections should be right and tight.
3) Readings should be taken carefully.
4) Switch off the power supply after completing the Experiment.

Quiz:
1. Convert the logic diagrams of Half adder for S and Cout to a NAND logic.
2. Convert the logic diagrams of Full adder for S and Cout to a NAND logic.
3. What is the drawback of a half adder?
4. How many half adders will be required for Implementing a full adder? Draw the circuit
diagram.

Suggested Reference: VLab

https://de-iitr.vlabs.ac.in/exp/half-full-adder/

References used by the students: (Sufficient space to be provided)

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit.
5. Quiz answers and submission in time.
 Experiment No: 6
To design and verify operation of Half Subtractor and Full Subtractor.

Date:

Competency and Practical Skills: To develop digital circuit building and troubleshooting
skills

Relevant CO: CO2

Objectives: (a) To understand the operation of half-subtractor

(b) To understand the operation of full-subtractor
(c) To use Boolean simplification methods to reduce the number of gates in the
design

Equipment/Instruments: TTL family ICs NAND gates (IC 7400), XOR gates (IC 7486),
AND gates (IC 7408), NOT gates (IC 7404), connecting wires, LEDs, 5-volt DC supply,
Breadboard, Multimeter.

Theory:
(1) Half Subtractor:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two
inputs and two outputs. The outputs are difference and borrow. The difference can be
applied using X-OR Gate, borrow output can be implemented using an AND Gate and an
inverter.

Figure 1. Block diagram and truth table of Half subtractor

Figure 2 Half subtractor circuit diagram

Procedure:
(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 14 & -ve to pin 7.
(c) Apply different combinations of inputs to the input terminals.
(d) Note the output for Half subtractor.
(e) The results should be in accordance with truth table.

Observation table:

Inputs Theoretical outputs Experimental outputs

A B Difference Borrow Difference Borrow

(2) Full subtractor

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor,
the logic circuit should have three inputs and two outputs. The two half subtractors put together
gives a full subtractor. The first half subtractor will be C and A B. The output will be the difference
output of the full subtractor. The expression AB assembles the borrow output of the half subtractor
and the second term is the inverted difference output of the first X-OR.

Figure 3. Block diagram and truth table of Full subtractor

 Figure 4 Full subtractor circuit diagram

Procedure:
(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 14 & -ve to pin 7.
(c) Apply different combinations of inputs to the input terminals.
(d) Note the output for Full subtractor.
(e) The results should be in accordance with truth table.

Observation table:

Inputs Theoretical outputs Experimental outputs

A B Borrow Difference Borrow Difference Borrow
in

Result :
The Half subtractor and Full subtractor circuits are verified.

PRECAUTIONS:
1) All connections should be according to the circuit diagram.
2) All connections should be right and tight.
3) Readings should be taken carefully.
4) Switch off the power supply after completing the Experiment.
Quiz:
1. Convert the logic diagrams of Half subtractor for difference and borrow to a NAND logic.
2. Convert the logic diagrams of Full subtractor adder for difference and borrowout to a NAND
logic.
3. How many half subtractors will be required for Implementing a full subtractor? Draw circuit
diagram.

Suggested Reference: VLab

https://de-iitr.vlabs.ac.in/exp/half-full-subtractor/index.html

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit.
5. Quiz answers and submission in time.
 Experiment No: 7

To design and verify operation of 4-bit full adder using IC 7483.

Date:

Competency and Practical Skills: To develop digital circuit building and troubleshooting
skills

Relevant CO: CO2

Objectives: (a) To understand the operation of a 4-bit full adder

(b) To use Boolean simplification methods to reduce the number of gates in the
design

Equipment/Instruments: TTL family IC- 7483, LEDs, Wires, 5-volt DC supply, Breadboard,
Multimeter.

Theory:
An adder circuit for addition of two n bit binary numbers consists of n full adder Circuits. A 4-bit
adder adds two 4-bits numbers, A and B. In addition, a 4-bit adder will have another single-bit input which
is added to the two numbers called the carry-in (Cin) bit. The output of the 4-bit adder is a 4-bit sum (S)
and a carry-out (Cout) bit.

Pin Configuration:

Figure 1 Pin configuration of 4-bit adder 7483.

Here A1, A2, A3, A4 : First 4 bit input

B1, B2, B3, B4 : Second 4 bit input
S1, S2, S3, S4 : 4 bit output
CO : Carry input
C4 : Carry output
 Figure 2 Logic diagram of 7483 4-bit full adder

Procedure:
(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 14 & -ve to pin 7.
(c) Apply different combinations of inputs to the input terminals.
(d) Note the output for 4-bit full adder.

Observation table:
Input Output

Cin A4 A3 A2 A1 B4 B3 B2 B1 S1 S2 S3 S4 Cout

Result :

PRECAUTIONS:
1) All connections should be according to the circuit diagram.
2) All connections should be right and tight.
3) Readings should be taken carefully.
4) Switch off the power supply after completing the Experiment.
Quiz:
1. How four-bit adder can perform subtraction?
2. What is a parallel adder?
3. What are the applications of a 4-bit adder and subtractor?

Suggested Reference: VLab

https://dld-iitb.vlabs.ac.in/exp/binary-adder-implementation/index.html

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit.
5. Quiz answers and submission in time.
 Experiment No: 8

To design and verify operation of Encoder.

Date:

Competency and Practical Skills: To develop digital circuit building and troubleshooting
skills

Relevant CO: CO2

Objectives: (a) To understand the operation of an Encoder

(b) To use Boolean simplification methods to reduce the number of gates in the
design

Equipment/Instruments: 74LS147 Decimal to BCD encoder, pull up resistors, key pads,

LEDs, Wires, 5-volt DC supply, Breadboard, Multimeter.

Theory: An encoder is a digital circuit that performs the inverse of a decoder, the encoder has 2n
(or less) input lines and n output lines ,the output lines generate the binary code corresponding to
the input value.

Design Decimal to BCD Encoder

Encoders are used to generate a coded output from a single active numeric input. In an encoder
circuit, normally all the lines are held high by the pull-up resistors connected to +5 V. To generate
a BCD output that is equivalent to a single selected decimal input, the switch corresponding to that
decimal is closed. (The switch acts as an active-low input.)

Figure 1 Simple Decimal to BCD Encoder

 Figure 2 Truth table of the above circuit

74LS147 decimal-to-4-bit BCD Priority Encoder IC

The 74LS147 provides the same basic function as the circuit shown in Fig. 1, basic Decimal to BCD
encoder but it has active-low outputs. This means that instead of getting an LLHH output when “3”
is selected, as in the previous encoder, you get HHLL. The two outputs represent the same thing
(“3”); one is expressed in positive true logic, and the other (the 74LS147) is expressed in negative
true logic. If you do not like negative true logic, you can slap inverters on the outputs of the 74LS147
to get positive true logic. The choice to use positive or negative true logic really depends on what
you are planning to drive.

Figure 3 Logic symbol and pin diagram of 74LS147

 Figure 4 Circuit diagram of Decimal to BCD encoder

Figure 5 Truth table of Decimal to BCD Encoder

Procedure:
(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 16 & -ve to pin 8.
(c) Apply different combinations of inputs to the input terminals.
(d) Note the output for Decimal to BCD Encoder.
Observation table:

Input Output BCD

Result :

PRECAUTIONS:
1) All connections should be according to the circuit diagram.
2) All connections should be right and tight.
3) Readings should be taken carefully.
4) Switch off the power supply after completing the Experiment.

Quiz:
1. What is a priority encoder circuit, and how does it differ from a regular encoder?
2. Differentiate Encoder and decoder.

Suggested Reference: VLab

https://de-iitr.vlabs.ac.in/exp/decoder-demultiplexer-encoder/index.html

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit.
5. Quiz answers and submission in time.
 Experiment No: 9

To design and verify the operation of Decoder and to set up and test a 7-segment
static display system to display the numbers 0 to 9.

Date:

Competency and Practical Skills: To develop digital circuit building and troubleshooting
skills

Relevant CO: CO2

Objectives: (a) To understand the operation of Decoder.

(b) To learn about types of seven-segment display
(c) To use Boolean simplification methods to reduce the number of gates in the
design

Equipment/Instruments: IC7447, 7-Segment display (common anode), Patch chords, 5-volt

DC supply, Breadboard, Multimeter.

Theory:
A decoder is a combinational circuit that connects the binary information from ‘n’ input
lines to a maximum of 2n unique output lines. The IC 7447 is a BCD to 7-segment pattern converter.
The IC 7447 takes the Binary Coded Decimal (BCD) as the input and gives the relevant 7 segment
code as the output.

Figure 1. IC 7447 Pin diagram.

The Light Emitting Diode (LED) finds its place in many applications in these modern electronic
fields. One of them is the Seven Segment Display. Seven-segment displays contain the arrangement
of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead (Anode or Cathode).
The purpose of arranging it in that passion is that we can make any number out of that by switching
ON and OFF the particular LED’s. Here is the block diagram of the Seven Segment LED
arrangement.
 Figure 2 Seven segment display

The 7-segment display, also written as “seven segment display”, consists of seven LEDs (hence its
name) arranged in a rectangular fashion as shown. Each of the seven LEDs is called a segment
because when illuminated, the segment forms a part of the numerical digit (both Decimal and Hex)
to be displayed.

An additional 8th LED is sometimes used within the same package thus allowing the indication of
a decimal point, (DP). When two or more 7-segment displays are connected together, numbers
greater than ten can be displayed.

Each of the seven LEDs in the display is given a positional segment with one of its connection pins
being brought straight out of the rectangular plastic package. These individually LED pins are
labelled from a through to g representing each individual LED. The other LED pins are connected
together and wired to form a common pin.

So, by forward biasing the appropriate pins of the LED segments in a particular order, some
segments will be light and the others will be dark allowing the desired character pattern of the
number to be generated on the display. This then allows us to display each of the ten decimal digits
0 to 9 on the same 7-segment display.

The displays common pin is generally used to identify which type of 7-segment display it is. As
each LED has two connecting pins, one called the “Anode” and the other called the “Cathode”,
there are therefore two types of LED 7-segment display called: Common Cathode (CC) and
Common Anode (CA).

The difference between the two displays, as their name suggests, is that the common cathode has
all the cathodes of the 7-segments connected directly together and the common anode has all the
anodes of the 7-segments connected together and is illuminated as follows.

1. The Common Cathode (CC) – In the common cathode display, all the cathode connections of the
LED segments are joined together to logic “0” or ground. The individual segments are illuminated
by the application of a “HIGH”, or logic “1” signal via a current limiting resistor to forward bias
the individual Anode terminals (a-g).
Common Cathode Configuration

2. The Common Anode (CA) – In the common anode display, all the anode connections of the
LED segments are joined together to logic “1”. The individual segments are illuminated by
applying a ground, logic “0” or “LOW” signal via a suitable current limiting resistor to the
Cathode of the particular segment (a-g).

Common Anode Configuration

BCD to Seven segment decoder display

Figure 3 BCD to seven segment display circuit diagram

Procedure:

(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 16 & -ve to pin 8.
(c) Apply different combinations of inputs to the input terminals.
(d) Note the output logic levels from 7447 IC to seven segment display.
(d) Note the output of the seven segment display.

Observation Table:
BCD inputs Output logic levels from 7447 to 7 Decimal
segments number
display
D C B A a b c d e f g

Quiz:

1. How can a 3 to 8 decoder be obtained using a 2 to 4 decoder? Draw the circuit diagram.
2. How to make a 4 to 16 decoder using a 3 to 8 decoder? Draw the circuit diagram.

Suggested Reference: VLab

https://de-iitr.vlabs.ac.in/exp/decoder-demultiplexer-encoder/index.html

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit..
5. Quiz answers and submission in time.
 Experiment No: 10

To design and implementation of 2-Bit Magnitude Comparator using logic gates

and 4-Bit Magnitude Comparator using IC 7485

Date:

Competency and Practical Skills: To develop digital circuit building and troubleshooting
skills

Relevant CO: CO2

Objectives: (a) To understand the operation of a 2-bit magnitude comparator

(b) To understand the operation of a 4-bit magnitude comparator
(c) To use Boolean simplification methods to reduce the number of gates in the
design

Equipment/Instruments: TTL family ICs (7408,7406,7432, and 74266), IC 7485, LEDs,

Wires, 5-volt DC supply, Breadboard, Multimeter.

Theory:
1) 2-Bit Magnitude Comparator:

A comparator used to compare two binary numbers, each of two bits, is called a 2-bit
magnitude comparator. It consists of four inputs and three outputs to generate less than,
equal to and greater than between two binary numbers.

The truth table for a 2-bit comparator is given below:

Figure-1: Truth Table of 2-Bit Comparator

 From the above truth table logical expressions for each output can be expressed as follows:

A > B : A1B1’ + A0B1’B0’ + A1A0B0’

A = B : A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’
: A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)
: (A0B0 + A0’B0’) (A1B1 + A1’B1’)
: (A0 Ex-Nor B0) (A1 Ex-Nor B1)
A < B : A1’B1 + A0’B1B0 + A1’A0’B0

By using these Boolean expressions, we can implement a logic circuit for this comparator
as given below:

Figure 2: Logic Circuit of 2-Bit Comparator

Procedure:

(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 14 & -ve to pin 7.
(c) Apply different combinations of inputs to the input terminals.
(d) Note the output for the 2-bit magnitude comparator.

Observation table:

Input Output
A1 A0 B1 B0 A>B A=B A<B
2) 4-bit magnitude Comparator:
A comparator used to compare two 4-bit words. The two 4-bit numbers are word A: A3 A2 A1 A0,
and word B: B3 B2 B1 B0, So the circuit has 8 inputs and 3 binary outputs: A>B, A=B and A<B.

Figure 3 Block diagram of 4-bit magnitude comparator.

Figure 4 Pin diagram of 7485 4-bit magnitude comparator.

Figure 3 and 4 show the block diagram and the pin configuration of IC 7485 for 4-bit magnitude
comparator. Three inputs are available for cascading comparators.

This comparator generates an output of 1 at one of the three comparison outputs such that:
• If word A is bigger than word B; A>B output is “1”,
• If word A is smaller than word B; A<B output is “1”,
• If word A is equal to word B; A=B output is “1”.

The two 4-bit numbers are A = A3 A2 A1 A0 and B3 B2 B1 B0 where A3 and B3 are the most
significant bits.

It compares each of these bits in one number with bits in that of other number and produces one of
the following outputs as A = B, A < B and A>B. The output logic statements of this converter are

• If A3 = 1 and B3 = 0, then A is greater than B (A>B). Or

• If A3 and B3 are equal, and if A2 = 1 and B2 = 0, then A > B. Or
• If A3 and B3 are equal & A2 and B2 are equal, and if A1 = 1, and B1 = 0, then A>B. Or
• If A3 and B3 are equal, A2 and B2 are equal and A1 and B1 are equal, and if A0 = 1 and
B0 = 0, then A > B.
From the above statements, the output A > B logic expression can be written as
The equal output is produced when all the individual bits of one number exactly coincide with the
corresponding bits of another number. Then the logical expression for A=B output can be written
as

E = (A3 Ex-NOR B3) (A2 Ex-NOR B2) (A1 Ex-NOR B1) (A0 Ex-NOR B0)

From the above output Boolean expressions, the logic circuit for this comparator can be
implemented by using logic gates as given below. In this the four outputs from the Ex-NOR gates
are applied to the AND gate to give the binary variable E or A = B. The other two outputs also use
Ex-NOR outputs to generate the Boolean functions as shown in the figure.

Figure 5. 4-bit Magnitude comparator

Truth Table of 4-bit Magnitude comparator

Procedure:

(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 16 & -ve to pin 8.
(c) Apply different combinations of inputs to the input terminals.
(d) Note the output for the 4-bit magnitude comparator.

Observation table:

Input Output

A3 A2 A1 A0 B3 B2 B1 B0 A>B A=B A<B

Result :

PRECAUTIONS:
1) All connections should be according to the circuit diagram.
2) All connections should be right and tight.
3) Readings should be taken carefully.
4) Switch off the power supply after completing the Experiment

Quiz:
1. Derive the Boolean expressions of 4-bit comparator. Draw the logic diagram for this
comparator.
2. Design an 8-bit comparator using two chips of IC 7485.

Suggested Reference: VLab

https://de-iitr.vlabs.ac.in/exp/comparator-using-logic-gates/theory.html

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit.
5. Quiz answers and submission in time.
 Experiment No: 11
Implementation of 4 X 1 Multiplexer using Logic gates and study of IC74151- 8
to 1 Multiplexer.

Date:

Competency and Practical Skills: To develop digital circuit building and troubleshooting
skills

Relevant CO: CO2

Objectives: (a) To understand the operation of 4 x 1 Multiplexer.

(b) To understand the operation of 8 x 1 Multiplexer.
(c) To use Boolean simplification methods to reduce the number of gates in the
design.

Equipment/Instruments: TTL family ICs (7408,7406,7432), IC 74151, LEDs, Wires , 5-volt

DC supply, Breadboard, Multimeter.

Theory:
The function of a multiplexer is to select the input of any ‘n’ input lines and feed that to one output
line. The function of a de-multiplexer is to inverse the function of the multiplexer. The shortcut
forms of multiplexer and de-multiplexers are mux and demux. Some multiplexers perform both
multiplexing and de-multiplexing operations.

Figure 1 Block diagram of Multiplexer and De-multiplexer

Multiplexer is a device that has multiple inputs and a single line output. The select lines determine
which input is connected to the output, and also to increase the amount of data that can be sent
over a network within certain time. It is also called a data selector.
Multiplexers are classified into four types:

a) 2-1 multiplexer (1 select line)

b) 4-1 multiplexer (2 select lines)

c) 8-1 multiplexer (3 select lines)

d) 16-1 multiplexer (4 select lines)

1.1) 4x1 Multiplexer

4x1 Multiplexer has four data inputs D0, D1, D2 & D3, two selection lines S0 & S1 and one output
Y. The block diagram of 4x1 Multiplexer is shown in the following figure. One of these 4 inputs
will be connected to the output based on the combination of inputs present at these two selection
lines. The Truth table of 4x1 Multiplexer is shown below.

Figure-2: Block diagram of 4x1 Multiplexer

Figure-3: Truth table of 4x1 Multiplexer

 Figure-4: Circuit diagram of 4x1 Multiplexer

Procedure:

(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 14 & -ve to pin 7.
(c) Apply different combinations of inputs to the input terminals.
(d) Note the output for 4 x 1 Multiplexer.

1.2) 8 X 1 Multiplexer

The 74151 IC is an 8-input, 1-output multiplexer that can be used to select one of the eight different
inputs and pass it to the output. It has a number of control inputs, including a "select" input and
three "address" inputs, which are used to specify the input that should be selected.

Figure 5 74151 IC DIP Diagram (Top view)

Figure 6 Logic diagram of 74151

Truth Table of 8 to 1 Multiplexer.

Result :

PRECAUTIONS:
1) All connections should be according to the circuit diagram.
2) All connections should be right and tight.
3) Readings should be taken carefully.
4) Switch off the power supply after completing the Experiment

Quiz:
1. What are the applications of Multiplexers?
2. Why MUX is called as a Data selector?
3. How many 4:1 MUX are required to implement 8:1 MUX?
4. How many control lines are required to implement 32:1 MUX?

Suggested Reference: VLab

https://de-iitr.vlabs.ac.in/exp/multiplexer-demultiplexer/theory.html

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit.
5. Quiz answers and submission in time.
 Experiment No: 12
Implementation of 1X4 Demultiplexer using Logic gates and study of IC 74154.

Date:

Competency and Practical Skills: To develop digital circuit building and troubleshooting
skills

Relevant CO: CO1

Objectives: (a) To understand the operation of 1 x 4 De-Multiplexer.

(b) To understand the operation of 1 x 8 De-Multiplexer.
(c) To use Boolean simplification methods to reduce the number of gates in the
design.

Equipment/Instruments: TTL family ICs (7408,7406) IC 74154, LEDs, Wires, 5-volt DC

supply, Breadboard, Multimeter.

Theory:
1.1) 1 to 4 Demultiplexer
A Demultiplexer performs the reverse operation of a Multiplexer. It accepts a single input and
distributes it over several outputs. The SELECT input code determines to which output the data
input will be transmitted. The Demultiplexer becomes enabled when the strobe signal is active
LOW. This circuit can also be used as binary-to-decimal decoder with binary inputs applied at the
select input lines and the output will be obtained on the corresponding line. These devices are
available as 2-line-to-4-line decoder, 3-line-to-8-line decoder, 4-line-to-16-line decoder. The output
of these devices is active LOW. Also, there is an active low enable/data input terminal available.
The figure below shows the block diagram of a Demultiplexer.

1x4 De-Multiplexer has one input Data(D), two selection lines, S0 & S1 and four outputs Y0, Y1,
Y2 & Y3. The block diagram of 1x4 De-Multiplexer is shown in the following figure.

Figure1 Block diagram of 1 to 4 Demultiplexer

 Figure 2 Truth table of 1x4 De-Multiplexer

Figure 3 Circuit diagram of 1 to 4 Demultiplexer

Procedure:

(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 14 & -ve to pin 7.
(c) Apply different combinations of inputs to the input terminals.
(d) Note the output for 1 x 4 Multiplexer.

1.2) 1 X 8 De-Multiplexer

A 1 to 8 demultiplexer consists of one input line, 8 output lines and 3 select lines. Let the input be
D, S0, S1 and S2 are the three select lines and the eight outputs are from Y0 to Y7. It is also called
as 3 to 8 demux because of the 3 selection lines. Below is the block diagram of 1 to 8 demux.
 Figure 4 Pin diagram of 74138

Figure 5 Circuit diagram of 1 to 8 Demultiplexer

Truth Table

Result :

PRECAUTIONS:
1) All connections should be according to the circuit diagram.
2) All connections should be right and tight.
3) Readings should be taken carefully.
4) Switch off the power supply after completing the Experiment

Quiz:
1. What are the applications of De-Multiplexers?
2. What is the difference between decoder and demultiplexer?
3. Differentiate between the functions of Multiplexer and Demultiplexer.

Suggested Reference: VLab

https://de-iitr.vlabs.ac.in/exp/multiplexer-demultiplexer/theory.html

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit.
5. Quiz answers and submission in time.
 Experiment No: 13
To verify the truth table of RS, JK, T and D flip-flops using NAND & NOR gates
ICs.

Date:

Competency and Practical Skills: To develop digital circuit building and troubleshooting
skills

Relevant CO: CO3

Objectives: (a) Understand how flip-flops can be developed from basic logic gates
(b) Understand the behavior of S-R and J-K flip-flops
(c) Understand how a flip-flop can serve as a storage element in a simple
controlled circuit

Equipment/Instruments: TTL family ICs (7408,7406,7432,7400,7402,7411), LEDs, Wires,

5-volt DC supply, Breadboard, Multimeter.

Theory:
Introduction

A flip-flop is an electronic circuit with two stable states that can be used to store binary data. The
stored data can be changed by applying varying inputs. Flip-flops and latches are fundamental
building blocks of digital electronics systems used in computers, communications, and many other
types of systems.

(1) R-S flip-flop

(2) D flip-flop
(3) J-K flip-flop
(4) T flip-flop

1) RS flip-flop
The basic NAND gate RS flip-flop circuit is used to store the data and thus provides feedback from
both of its outputs back to its inputs. The RS flip-flop has three inputs, SET, RESET and clock
pulse.
 Figure 1 (a) Logic diagram and (b) Truth table of SR Flip-flop.

Figure 2 Characteristics table of SR flip-flop

2) D flip-flop
A D flip-flop has a single data input. This type of flip-flop is obtained from the SR flip-flop by
connecting the R input through an inverter, and the S input is connected directly to data input. The
modified clocked SR flip-flop is known as D-flip-flop and is shown below. From the truth table of
SR flip-flop, we see that the output of the SR flip-flop is in an unpredictable state when the inputs
are the same and high. In many practical applications, these input conditions are not required. These
input conditions can be avoided by making them complement of each other.
 Figure 3 Circuit diagram of D flip-flop

Figure 4 Characteristics table of D flip-flop.

3) J-K flip-flop
In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RS flip-flop circuit may be
re-joined if both inputs are 1. Then also the outputs are complement of each other as shown in the
characteristics table below.

Figure 5 Circuit diagram of J K Flip-flop.

 Figure 6 Characteristics table of JK flip-flop

4) T flip-flop
T flip-flop is known as toggle flip-flop. The T flip-flop is a modification of the J-K flip-flop. Both
the JK inputs of the JK flip – flop are held at logic 1 and the clock signal continues to change as
shown in the table below.

Figure 7 Circuit diagram of T flip-flop

Figure 8 Characteristics table of T flip-flop

Procedure:

(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 14 & -ve to pin 7.
(c) Apply different combinations of inputs to the input terminals.
(d) Note the output for all the flip flops.

Result :

PRECAUTIONS:
1) All connections should be according to the circuit diagram.
2) All connections should be right and tight.
3) Readings should be taken carefully.
4) Switch off the power supply after completing the Experiment

Quiz:
1. What is the advantage of JK flip-flop over RS flip-flop?
2. What is the difference between the S-R latch and the D latch?
3. What is the difference between a synchronous and an asynchronous input?
4. Describe what the inputs need to be to place the J-K flip-flop in toggle mode.

Suggested Reference: VLab

https://de-iitr.vlabs.ac.in/exp/truth-tables-flip-flops/index.html

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit.
5. Quiz answers and submission in time.
 Experiment No: 14
To analyze the circuit and truth table of a 4-bit Bidirectional Universal shift
register by using IC 74194.

Date:

Competency and Practical Skills:

To develop digital circuit building and troubleshooting skills

Relevant CO: CO4

Objectives: (a) To construct and test the 74194 TTL IC register wired as a serial-load
shift right register.
(b) To construct and test the 74194 TTL IC register wired as a serial-load
shift left register.
(c) To construct and test the 74194 TTL IC register wired as a parallel-load
shift register.

Equipment/Instruments: TTL IC 74194, LEDs, Wires, 5-volt DC supply, Bread Board,

Multimeter.

Theory:
A register capable of shifting in one direction only is called unidirectional shift register. One that
can shift in both directions is known as a bidirectional shift register. If the register has both shifts
and parallel‐load capabilities, it is referred to as a universal shift register.

Figure 1 Four‐bit universal shift register

The circuit consists of four D flip‐flops and four multiplexers. The four multiplexers have two
common selection inputs s1 and s0. Input 0 in each multiplexer is selected when s1s0= 00, input 1
is selected when s1s0=01, and similarly for the other two inputs. The selection inputs control the
mode of operation of the register according to the function entries mentioned in table 1. When
s1s0=00, the present value of the register is applied to the D inputs of the flip flops. This condition
forms a path from the output of each flip flop into the input of the same flip flops so that the output
recirculates to the input in this mode of operation. The next clock edge transfers into each flip flop
the binary value it held previously, and no change of state occurs.

Table 1

When s1s0= 01, terminal 1 of the multiplexer inputs has a path to the D inputs of the flip flops. This
causes a shift right operation, with the serial input transferred into flip flop A3. When s1s0=10, a
shift left operation results, with the other serial input going into flip flop A0. Finally, when s1s0=11,
the binary information on the parallel input lines is transferred into the register simultaneously
during the next clock edge.

Figure 2 Connection diagram of 74194

Figure 3 Logic diagram of IC 74194 (Refer https://www.electronicscomp.com/datasheet/74ls194-
ic-datasheet.pdf)

Procedure:

(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 16 & -ve to pin 8.
(c) Apply different combinations of inputs to the input terminals.
(d) Note output shift left, shift right and parallel output.

Result :

PRECAUTIONS:
1) All connections should be according to the circuit diagram.
2) All connections should be right and tight.
3) Readings should be taken carefully.
4) Switch off the power supply after completing the Experiment

Quiz:
1. What are the 4 modes of shift register?
2. What are the 2 main functions of shift registers?
3. What is the application of shift register?

Suggested Reference: VLab

https://de-iitr.vlabs.ac.in/exp/4bit-sipo-shift-register/index.html

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit.
5. Quiz answers and submission in time.
 Experiment No: 15

Design and verify the BCD counter using IC7490.

Date:

Competency and Practical Skills: To develop digital circuit building and troubleshooting
skills

Relevant CO: CO4 and CO5

Objectives: (a) To understand the operation of an asynchronous counter

(b) To implement BCD counter using IC 7490
(c) To design and implement BCD counter using decoder and seven segment
display

Equipment/Instruments: TTL IC 7490, 7447, 7-segment display, current limiting resistors,

Wires, 5-volt DC supply, Breadboard, Multimeter.

Theory:
IC 7490: Ripple counter IC 7490 is a T.T.L M.S.I decade counter. It contains two counter circuits
mod-2 counter and mod-5 counter using four M-S J-K flip flops and an additional logic. Each of
these counter circuits has one asynchronous master set terminal MS and one asynchronous master
reset terminal MR. Both these controls are active high and override the clock input. Master set
terminal also overrides master reset terminal.

By activating the set terminal, counter gives output equal to its maximum count i.e. 1 for mod-2
counter output and 101 for mod-5 counter. By activating the reset terminal, the counter output is
equal to the initial count i.e. 0 for both the counters. Both the counters have separate negative edge
triggered clock inputs i.e. mod-2 counter clock input indicated as CP0 & mod-5 counter clock input
indicated as CP1. Mod -2 counter output Q0 can be connected to the clock input CP1 of the mod-
5 counter, whose outputs are Q3, Q2, Q1 respectively. The combined output of this cascaded
connection i.e. Q3,Q2, Q1,Q0 gives mod-10 or BCD counter operation.

BCD Counter State Diagram

Figure 1 BCD counter state diagram

A decade counter counts in a sequence of ten and then returns back to zero after the count of nine.
Obviously to count upto a binary value of nine, the counter must have at least four flip-flops within
its chain to represent each decimal digit as shown.
Then a decade counter has four flip-flops and 16 potential states, of which only 10 are used and if
we connected a series of counters together we could count to 100 or 1,000 or to whatever final count
number we choose.

The 74LS90 BCD Counter

The 74LS90 integrated circuit is basically a MOD-10 decade counter that produces a BCD output
code. The 74LS90 consists of four master-slave JK flip-flops internally connected to provide a
MOD-2 (count-to-2) counter and a MOD-5 (count-to-5) counter. The 74LS90 has one independent
toggle JK flip-flop driven by the CLK A input and three toggle JK flip-flops that form an
asynchronous counter driven by the CLK B input as shown.

Figure 2 Pin diagram of 74LS90

Figure 3 Internal diagram of 74LS90

The counter’s four outputs are designated by the letter symbol Q with a numeric subscript equal to
the binary weight of the corresponding bit in the BCD counter circuits code. For example, QA, QB,
QC and QD. The 74LS90 counting sequence is triggered on the negative going edge of the clock
signal, that is when the clock signal CLK goes from logic 1 (HIGH) to logic 0 (LOW).
The additional input pins R1 and R2 are counter “reset” pins while inputs S1 and S2 are “set” pins.
When connected to logic 1, the Reset inputs R1 and R2 reset the counter back to zero, 0 (0000), and
when the Set inputs S1 and S2 are connected to logic 1, they Set the counter to maximum, or 9
(1001) regardless of the actual count number or position.

The 74LS90 counter consists of a divide-by-2 counter and a divide-by-5 counter within the same
package. Then we can use either counter to produce a divide-by-2 frequency counter only, a divide-
by-5 frequency counter only or the two together to produce our desired divide-by-10 BCD counter.

With the four flip-flops making up the divide-by-5 counter section disabled, if a clock signal is
applied to input pin 14 (CLKA) and the output taken from pin 12 (QA), we can produce a standard
divide-by-2 binary counter for use in frequency dividing circuits as shown.

74LS90 Divide-by-2 Counter

Figure 4 74LS90 as a divide by 2 counter configuration

To produce a standard divide-by-5 counter, we can disable the first flip-flop above, and apply the
clock input signal directly to pin 1 (CLKB) with the output signal being taken from pin 11 (QD) as
shown.

74LS90 Divide-by-5 Counter

Figure 5 74LS90 as a divide by 5 counter configuration

Note that with this divide-by-5 counter configuration, the output waveform is not symmetrical but
has a 4:1 mark-space ratio. That is four input clock signals creates a LOW or logic “0” output and
the fifth input clock signal produces a HIGH or logic “1” output.

To produce a divide-by-10 BCD decade counter, both internal counter circuits are used giving a 2
times 5 divide-by value. Since the first output QA from flip-flop “A” is not internally connected to
the succeeding stages, the counter can be extended to form a 4-bit BCD counter by connecting this
QA output to the CLKB input as shown.

74LS90 Divide-by-10 Counter

 Figure 6 74LS90 as a divide by 10 counter configuration

74LS90 BCD Decade Counter

Figure 7 74LS90 BCD decade counter

Procedure:

(a) Fix the IC on the breadboard & connect it with the power supply (DC +5V and GND).
(b) Connect the +ve terminal of the supply to pin 5 & -ve to pin 10.
(c) Connect a pushbutton switch (SW1) to clock input CLKA, each time the pushbutton
switch is released the counter will count by one.
(d) Connect light emitting diodes (LED’s) to the output terminals, QA, QB, QC and QD as
shown
(e) Note the binary coded decimal count.
(f) Successive applications of the push-button switch, SW1 will increase the count up to nine,
1001. At the tenth application the outputs ABCD will reset back to zero to start a new
count sequence.
4-bit BCD Counter Circuit

Figure 8 4 bit BCD counter using 74LS90 and decoder driver 7447 and seven segment display

The 74LS47 display decoder receives the BCD code and generates the necessary signals to activate
the appropriate LED segments responsible for displaying the number of pulses applied. As the
74LS47 decoder is designed for driving a common-anode display, a LOW (logic-0) output will
illuminate an LED segment while a HIGH (logic-1) output will turn it “OFF”. For normal operation,
the LT (Lamp test), BI/RBO (Blanking Input/Ripple Blanking Output) and RBI (Ripple Blanking
Input) must all be open or connected to logic-1 (HIGH).

Note that while the 74LS47 has active LOW outputs and is designed to decode a common anode 7-
segment LED display, the 74LS48 decoder/driver IC is exactly the same except that it has active
HIGH outputs designed to decode a common cathode 7 segment display. So depending upon the
type of 7-segment LED display you have you may need a 74LS47 or a 74LS48 decoder IC.

The 74LS47 binary coded decimal inputs can be connected to the corresponding outputs of the
74LS90 BCD Counter to display the count sequence on the 7-segment display as shown each time
the push button SW1 is pressed. By changing the position of the push button and 1kΩ resistor, the
count can be made to change on the activation or release of the push button switch, SW1.

2-digit BCD Counter from 00 to 99

Figure 9 BCD counter for 2 digit count

Circuit shown in figure 8 is a simple 0 to 9 digital counter using a 74LS90 BCD Counter and a
74LS47 7-segment display driver. To count above 10 and produce a 2-digit base-ten counter and
display, we need to cascade two separate divide-by-ten counters together. A 2-digit BCD counter
would count in decimal from 00 to 99 (0000 0000 to 1001 1001) and then reset back to 00. Note
that although it will be a 2-digit counter, values representing Hexadecimal numbers from A through
F are not valid in this code.

Likewise, if we wanted to count from 0 up to 999 (0000 0000 0000 to 1001 1001 1001), then three
cascaded decade counters are required. In fact, multiple decade counters can be constructed simply
by cascading together individual BCD counter circuits, one for each decade as shown in figure 9.

Result:

PRECAUTIONS:
1) All connections should be according to the circuit diagram.
2) All connections should be right and tight.
3) Readings should be taken carefully.
4) Switch off the power supply after completing the Experiment

Quiz:
1. Draw the circuitry needed for a mod-8 counter.
2. How does the duty cycle change from the clock input for each FF?
3. What is the difference between synchronous counter and asynchronous counter?
4. What do you understand by state diagram?

Suggested Reference: VLab

https://de-iitr.vlabs.ac.in/exp/4bit-synchronous-asynchronous-counter/

References used by the students:

Rubric wise marks obtained:

Rubrics 1 2 3 4 5 Total
Marks

Rubrics:
1. Group work while performing experiment on Lab.
2. Understand the concept while performing experiment
3. Individual work done while connecting and taking results of circuit.
4. Ability to analyse the logic and connection of the given circuit.
5. Quiz answers and submission in time.
 Experiment No: 16

Simulation of Logic circuits using Multisim simulator

Date:

Competency and Practical Skills: To develop digital circuit using Multisim simulator

Relevant CO: CO1, CO2, CO3, CO4 and CO5

Objectives: Learning how to simulate digital logic circuits using Multisim software.

Equipment/Instruments: Computer and Multisim simulator tool or online Multisim live

online circuit simulator.

Theory:
Multisim is an industry-standard, best-in-class SPICE simulation environment. t is industry
standard SPICE simulation and circuit design software for analog, digital, and power electronics in
education and research. Multisim software integrates industry-standard SPICE simulation with an
interactive schematic environment to instantly visualize and analyze electronic circuit behaviour.

(1) Design and simulate Half and Full Adder circuit.

(2) Design and simulate 4-bit full adder circuit
(3) Design and simulate Multiplexer 8:1 circuit.

(4) Design and simulate De multiplexer 1:8 circuit.

(5) Design and simulate BCD to seven segment decoder.

(6) Design and simulate BCD to Decimal decoder.

(7) Design and simulate decade counter.