21050 PCI-to-PCI Bridge

Preliminary Data Sheet

Product Features
P

■ Complies fully with Revision 2.0 of the ■ Provides ISA-mode for I/O transaction
PCI Local Bus Specification. filtering
■ Supports two 32-bit PCI buses ■ Provides two programmable video graphics
■ Provides maximum clock frequency of 33 adapter (VGA) bits that support forwarding
megahertz of VGA memory and I/O addresses, or
forwarding of VGA palette I/O writes
■ Provides concurrent primary and secondary
bus operation ■ Provides master latency timers and target
wait timers, for each PCI interface, which
■ Conditionally forwards the following limit the amount of latency on either bus
transactions:
■ Provides concurrent resource lock
— Memory read and write transactions in operation
either direction
■ Propagates locks across the 21050
— I/O read and write transactions in either
■ Provides seven secondary PCI bus clock
direction outputs
— Configuration read and write ■ Enables the following central functions
transactions in the downstream direction through s_cfn_l input pin for secondary
— Configuration write transactions to bus:
special cycles in either direction — Programmable rotating arbitration
■ Supports memory transaction filtering function supporting up to six secondary
through two programmable memory bus masters
address regions-one prefetchable and one — Secondary PCI bus parking at the 21050
non-prefetchable
■ Provides pins for buffer empty status and
■ Supports read prefetching for memory read write posting control
transactions
■ Supports perr and serr signals with error
■ Provides up to eight dwords (32 bytes) of checking functionality
write posting for memory write transactions
■ Provides I/O transaction filtering through
one programmable memory I/O address
region

.Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.

Order Number: 278139-001

September 1998

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 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 21050 PCI-to-PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.

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 21050 PCI-to-PCI Bridge

Contents
1.0 Introduction........................................................................................................................ 1
1.1 Purpose ................................................................................................................ 1
1.2 Audience .............................................................................................................. 1
1.3 Manual Organization ............................................................................................ 1
1.4 General Description.............................................................................................. 2
1.5 Architecture Overview .......................................................................................... 4
2.0 21050 Pin Assignment ...................................................................................................... 5
2.1 Signal Types......................................................................................................... 6
2.2 Alphabetic 21050 Pin Assignment List ................................................................. 6
2.3 Numeric 21050 Pin Assignment List .................................................................... 9
3.0 Signal Description ........................................................................................................... 13
3.1 Primary PCI Bus Signals .................................................................................... 14
3.2 Secondary PCI Bus Signals ............................................................................... 15
3.3 Secondary Bus Arbiter Signals........................................................................... 17
3.4 Clock, Reset, and Miscellaneous Signals .......................................................... 17
4.0 Functional Description..................................................................................................... 19
4.1 PCI Bus Interfaces ............................................................................................. 19
4.2 Primary PCI Bus Interface.................................................................................. 19
4.2.1 Secondary PCI Bus Interface ................................................................ 19
4.3 PCI Address Phase ............................................................................................ 20
4.3.1 Linear Increment Address Mode ........................................................... 20
4.3.2 Address and Data Stepping .................................................................. 20
4.3.3 Dual Addressing .................................................................................... 20
4.4 Device Select (devsel) Generation..................................................................... 21
4.5 Transaction Forwarding...................................................................................... 21
4.5.1 Transaction Support .............................................................................. 22
4.5.2 Data Path .............................................................................................. 23
4.5.3 Write Transactions ................................................................................ 23
4.5.3.1 Non-Posted Write Transactions ............................................ 23
4.5.3.2 Use of Non-Posted Write Transactions................................. 24
4.5.3.3 Posted Write Transactions .................................................... 25
4.5.3.4 Use of Posted Write Transactions ........................................ 26
4.5.3.5 Write Boundaries .................................................................. 27
4.5.3.6 Conversion of Memory Write and Invalidate Transactions.... 27
4.5.3.7 Fast Back-to-Back Write Transactions.................................. 28
4.5.4 Read Transactions ................................................................................ 28
4.5.4.1 Non-Prefetchable Reads....................................................... 28
4.5.4.2 The Use of Non-Prefetchable Reads .................................... 30
4.5.4.3 Prefetchable Reads .............................................................. 30
4.5.4.4 The Use of Prefetchable Reads ............................................ 33
4.5.4.5 Read Boundaries .................................................................. 33
4.5.5 Configuration Transactions ................................................................... 34
4.5.5.1 Type 0 Configuration Transactions ....................................... 35
4.5.5.2 Type 1 Configuration Transactions ....................................... 35
4.5.5.3 Type 1 to Type 0 Conversion ................................................ 36

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 21050 PCI-to-PCI Bridge

4.5.5.4 Type 1 to Type 1 Forwarding ................................................ 37

4.5.5.5 Type 1 to Special Cycle Conversion ..................................... 38
4.5.6 Special Cycles....................................................................................... 39
4.5.7 Interrupt Acknowledge .......................................................................... 40
4.6 Transaction Termination .................................................................................... 40
4.6.1 Initiator Termination .............................................................................. 40
4.6.1.1 21050 as Target.................................................................... 40
4.6.1.2 21050 as Initiator .................................................................. 40
4.6.2 Target Termination................................................................................ 41
4.6.2.1 Target Termination Initiated by Target.................................. 42
4.6.2.2 Target Termination Initiated by 21050 .................................. 49
4.7 Address Decoding.............................................................................................. 49
4.7.1 Memory Address Decoding................................................................... 50
4.7.1.1 Memory Transaction Forwarding Based on Address
Ranges 50
4.7.1.2 Disabling a Memory Address Range .................................... 50
4.7.1.3 VGA Frame Buffer Support................................................... 50
4.7.1.4 Dual Transaction Addressing................................................ 50
4.7.2 I/O Address Decoding ........................................................................... 51
4.7.2.1 I/O Transaction Forwarding Based on Address Range ........ 51
4.7.2.2 Disabling the I/O Address Range.......................................... 51
4.7.2.3 ISA Mode .............................................................................. 51
4.7.3 VGA I/O Support ................................................................................... 52
4.7.3.1 VGA Mode ............................................................................ 53
4.7.3.2 VGA Palette Snooping .......................................................... 53
4.8 Latency............................................................................................................... 53
4.8.1 Master Latency Timer ........................................................................... 54
4.8.2 Target Wait Timer ................................................................................. 54
4.8.3 Burst Limit Counter ............................................................................... 54
4.9 Deadlock Avoidance .......................................................................................... 55
4.9.1 Read Operations ................................................................................... 55
4.9.2 Posted Write Operations ....................................................................... 55
4.9.3 Non-Posted Write Operations ............................................................... 55
4.10 Data Synchronization ......................................................................................... 56
4.11 Exclusive Access ............................................................................................... 56
4.11.1 Acquiring Exclusive Access................................................................... 56
4.11.2 Maintaining Exclusive Access ............................................................... 59
4.11.3 Ending Exclusive Access ...................................................................... 60
4.11.4 21050 as a Locked Target .................................................................... 61
4.12 Error Handling .................................................................................................... 62
4.12.1 Address Parity Errors ............................................................................ 62
4.12.2 Data Parity Errors on Initiator Bus......................................................... 62
4.12.3 Data Parity Errors on Target Bus .......................................................... 63
4.12.4 Other Errors .......................................................................................... 64
4.13 PCI Bus Arbitration............................................................................................. 65
4.13.1 Primary PCI Bus Arbitration .................................................................. 65
4.13.2 Secondary PCI Bus Arbitration ............................................................. 65
4.13.2.1 Secondary Bus Arbiter Protocol............................................ 66
4.13.2.2 Priority Schemes................................................................... 66
4.13.2.3 Request Mask Timer............................................................. 66
4.13.2.4 Secondary Bus Arbiter Disabled ........................................... 67

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 21050 PCI-to-PCI Bridge

4.13.2.5 Secondary Bus Parking ........................................................ 67

4.14 Clocks................................................................................................................. 67
4.15 Reset .................................................................................................................. 68
4.15.1 Primary Reset........................................................................................ 68
4.15.2 Secondary Reset................................................................................... 68
4.15.3 Chip Reset............................................................................................. 68
4.16 Buffer Control ..................................................................................................... 69
5.0 Configuration Register Description.................................................................................. 71
5.1 Predefined Header Space Register Description................................................. 72
5.1.1 Device ID and Vendor ID Register ........................................................ 72
5.1.2 Primary Status and Primary Command Register .................................. 72
5.1.3 Class Code/Programming Interface/Revision ID Register .................... 73
5.1.4 Primary Master Latency Timer/Cache Line Size/Header Type ............. 74
5.1.5 Reserved Registers (10-14 Hex)........................................................... 74
5.1.6 Primary Bus Number/Secondary Bus Number/Subordinate Bus
Number/Secondary Master Latency Timer Register ............................. 75
5.1.7 I/O Base Address/I/O Limit Address/Secondary Status Register .......... 76
5.1.8 Memory Base Address/Memory Limit Address Register ....................... 77
5.1.9 Prefetchable Memory Base Address/Prefetchable Memory Limit
Address Register................................................................................... 78
5.1.10 Reserved Registers (28-38 Hex)........................................................... 78
5.1.11 Interrupt Pin/Bridge Control Register .................................................... 79
5.2 Implementation-Specific 21050 Register Descriptions....................................... 80
5.2.1 Chip Control/Diagnostic Control/Burst Limit Counter/serr Disable
Register ................................................................................................. 80
5.2.2 Primary Target Wait Timer/Secondary Target Wait Timer Register ...... 81
5.2.3 Secondary Write Attempt Counter Register .......................................... 82
5.2.4 Primary Write Attempt Counter Register ............................................... 82
5.2.5 Reserved Registers (50h-FFh) .............................................................. 83
6.0 Diagnostics and Test Mechanisms.................................................................................. 85
6.1 Test Pins and Nand Tree Implementation.......................................................... 85
6.1.1 Diagnostic Control Register................................................................... 85
7.0 21050 Specifications ....................................................................................................... 87
7.1 Mechanical Specifications .................................................................................. 87
7.1.1 21050 Package ..................................................................................... 87
7.1.2 Absolute Maximum Ratings................................................................... 88
7.2 Electrical Specifications...................................................................................... 89
7.3 Interface Signal AC Electrical Specifications...................................................... 89
7.3.1 Interface Signal AC Timing Specifications ............................................ 90
7.3.2 Input Signal AC Timing Specifications .................................................. 91

Figures
1-1 21050 PCI-to-PCI Bridge on the System Board ................................................... 2
1-2 21050 PCI-to-PCI Bridge with Option Cards ........................................................ 3
1-3 21050 PCI-to-PCI Bridge Block Diagram ............................................................. 4
2-1 21050 Pinout Diagram.......................................................................................... 5
4-1 21050 Data Path ................................................................................................ 23

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 21050 PCI-to-PCI Bridge

4-2 I/O Write Timing ................................................................................................. 24

4-3 Simultaneous Upstream and Downstream Posted Memory Writes ................... 26
4-4 I/O Read Timing ................................................................................................. 29
4-5 Memory Read with Prefetching up to Cache Line Boundary ............................. 31
4-6 Memory Read multiple with Extra Prefetching ................................................... 32
4-7 Configuration Address Formats ......................................................................... 34
4-8 Type 0 Configuration Write Access and Configuration Read Access ................ 35
4-9 Type 1 to Type 0 Configuration Write and Read................................................ 37
4-10 Type 1 Configuration Write to Special Cycle Downstream ................................ 39
4-11 I/O Write with Target Abort................................................................................. 43
4-12 Downstream Memory Read with Target Abort ................................................... 44
4-13 Non-Posted I/O Write with Target Retry............................................................. 45
4-14 Memory Read with Target Retry ........................................................................ 46
4-15 Posted Write with Target Retry .......................................................................... 48
4-16 Downstream I/O Forwarding in ISA Mode.......................................................... 52
4-17 Memory Read with Lock Acquisition .................................................................. 57
4-18 Read with Lock Acquisition Attempt................................................................... 58
4-19 Downstream Memory Write with Lock Continuation .......................................... 59
4-20 Memory Write with End of Lock ......................................................................... 61
4-21 p_clk and s_clk Relative Timing......................................................................... 67
5-1 Configuration Space Map................................................................................... 71
7-1 Package Dimensions ......................................................................................... 88
7-2 p_clk and s_clk AC Timing................................................................................. 91
7-3 AC Timing Waveforms ....................................................................................... 92

Tables
1-1 Major Sub-Blocks of the 21050 ............................................................................ 4
2-2 Alphabetic Pin Assignment List (Sheet 1 of 4) ..................................................... 6
2-3 Numeric Pin Assignment List (Sheet 1 of 4) ........................................................ 9
3-4 Signal Types ...................................................................................................... 13
3-5 Primary OCI Bus Signals (Sheet 1 of 2)............................................................. 14
3-6 Secondary PCI Bus Signals (Sheet 1 of 2) ........................................................ 15
3-7 Secondary Bus Arbiter Signals .......................................................................... 17
3-8 Clock, Reset and Miscellaneous Signals (Sheet 1 of 2) .................................... 17
4-1 xcbe_l Commands ............................................................................................. 21
4-2 Transaction Forwarding and Filtering ................................................................ 22
4-3 Device Number to s_ad Signal Mapping............................................................ 36
4-4 Data Parity Errors Signals for Forwarded Transactions ..................................... 63
4-5 p_serr_l Assertion Conditions ............................................................................ 64
5-1 Device ID and Vendor ID Register ..................................................................... 72
5-2 Primary Status and Primary Command Register (Sheet 1 of 2) ........................ 72
5-3 Class Code/Programming Interface/Revision ID Register ................................. 73
5-4 Primary Master Latency Timer/Cache Line Size/Header Type Register............ 74
5-5 Reserved Registers (10–14 Hex) ....................................................................... 75
5-6 Primary Bus Number/Secondary Bus Number/Subordinate Bus
Number/Secondary Master Latency Timer ....................................................... 75
5-7 I/O Base Address/I/O Limit Address/Secondary Status Registers..................... 76
5-8 Memory Base Address/Memory Limit Address Register.................................... 77
5-9 Prefetchable Memory Base Addr./Prefetchable Memory Limit Addr. Register .. 78
5-10 Reserved Registers (28–38 Hex) ....................................................................... 79

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 21050 PCI-to-PCI Bridge

5-11 Interrupt Pin/Bridge Controller Register (Sheet 1 of 2)....................................... 79

5-12 Chip Control/Diagnostic Control/Burst Limit Counter/serr Disable Register ...... 80
5-13 Primary Target Wait Timer/Secondary Target Wait Timer Register................... 81
5-14 Secondary Write Attempt Counter Register ....................................................... 82
5-15 Primary Write Attempt Counter Register ............................................................ 82
5-16 Reserved Registers (50h – FFh) ........................................................................ 83
7-1 Lead Counts and Dimensional Attributes .......................................................... 87
7-2 Absolute Maximum Ratings................................................................................ 88
7-3 Functional Operating Range .............................................................................. 89
7-4 DC Specifications .............................................................................................. 89
7-5 Shared Signal Output Parameters ..................................................................... 89
7-6 p_clk and s_clk AC Timing ................................................................................. 90
7-7 Input Signal AC Timings..................................................................................... 91
7-8 xrst_l Timing Specifications................................................................................ 92

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 21050 PCI-to-PCI Bridge

1.0 Introduction

1.1 Purpose
This data sheet describes the 21050 PCI-to-PCI bridge chip (21050). The 21050 expands the
electrical capacity of all PCI systems. The 21050 allows motherboard designers to add more PCI
devices or more PCI option card slots than a single PCI bus can support. Option card designers can
use the 21050 to implement multiple device PCI option cards.

This document is not intended to describe the details of PCI protocol.

1.2 Audience
This document is for chip designers who need to expand the electrical capacity of their PCI bus
architectures.

1.3 Manual Organization

This datasheet consists of the following:
• Chapter 1.0, “Introduction” is an overview of the 21050.
• Chapter 2.0, “21050 Pin Assignment” lists the 21050 pin assignment in alphabetic and
numeric order.
• Chapter 3.0, “Signal Description” provides a description of pin signals.
• Chapter 4.0, “Functional Description” describes chip functions, including bus interfaces,
transaction types, transaction termination, address decoding, arbitration, and other functions.
• Chapter 5.0, “Configuration Register Description” provides programmer reference
information about configuration space registers.
• Chapter 6.0, “Diagnostics and Test Mechanisms” provides diagnostics information.
• Chapter 7.0, “21050 Specifications” lists the mechanical and electrical characteristics of the
chip.

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 21050 PCI-to-PCI Bridge

1.4 General Description

The 21050 has two PCI interfaces. The primary PCI interface connects directly to the PCI bus
closest to the host CPU. The secondary PCI interface creates a new and independent PCI bus. The
primary function of the bridge is to allow transactions to occur between a master on one PCI bus
and a target on the other PCI bus.

The 21050 also allows the two PCI buses to operate independently. A master and a target located
on the same PCI bus can communicate with each other even if the other PCI bus is busy. As a
result, the 21050 can isolate traffic between devices on one PCI bus from devices on other PCI
buses. This is a major benefit to system performance in some applications such as multimedia.

The 21050 can extend a system beyond the electrical loading limits of a single PCI bus. Each new
PCI bus created by the addition of a 21050 provides support for additional electrical loads.
Motherboard designers can use the 21050 to add more PCI devices or PCI option card connectors
to the motherboard. Figure 1-1 shows the 21050 on the system board.
Figure 1-1. 21050 PCI-to-PCI Bridge on the System Board

PCI Option Slots

CPU

Memory
and
Cache 21050

32-Bit PCI Bus

Core
Graphics
Logic PCI Option Slots

ISA or EISA
Option Slots
PCI Bus
21050

32-Bit PCI Bus

ISA or ISA or EISA Bus

SCSI LAN EISA
Bridge

Support
Chip

Floppy
Keyboard
Serial
Parallel
Toy
Audio
A4912-01

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 21050 PCI-to-PCI Bridge

Option card designers can use a 21050 to implement multiple device PCI option cards. Without a
21050, you can attach only one PCI device to the PCI option connector (the PCI Local Bus
Specification, Revision 2.1 restricts PCI option cards to a single connection per PCI signal in the
option card connector). In this application, the 21050 creates an independent PCI bus on the option
card to which many devices can be attached.

Figure 1-2 shows the 21050 with option cards.

Figure 1-2. 21050 PCI-to-PCI Bridge with Option Cards

LAN LAN LAN LAN

Chip Chip Chip Chip

21050
PCI Bus

PCI Bus

A4913-01

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 21050 PCI-to-PCI Bridge

1.5 Architecture Overview

Figure 1-3 shows the major functions of the 21050, and Table 1-1 describes the major sub-blocks.
The 21050 is packaged in a 208-pin plastic quad flat-pack.
Figure 1-3. 21050 PCI-to-PCI Bridge Block Diagram

Primary Secondary
Control Control

Primary Target/ Secondary Target/

Secondary Master Control Primary Master Control
(PSM) (SPM)

Secondary to Primary Data Path (SPD)

Primary Secondary
Data Path Data Path

Primary to Secondary Data Path (PSD)

Secondary
Configuration Registers (REG) Arbitration
(ARB)

Buffer Clocks and s_req_l<5:0>

Control Pins Diagnostic s_gnt_l<5:0> LJ-03239.AI4

Table 1-1. Major Sub-Blocks of the 21050

Block Description

Machine and control logic for all transactions initiated on the primary interface, whether the
PSM
transaction is intended for the 21050 itself or a target on the secondary side of the 21050.
Machine and control logic for all transactions initiated on the secondary interface. All such
SPM transactions are intended for a target on the primary interface, since 21050 registers are not
accessible from the secondary interface.
Data path for data received on the secondary interface and driven on the primary interface. Used
SPD
for writes initiated on the secondary PCI bus or reads initiated on the primary PCI bus.
Data path for data received on the primary interface and driven on the secondary interface. Used
PSD
for writes initiated on the primary PCI bus or reads initiated on the secondary PCI bus.
REG Configuration registers and corresponding control logic. Accessible from the primary interface only.
Logic for secondary bus arbitration. Receives s_req_l[5:0], as well as the PPB secondary bus
ARB
request, and drives one of the s_gnt_l[5:0] lines or the PPB secondary bus grant.

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 21050 PCI-to-PCI Bridge

2.0 21050 Pin Assignment

The 21050 is divided into three main functions:

• Primary PCI bus interface that interacts with the bus closest to the CPU
• Secondary PCI bus interface that interacts with the bus that is farther from the CPU
• Power supply and miscellaneous functions
Figure 2-1 shows the 21050 signals, and the 21050 pin assignments are listed in alphabetic and
numeric order at the end of this chapter.
Figure 2-1. 21050 Pinout Diagram

p_cbe_l<0>
s_cbe_l<1>

s_cbe_l<0>

p_ad<00>
p_ad<01>
p_ad<02>

p_ad<03>

p_ad<04>

p_ad<05>

p_ad<06>
p_ad<07>

p_ad<08>

p_ad<09>

p_ad<10>
p_ad<11>
p_ad<12>

p_ad<13>
p_ad<14>
s_ad<15>

s_ad<14>
s_ad<13>

s_ad<12>
s_ad<11>
s_ad<10>

s_ad<09>
s_ad<08>

s_ad<07>
s_ad<06>

s_ad<05>

s_ad<04>
s_ad<03>

s_ad<02>
s_ad<01>
s_ad<00>
vdd

vdd

vdd

vdd

vdd

vdd

vdd
vss

vss

vss

vss

vss

vss

vss

vss
nc

nc

nc
208

205

200

195

190

185

180

175

170

165

160
nc 1 p_ad<15>
s_par 155 nc
vdd p_cbe_l<1>
s_serr_l p_par
s_perr_l 5 vss
s_lock_l p_serr_l
vss 150 p_perr_l
s_stop_l vss
s_devsel_l p_lock_l
vdd 10 vss
s_trdy_l p_stop_l
s_irdy_l 145 p_devsel_l
s_frame_l vdd
vss p_trdy_l
s_cbe_l<2> 15 p_irdy_l
s_ad<16> p_frame_l
s_ad<17> 140 vss
vdd p_cbe_l<2>
s_ad<18> p_ad<16>
vdd 20 nc
s_ad<19> p_ad<17>
s_ad<20> 135 vdd
vss p_ad<18>
s_ad<21>

s_ad<22>
nc 25 21040 p_ad<19>
vss
p_ad<20>
vdd 130 p_ad<21>
s_ad<23> p_ad<22>
s_cbe_l<3>
s_ad<24>
vss
30 DC287 vss
p_ad<23>
nc
s_ad<25> 125 p_idsel
vss vdd
s_ad<26> p_cbe_l<3>
s_ad<27> 35 p_ad<24>
vss vdd
s_ad<28> 120 p_ad<25>
s_ad<29> p_ad<26>
vdd vss
s_ad<30> 40 p_ad<27>
nc p_ad<28>
s_ad<31> 115 p_ad<29>
vss vdd
s_gnt_l<5> p_ad<30>
s_gnt_l<4> 45 p_ad<31>
vdd p_req_l
s_gnt_l<3> 110 p_gnt_l
s_gnt_l<2> vss
s_gnt_l<1> p_rst_l
vss 50 nc
s_gnt_l<0> nc
s_cfn_l 105 nc
100
55

90

95
60

65

80

85
70

75
vdd
vdd
vss
s_rst_l

vdd

vdd

vdd

vdd

vdd
s_req_l<0>
s_req_l<1>
s_req_l<2>
s_req_l<3>
s_req_l<4>
s_req_l<5>

vss

vss

vss

vss

vss

vss

vss
nc
nc
nc

nc
nc
nc
nc

s_dispst_l

nc
nc
nc
s_clk_o<0>

s_clk_o<1>

s_clk_o<2>

s_clk_o<3>

s_clk_o<4>

s_clk_o<5>

s_clk_o<6>

s_bufne_l

go_z
s_clk

p_clk

nand_out

nc
nc
nc
nc
nc
nc
nc

LJ-03383.AI4

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 21050 PCI-to-PCI Bridge

2.1 Signal Types

The following table defines the 21050 signal types referred to in this chapter.

Signal Type Definition

I Standard input only.

O Standard output only.
ts Tristate bidirectional.
Sustained tristate. Active low signal must be pulled high for one cycle when
sts
deasserting.
od Standard open drain.
P Power or ground.

2.2 Alphabetic 21050 Pin Assignment List

Table 2-2 lists the 21050 pins in alphabetic order.

Table 2-2. Alphabetic Pin Assignment List (Sheet 1 of 4)

Pin1 Pin Number Type Pin1 Pin Number Type

go_z 93 I nc 104 --
nand_out 92 O nc 105 --
nc 1 -- nc 106 --
nc 25 -- nc 107 --
nc 41 -- nc 126 --
nc 64 -- nc 105 --
nc 65 -- nc 137 --
nc 66 -- nc 155 --
nc 83 -- nc 166 --
nc 84 -- nc 174 --
nc 85 -- nc 189 --
nc 86 -- p_ad<00> 181 ts
nc 95 -- p_ad<01> 180 ts
nc 96 -- p_ad<02> 179 ts
nc 97 -- p_ad<03> 177 ts
nc 98 -- p_ad<04> 175 ts
nc 99 -- p_ad<05> 173 ts
nc 100 -- p_ad<06> 171 ts
nc 101 -- p_ad<07> 170 ts
nc 102 -- p_ad<08> 167 ts
nc 103 -- p_ad<09> 165 ts

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 21050 PCI-to-PCI Bridge

Table 2-2. Alphabetic Pin Assignment List (Sheet 2 of 4)

Pin1 Pin Number Type Pin1 Pin Number Type

p_ad<10> 163 ts p_stop_l 146 sts

p_ad<11> 162 ts p_trdy_l 143 sts
p_ad<12> 161 ts s_ad<00> 183 ts
p_ad<13> 159 ts s_ad<01> 184 ts
p_ad<14> 158 ts s_ad<02> 185 ts
p_ad<15> 156 ts s_ad<03> 187 ts
p_ad<16> 138 ts s_ad<04> 188 ts
p_ad<17> 136 ts s_ad<05> 190 ts
p_ad<18> 134 ts s_ad<06> 192 ts
p_ad<19> 133 ts s_ad<07> 193 ts
p_ad<20> 131 ts s_ad<08> 197 ts
p_ad<21> 130 ts s_ad<09> 198 ts
p_ad<22> 129 ts s_ad<10> 200 ts
p_ad<23> 127 ts s_ad<11> 201 ts
p_ad<24> 122 ts s_ad<12> 202 ts
p_ad<25> 120 ts s_ad<14> 205 ts
p_ad<26> 119 ts s_ad<15> 207 ts
p_ad<27> 117 ts s_ad<16> 16 ts
p_ad<28> 116 ts s_ad<17> 17 ts
p_ad<29> 115 ts s_ad<18> 19 ts
p_ad<30> 113 ts s_ad<19> 21 ts
p_ad<31> 112 ts s_ad<20> 22 ts
p_cbe_l<0> 168 ts s_ad<21> 24 ts
p_cbe_l<1> 154 ts s_ad<22> 26 ts
p_cbe_l<2> 139 ts s_ad<23> 28 ts
p_cbe_l<3> 123 ts s_ad<24> 30 ts
p_clk 87 I s_ad<25> 32 ts
p_devsel_l 145 sts s_ad<26> 34 ts
p_frame_l 141 sts s_ad<27> 35 ts
p_gnt_l 110 I s_ad<28> 37 ts
p_idsel 125 I s_ad<29> 38 ts
p_irdy_l 142 sts s_ad<30> 40 ts
p_lock_l 148 sts s_ad<31> 42 ts
p_par 153 ts s_bufne_l 91 O
p_perr_l 150 sts s_cbe_l<0> 195 ts
p_req_l 111 ts s_cbe_l<1> 208 ts
p_rst_l 108 I s_cbe_l<2> 15 ts
p_serr_l 151 od s_cbe_l<3> 29 ts

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Table 2-2. Alphabetic Pin Assignment List (Sheet 3 of 4)

Pin1 Pin Number Type Pin1 Pin Number Type

s_cfn_l 52 I vdd 20 P
s_clk 63 I vdd 61 P
s_clk_o<0> 68 O vdd 124 P
s_clk_o<1> 70 O vdd 176 P
s_clk_o<2> 72 O vdd 3 P
s_clk_o<3> 74 O vdd 10 P
s_clk_o<4> 76 O vdd 18 P
s_clk_o<5> 78 O vdd 27 P
s_clk_o<6> 80 O vdd 39 P
s_devsel_l 9 sts vdd 46 P
s_dispst_l 90 I vdd 62 P
s_frame_l 13 sts vdd 69 P
s_gnt_l<5> 44 ts vdd 73 P
s_gnt_l<4> 45 ts vdd 77 P
s_gnt_l<3> 47 ts vdd 81 P
s_gnt_l<2> 48 ts vdd 88 P
s_gnt_l<1> 49 ts vdd 114 P
s_gnt_l<0> 51 ts vdd 121 P
s_irdy_l 12 sts vdd 135 P
s_lock_l 6 sts vdd 144 P
s_par 2 ts vss 82 P
s_perr_l 5 sts vss 94 P
s_req_l<0> 53 I vss 109 P
s_req_l<1> 54 I vss 118 P
s_req_l<2> 55 I vss 128 P
s_req_l<3> 56 I vss 59 P
s_req_l<4> 57 I vss 67 P
s_req_l<5> 58 I vss 71 P
s_rst_l 60 O vss 75 P
s_serr_l 4 I vss 79 P
s_stop_l 8 sts vss 43 P
s_trdy_l 11 sts vss 50 P
vdd 157 P vss 132 P
vdd 164 P vss 140 P
vdd 178 P vss 147 P
vdd 186 P vss 152 P
vdd 194 P vss 160 P
vdd 203 P vss 169 P

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Table 2-2. Alphabetic Pin Assignment List (Sheet 4 of 4)

Pin1 Pin Number Type Pin1 Pin Number Type

vss 33 P vss 172 P

vss 89 P vss 182 P
vss 149 P vss 191 P
vss 196 P vss 199 P
vss 7 P vss 206 P
vss 14 P vss 31 P
vss 23 P vss 36 P
1.
nc—Do not connect these pins on the board.

2.3 Numeric 21050 Pin Assignment List

Table 2-3 lists the 21050 pins in numeric order.

Table 2-3. Numeric Pin Assignment List (Sheet 1 of 4)

Pin1 Pin Number Type Pin1 Pin Number Type

nc 1 -- s_ad<21> 24 ts
s_par 2 ts nc 25 --
vdd 3 P s_ad<22> 26 ts
s_serr_l 4 I vdd 27 P
s_perr_l 5 sts s_ad<23> 28 ts
s_lock_l 6 sts s_cbe_l<3> 29 ts
vss 7 P s_ad<24> 30 ts
s_stop_l 8 sts vss 31 P
s_devsel_l 9 sts s_ad<25> 32 ts
vdd 10 P vss 33 P
s_trdy_l 11 sts s_ad<26> 34 ts
s_irdy_l 12 sts s_ad<27> 35 ts
s_frame_l 13 sts vss 36 P
vss 14 P s_ad<28> 37 ts
s_cbe_l<2> 15 ts s_ad<29> 38 ts
s_ad<16> 16 ts vdd 39 P
s_ad<17> 17 ts s_ad<30> 40 ts
vdd 18 P nc 41 --
s_ad<18> 19 ts s_ad<31> 42 ts
vdd 20 P vss 43 P
s_ad<19> 21 ts s_gnt_l<5> 44 ts
s_ad<20> 22 ts s_gnt_l<4> 45 ts

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Table 2-3. Numeric Pin Assignment List (Sheet 2 of 4)

Pin1 Pin Number Type Pin1 Pin Number Type

vss 23 P vdd 46 P
s_gnt_l<3> 47 ts vdd 73 P
s_gnt_l<2> 48 ts s_clk_o<3> 74 O
s_gnt_l<1> 49 ts vss 75 P
vss 50 P s_clk_o<4> 76 O
s_gnt_l<0> 51 ts vdd 77 P
s_cfn_l 52 I s_clk_o<5> 78 O
s_req_l<0> 53 ts vss 79 P
s_req_l<1> 54 I s_clk_o<6> 80 O
s_req_l<2> 55 I vdd 81 P
s_req_l<3> 56 I vss 82 P
s_req_l<4> 57 I nc 83 --
s_req_l<5> 58 I nc 84 --
vss 59 P nc 85 --
s_rst_l 60 O nc 86 --
vdd 61 P p_clk 87 I
vdd 62 P vdd 88 P
s_clk 63 I vss 89 P
nc 64 -- s_dispst_l 90 I
nc 65 -- s_bufne_l 91 O
nc 66 -- nand_out 92 O
vss 67 P go_z 93 I
s_clk_o<0> 68 O vss 94 P
vdd 69 O nc 95 --
s_clk_o<1> 70 O nc 96 --
vss 71 P nc 97 --
s_clk_o<2> 72 O nc 98 --
nc 99 -- p_idsel 125 ts
nc 100 -- nc 126 --
nc 101 -- p_ad<23> 127 ts
nc 102 -- vss 128 P
nc 103 -- p_ad<22> 129 ts
nc 104 -- p_ad<21> 130 ts
nc 105 -- p_ad<20> 131 ts
nc 106 -- vss 132 P
nc 107 -- p_ad<19> 133 ts
p_rst_l 108 I p_ad<18> 134 ts
vss 109 P vdd 135 P

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Table 2-3. Numeric Pin Assignment List (Sheet 3 of 4)

Pin1 Pin Number Type Pin1 Pin Number Type

p_gnt_l 110 I p_ad<17> 136 ts

p_req_l 111 ts nc 137 P
p_ad<31> 112 ts p_ad<16> 138 ts
p_ad<30> 113 ts p_cbe_l<2> 139 ts
vdd 114 P vss 140 P
p_ad<29> 115 ts p_frame_l 141 sts
p_ad<28> 116 ts p_irdy_l 142 sts
p_ad<27> 117 ts p_trdy_l 143 sts
vss 118 P vdd 144 P
p_ad<26> 119 ts p_devsel_l 145 sts
p_ad<25> 120 ts p_stop_l 146 sts
vdd 121 P vss 147 P
p_ad<24> 122 ts p_lock_l 148 sts
p_cbe_l<3> 123 ts vss 149 P
vdd 124 P p_perr_l 150 sts
p_serr_l 151 od p_ad<04> 175 ts
vss 152 P vdd 176 P
p_par 153 ts p_ad<03> 177 ts
p_cbe_l<1> 154 ts vdd 178 P
nc 155 -- p_ad<02> 179 ts
p_ad<15> 156 ts p_ad<01> 180 ts
vdd 157 P p_ad<00> 181 ts
p_ad<14> 158 ts vss 182 P
p_ad<13> 159 ts s_ad<00> 183 ts
vss 160 P s_ad<01> 184 ts
p_ad<12> 161 ts s_ad<02> 185 ts
p_ad<11> 162 ts vdd 186 P
p_ad<10> 163 ts s_ad<03> 187 ts
vdd 164 P s_ad<04> 188 ts
p_ad<09> 165 ts nc 189 --
nc 166 -- s_ad<05> 190 ts
p_ad<08> 167 ts vss 191 P
p_cbe_l<0> 168 ts s_ad<06> 192 ts
vss 169 P s_ad<07> 193 ts
p_ad<07> 170 ts vdd 194 P
p_ad<06> 171 ts s_cbe_l<0> 195 ts
vss 172 P vss 196 P
p_ad<05> 173 ts s_ad<08> 197 ts

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Table 2-3. Numeric Pin Assignment List (Sheet 4 of 4)

Pin1 Pin Number Type Pin1 Pin Number Type

nc 174 -- s_ad<09> 198 ts

vss 199 P s_ad<11> 201 ts

s_ad<10> 200 ts s_ad<12> 202 ts
1.
nc—Do not connect these pins on the board.

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3.0 Signal Description

This chapter contains a detailed description of 21050 signals. Signals are divided into four major
functions:
• Primary PCI bus
• Secondary PCI bus
• Secondary bus arbiter
• Clocks, reset, and miscellaneous

Note: The _l symbol at the end of a signal name indicates that the active, or asserted state occurs when
the signal is at a low-voltage level. If the _l symbol is not present after the signal name, then the
signal is asserted at the high voltage level.

The following table describes the signal types referred to in this chapter.

Table 3-4. Signal Types

Signal Type Definition

I Standard input only.

O Standard output only.
ts Tristate bidirectional.
Sustained tristate. Active low signal must be pulled high for one cycle when
sts
deasserting.
od Standard open drain.
P Power or ground.

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3.1 Primary PCI Bus Signals

The following table describes the primary PCI bus signals.

Table 3-5. Primary OCI Bus Signals (Sheet 1 of 2)

Signal Name Type Description

Primary PCI interface address/data. These signals represent a multiplexed

PCI address and data bus. During an address phase of a transaction,
p_ad<31:0> ts p_ad<31:0> contains a physical byte address. During subsequent data
phases, p_ad<31:0> contains data. A PCI bus transaction consists of one
or two address phases followed by one or more data phases.
Primary PCI interface command/byte enables. These signals are
multiplexed bus command and byte enables. During an address phase of
a transaction, p_cbe_l<3:0> contains the bus command that defines the
p_cbe_l<3:0> ts
type of PCI transaction. During data phases, p_cbe_l<3:0> contains byte
enables dictating which byte lanes carry valid data. p_cbe_l<0> applies to
byte 0; p_cbe_l<3> applies to byte 3.
Primary PCI interface cycle frame. p_frame_l is driven by the initiator of
the transaction to indicate the beginning and duration of an access on the
primary PCI bus. p_frame_l assertion indicates the beginning of an
p_frame_l sts access. While p_frame_l is asserted, data transfers continue. The
deassertion of p_frame_l indicates the final data phase. The bridge
samples p_frame_l as an input and also drives p_frame_l when acting as
the initiator of a transaction on the primary PCI bus.
Primary PCI interface target ready. This signal indicates the target’s ability
to complete the current data phase of a transaction on the primary PCI
p_trdy_l sts bus. The bridge drives p_trdy_l when acting as a target on the primary PCI
bus and samples p_trdy_l when acting as an initiator on the primary PCI
bus.
Primary PCI interface initiator ready. This signal indicates the initiator’s
ability to complete the current data phase of a transaction on the primary
p_irdy_l sts PCI bus. The ridge drives p_irdy_l when acting as an initiator on the
primary PCI bus and samples p_irdy_l when acting as a target on the
primary PCI bus.
Primary PCI interface stop indicator. This signal indicates that the current
target is requesting the bus initiator to stop the current transaction on the
p_stop_l sts primary PCI bus. The bridge drives p_stop_l when acting as a target on
the primary PCI bus and samples p_stop_l when acting as an initiator on
the primary PCI bus.
Primary PCI interface resource lock. Indicates an atomic operation that
may require multiple transactions to complete. Resources in the bridge
cannot be locked, but the bridge does propagate locks across the bridge.
p_lock_l sts
The bridge samples p_lock_l when acting as a target on the primary PCI
bus and drives p_lock_l when acting as an initiator on the primary PCI bus
on behalf of a master on the secondary bus.
Initialization device select. Used as a chip select during configuration read
and write commands. If p_idsel is detected asserted and the transaction is
p_idsel I
a Type 0 configuration command, then the bridge responds as a target to
the transaction by asserting p_devsel_l.
Primary PCI interface device select. Asserted by the bridge through
positive decoding of the address on p_ad<31:0>. When it is accepting a
transaction for an internal configuration access or when it is forwarding a
p_devsel_l sts transaction across the bridge. The bridge samples p_devsel_l when it is
acting as an initiator on the primary PCI bus, and expects p_devsel_l to be
asserted within five cycles of p_frame_l assertion. Otherwise, the
transaction is terminated with an master abort.

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Table 3-5. Primary OCI Bus Signals (Sheet 2 of 2)

Signal Name Type Description

Primary PCI interface parity. Even parity, calculated on 36 bits composed

of p_ad<31:0> and p_cbe_l<3:0>. The p_par signal is generated for all
address and data phases and is valid one clock cycle after valid data or
address is driven on p_ad<31:0>. The p_par signal is driven and tristated
identically to p_ad, except that it is delayed one clock cycle. The p_par
p_par ts
signal is driven by the bridge when acting as an initiator during address
phases and write data phases. The p_par signal is driven by the bridge
when acting as a target during read data phases. The p_par signal is
sampled as an input during all address phases, and when acting as a
target during write data phases.
Primary PCI interface system error. Can be pulsed by any device residing
on the primary PCI bus that detects a system error condition. The bridge
can be enabled to assert p_serr_l as a result of address parity error
p_serr_l od
detection, special cycle data parity error, s_serr_l assertion, master aborts
or target aborts during posted writes, data parity error during posted
writes, and undelivered posted write data.
Primary PCI interface parity error detected. Asserted when a data parity
error is detected, and corresponds to p_par driven one clock cycle earlier.
p_perr_l sts
The bridge asserts p_perr_l when it detects a write data parity error when
acting as a target, or a read data parity error when acting as an initiator.
Primary PCI bus request. Asserted by the bridge to indicate to the bus
p_req_l ts
arbiter that it wants to use the primary PCI bus.
Primary PCI bus grant. When asserted, indicates to the bridge that access
p_gnt_l I to the primary PCI bus is granted. The bridge can start a transaction as
soon as p_gnt_l is asserted and the bus is idle.

3.2 Secondary PCI Bus Signals

The following table describes the secondary PCI bus signals.

Table 3-6. Secondary PCI Bus Signals (Sheet 1 of 2)

Signal Name Type Description

Secondary PCI interface address/data. These signals represent a

multiplexed PCI address and data bus. During an address phase of a
transaction, s_ad<31:0> contains a physical byte address. During
s_ad<31:0> ts
subsequent data phases, s_ad<31:0> contains data. A PCI-to-PCI bridge
transaction consists of one or two address phases followed by one or
more data phases.
Secondary PCI interface command/byte enables. These signals represent
multiplexed bus command and byte enables. During an address phase of
a transaction, s_cbe_l<3:0> contains the bus command defining the type
s_cbe_l<3:0> ts
of PCI transaction. During data phases, s_cbe_l<3:0> contains byte
enables dictating which byte lanes carry valid data. s_cbe_l<0> applies to
byte 0; s_cbe_l<3> applies to byte 3.
Secondary PCI interface cycle frame. Driven by the initiator of the
transaction to indicate the beginning and duration of an access on the
secondary PCI bus. The assertion of s_frame_l indicates the beginning of
s_frame_l sts an access. While s_frame_l is asserted, data transfers continue. The
deassertion of s_frame_l indicates the final data phase. The bridge
samples s_frame_l as an input and also drives s_frame_l when acting as
the initiator of a transaction on the secondary PCI bus.

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Table 3-6. Secondary PCI Bus Signals (Sheet 2 of 2)

Signal Name Type Description

Secondary PCI interface target ready. This signal indicates the target
agent’s ability to complete the current data phase of a transaction on the
s_trdy_l sts secondary PCI bus. The bridge drives s_trdy_l when acting as a target on
the secondary PCI bus and samples s_trdy_l when acting as an initiator on
the secondary PCI bus.
Secondary PCI interface initiator ready. This signal indicates the initiator’s
ability to complete the current data phase of a transaction on the
s_irdy_l sts secondary PCI bus. The bridge drives s_irdy_l when acting as an initiator
on the secondary PCI bus and samples s_irdy_l when acting as a target
on the secondary PCI bus.
Secondary PCI interface stop indicator. This signal indicates that the
current target is requesting the bus initiator to stop the current transaction
s_stop_l sts on the secondary PCI bus. The bridge drives s_stop_l when acting as a
target on the secondary PCI bus and samples s_stop_l when acting as an
initiator on the secondary PCI bus.
Secondary PCI interface resource lock. Indicates an atomic operation that
may require multiple transactions to complete. The bridge cannot be
locked, but it does propagate locks across the bridge. The bridge samples
s_lock_l sts
s_lock_l when acting as a target on the secondary PCI bus and may drive
s_lock_l when acting as an initiator on the secondary PCI bus on behalf of
a master on the primary bus.
Secondary PCI interface device select. Asserted by the bridge through
positive decoding of the address on s_ad<31:0>. When it is forwarding a
transaction upstream across the bridge. The bridge samples s_devsel_l
s_devsel_l sts
when it is acting as an initiator on the secondary PCI bus, and expects
s_devsel_l to be asserted within five cycles of s_frame_l assertion.
Otherwise, the transaction is terminated with a master abort.
Secondary PCI interface parity. Even parity calculated on 36 bits
composed of s_ad<31:0> and s_cbe_l<3:0>. The s_par signal is
generated for all address and data phases and is valid one clock cycle
after valid data or address is driven on s_ad. The s_par signal is driven
and tristated identically to s_ad, except that it is delayed clock cycle. The
s_par ts
s_par signal is driven by the bridge when acting as an initiator during
address phases and write data phases. The s_par signal is driven by the
bridge when acting as a target during read data phases. The s_par signal
is sampled as an input during all address phases, and when acting as a
target during write data phases.
Secondary PCI interface system error. Can be pulsed by any device
residing on the secondary PCI bus that detects a system error condition.
s_serr_l I The bridge does not assert s_serr_l as an output. The bridge can be
enabled to detect assertion of s_serr_l as an input and cause p_serr_l to
assert as a result.
Secondary PCI interface parity error detected. Asserted when a data parity
error is detected, and corresponds to s_par driven one clock cycle earlier.
s_perr_l sts
The bridge asserts s_perr_l when it detects a write data parity error when
acting as a target, or a read data parity error when acting as an initiator.

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3.3 Secondary Bus Arbiter Signals

The following table describes the secondary bus arbiter signals.

Table 3-7. Secondary Bus Arbiter Signals

Signal Name Type Description

Secondary PCI bus request inputs. The bridge accepts up to six

secondary bus inputs to its secondary bus arbiter. The bridge input to the
arbiter is an internal chip signal. An asserted level on one of the
s_req_l<5:0> pins indicates that an initiator wishes to use the secondary
s_req_l<5:0> I
PCI bus. If the internal arbiter is disabled, then the s_req_l input is
reconfigured to be an external secondary bus grant input. In this case, an
asserted level on s_req_l<0> indicates that the bridge can start an access
on the secondary bus.
Secondary PCI bus grant outputs. The bridge secondary bus arbiter can
assert one of the s_gnt_l<5:0> outputs to indicate that an initiator can start
an access the secondary PCI bus if the bus is idle. Only one s_gnt_l<5:0>
signal can be asserted during any given clock cycle. The bridge bus grant
s_gnt_l<5:0> ts is an internal chip signal. The arbiter can be configured to be in rotating
mode, or in a dual alternating/rotating mode. If the internal arbiter is
disabled, then the s_gnt_l<0> output is reconfigured to be the bridge
external secondary bus request. The bridge will then assert this signal
whenever it wants to use the secondary PCI bus.
Secondary central function enable. When low, the on-chip secondary bus
arbiter is enabled. Also, the secondary PCI bus will be parked at the bridge
when the bus is idle. When high, the on-chip secondary bus arbiter is
disabled and an external arbiter should be used. The s_gnt_l<0> input is
s_cfn_l I reconfigured to be the bridge’s external secondary bus request, and the
s_req_l<0> input is reconfigured to be the bridge’s external secondary bus
grant. The external arbiter must also park the secondary bus, and can park
the bus at the bridge by asserting s_req_l<0> when the secondary bus is
idle.

3.4 Clock, Reset, and Miscellaneous Signals

The following table describes the clock, reset, and miscellaneous signals.

Table 3-8. Clock, Reset and Miscellaneous Signals (Sheet 1 of 2)

Signal Name Type Description

Primary PCI bus clock input. Provides timing for all transactions on the
primary PCI bus. All primary PCI bus inputs are sampled on the rising
p_clk I edge of p_clk, and all primary PCI bus outputs are driven from the rising
edge of p_clk. Frequencies supported by the bridge range from 0 to 33
megahertz.
Primary PCI bus reset. Forces the bridge to a known state. All register
state is cleared and all primary PCI bus outputs are tristated. The p_rst_l
p_rst_l I signal may be asynchronous with p_clk. The p_rst_l signal must be
asserted for at least ten PCI clock cycles in order to reset the bridge
properly.

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Table 3-8. Clock, Reset and Miscellaneous Signals (Sheet 2 of 2)

Signal Name Type Description

Secondary PCI bus clock input. Provides timing for all transactions on the
secondary PCI bus. All secondary PCI bus inputs, as well as
miscellaneous inputs with s_ prefixes, are sampled on the rising edge of
s_clk I
s_clk; all secondary PCI bus outputs, as well as miscellaneous outputs
with s_ prefixes, are driven from the rising edge of s_clk. Frequencies
supported by the bridge range from 0 to 33 megahertz.
Secondary PCI bus clock outputs. Clock outputs are buffered versions of
p_clk and may be used as secondary PCI bus clocks. If used, one of these
s_clk_o<6:0> O clock outputs must be used as a bridge s_clk input. The s_clk_o<6:0>
clock may not be used to drive connector slots, and may not be used for
the p_clk input of another 21050.
Secondary PCI bus reset. Asserted by the bridge under any of the
following conditions:
• The p_rst_l signal is asserted.
• The secondary reset bit is set.
• The chip reset bit is set.
s_rst_l O
When the bridge asserts s_rst_l, it tristates all secondary PCI control
signals, and drives zeros on s_ad, s_cbe_l, and s_par. The s_rst_l signal
remains asserted until p_rst_l is deasserted, or the secondary reset bit is
cleared. Assertion of s_rst_l does not clear the bridge register state, and
bridge configuration registers are still accessible from the primary
interface.
Disable posting control. When the bridge detects this input asserted, the
bridge asserts s_bufne_l if any write data exists in data buffers. If the
bridge is configured to disable posting upon s_dispst_l assertion, no write
s_dispst_l I
data is posted and write transactions are limited to single burst transfers
until s_dispst_l is deasserted. This signal should be tied high if no external
disable posting control is required.
Buffer not empty indication. When the bridge asserts this output, write data
stored in bridge data buffers at the time of s_dispst_l assertion is not yet
s_bufne_l O
flushed. When deasserted, any write data in data buffers at the time of
s_dispst_l assertion is flushed.
Diagnostic tristate control. When asserted, tristates all bidirectional and
goz_l I
tristateable output pins.
Nand tree diagnostic output. This pin is dedicated to the diagnostic Nand
tree. The Nand tree starts at s_dispst_l and runs counter-clockwise. All
nand_out O
inputs, except p_clk and s_clk, are used in the Nand tree. The goz_l signal
should be asserted when the Nand tree feature is used.

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4.0 Functional Description

This chapter provides a functional description of the 21050 including:

• Bus interfaces and arbitration
• Transaction types
• Latency control, exclusive access, and error handling

4.1 PCI Bus Interfaces

The 21050 bridges system traffic between the primary PCI bus or the PCI bus closer to the CPU,
and the secondary PCI bus or the bus farther from the CPU.

4.2 Primary PCI Bus Interface

The 21050 can act as either initiator or target on the primary PCI bus. Primary PCI bus signal
names are prefaced with p_.

The primary PCI interface consists of the standard set of PCI signals. No sideband signals are defined.

4.2.1 Secondary PCI Bus Interface

Secondary PCI bus signal names are prefaced with s_.

In addition to the standard PCI bus signals, the secondary PCI interface implements additional
arbiter, data synchronization, and clock signals. The use of these signals is not required for proper
functionality. The secondary interface has neither an idsel input or a reset input.

The secondary interface has one input, s_dispst_l, for write buffer flushing and disabling of write
posting. A secondary interface output, s_bufne_l, indicates when data in write buffers at the time of
s_dispst_l assertion are emptied.

The secondary PCI interface accepts a separate clock signal for driving and sampling the secondary
data and control signals. The 21050 assumes that the secondary clock is a buffered version of the
primary clock. For a description of the skew specification between p_clk and s_clk, see
Section 4.14.

The 21050 also generates seven buffered versions of p_clk, called s_clk_o<6:0>, which may be
used as secondary interface clocks, one of which may be connected to s_clk.

The secondary interface has a reset output, s_rst_l, that the 21050 drives when it detects p_rst_l
asserted or the secondary reset control bit is set, or when the chip reset bit is set.

Configuration accesses forwarded to the secondary bus use the upper s_ad pins during the address
cycle as outgoing secondary idsel signals. The secondary interface does not have an idsel input
because 21050 configuration space is accessible from the primary interface only.

Preliminary Datasheet 19

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 21050 PCI-to-PCI Bridge

4.3 PCI Address Phase

The PCI address phase is denoted by a falling edge of xframe_l. A typical PCI transaction consists
of a single address phase that lasts for one PCI clock cycle. An exception to this is the dual address
transaction, which contains a 64-bit address driven in two subsequent PCI clock cycles. The falling
edge of xframe_l indicates the first address phase.

During a PCI address phase, the xad<31:0> signals carry the address of the transaction, while
xcbe_l<3:0> signals carry the transaction code.

The 21050 supports the following address phase features:

• Linear increment address mode
• Address and data stepping
• Dual address support

4.3.1 Linear Increment Address Mode

The 21050 supports only linear increment address mode. If any other address mode is detected, the
21050 disconnects the transaction after the first burst.

4.3.2 Address and Data Stepping

The 21050 supports address and data stepping by other address and data sources as a target.

The 21050 uses address stepping as a master only when generating a Type 0 configuration address
phase on the secondary bus. One address step cycle is needed to allow the secondary bus idsel
signal to become valid, since it may be connected to an s_ad line through resistive coupling.

When address stepping is used, the secondary bus arbiter may deassert a grant before the assertion
of s_frame_l but it never asserts another grant in the same PCI cycle as the deassertion when the
secondary PCI bus is idle. This prevents address contention when address stepping is used on the
secondary interface.

4.3.3 Dual Addressing

Dual-address transactions provide a mechanism to generate a 64-bit address on a 32-bit PCI bus. A
dual-address transaction consists of two address phases. The first address phase contains the
least-significant 32 bits of the address on xad<31:0> and the dual-address command on
xcbe_l<3:0>. The second address phase contains the most-significant 32 bits of the address on
xad<31:0> and the transaction type command on xcbe_l<3:0>.

The 21050 responds to all dual-address transactions on the secondary bus, and forwards them to the
primary bus. The 21050 ignores all dual-address transactions initiated on the primary bus.

When forwarding a dual-address transaction upstream, the 21050 may post write data or prefetch
read data, depending on the transaction type. The 21050 follows the same guidelines for posting
and prefetching as described for the specific transaction types.

20 Preliminary Datasheet

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 21050 PCI-to-PCI Bridge

4.4 Device Select (devsel) Generation

In all transactions crossing the 21050 that require a return of xdevsel_l to the initiator, the 21050
performs positive decoding of the address information and conditionally returns xdevsel_l with medium
timing to the initiator of the transaction. This ensures that xdevsel_l is returned to the initiating device
within the minimum allowed number of PCI clock cycles (5) after assertion of xframe_l.

If the 21050 does not receive an asserted value of ydevsel_l from the target device within the
required number of PCI cycles after the 21050 asserts yframe_l, the 21050 performs a master abort
on the target bus. The 21050 may be configured to handle master aborts in two different ways
based on the Master Abort Mode bit.

In default mode, the 21050 asserts xtrdy_l on the initiator bus and completes the transaction. Write
data is not delivered, and read data is driven as FFFFFFFFh. The Received Master Abort bit is set
in the status register corresponding to the target bus.

If the Master Abort Mode bit is set, then the 21050 is enabled to perform a target abort on the
initiator bus when a master abort is detected on the target bus for read and non-posted write
operations. The 21050 asserts p_serr_l if a master abort occurs during a posted write, if the primary
serr driver enable is set and the serr disable for master abort is not set. The Received Master Abort
bit is set in the status register corresponding to the target bus. For reads and non-posted writes, the
Signaled Target Abort bit is set in the status register corresponding to the initiator bus. For posted
writes, the Signaled System Error bit is set in the Primary Status Register.

4.5 Transaction Forwarding

The 21050 forwards all types of memory, I/O, and configuration commands, and also generates
special cycles.

PCI commands are defined by the xcbe_l signals during the address phase. Table 4-1 lists the
xcbe_l commands.

Table 4-1. xcbe_l Commands

xcbe_l PCI Command xcbe_l PCI Command

0000 Interrupt acknowledge 1000 Reserved

0001 Special cycle 1001 Reserved
0010 I/O read 1010 Configuration read
0011 I/O write 1011 Configuration write
0100 Reserved 1100 Memory read multiple
0101 Reserved 1101 Reserved
0110 Memory read 1110 Memory read line
0111 Memory write 1111 Memory write and invalidate

Preliminary Datasheet 21

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 21050 PCI-to-PCI Bridge

4.5.1 Transaction Support

Table 4-2 shows which transactions are supported by the 21050, and whether posting or
prefetching is used for a particular transaction under normal operating conditions.

P → S indicates transactions in which the initiator resides on the primary side and the target resides
on the secondary side.

S → P indicates transactions in which the initiator resides on the secondary side and the target
resides on the primary side.

Table 4-2. Transaction Forwarding and Filtering

Transaction P→S S→P Notes

Interrupt acknowledge No No —
Special cycle No No —
I/O read Yes Yes Limited to one data transfer; no prefetching.
I/O write Yes Yes Limited to one data transfer; no posting.
Allows prefetching and multiple data transfers if
Memory read Yes Yes addressing the prefetchable memory range;
otherwise, limited to one data transfer; no prefetching.
Memory write Yes Yes Posting and multiple data transfers allowed.
Upstream: Type 1 → Type 1 only. Limited to one data
Configuration read Yes Yes
transfer; no prefetching.
Upstream: Type 1 → Type 1 and Type 1 → special
Configuration write Yes Yes
cycle only. Limited to one data transfer; no posting.
Allows prefetching and multiple data transfers with
Memory read multiple Yes Yes certain restrictions. See Section 4.5.4.4 and
Section 4.5.4.5.
Allows prefetching and multiple data transfers with
Memory read line Yes Yes certain restrictions. See Section 4.5.4.4 and
Section 4.5.4.5.
Memory write and
Yes Yes Posting and multiple data transfers allowed.
invalidate
Configuration write →
Yes Yes —
special cycle
Posting, prefetching, and burst limitations dependent
Dual address No Yes
on transaction type.

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 21050 PCI-to-PCI Bridge

4.5.2 Data Path

Figure 4-1 shows the data path for forwarding transactions across the 21050. In each direction
eight data buffers are used for either read or write data, and an additional register is used to hold
and track addresses.
Figure 4-1. 21050 Data Path

Data 0
Data 1
p_ad
Data 2
Data 3
Data 4 s_ad
Data 5
Data 6
Data 7
Address

Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Address LJ-03235.AI4

4.5.3 Write Transactions

Write transactions may be posted or non-posted. Posted write transactions allow multiple burst data
transfers to the 21050 before access to the target device is acquired. Non-posted write transactions
are limited to a single data phase. Data is not transferred from the initiator until it is transferred to
the target. Posted and non-posted write behavior is described in the following sections.

4.5.3.1 Non-Posted Write Transactions

When a non-posted write that will be forwarded is initiated, the 21050 returns xdevsel_l to the
initiator and attempts to gain access to the target bus. After the initiator presents the write data, as
indicated by an asserted value of xirdy_l, and the 21050 obtains possession of the target bus, the
21050 propagates the write data across the 21050 and transfers the data to the target. After data is
successfully transferred to the target by assertion of yirdy_l and ytrdy_l, the 21050 transfers the
write data from the initiator by asserting xtrdy_l. Up to this point, the initiator is held in wait states
through a target stall. Note that for this type of write, additional latency is incurred since
information is propagated in both directions across the 21050. Writes of this type are limited to a
single data transfer.

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 21050 PCI-to-PCI Bridge

Figure 4-2 shows a non-posted I/O write transaction where the bridge returns a target disconnect
after the first data transfer.
Figure 4-2. I/O Write Timing

p_clk

p_ad<31:0> Addr Data

p_cbe_l<3:0> 3 0

p_frame_l

p_irdy_l

p_stop_l

p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> Addr Data

s_cbe_l<3:0> 3 0

s_frame_l

s_irdy_l

s_trdy_l

s_devsel_l

LJ-03292.AI4

4.5.3.2 Use of Non-Posted Write Transactions

Non-posted write transactions are used for:
• I/O writes
• Configuration writes
• Memory writes when s_dispst_l is asserted and the Posting Disabled bit is set in the Chip
Control register
• Memory writes when the target bus is locked, indicated by ylock_l asserted.

24 Preliminary Datasheet

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 21050 PCI-to-PCI Bridge

4.5.3.3 Posted Write Transactions

When a posted write that will be forwarded is initiated, the 21050 returns both xdevsel_l and
xtrdy_0 to the initiator to start accepting write data, before the 21050 acquires access to the target
bus. The 21050 attempts to gain access to the target bus in the same manner and with the same
timing as for the non-posted write.

Figure 4-3 shows a posted write transaction. In this diagram, data is posted simultaneously to both
upstream and downstream write buffers from both primary and secondary buses. When the secondary
bus becomes idle, the bridge delivers downstream write data to the secondary bus target. When the
downstream transaction is complete, upstream write data is delivered to the primary bus target.

For posted write transactions crossing the 21050, the initiator can post up to 8 dwords of data to the
21050 while access to the target bus is acquired. If the 21050 does not receive a target response (an
asserted value of xtrdy_l) by the time the eighth dword is about to be transferred, the 21050
performs a target disconnect on the eighth dword transfer. This is because the 21050 cannot
guarantee that the ninth dword will be transferred within eight PCI clock cycles.

If the target returns xtrdy_l before the write buffer is filled and more than eight dwords are to be
transferred, the 21050 allows continuous write data transfers from the initiator until a write
boundary is reached. If the target device stalls, causing the write buffer to fill, the 21050 causes a
target stall on the initiating bus until buffer space is available.

Write buffering allows posted write transactions to proceed at the maximum transfer rate of one
data transfer per PCI clock cycle. The 21050 introduces a delay of two PCI clock cycles between
interfaces, but buffering hides the effects this latency would have on throughput.

Preliminary Datasheet 25

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 21050 PCI-to-PCI Bridge

Figure 4-3. Simultaneous Upstream and Downstream Posted Memory Writes

p_clk

p_ad<31:0> dAddr dData1 dData2 dData3 dData4

p_cbe_l<3:0> 7 0

p_frame_l

p_irdy_l

p_trdy_l

p_devsel_l

p_req_l

p_gnt_l

s_clk

s_ad<31:0> uAddr uData1 uData2 uData3 uData4 dAddr dData1

s_cbe_l<3:0> 7 0 7 0

s_frame_l

s_irdy_l

s_trdy_l

s_devsel_l

p_clk

p_ad<31:0> uAddr uData1 uData2 uData3 uData4

p_cbe_l<3:0> 7 0

p_frame_l

p_irdy_l

p_trdy_l

p_devsel_l

p_req_l

p_gnt_l

s_clk

s_ad<31:0> dData1 dData2 dData3 dData4

s_cbe_l<3:0> 0

s_frame_l

s_irdy_l

s_trdy_l

s_devsel_l

LJ-03293.AI4

4.5.3.4 Use of Posted Write Transactions

Posted write transactions are used for:
• Memory write transactions
• Memory write and invalidate transactions
For posted write transactions, s_dispst_l must be deasserted or the Disable Posting bit must not be
set in the Chip Control register in 21050 configuration space. In addition, the target bus must not be
locked, that is, ylock_l must be deasserted.

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 21050 PCI-to-PCI Bridge

4.5.3.5 Write Boundaries

The 21050 imposes write boundaries on posted write transactions. When the 21050 detects a write
boundary, it returns a target disconnect to the initiator and completes delivery of posted write data
up to the point of disconnection.

Posted writes are disconnected at cache line boundaries if both of the following conditions occur:
• Transaction is a memory write and invalidate
• Cache line size is set to a non-zero value, but is less than sixteen.
Posted writes are disconnected at a 256-dword boundary if one of the following conditions occur:
• Transaction is a memory write
• Transaction is a memory write and invalidate, and the cache line size register is 0 or greater
than or equal to 16. (Converted to memory write.)

The cache line size is programmable in the Cache Line size register in 21050 configuration space.

4.5.3.6 Conversion of Memory Write and Invalidate Transactions

If the 21050 cannot guarantee transfer of a memory write and invalidate transaction up to a cache
line boundary, it converts the transaction to a memory write transaction on the target bus. The
21050 converts a memory write transaction in each of the following situations:
• Cache line size register is set to 0—the 21050 does not know the cache line size.
• Cache line size register is set to 16 dwords or greater-the 21050 is unable to buffer an entire
cache line.
• Target has returned a target disconnect and a partial cache line remains in write buffers.
• Cache line size register is set to a value greater than the burst limit counter, and the burst limit
counter is non-zero.

The 21050 assumes that the cache line size is a power of 2. If a value that is not a power of 2 is
written into the cache line size register, the 21050 assumes the next lower power of 2 number as the
cache line size (that is, if a 6 is written, a cache line size of 4 is used).

Preliminary Datasheet 27

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 21050 PCI-to-PCI Bridge

4.5.3.7 Fast Back-to-Back Write Transactions

The 21050 is capable of responding to fast back-to-back write transactions. The 21050 does not use
fast timing for xdevsel_l assertion and the 21050 state machine logic is able to detect the beginning
of the second transaction and accurately decode the address. However, if the first transaction is a
posted write and both transactions are directed across the 21050, the 21050 returns a target retry in
response to the second transaction. This is because the 21050 cannot accept the second transaction
until the first transaction is complete on both the primary and secondary interfaces. In the case of a
posted write, the transaction completes on the initiator bus before it completes on the target bus.
The 21050 can forward back-to-back non-posted writes. The 21050 can also accept fast
back-to-back single burst configuration writes to its configuration space.

4.5.4 Read Transactions

Read transactions may prefetch or not prefetch. Reads that do not use prefetching are limited to one
data phase and only data requested by the initiator is read. Reads that use prefetching can consist of
multiple data phases and can read additional data than that requested by the initiator.

For either type of read that crosses the 21050, possession of both the initiator and target bus, as
well as any intermediate PCI buses between the two, must be gained before any data is transferred
from the target. Non-prefetchable and prefetchable reads are discussed in the following sections.

4.5.4.1 Non-Prefetchable Reads

When a non-prefetchable read to be forwarded is initiated, the 21050 returns xdevsel_l to the
initiator and attempts to gain access to the target bus. When the 21050 initiates the transaction on
the target bus, it asserts yframe_l for only one cycle, indicating a single data transfer request. The
21050 also asserts only those byte enables asserted by the initiator so that nonrequested data is not
read. The 21050 holds the initiator in wait states with a target stall until the target device has
returned ydevsel_l and ytrdy_l to the 21050, indicating that read data is ready. The 21050
propagates the read data across the 21050, asserting xtrdy_l to transfer it to the initiator. If a
multiple burst transfer is requested, then the 21050 also asserts xstop_l, indicating that no more
data will be transferred.

Figure 4-4 shows a non-prefetchable I/O read that is disconnected after the first data transfer.

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 21050 PCI-to-PCI Bridge

Figure 4-4. I/O Read Timing

p_clk

p_ad<31:0> Addr Data

p_cbe_l<3:0> 2 0

p_frame_l

p_irdy_l

p_stop_l

p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> Addr Data

s_cbe_l<3:0> 2 0

s_frame_l

s_irdy_l

s_trdy_l

s_devsel_l

LJ-03384.AI4

4.5.4.2 The Use of Non-Prefetchable Reads

The 21050 treats the following transactions as non-prefetchable:
• I/O read
• Configuration read
• Memory read and the read address for a downstream read falls into the non-prefetchable
memory address range (Section 4.7)
• Upstream memory read and the prefetch disable bit is set in the Chip Control register in 21050
configuration space.

In addition, the 21050 never prefetches data for any type of read where only a single dword is requested
and the initiator is not held in wait state (that is, when xframe_l is asserted for only one cycle).

4.5.4.3 Prefetchable Reads

The protocol for target access is similar to that for non-prefetchable reads. When a prefetchable read
to be forwarded is initiated, the 21050 returns xdevsel_l to the initiator and attempts to gain access to
the target bus. When the 21050 gains access to the target bus and begins the read transaction, it asserts
all byte enables for all data transfers, regardless of which byte enables are asserted by the initiator.

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 21050 PCI-to-PCI Bridge

The 21050 holds the initiator in wait states by a target stall until the target device has returned
ydevsel_l and ytrdy_l to the 21050, indicating that read data is ready. The 21050 propagates the read
data across the 21050, asserting xtrdy_l to transfer the data to the initiator.

In prefetchable read (unlike a non-prefetchable read), the 21050 keeps yframe_l asserted on the
target bus until either a read boundary is reached or until xframe_l deasserts on the target bus,
whichever comes first.

In the case of xframe_l deassertion, up to four extra dwords that are not requested by the initiator
due to 21050 latency, may be read from the target. These extra dwords are discarded. If a read
boundary is encountered before the initiator deasserts xframe_l, no nonrequested dwords are read.

Figure 4-5 and Figure 4-6 show prefetchable reads.

Figure 4-5 shows a read up to a cache line boundary. If the initiator had requested more data, it
would have been disconnected by the 21050.

Figure 4-6 shows how extra dwords may be read due to the effects of bridge latency when
forwarding the xframe_l signal.
Figure 4-5. Memory Read with Prefetching up to Cache Line Boundary

p_clk

p_ad<31:0> Addr Data1 Data2 Data3 Data4

p_cbe_l<3:0> E 0

p_frame_l

p_irdy_l

p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> Addr Data1 Data2 Data3 Data4

s_cbe_l<3:0> E 0

s_frame_l

s_irdy_l

s_trdy_l

s_devsel_l

LJ-03295.AI4

30 Preliminary Datasheet

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 21050 PCI-to-PCI Bridge

Figure 4-6. Memory Read multiple with Extra Prefetching

p_clk

p_ad<31:0> Addr Data1 Data2 Data3 Data4

p_cbe_l<3:0> C 0

p_frame_l

p_irdy_l

p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> Addr Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8

s_cbe_l<3:0> C 0

s_frame_l

s_irdy_l

s_trdy_l

s_devsel_l

LJ-03294.AI4

4.5.4.4 The Use of Prefetchable Reads

The 21050 treats the following transactions as prefetchable:
• Memory read line
• Memory read multiple
• Memory read and address of a downstream read falls into the prefetchable address range
(Section 4.7)
• Upstream read and the Prefetch Disable bit is not set in the Chip Control register in 21050
configuration space

4.5.4.5 Read Boundaries

The 21050 imposes read boundaries on prefetchable reads. When a read boundary is reached, the
21050 deasserts yframe_l to the target at the beginning of the last data phase to indicate that only
one more dword will be read. When the 21050 delivers this last longword to the initiator, the 21050
asserts xstop_l with xtrdy_l, causing a disconnect to occur on that data phase.

Prefetchable reads are disconnected on cache line boundaries if the cache line size register is set to
a value other than 0 and one of the following is true:
• Transaction is a memory read and both of these occur:
— Read address falls into the prefetchable address range for downstream reads

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 21050 PCI-to-PCI Bridge

— Prefetch Disable bit is not set in the Chip Control register for upstream reads
• Transaction is a memory read line
• Transaction is a memory read multiple and both of these occur:
— Read address falls into non-prefetchable address range for downstream reads
— Prefetch Disable bit is set in the Chip Control register for upstream reads

Figure 4-5 shows a prefetchable read disconnecting on a cache line boundary.

Prefetchable reads are disconnected on a 256-dword boundary if:

• Transaction is a memory read and the follow is true:
— Cache line size register has a value of 0
— Read address falls into the prefetchable address range for downstream reads
— Prefetch Disable bit is not set in the Chip Control register for upstream reads
• Transaction is a memory read line and the cache line size register has a value of 0.
• Transaction is a memory read multiple and
— Cache line size register has a value of 0
— Read address falls into the prefetchable address range for downstream reads
— Prefetch Disable bit is not set in the Chip Control register for upstream reads

The 21050 assumes that the cache line size is a power of 2. If a value that is not a power of 2 is
written into the cache line size register, the 21050 assumes the next lower power of 2 number as the
cache line size (if a 6 is written, then a cache line size of 4 is used).

4.5.5 Configuration Transactions

In order to support hierarchical bridging, two types of configuration accesses are defined, Type 0
and Type 1. A Type 0 configuration transaction, designated when xad<1:0> is set to 00, indicates
that the configuration transaction is intended for a device that resides on that PCI bus. A Type 1
configuration transaction, designated when xad<1:0> is set to 01, indicates that the configuration
transaction is to be passed on to another PCI bus.

Figure 4-7 shows the address formats of Type 0 and Type 1 configuration accesses.

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 21050 PCI-to-PCI Bridge

Figure 4-7. Configuration Address Formats

31 11 10 08 07 02 01 00

Function
Reserved Register Number 0 0
Number

Type 0

31 24 23 16 15 11 10 08 07 02 01 00

Device Function
Reserved Bus Number Register Number 0 1
Number Number

Type 1

LJ-03237.AI4

The 21050 can respond as the intended target to Type 0 configuration transactions initiated on the
primary PCI bus. The 21050 ignores all Type 0 transactions initiated on the secondary PCI bus.
Type 0 transactions are never forwarded across the 21050.

The 21050 forwards and converts Type 1 configuration transactions downstream as one of the
following:
• Type 1 (on the primary PCI bus) to Type 0 (on the secondary PCI bus)
• Type 1 (on the primary PCI bus) to Type 1 (on the secondary PCI bus)
• Type 1 write (on primary PCI bus) to Special Cycle (on secondary PCI bus)
The 21050 forwards and converts Type 1 configuration transactions upstream as one of the
following:
• Type 1 (on the secondary PCI bus) to Type 1 (on the primary PCI bus)
• Type 1 write (on the secondary PCI bus) to special cycle (on the primary PCI bus)
Configuration write transactions cannot be posted. Transactions are disconnected after transfer of the
first dword. The initiator is held in wait states by the 21050 until data is successfully transferred to the
target. Configuration read transactions do not use prefetching. Transactions are disconnected after
transfer of the first dword, and no additional dwords are read from the target during the transaction.

4.5.5.1 Type 0 Configuration Transactions

The 21050 responds only to Type 0 transactions as the intended target on the primary PCI bus. All
other Type 0 transactions are ignored. The 21050 responds as the intended target to a Type 0
transaction on the primary bus when, during the address phase the following occurs:
• p_idsel is asserted.
• p_ad<1:0> is set to 0.
• Function number on p_ad<10:8> is set to 0.
If these conditions are not met, then the 21050 ignores the transaction. If these conditions are
satisfied, the 21050 performs an access to its configuration state. The register number addresses a
particular dword in 21050 configuration space.

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 21050 PCI-to-PCI Bridge

Configuration access to the 21050 configuration space is disconnected after one dword transfer.
Figure 4-8 shows a configuration read and write access to the 21050.
Figure 4-8. Type 0 Configuration Write Access and Configuration Read Access

p_clk

p_ad<31:0> Addr Data Addr Data

p_cbe_l<3:0> B 0 A 0

p_frame_l

p_irdy_l

p_trdy_l

p_devsel_l

p_idsel

LJ-03291.AI4

4.5.5.2 Type 1 Configuration Transactions

In order to determine whether a Type 1 configuration transaction will be forwarded or converted,
bus numbers are assigned to each PCI bus in the system. The following bus numbers are
programmable in the 21050 configuration space:
• Primary bus number–designates the bus number for the 21050 primary bus
• Secondary bus number–designates the bus number for the 21050 secondary bus
• Subordinate bus number–designates the highest bus number of a PCI bus behind the 21050
The range defined by the secondary bus number (inclusive) and the subordinate bus number
(inclusive) specify the range of all buses that are downstream from the 21050.

Before any configuration accesses can be made to the secondary PCI bus or to any other
hierarchical PCI buses on the secondary side of the 21050, the secondary bus number of this 21050
must be initialized in the 21050 configuration space.

4.5.5.3 Type 1 to Type 0 Conversion

The 21050 forwards a Type 1 transaction downstream and converts it to a Type 0 transaction when
the transaction is intended for a device on the secondary PCI bus. A Type 1 transaction is
forwarded downstream and converted to a Type 0 transaction when the following conditions are
met during the address phase:
• p_ad<1:0> is 01, indicating a Type 1 transaction.
• Value on p_ad<23:16> matches the secondary bus number.
If these conditions are met, the 21050 asserts p_devsel_l to indicate that the cycle has been
accepted. The 21050 generates a Type 0 configuration transaction on the secondary bus with
s_ad<1:0> equal to 0 and one of the s_ad<31:16> lines, acting as idsel signals on the secondary bus
is asserted.

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 21050 PCI-to-PCI Bridge

Table 4-3 shows the appropriate address line to be asserted is derived from the device number
driven on p_ad<15:11>.

Table 4-3. Device Number to s_ad Signal Mapping

Device Device
Secondary IdSel
Number Number Secondary IdSel s_ad<31:16>
s_ad<31:16>
p_ad<15:11> p_ad<15:11>

00000 0000 0000 0000 0001 01000 0000 0001 0000 0000
00001 0000 0000 0000 0010 01001 0000 0010 0000 0000
00010 0000 0000 0000 0100 01010 0000 0100 0000 0000
00011 0000 0000 0000 1000 01011 0000 1000 0000 0000
00100 0000 0000 0001 0000 01100 0001 0000 0000 0000
00101 0000 0000 0010 0000 01101 0010 0000 0000 0000
00110 0000 0000 0100 0000 01110 0100 0000 0000 0000
00111 0000 0000 1000 0000 01111 1000 0000 0000 0000
10000 — 11110 0000 0000 0000 0000
Generate Special
11111 Cycle (R.No. = 00h) 0000 0000 0000 0000
(R.No. > 01h)

The 21050 can generate Type 0 configuration cycles for up to 16 devices. Configuration
transactions with device numbers greater than 0Fh can still be forwarded, but the 21050 will not
assert any of the s_ad<31:16> lines acting as secondary bus idsel lines. Such a transaction is likely
to result in a master abort, unless some external assertion of a secondary bus idsel line is
performed. One cycle of additional address stepping is used when driving a Type 0 address in order
to allow time for the secondary bus idsel line to the target to become valid.

Note: The 21050 never performs a Type 1 to Type 0 conversion upstream.

Preliminary Datasheet 35

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 21050 PCI-to-PCI Bridge

Figure 4-9 shows Type 1 to Type 0 forwarding of configuration read and write transactions.
Figure 4-9. Type 1 to Type 0 Configuration Write and Read

p_clk

p_ad<31:0> 27839 Data 27839

p_cbe_l<3:0> B 0 A

p_frame_l

p_irdy_l

p_stop_l

p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> 80000038 Data

s_cbe_l<3:0> B 0

s_frame_l

s_irdy_l

s_stop_l

s_trdy_l

s_devsel_l

p_clk

p_ad<31:0> 27839 Data

p_cbe_l<3:0> A 0

p_frame_l

p_irdy_l

p_stop_l

p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> 80000038 Data

s_cbe_l<3:0> A 0

s_frame_l

s_irdy_l

s_stop_l

s_trdy_l

s_devsel_l

LJ-03296.AI4

4.5.5.4 Type 1 to Type 1 Forwarding

When the 21050 receives a Type 1 transaction that is intended for any device not on the secondary
bus, it forwards the transaction as Type 1. Type 1 to Type 1 transactions may be forwarded
upstream or downstream. In this case, the address is forwarded exactly as received on the initiating
bus; no conversion is performed.
A Type 1 transaction is forwarded downstream as a Type 1 transaction when the following
conditions are met during the address phase:
• The value on p_ad<1:0> is equal to 01b.
• The value on p_ad<23:16> is greater than the secondary bus number, but less than or equal to
the subordinate bus number.

36 Preliminary Datasheet

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 21050 PCI-to-PCI Bridge

If these conditions are met, the 21050 asserts p_devsel_l to indicate that the transaction is accepted.
The 21050 generates a Type 1 transaction on the secondary interface. At least two levels of
PCI-to-PCI bridging are crossed before xtrdy_l can be returned to the initiator for writes or reads,
because the target device resides on a bus downstream from the secondary PCI bus.
A Type 1 transaction is forwarded upstream as a Type 1 transaction when the following conditions
are met during the address phase:
• The value on p_ad<1:0> is equal to 01b.
• The value on p_ad<23:16> is not equal to the primary bus number, and is outside of the range
defined by the secondary and subordinate bus numbers.
This indicates that the transaction is intended for a device upstream of the 21050, but not on the
21050 primary bus.

4.5.5.5 Type 1 to Special Cycle Conversion

Configuration write transactions can be used to pass special cycle messages throughout the PCI bus
hierarchy. Type 1 configuration transactions can be converted and forwarded as special cycles in
either direction. The write data is used as the special cycle message.

The 21050 forwards a Type 1 configuration write from the primary bus and converts it to a special
cycle on the secondary bus when the following conditions are met during the address phase:
• The device number on p_ad<15:11> is equal to all 1’s.
• The function number on p_ad<10:8> is equal to all 1’s.
• The register number on p_ad<7:2> is equal to all 0’s.
• p_ad<1:0> is equal to 01b.
• The value on p_ad<23:16> is equal to the 21050 secondary bus number.

If these conditions are met, the 21050 generates a special cycle on the secondary bus using the
same address and data that was used for the primary configuration write.

Figure 4-10 shows the write forwarded as a special cycle downstream.

Preliminary Datasheet 37

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 21050 PCI-to-PCI Bridge

Figure 4-10. Type 1 Configuration Write to Special Cycle Downstream

p_clk

p_ad<31:0> 2FF01 Data

p_cbe_l<3:0> B 0

p_frame_l

p_irdy_l

p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> 2FF01 Data

s_cbe_l<3:0> 1 0

s_frame_l

s_irdy_l

s_trdy_l

s_devsel_l

LJ-03297.AI4

The 21050 forwards a Type 1 configuration write from the secondary bus and converts it to a
special cycle on the primary bus when the following conditions are met during the address phase:
• The device number on s_ad<15:11> is equal to all 1’s.
• The function number on s_ad<10:8> is equal to all 1’s.
• The register number on s_ad<7:2> is equal to all 0’s.
• s_ad<1:0> is equal to 01b.
• The value on s_ad<23:16> is equal to the 21050 primary bus number.

If these conditions are met, the 21050 generates a special cycle on the primary bus using the same
address and data used for the primary configuration write.

4.5.6 Special Cycles

The 21050 ignores all special cycle transactions generated on either primary or secondary PCI buses.

The 21050 provides a mechanism to generate special cycles on either the primary or secondary PCI
bus through a configuration write transaction (Section 4.5.5.5).

38 Preliminary Datasheet

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 21050 PCI-to-PCI Bridge

4.5.7 Interrupt Acknowledge

The interrupt acknowledge transaction is a read operation to the interrupt controller. It is assumed
that the interrupt controller resides on the primary side of the 21050. Therefore, all interrupt
acknowledge transactions are ignored by the 21050.

4.6 Transaction Termination

The 21050 supports both initiator-initiated terminations and target-initiated terminations as both
initiator and target. A transaction is complete when both xframe_l and xirdy_l are deasserted.

4.6.1 Initiator Termination

There are two types of initiator termination:
• Normal termination
• Initiator abort–no target responds to transaction

4.6.1.1 21050 as Target

If the 21050 is acting as a target during a transaction, then the only type of initiator termination
possible is normal termination, in which the initiator deasserts xframe_l to indicate that the next
data transfer is the last transfer, and then deasserts xirdy_l at the completion of the last data transfer.
When the 21050 detects the deassertion of xframe_l, the 21050 knows to end the transaction and
deassert and tristate xtrdy_l, xstop_l and xdevsel_l after the next data transfer.

4.6.1.2 21050 as Initiator

When acting as the initiator, the 21050 can terminate a transaction normally or through a master abort.

4.6.1.2.1 Normal Termination

The 21050 uses normal termination whenever a target responds with assertion of ydevsel_l. The
21050 terminates the following transactions normally:
• Non-posted write or non-prefetched read, when a single dword burst has been transferred
• Prefetched read, when a read boundary is reached or when the initiator deasserts xframe_l (in
the latter case, up to four extra dwords may read from the target, which are discarded)
• Posted write, when the write buffer empties and the initiator completes the transaction on the
initiator bus
• Prefetched read or a posted write, when the master latency timer expires and the initiator does
not have the bus grant

Preliminary Datasheet 39

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 21050 PCI-to-PCI Bridge

4.6.1.2.2 Master Abort Termination

If the 21050 initiates a transaction and no target responds within five PCI clock cycles after
yframe_l assertion, the 21050 terminates the transaction with a master abort, indicating an error
condition. During a master abort termination, the 21050 deasserts yframe_l, and one PCI cycle
later, deasserts yirdy_l. If yframe_l is already deasserted (only one dword was requested), yirdy_l
can be deasserted five PCI clock cycles after yframe_l assertion.

The 21050 has two modes of responding to the initiator on the initiating PCI bus (where the 21050
is a target) when a master abort occurs on the target bus (where the 21050 is an initiator). The
master abort response mode is set through the Master Abort Mode bit in the Bridge Control
register. If the bit is not set (default mode), then the 21050 responds to a master abort as follows:
• Sets the Received Master Abort bit in the status register corresponding to the target bus.
• For a write, asserts xtrdy until one cycle after xframe_l deassertion on the initiating bus,
transferring write data from the initiator. Write data is discarded.
• For a read, asserts xtrdy until one cycle after xframe_l deassertion on the initiating bus and
returns FFFFFFFFh for all requested data dwords.

If the Master Abort Mode bit is set, then the 21050 responds to a master abort as follows:
• Sets the Received Master Abort bit in the status register corresponding to the target bus.
• For a non-posted write, returns a target abort to the initiator. The Signaled Target Abort bit is
set in the status register corresponding to the initiator bus.
• For a posted write, asserts p_serr_l if the p_serr_l driver control bit in the Command Register
is set, and the p_serr_l Disable for Master Abort on Posted Write is not set. If p_serr_l is
asserted, sets the Signaled System Error bit in the primary status register.
• For a read, returns a target abort to the initiator. The Signaled Target Abort bit is set in the
status register corresponding to the initiator bus.

A master abort during a special cycle is not considered abnormal termination, so none of the
previous scenarios apply for special cycles. No event bits are set, and the 21050 performs a normal
target termination in response to the configuration write on the initiator (master) bus.

4.6.2 Target Termination

The 21050 supports the following types of target termination:

ystop_l asserted and ydevsel_l deasserted indicates that the target will
Target abort
never be able to respond to the transaction.
ystop_l and ydevsel_l asserted and ytrdy_l deasserted indicates that the
Target retry target is not in state ready to accept data. No data is transferred during
this transaction.
ystop_l, ytrdy_l, and ydevsel_l asserted indicates that this data transfer
Target disconnect A/B is to be the last data transfer on the transaction. At least one dword is
transferred during the transaction.
ystop_l and ydevsel_l asserted and ytrdy_l deasserted after previous
Target disconnect C data transfers are made indicates that the most recent data transfer was
the last one of the transaction.

40 Preliminary Datasheet

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 21050 PCI-to-PCI Bridge

4.6.2.1 Target Termination Initiated by Target

If the 21050 acts as initiator and detects a target abort, retry, or disconnect through assertion of
ystop_l, then the 21050 terminates the transaction on the target bus as soon as possible by
deasserting yframe_l and asserting yirdy_l. The 21050 then deasserts yirdy_l one cycle later.

The 21050 responds in different ways on the initiator bus to target terminations on the target bus,
depending on the type of transaction. See Section 4.6.2.1.1 for a summary of 21050 response to
target terminations on the target bus.

If a target abort is detected on the target bus, the 21050 does the following:
• Sets the Received Target Abort bit in the status register corresponding to the target bus.
• If the transaction is a read or a non-posted write, returns target abort to the initiator and sets the
Signaled Target Abort bit in the status register that corresponds to the initiator bus.
• If the transaction is a posted write, then the 21050:
— If the p_serr_l driver enable is set and the serr Disable for Target Abort on Posted Write is
not set, asserts p_serr_l.
— If p_serr_l is driven, sets the Signaled System Error bit in the Primary Status Register.
— Discards any remaining write data; no attempt at delivery.

Figure 4-11 shows a target abort during an I/O write, and Figure 4-12 shows a memory read with
target abort.

Preliminary Datasheet 41

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 21050 PCI-to-PCI Bridge

Figure 4-11. I/O Write with Target Abort

p_clk

p_ad<31:0> Addr Data

p_cbe_l<3:0> 3 0

p_frame_l

p_irdy_l
p_stop_l
p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> Addr Data

s_cbe_l<3:0> 3 0

s_frame_l

s_irdy_l

s_stop_l

s_trdy_l

s_devsel_l

LJ-03306.AI4

42 Preliminary Datasheet

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 21050 PCI-to-PCI Bridge

Figure 4-12. Downstream Memory Read with Target Abort

p_clk

p_ad<31:0> Addr

p_cbe_l<3:0> 6 0

p_frame_l

p_irdy_l
p_stop_l
p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> Addr

s_cbe_l<3:0> 6 0

s_frame_l

s_irdy_l

s_stop_l

s_trdy_l

s_devsel_l

LJ-03305.AI4

If a target retry is detected on the target bus, the 21050 does the following:
• If the transaction is a read or non-posted write, returns a target retry to the initiator. No data is
transferred to or from the initiator or target.
• If the transaction is a posted write, allows up to a maximum of eight dwords to be transferred
from the initiator to 21050 write buffers before returning a target disconnect.

Preliminary Datasheet 43

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 21050 PCI-to-PCI Bridge

Figure 4-13 shows a target retry during an I/O write, and Figure 4-14 shows a memory read with
target retry.
Figure 4-13. Non-Posted I/O Write with Target Retry

p_clk

p_ad<31:0> Addr Data 1

p_cbe_l<3:0> 3 0

p_frame_l

p_irdy_l
p_stop_l
p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> Addr Data 1

s_cbe_l<3:0> 3 0

s_frame_l

s_irdy_l

s_stop_l

s_trdy_l

s_devsel_l

LJ-03304.AI4

44 Preliminary Datasheet

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 21050 PCI-to-PCI Bridge

Figure 4-14. Memory Read with Target Retry

p_clk

p_ad<31:0> Addr

p_cbe_l<3:0> 6 0

p_frame_l

p_irdy_l
p_stop_l
p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> Addr

s_cbe_l<3:0> 6 0

s_frame_l

s_irdy_l

s_stop_l

s_trdy_l

s_devsel_l

LJ-03303.AI4

If a target disconnect is detected on the target bus, the 21050 does the following:
• If the transaction is a non-prefetched read or non-posted write takes no additional action as the
21050 restricts these types of transactions to a single dword transfer.
• If the transaction is a prefetched read, then the 21050 returns a target disconnect to the initiator
after all requested data read from the target is transferred to the initiator.
• If the transaction is a posted write, then the 21050 allows up to a maximum of 8 dwords to be
transferred from the initiator to 21050 write buffers before returning a target disconnect (until
the write buffer fills).

4.6.2.1.1 Target Termination Summary

The following table summarizes the 21050 response to target termination scenarios for different
types of transactions.

Preliminary Datasheet 45

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 21050 PCI-to-PCI Bridge

Target
Transaction Type Chip Action
Termination

Accepts up to 8 dwords until write buffer is full. Attempts to deliver

Posted write Retry
write data up to 224 times; if unsuccessful, asserts p_serr_l.
Accepts up to 8 dwords until write buffer is full. Attempts to deliver
Disconnect
write data up to 224 times; if unsuccessful, asserts p_serr_l.
Returns target abort to initiator if posting not complete. Asserts
Abort p_serr_l if the serr_l disable for this condition is not set and the
p_serr_l driver enable is set.
Maintains assertion of xtrdy_l to initiator; data is not delivered. Asserts
No response p_serr_l if the serr disable for this condition is not set and the p_serr_l
driver enable is set.

Non-posted write Retry Returns target retry to initiator.

Because the 21050 is limited to one burst, it always returns target
Disconnect
disconnect to initiator after one data transfer.
Abort Returns target abort to initiator.
Mode 0: Asserts xtrdy_l to initiator; data is not delivered.
No response
Mode 1: Returns target abort to initiator.

Prefetched read Retry Returns target retry to initiator.

Disconnect Returns target disconnect to initiator.
Abort Returns target abort to initiator.
Mode 0: Asserts xtrdy_l to initiator; returns FFFFFFFFh.
No response
Mode 1: Returns target abort to initiator.

Non-prefetched read Retry Returns target retry to initiator.

Because the 21050 is limited to one burst, it always returns target
Disconnect
disconnect to initiator after one data transfer.
Abort Returns target abort to initiator.
Mode 0: Asserts xtrdy_l to initiator; returns FFFFFFFFh.
No response
Mode 1: Returns target abort to initiator.

4.6.2.1.2 Delivery of Posted Write Data after Transaction Termination

If a target retry or target disconnect is received by the 21050 during a posted write, the 21050
allows the initiator to continue posting write data until the write buffer is full (a maximum of
8 dwords). After the target retry or disconnect is received by the 21050, posted write data may still
remain in the write buffers that has not been transferred to the target.

When write data remains in the 21050 write buffers after a transaction to the target is terminated,
whether by target termination or master latency timer expiration, the 21050 reattempts the write
transaction to the target in order to empty the 21050 write buffer. The 21050 continues to attempt
the write transaction until the write data is successfully transferred, or until the maximum number
of attempts 224 (16777216) are completed. The purpose of the write counter is to prevent indefinite
hangs if the 21050 is unable to deliver write data.

Figure 4-15 shows a target retry during a posted write with subsequent write attempts.

46 Preliminary Datasheet

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 21050 PCI-to-PCI Bridge

Figure 4-15. Posted Write with Target Retry

p_clk

p_ad<31:0> Addr Data 1 Data 2 Data 3 Data 4

p_cbe_l<3:0> 7 0

p_frame_l

p_irdy_l
p_stop_l
p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> Addr Data 1 Addr Data 1 Data 2 Data 3 Data 4

s_cbe_l<3:0> 7 0 7 0

s_frame_l

s_irdy_l

s_stop_l

s_trdy_l

s_devsel_l

LJ-03302.AI4

If the maximum number of attempts are made and the 21050 has not successfully transferred the
buffered data, the 21050 asserts the p_serr_l line, if the p_serr_l driver enable is set and the serr
Disable for Delivery of Posted Write Data Failed is not set. The write data is discarded.

If the transaction is a memory write and invalidate and the write is disconnected after partial cache
line transfer, remaining attempts at delivery of write data will use the memory write command
because a partial cache line will be transferred.

Preliminary Datasheet 47

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 21050 PCI-to-PCI Bridge

4.6.2.2 Target Termination Initiated by 21050

The 21050 may return target retries or target disconnects to the initiator for reasons other than
target retry or disconnect from the intended target.

The 21050 returns a target retry to the initiator in the following situations:
• The 21050 is involved in another transaction or there is data in one of the 21050 write buffers.
The 21050 does allow posted writes to proceed simultaneously in opposite directions,
assuming that the corresponding write buffer is empty when the transaction starts.
• The transaction is a read or non-posted write, the target wait timer is expired, and the 21050
does not have the grant for the target bus.
• The transaction is a locked transaction, but the target bus lock is already being used by another
initiator.

The 21050 returns a target disconnect to the initiator for the following transactions:
• Non-posted write or non-prefetched read, and this is the first data transfer
• Posted write, and the write buffer fills (8 dwords) before the intended target returns ytrdy_l
• Posted write, and the write buffer fills (8 dwords) after expiration of the master latency timer
and before the target returns ytrdy_l for a subsequent write attempt
• Posted write, and a write boundary has been reached
— Cache line boundary for memory write and invalidate
— 256-dword boundary for memory write
• Prefetched read, and the transaction on the target bus is terminated due to master latency timer
expiration
• Prefetched read, and a read boundary is reached
Cache line or 256-dword boundary for memory-type reads, depending on various conditions
• Burst count limit is reached
A target abort is returned to the initiator by the 21050 only when a target abort is detected on the
target bus during a read or non-posted write, or an initiator abort occurs on the target bus and the
Master Abort Mode bit is set.

4.7 Address Decoding

The 21050 has three programmable address ranges which determine whether memory and I/O
transactions are forwarded across the 21050 or ignored. There are two address ranges for memory
transactions, and a single address range for I/O transactions. The 21050 also has an ISA
Compatibility mode and two modes of operation for VGA support.

There are no address holes when forwarding and filtering memory and I/O transactions. If
transactions with a given address are forwarded across the 21050 from one bus, they will be
ignored when initiated on the other bus.

Similarly, if transactions with a given address are ignored on one PCI bus, they will be forwarded
when initiated on the other bus.

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 21050 PCI-to-PCI Bridge

4.7.1 Memory Address Decoding

The 21050 implements two programmable memory ranges for memory transaction forwarding:
• A non-prefetchable address range specified by a Memory Base Address register (inclusive)
and Memory Limit Address register (inclusive) in configuration space. Downstream memory
read transactions addressing this space do not use prefetching. The space has a minimum size,
granularity, and alignment of 1 megabyte.
• A prefetchable address range specified by a Prefetchable Memory Base Address register
(inclusive) and Prefetchable Memory Limit Address register (inclusive) in configuration
space. Downstream memory read transactions addressing this space use prefetching. The
space has a minimum size, granularity, and alignment of 1 megabyte.

4.7.1.1 Memory Transaction Forwarding Based on Address Ranges

When the 21050 detects a memory read or memory write operation, it compares the address against
two address ranges in order to determine whether the transaction is forwarded or not.

If the initiator is on the primary bus, then the address must fall within one of these two defined
address ranges in order for the transaction to be forwarded to the secondary bus. There should be
no overlap between the two ranges; if overlap exists, the guidelines for the non-prefetchable space
are used.

If a memory operation is initiated on the secondary bus, the 21050 checks to see if the address falls
outside of both of the address ranges described by the prefetchable and non-prefetchable memory
base and limit address registers. If the address is outside of these ranges, the transaction is
forwarded to the primary bus and the 21050 acts as an initiator on that bus, and as a target on the
secondary bus.

4.7.1.2 Disabling a Memory Address Range

Setting the memory limit address register to a value less than its respective memory base address
register turns that address range off. If both memory limit registers are set to a value less than their
respective memory base address registers, the 21050 will not forward any memory transactions
from the primary to secondary bus, but will forward all memory transactions initiated on the
secondary bus to the primary bus. Note that the reset condition for the registers defines an address
space of 00000000h—000FFFFFh in both prefetchable and non-prefetchable space for forwarding
to the secondary bus.

4.7.1.3 VGA Frame Buffer Support

The 21050 also performs some memory address decoding and forwarding for frame buffer
memory. If the frame buffer memory range is enabled by the VGA Enable bit in the Bridge Control
register configuration space, transactions initiated on the primary bus with memory addresses in
the range 000A0000h—000BFFFFh will be forwarded downstream, and transactions initiated on
the secondary bus whose addresses fall within that range will be ignored. Read operations to frame
buffer memory will be treated as prefetchable.

4.7.1.4 Dual Transaction Addressing

Dual address transactions are never forwarded downstream, and are always forwarded upstream.
No address decoding is performed.

Preliminary Datasheet 49

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 21050 PCI-to-PCI Bridge

4.7.2 I/O Address Decoding

The 21050 implements a single programmable memory range for I/O transaction forwarding
specified by an I/O Base Address register (inclusive) and I/O Limit Address register (inclusive) in
configuration space. The space has a minimum size, granularity, and alignment of 4 K and a
maximum I/O space of 64 K.

4.7.2.1 I/O Transaction Forwarding Based on Address Range

If an I/O transaction is initiated on the primary bus, and the address falls inside the range defined
by the I/O Base Address register and I/O Limit Address register, the 21050 forwards the
transaction to the secondary bus. The 21050 acts as an initiator on the secondary bus and as a target
on the primary bus.

If an I/O read or write transaction is initiated on the secondary bus, the 21050 forwards the
transaction to the primary bus if the address falls outside the address range described by the I/O
Base Address register and I/O Limit Address register.

Any transactions that address over 64 K of I/O space are ignored on the primary PCI bus and
forwarded upstream from the secondary PCI bus.

4.7.2.2 Disabling the I/O Address Range

If the I/O Limit Address register is set to a value less than the I/O Base Address register, the 21050
will not forward any I/O transactions from the primary to secondary bus, but will forward all I/O
transactions initiated on the secondary bus to the primary bus. Note that the reset condition for the
registers defines an address space of 0000h—0FFFh for forwarding to the secondary bus.

4.7.2.3 ISA Mode

The 21050 may be programmed to be ISA-bus aware through the ISA Mode bit in the Bridge
Control register in configuration space. This feature enables a finer granularity filtering mechanism
for I/O read and write transactions. ISA I/O target cards decode only the lowest 10 bits of the
address, which represents 1K of address space. The upper 768 bytes of this 1 K address space are
allocated to general I/O ISA target cards. Because these devices do not decode the upper address
bits <15:10>, their addresses are aliased and repeated 64 times, for every 1 K chunk in the 64 K
address space. Thus, if an ISA card is present it would respond to its address in every 1 K chunk.

Because of address aliasing, non-ISA devices should not use I/O addresses in the upper 768 bytes
of each 1 K chunk if an ISA card is present. Likewise, the 21050 should not forward transactions in
this address range if an ISA card is present, regardless of whether the address falls within the I/O
base and limit address range.

Only transactions addressing the first 256 bytes of each 1 K chunk can be forwarded. When ISA
Mode Enable is set, the 21050 prevents the forwarding of I/O transactions that address the top
768 bytes of each 1 K chunk in I/O space. This blocking mechanism affects only those transactions
initiated on the primary bus. The 21050 will not respond to blocked transactions on the initiating
(primary) bus. However, as a consequence, addresses of I/O transactions initiated on the secondary
bus that fall into the upper 768 K range will be forwarded upstream, regardless of where the
address falls with respect to the I/O base and limit address range.

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 21050 PCI-to-PCI Bridge

If the ISA Mode Enable bit is not set, transactions that address the upper 768 bytes of each 1 K
chunk of I/O space are forwarded or filtered normally according to the I/O Base Address and I/O
Limit Address registers. Figure 4-16 shows the ISA mode for downstream forwarding when the
enable is set. In order to correctly use the ISA mode, the I/O Base and Limit address register should
be set so that there is no overlap with ISA or EISA system-specific addresses in the lower
256 bytes of the first 4 Ks of I/O space.
Figure 4-16. Downstream I/O Forwarding in ISA Mode
.
.
n+3 Kb

Block Forwarding

Forward
n+2 Kb

Block Forwarding

Forward
n+1 Kb

768
Block Forwarding Bytes

256
Forward
Bytes
n Kb

Block Forwarding

Forward
n-1 Kb
.
.
. ISA-Aware Enable = 1
LJ-03236.AI4

4.7.3 VGA I/O Support

The 21050 has two modes of VGA support:
• VGA Mode for forwarding all VGA memory and I/O accesses enabled when the VGA Enable
bit is set in the Bridge Control register in configuration space
• VGA Snoop Mode for snooping (forwarding) VGA palette I/O writes, enabled when the VGA
Snoop bit is set in the Bridge Command register in configuration space

4.7.3.1 VGA Mode

When VGA Mode is enabled, the 21050 forwards downstream all memory transactions that
address frame buffer memory and all I/O transactions that address VGA I/O space
(Section 4.7.1.3).

In VGA Mode, any I/O transactions in the 03B0h—03DFh range, with the exception of printer port
byte addresses 3BCh—3BFh, are forwarded downstream when initiated on the primary bus, and
ignored if initiated on the secondary bus. When VGA Mode is enabled, bits <31:16> of the I/O

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 21050 PCI-to-PCI Bridge

address must be 0 in order for the 21050 to recognize and forward VGA I/O transactions. Bits
<15:10> will not be decoded. VGA I/O addresses are aliased in every 1K block of I/O space. These
aliased transactions are forwarded.

This VGA I/O forwarding is independent of the I/O address region and the ISA Mode filtering.
This means that whenever the VGA bit is set, the transactions previously described are forwarded
regardless of whether they fall inside the I/O Base and Limit Address range, and regardless of
whether the ISA Mode bit is set.

If the VGA enable bits are not set, the 21050 uses the Base and Limit Address registers for memory
and I/O forwarding, and VGA addresses are forwarded or filtered depending on whether they fall
within the base and limit address ranges. If ISA Mode is enabled and VGA Mode is disabled, VGA
I/O transactions are not forwarded downstream, since the addresses fall within the upper 768-byte
address range.

4.7.3.2 VGA Palette Snooping

When the VGA Snoop Mode bit is set, the 21050 positively decodes and forwards downstream
VGA palette register writes. VGA palette register writes use I/O byte addresses 03C6h, 03C8h, and
03C9h. Bits <31:16> must be 0 while bits <15:10> may be any value. If VGA Snoop Mode is
enabled, the 21050 ignores any write transactions initiated on the secondary bus that use these three
addresses. The 21050 ignores read transactions from the primary bus that use these addresses, but
forwards upstream those initiated on the secondary bus.

The 21050 does not check byte enables when these I/O addresses are forwarded, but forwards byte
enables as generated by the initiator. The VGA Palette Snoop Mode should not be used with VGA
mode. However, if both bits are set, VGA Mode behavior is used.

4.8 Latency
Under normal data transfer conditions, there will be two PCI clock cycles of delay between data
driven on one PCI bus and data driven on the opposite bus. Increased latency occurs after the
address phase of a transaction, with the exception of posted writes because the 21050 must gain
access to the target bus and detect a response from the target before any data transfers may proceed.
This latency increases for every level of PCI-to-PCI bridging that the transaction uses. If the 21050
target wait timer is enabled and expires before the 21050 gains access to the target bus, the 21050
performs a target retry to the initiator and deasserts its request for the target bus.

For multiple burst read or write transactions, data transfers may occur on every PCI clock cycle.
Data buffering in the 21050 allows it to hide the effects of 21050 latency on throughput. With the
exception of the first data phase, the total length of all stall conditions remains the same on both the
initiator and target buses. No extra stall cycles are added as a result of 21050 latency. Due to 21050
latency and prefetching, up to four extra reads from the target may be performed at the end of a
prefetched read transaction.

4.8.1 Master Latency Timer

The 21050 implements two programmable master latency timers.
• The primary master latency timer–used when the 21050 acts as an initiator on the primary PCI
bus.

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• The secondary master latency timer–used when the 21050 acts as an initiator on the secondary
PCI bus.

The appropriate master latency timer is started when the 21050 asserts yframe_l. If the master
latency timer expires and the bus grant is deasserted, the initiator must deassert yframe_l at the
beginning of the next data phase, with the possible exception of memory write and invalidate
transactions. If the grant is still asserted when the latency timer expires, the initiator may retain
control of the bus and continue the transaction until the grant deasserts.

Upon termination of the target bus transaction, due to master latency timer expiration, the 21050:
• For a read, returns a target disconnect to the initiator when the last dword read from the target
is driven on the initiating bus.
• For posted memory write, allows the initiator to continue posting data until the write buffer is
full, and then returns a target disconnect. Write data is delivered to the target with subsequent
memory write transactions initiated by the 21050.
• For a memory write and invalidate, performs no extra action because the initiator may
terminate these transactions only on cache line boundaries. The 21050 always terminates a
memory write and invalidate on the first cache line boundary.

4.8.2 Target Wait Timer

The 21050 implements two programmable target wait timers, one for the primary interface and one
for the secondary interface. The appropriate timer is started when the 21050 asserts xdevsel_l to the
initiator. If the 21050 is waiting for access to the target bus before the transaction can proceed on
the initiator bus, the target wait timer is expired, and the 21050 does not have the target bus grant,
the 21050 deasserts its request for the target bus and returns a target retry on the initiator bus.

If the target wait timer expires and the 21050 has the bus grant but cannot yet start the transaction
because the target bus is still busy, no action occurs and the 21050 may continue with the
transaction. However, if the grant is subsequently deasserted before the 21050 can start its
transaction, the 21050 must deassert its request and return a target retry to the initiator.

The maximum value for this timer is 28 PCI cycles, which is approximately 7.6 microseconds for a
33-megahertz system. This feature is disabled if the register contains a value of 0.

4.8.3 Burst Limit Counter

The 21050 provides a programmable burst limit counter. This allows the user to limit the number of
data transfers per transaction. For example, the user may wish to use the burst limit counter to limit
power dissipation for thermal reasons. Data bursts can be limited to 1 to 64 bursts per transaction.
A value of 0 in this register places no burst limit on transactions. If the burst counter expires during
a transaction, then the 21050 terminates the transaction normally on the target bus by deasserting
yframe_l, and returns a target disconnect to the initiator.

The burst counter applies to both upstream and downstream transactions.

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4.9 Deadlock Avoidance

The following rules apply to transactions that cross the 21050:
• In most cases, the current transaction crossing the 21050 must be complete on both interfaces
before the next transaction to be forwarded can proceed. However, there are some exceptions:
— Posted writes may be transferred to the 21050 on both interfaces simultaneously, although
data is driven to the target on one interface at a time.
— Configuration access to 21050 configuration space will be allowed to proceed if an
upstream posted write is in progress or if there is data in upstream write buffers.
• If transactions initiated close to the same time on both the primary and secondary buses are
intended for targets on the opposite interface, and at least one of the transactions is not a
postable write,
— The transaction initiated first is forwarded across the 21050, and the 21050 performs a
target retry in response to the second transaction.
— If both transactions are initiated during the same PCI cycle, the transaction initiated on the
primary bus is forwarded across the 21050, and the 21050 performs a target retry in
response to the secondary bus transaction.

4.9.1 Read Operations

For all read operations, if a read is already initiated on one PCI bus intended for a target on the
opposite PCI bus, and a second transaction, also intended to cross the 21050, is initiated on the
opposite bus before the read occurs, the 21050 issues a retry to the initiator of the second transaction.

4.9.2 Posted Write Operations

For posted write transactions, in order to prevent potential deadlock conditions in a hierarchical PCI
bus environment, the 21050 allows memory write data to be posted simultaneously in both directions.

If the target bus is not idle by the time the write buffer fills, the write transaction is disconnected.
This applies to both the upstream and the downstream transactions.

4.9.3 Non-Posted Write Operations

For all non-posted write operations, if a non-posted write is already initiated on one PCI bus
intended for a target on the opposite PCI bus, and a second transaction, also intended to cross the
21050, is initiated on the opposite bus before the non-posted write occurs, the 21050 issues a retry
to the initiator of the second transaction.

4.10 Data Synchronization

Data synchronization should be handled by the device or device driver as described in the PCI
Specification. The 21050 cannot guarantee that write buffers are flushed before interrupts are
delivered to the processor. However, the 21050 does implement two external pins, s_bufne_l and
s_dispst_l, which may aid in data synchronization. These pins indicate buffer empty status and
control write posting (Section 4.16).

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4.11 Exclusive Access

The 21050 supports the resource lock mechanism to achieve exclusive access to a target for
transactions that cross the 21050. Primary and secondary bus lock mechanisms are assumed to be
concurrent, except when a locked transaction crosses the 21050.

4.11.1 Acquiring Exclusive Access

If the initiator wants to create a lock on a target on the other side of the 21050, the initiator must
first gain access to the xlock_l signal on its bus.

A lock is gained on the initiating bus when the initiator:

• Acquires access to the initiator bus while xlock_l is deasserted
• Deasserts xlock_l during the address phase of the transaction
• Asserts xlock_l one cycle later
After the initiator gains the lock on its bus, the 21050 attempts to gain access to ylock_l on the
target bus. The 21050 must:
• Acquire access to the target bus while ylock_l is deasserted
• Deassert ylock_l during the address phase of the transaction
• Assert ylock_l one cycle later

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Note that, in accordance with the PCI Specification, the first transaction of a locked sequence must
be a read. Figure 4-17 shows a downstream read with lock acquisition.
Figure 4-17. Memory Read with Lock Acquisition

p_clk

p_ad<31:0> Addr Data

p_cbe_l<3:0> 6 0

p_frame_l

p_irdy_l

p_lock_l

p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> Addr Data

s_cbe_l<3:0> 6 0

s_frame_l

s_irdy_l

s_lock_l

s_trdy_l

s_devsel_l

LJ-03298.AI4

For a locked transaction involving a dual address transaction, the xlock_l signal should deassert
during the first address phase, and reassert at the start of the second address phase.

If a target retry, target abort, or master abort occurs in response to the first transaction in a locked
sequence before any data is transferred, the initiator must relinquish the lock by deasserting
xlock_l. This implies that, if the intended target returns a target retry or target abort, causing the
21050 to relinquish the lock on the target bus, this target termination must be passed back to the
initiator in order to force the initiator to relinquish the lock on the initiator bus. Because the first
transaction of a locked series of transactions is a read, the 21050 normally performs this action.

In some situations, the 21050 causes a target retry to occur in response to a lock acquisition
transaction by the initiator, causing the initiator to relinquish the bus:
• The 21050 chip is already forwarding another transaction.
• The ylock_l signal on the target bus is asserted, indicating that another initiator has control of
the lock on the target bus (Figure 4-18).
• The target wait timer expires before access to the target bus is gained.

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Figure 4-18 shows a target retry due to the target bus lock being busy.

If the 21050 detects a master abort on the target bus, this condition is returned to the initiator bus as
either normal termination or a target abort. If a target abort is returned, the initiator relinquishes the
lock. If normal termination occurs, then the initiator should recognize that the FFFFFFFFh read
data condition indicates a master abort; otherwise the initiator might retain possession of the lock
until the locked sequence ends.
Figure 4-18. Read with Lock Acquisition Attempt

p_clk

p_ad<31:0> Addr

p_cbe_l<3:0> 6 0

p_frame_l

p_irdy_l

p_lock_l

p_stop_l

p_trdy_l

p_devsel_l

s_clk

s_ad<31:0>

s_cbe_l<3:0>

s_frame_l

s_irdy_l

s_stop_l

s_lock_l

s_trdy_l

s_devsel_l

LJ-03301.AI4

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4.11.2 Maintaining Exclusive Access

After a lock is achieved on both buses, it must be maintained on both buses until the initiator
relinquishes the lock or until a master abort or target abort is detected on any locked transaction. A
transaction is considered a locked transaction when the initiator deasserts xlock_l at the start of the
address cycle, then asserts xlock_l one phase later.

Figure 4-19 shows a downstream memory write with lock continuation.

The 21050 always relinquishes the lock on the target bus upon detection of the master abort
condition. After a lock is established, if a master abort occurs on a subsequent locked write, then
the 21050 relinquishes the lock on the target bus and the target becomes unlocked. However, if the
21050 is in default master abort mode, then the initiator can keep xlock_l asserted on the initiator
bus because the initiator does not know the transaction on the target bus resulted in a master abort.
The only effect this should have is to tie up the xlock_l signal longer than necessary. If the 21050 is
configured to return target abort when a master abort is detected, both initiator and 21050 will
relinquish the initiator and target bus locks.
Figure 4-19. Downstream Memory Write with Lock Continuation

p_clk

p_ad<31:0> Addr Data1

p_cbe_l<3:0> 7 0

p_frame_l

p_irdy_l

p_lock_l

p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> Addr Data1

s_cbe_l<3:0> 7 0

s_frame_l

s_irdy_l

s_lock_l

s_trdy_l

s_devsel_l

LJ-03299.AI4

Target aborts are passed back to the initiator for all transactions, as posted writes are not allowed
when the target bus is locked. To prevent deadlocks when locks are in use, all writes are not
postable as long as ylock_l on the target bus is asserted. This allows the 21050 to:
• Pass back any target aborts, so the lock can be relinquished on the initiator bus.

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• To detect master aborts on the secondary bus and cause the initiator to relinquish the lock. The
21050 can be configured to return a target abort on the initiator bus when a master abort is
detected. When in this mode, a master abort that is returned to the initiator as a target abort,
will cause the initiator to relinquish the lock.
• To pass back any target retries to the initiator of the transaction, and allows the initiator that
has locked the target to forward transactions across the 21050 to the locked target. This
prevents deadlock if a different initiator attempts to access a locked target across the 21050
when posted write and write data are stranded in write buffers.

4.11.3 Ending Exclusive Access

Exclusive access is terminated when the xlock_l is deasserted at the end of a transaction.
Deassertion of xlock_l must occur no earlier than the first cycle where xframe_l and xirdy_l are
deasserted, ending the transaction. The xlock_l signal can be deasserted after this point, and should
be deasserted as soon as possible.

When exclusive access is terminated on the last data phase of a transfer, the 21050 may not be able
to release the lock on the target bus until two cycles after the deassertion of xlock_l on the initiator
bus. This delay is due to the 2-clock-cycle latency of the 21050. Therefore, the ylock_l might stay
asserted for a few cycles after completion on the last data phase on the target bus.

Figure 4-20 shows a memory write which ends a series of locked transactions.

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Figure 4-20. Memory Write with End of Lock

p_clk

p_ad<31:0> Addr Data

p_cbe_l<3:0> 7 0

p_frame_l

p_irdy_l

p_lock_l

p_trdy_l

p_devsel_l

s_clk

s_ad<31:0> Addr Data

s_cbe_l<3:0> 7 0

s_frame_l

s_irdy_l

s_lock_l

s_trdy_l

s_devsel_l

LJ-03300.AI4

4.11.4 21050 as a Locked Target

The 21050 does not support lock as an intended target.

4.12 Error Handling

The 21050 implements the data parity error signals p_perr_l and s_perr_l on both interfaces, and
also implements the address parity and system error signals p_serr_l and s_serr_l on both
interfaces. This section describes parity checking and generation, as well as the different conditions
under which p_serr_l is asserted.

4.12.1 Address Parity Errors

If the 21050 detects an address parity error on either interface, then the 21050:
• Does not respond as a target to the transaction.

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• Sets the Detected Parity Error bit in the Status register that corresponds to the interface where
the parity error was detected.
• Asserts p_serr_l and set the Signaled System Error bit in the Primary Status register if:
— The p_serr_l Driver Enable is set.
— The Parity Error Response bit is set in the Command register (if detected on the primary
interface) or the Bridge Control register (if detected on the secondary interface).
— For secondary bus address parity errors, the SErr Forward Enable bit is set in the Bridge
Control register.

4.12.2 Data Parity Errors on Initiator Bus

If the 21050 detects a data parity error during a write transaction on the initiator bus, then the
21050:
• Sets the detected Parity Error bit in the Status register that corresponds to the initiator bus.
• Asserts xperr_l if the Parity Error Response bit is set in the Command register (if the primary
bus is the initiator bus) or the Bridge Control register (if the secondary bus is the initiator bus).
• Continues with the transaction.
• If a write transaction, forwards the bad parity condition with corresponding data to the target
bus so that the target device is aware of the bad parity.

4.12.3 Data Parity Errors on Target Bus

If the 21050 detects a data parity error during a read operation on the target bus, then the 21050:
• Sets the Detected Parity Error bit in the Status register that corresponds to the target bus.
• Asserts yperr_l if the Parity Error Response bit is set in the Command register (if the primary
bus is the target bus) or the Bridge Control register (if the secondary bus is the target bus).
• Sets the Data Parity Reported bit in the Status register that corresponds to the target bus if the
Parity Error Response bit is set.
• Returns the bad parity with the corresponding read data back to the initiator.
• Continues with the transaction normally.
If the 21050 detects yperr_l asserted during a write operation on the target bus, the 21050 sets the
Data Parity Reported bit in the Status register that corresponds to the target bus if the Parity Error
Response bit is set.

If the transaction is a non-posted write and a data parity error is signaled, if possible, the 21050
asserts xperr_l on the initiator bus two cycles after write data is transferred from the initiator, if the
Parity Error Response bit that corresponds to the initiator bus is set. If the timing of the transaction
prevents assertion of xperr_l on the initiator bus, the 21050 asserts p_serr_l if:
• The Parity Error Response bit corresponding to the target bus is set.
• The p_serr_l Driver Enable bit is set.
• The serr disable for posted write parity errors is not set.

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If the transaction is a posted write, then the 21050 asserts p_serr_l and set the Signaled System
Error bit in the Primary Status register if:
• The Parity Error Response bit corresponding to the target bus is set.
• The p_serr_l Driver Enable bit is set.
• The serr disable for posted write parity errors is not set.
In this case, the 21050 cannot pass back bad parity (because it is a write) or assert xperr_l during
the proper cycle (because data is posted).

Table 4-4 lists parity error signaling for transactions that are forwarded.

Table 4-4. Data Parity Errors Signals for Forwarded Transactions

Parity Error
Transaction Initiator Bus Target Bus Primary Bus
Detected on
Target bus — yperr_l2 p_serr_l1,4
Posted write
Initiator bus xperr_l1 yperr_l2,3 —
Non-posted Target bus xperr_l1,5 yperr_l2,3 p_serr_16
write Initiator bus xperr_l1 yperr_l —
Target bus xperr_l3,7 yperr_l1 —
Any read
Initiator bus xperr_l7 — —
1.
Signal asserted by 21050.
2.
Signal asserted by target.
3.
Asserted because bad parity is passed with data across the 21050.
4.
serr disable for this event must be clear to assert p_serr_l.
5.
If timing allows, otherwise assert p_serr_l.
6.
If xperr_l cannot be asserted.
7.
Signal asserted by initiator.

4.12.4 Other Errors

The 21050 may be configured to assert p_serr_l for a variety of error conditions:
• A yperr_l assertion on target bus is detected during posted write transaction.
• Inability to deliver posted write data after 224 attempts, as a result of target retry or disconnect.
• A target abort is detected during a posted write transaction.
• A master abort is received during a posted write transaction.

Each condition has a corresponding disable bit in the serr disable register, that, when set, prevents
p_serr_l from asserting when that condition occurs.

The 21050 has a s_serr Forward Enable bit in the Bridge Control register which allows forwarding
of s_serr_l to p_serr_l. The 21050 sets the Detected System Error bit in the secondary status
register and the signaled system error bit in the primary status register. The 21050 does not assert
s_serr_l.

The p_serr_l Driver Enable bit must be set in the command register for the signal to be driven for
any reason. If the 21050 drives p_serr_l, it also sets the Signaled System Error bit in the Primary
Device Status register.

When the p_serr_l signal is detected as asserted, the condition that caused the assertion may be
decoded by checking the conditions listed in Table 4-5.

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Table 4-5. p_serr_l Assertion Conditions

p_serr_l Assertion Condition Asserted Status Bits

Signaled System Error in primary status register and

s_serr_l detected as asserted
Detected System Error in secondary status register
Signaled System Error in primary status register and
xperr_l detected on target bus during posted write Detected Parity Error in either primary or secondary
status register
Signaled System Error in primary status register and
Unable to deliver posted write data after 224 attempts no other serr-related status bits asserted in the 21050
or in secondary bus devices
Signaled System Error in primary status register and
Target abort detected during posted write Received Target Abort in either primary or secondary
status register
Signaled System Error in primary status register and
No target response during posted write Received Master Abort in either primary or secondary
status register

4.13 PCI Bus Arbitration

This section describes the primary and secondary PCI bus arbitrations.

4.13.1 Primary PCI Bus Arbitration

The primary bus arbitration interface is a single request output and a grant input. The 21050 does
not implement any centralized arbitration functions for the primary bus. The 21050 initiates
transactions on the primary bus on behalf of initiators on the secondary bus.

The 21050 asserts p_req_l when it needs to forward a transaction upstream. During the cycle
immediately after the 21050 detects an asserted level on p_gnt_l and the primary bus is idle, the
21050 starts the transaction on the primary bus by:
• Asserting p_frame_l
• Driving the address on p_ad<31:0>
• Driving the command on p_cbe_l<3:0>
• Deasserting p_req_l

The 21050 may deassert p_req_l at any time before starting a transaction, for example, due to
expiration of the target wait timer.

The 21050 performs bus parking duties (driving p_ad, p_cbe_l, and p_par when the bus is idle)
only when p_gnt_l is asserted and p_req_l is deasserted.

4.13.2 Secondary PCI Bus Arbitration

The secondary bus central function pin, s_cfn_l, determines whether the 21050 performs
arbitration for access to the secondary PCI bus. If asserted low, the 21050 performs arbitration.
Otherwise, arbitration is assumed to be performed externally.

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The secondary PCI arbitration function can support up to six bus masters, in addition to the 21050.

The 21050 includes itself in the arbitration for those transactions in which it is acting on behalf of
an initiator on the primary bus. Because the primary and secondary buses operate concurrently,
grants are given out independently of the status of the primary bus, and independently of the
primary bus arbitration scheme. However, for all transactions that cross the 21050 except posted
writes, both the primary and secondary buses must be acquired before data transfers on either bus
can proceed.

4.13.2.1 Secondary Bus Arbiter Protocol

The arbiter re-assigns priorities every time s_frame_l is asserted (every time a new transaction
starts). This starts a new arbitration cycle. From this point until the next transaction starts, the
arbiter asserts the grant signal that corresponds to the highest priority request that is asserted.

If a grant for a particular request is asserted and a higher priority request subsequently asserts, then
the arbiter deasserts the asserted grant signal and asserts the grant that corresponds to the new
higher priority request on the next PCI clock cycle.

If the secondary PCI bus is busy (either s_frame_l or s_irdy_l is asserted), then the arbiter may
deassert one grant and assert another grant during the same PCI clock cycle. If the secondary PCI
bus is idle, then the arbiter never asserts a grant signal in the same PCI cycle that it deasserts
another. If it deasserts one grant, it asserts the next grant no earlier than one PCI clock cycle later.

If the 21050 detects that an initiator has failed to assert s_frame_l after 16 cycles of both grant
assertion and an idle bus condition, the arbiter deasserts the grant. That initiator does not receive
any more grants until it deasserts its request for at least one PCI clock cycle.

4.13.2.2 Priority Schemes

The 21050 offers two priority schemes that can be selected by using the Arbitration Mode Select
bit in the Chip Control register.

Alternating Mode

The default priority scheme selected upon reset gives the 21050 highest priority on alternate
arbitration cycles. This mode is selected when the Arbitration Mode Select is low. For cycles
during which the 21050 does not have highest priority, the priority rotates evenly among the six
external request inputs.

Rotating Mode

If the Arbitration Mode Select bit is set, a simple rotating priority scheme is used, in which highest
priority rotates evenly between the seven request inputs (six external requests and the 21050
request).

4.13.2.3 Request Mask Timer

The 21050 implements a programmable request mask timer. If the 21050 issues a target retry in
response to a secondary bus initiator, the request mask timer is started. That secondary bus initiator
request is then masked for the number of PCI cycles programmed in the request mask timer which
is contained in the Chip Control register in 21050 configuration space. When the timer expires, that

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initiator’s bus request may again be serviced. If a target retry is subsequently returned by the 21050
to another secondary bus initiator before expiration of the request mask timer, the latter’s bus
request is masked only for the number of PCI cycles remaining in the timer.

4.13.2.4 Secondary Bus Arbiter Disabled

If s_cfn_l is tied high, it is assumed that secondary bus arbitration is performed externally to the
21050 and the secondary bus arbiter is disabled. The 21050 then reconfigures the following:
• s_gnt_l<0> as secondary bus request output
• s_req_l<0> as secondary bus grant input
• s_gnt_l<5:1> outputs deasserted
• s_req_l<5:1> inputs ignored

In this case, the 21050 secondary arbitration interface protocol is similar to the primary arbitration
interface protocol.

4.13.2.5 Secondary Bus Parking

If s_cfn_l is asserted low, the 21050 by default drives s_ad, s_cbe_l and s_par when the secondary
bus is idle. If s_cfn_l is deasserted, the 21050 only drives these signals if s_req_l<0>, configured as
the 21050 external grant, is asserted.

Note: The s_cfn_l signal should be tied high or low through a resistive device since the input is connected
to the diagnostic Nand tree and must be toggled during Nand tree testing.

4.14 Clocks
The 21050 has two clock inputs. The p_clk signal is referenced to the primary interface. All
primary PCI bus signals are driven and sampled with p_clk. The s_clk signal is used by the
secondary interface. All secondary PCI bus signals are driven and sampled with s_clk.
• Both clocks operate at the same frequency and are synchronous to each other.
• The maximum clock skew between p_clk and s_clk is no greater than 7 nanoseconds.
• The minimum clock skew between p_clk and s_clk is no less than 0 nanoseconds.
• The maximum operating frequency of the clocks is 33 Megahertz.

Figure 4-21 shows the relative timing.

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Figure 4-21. p_clk and s_clk Relative Timing

t t
skew skew

p_clk

s_clk

LJ-03238.AI4

The 21050 provides seven outputs, s_clk_o<6:0>, which can be used as secondary clock outputs.
• One of these outputs can be fed back into the s_clk input of the 21050.
• The other six clock outputs can be used as clock inputs for secondary bus devices. If these
clock outputs are used for clock distribution, the s_clk input must still meet the timing
requirements listed in Chapter 7.0.

Here are suggested guidelines for using the secondary clock outputs:
• Secondary clocks should not be used to drive option card clocks or as a clock input to another
21050 chip.
• Secondary clock delay external to the 21050 should not exceed 2 nanoseconds.

4.15 Reset
This section describes the primary, secondary, and chip reset bits.

4.15.1 Primary Reset

The 21050 has one reset input, p_rst_l. When asserted, p_rst_l causes the 21050 to immediately
tristate all primary and secondary PCI interface signals. The 21050 resets all registers to 0 and
clears all write buffers, unless designated otherwise (Chapter 5.0). The p_rst_l asserting and
deasserting edges may be asynchronous to p_clk and s_clk.

4.15.2 Secondary Reset

The 21050 is responsible for driving the secondary reset signal. There are three conditions during
which s_rst_l can be asserted:
• When p_rst_l is asserted.
The s_rst_l remains asserted as long as p_rst_l is asserted.
• When the Secondary Reset bit in the Diagnostic Control register is set.
The s_rst_l signal remains asserted until the Secondary Reset bit is cleared by a configuration
write.

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• When the Chip Reset bit in the Diagnostic Control register is set, s_rst_l remains asserted until
the Secondary Reset bit is cleared by a configuration write.

When s_rst_l is asserted, s_ad, s_cbe, and s_par are immediately tristated and then driven low
within a couple of clock cycles, while all other secondary interface signals are tristated. The 21050
still responds to accesses to its configuration space on the primary interface. Write buffers in both
directions are cleared.

4.15.3 Chip Reset

The 21050 can be reset by setting the Chip Reset bit in the Diagnostic Control register. As soon as
the chip reset is completed, the Chip Reset bit is automatically cleared within six PCI clock cycles
and the chip is ready for configuration. While the chip is in reset, the 21050 is inaccessible for any
type of transaction to or across it.

4.16 Buffer Control

The 21050 implements one input, s_dispst_l, and one output, s_bufne_l, on the secondary interface
that controls write buffer posting.

When an asserted value of s_dispst_l is detected, the 21050 asserts s_bufne_l two cycles later if
write data exists in either upstream or downstream data buffers. As long as write data that was in
the write buffers at the time of s_dispst_l assertion remains in the write buffers, s_bufne_l remains
asserted. s_bufne_l does not reflect status of data that was posted subsequent to s_dispst_l
assertion. After the data that was in the write buffers at the time of the s_dispst_l assertion is
flushed, the 21050 deasserts s_bufne_l.

The 21050 can be configured to disable posting by setting the Disable Posting bit in the Chip
Control register after s_dispst_l is asserted. In this case, posting remains disabled until s_dispst_l is
deasserted. While posting is disabled, all writes must wait for target response before transferring
data from the initiator, and are disconnected after one data transfer.

If the 21050 is configured so that posting is not disabled, the 21050 continues to accept posted
writes in the normal manner, even during assertion of s_dispst_l. If no external control of bridge
write posting is necessary, s_dispst_l should be tied high.

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5.0 Configuration Register Description

This chapter provides programmer reference material for all 21050 configuration space registers.
Configuration space registers include the predefined PCI device and 21050 registers, as well as
other implementation-specific registers used during initialization. All registers located in
configuration space are accessible only from the primary bus interface of the 21050. Figure 5-1
shows a configuration space map.
Figure 5-1. Configuration Space Map

31 16 15 00

Device ID Vendor ID 00h

Primary Interface Status Primary Interface Command 04h

Class Code Revision ID 08h

Reserved Header Type Primary Latency Cache Line Size 0Ch

Timer

Reserved 10h

Reserved 14h

Secondary Subordinate Bus Secondary Bus Primary Bus 18h

Latency Timer Number Number Number

Secondary Interface Status I/O Limit Address I/O Base Address 1Ch

Memory Limit Address Memory Base Address 20h

Prefetchable Memory Limit Address Prefetchable Memory Base Address 24h

Reserved 28h

Reserved 2Ch

Reserved 30h

Reserved 34h

Reserved 38h

Bridge Control Interrupt Pin Reserved 3Ch

SErr Event Disable Burst Limit Counter Diagnostic Control Chip Control 40h

Secondary Target Primary Target 44h

Reserved Wait Timer Wait Timer

Secondary Write Attempt Counter 48h

Primary Write Attempt Counter 4Ch

50h -
Reserved FFh

LJ-03284.AI4

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5.1 Predefined Header Space Register Description

This section provides a detailed description of predefined configuration space registers in the 21050.

5.1.1 Device ID and Vendor ID Register

This section describes the device ID and vendor ID register.

31 16 15 00

h Device ID Vendor ID

LJ-03240.AI4

Table 5-1. Device ID and Vendor ID Register

Address 00 hex —
Access <31:0> Read only.
Device ID identifies this device as the 21050 and is internally hardwired to
Field description <31:16>
be 0001h.
The Vendor ID identifies the vendor of this device and is internally hard
<15:0>
wired to be 1011h.

5.1.2 Primary Status and Primary Command Register

This section describes the primary status and primary command register.

31 16 15 00

04h Primary Status Primary Command

LJ-03241.AI4

Table 5-2. Primary Status and Primary Command Register (Sheet 1 of 2)

Address 04 hex —
Access <31:27> Read/write-1-to-clear.
<26:25> Read only.
<24> Read/write-1-to-clear.
<23> Read only.
<22:9> Read only as 0.
<8:5> Read/write.
<4:3> Read only.
<2:0> Read/write.
Field description <31> Detected Parity Error on primary bus.
<30> Signaled System Error on primary bus.
<29> Received Master Abort on primary bus.
<28> Received Target Abort on primary bus.
<27> Signaled Target Abort on primary bus.

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Table 5-2. Primary Status and Primary Command Register (Sheet 2 of 2)

p_devsel_l timing for the 21050 acting as target on primary bus. Set to 01b
<26:25>
to designate medium timing.
Data Parity Detected. Set when the 21050 is acting as a master on the
primary bus, p_perr_l is detected as asserted, or a parity error is detected
<24>
on the primary bus, and the Parity Error Response bit in the primary
command register is set.
Fast back-to-back capable. Reads only as a 1 to indicate that the 21050 can
<23>
respond to fast back-to-back transactions on the primary bus.
<22:10> Reserved. Reads only as 0.
Fast back-to-back control. Reads only as 0 to indicate that the 21050 will
<9>
not perform fast back-to-back accesses to targets on the primary bus.
p_serr_l driver enable. If high, the 21050 can drive p_serr_l. If low, the
<8>
p_serr_l driver is disabled. Reset to 0.
Wait Cycle Control. Reads only as 0 to indicate that the 21050 does not do
<7> address stepping, with the exception of downstream Type 1 to Type 0
configuration transactions.
Parity error response. When this bit is low, parity checking is disabled on the
<6>
primary bus interface. Reset to 0.
VGA Snoop Enable. If set, enables VGA snooping for the 21050. The 21050
<5> positively decodes VGA palette register I/O writes and ignores palette
register I/O reads.
<4:3> Reserved. Read only as 0.
Master enable. When set high, 21050 can act as a master on the primary
<2>
bus. Reset to 0.
Memory transaction target enable. When set high, the 21050 can respond
<1>
as a target to memory transactions on the primary bus. Reset to 0.
I/O Transaction target enable. When set high, the 21050 can respond as a
<0>
target to I/O transactions on the primary bus. Reset to 0.

5.1.3 Class Code/Programming Interface/Revision ID Register

This section describes the class code/programming interface/revision ID register.

31 24 23 16 15 08 07 00

08h Base Class Code Sub-Class Code Prog. Interface Revision ID

LJ-03242.AI4

Table 5-3. Class Code/Programming Interface/Revision ID Register

Address 08 hex —
Access <31:0> Read only.
Base class code of the device. Reads as 06h to indicate that it is a 21050
Field description <31:24>
device.
Sub-class code of the device. Reads as 04 hex to indicate that device is a
<23:16>
21050.
<15:8> Programming interface of the device. Reads as all 0’s.
<7:0> Revision ID for the 21050.

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5.1.4 Primary Master Latency Timer/Cache Line Size/Header Type

This section describes the primary master latency timer (MLT)/cache line size/header type register.

31 24 23 16 15 08 07 00

0Ch Reserved Header Type Primary MLT Cache Line Size

LJ-03243.AI4

Table 5-4. Primary Master Latency Timer/Cache Line Size/Header Type Register
Address 0C hex —
Access <31:24> Reads only as 0’s.
<23:16> Read only.
<15:11> Read/write.
<10:8> Read only as 0’s.
<7:0> Read/write.
Field description <31:24> Reserved. Reads as all 0’s.
Header type. Defines the layout of addresses 10 hex through 3F hex in
<23:16> configuration space. Reads only as 01 hex to indicate that the register
layout conforms to the PCI-PCI bridge layout.
Master latency timer for primary interface. Designates the maximum
number of PCI clock cycles from the assertion of p_frame_l until the
<15:8>
expiration of the timer. The lower 3 bits are read only, giving a granularity of
eight PCI clock cycles. If 0, the timer is not used. Reset to 0.
Cache line size. Designates the cache line size for the system in units of
32-bit words. The cache line size is restricted to be a power of 2. The most
significant 1 in the cache line size register is used to set the cache line size.
<7:0>
Any other 1’s are ignored. Used when terminating memory write and
invalidate transactions and when prefetching during memory read type
transactions. Reset to 0.

5.1.5 Reserved Registers (10-14 Hex)

This section describes the reserved registers (10-14 hex).

31

10h Reserved

14h Reserved

LJ-03244.AI4

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Table 5-5. Reserved Registers (10–14 Hex)

Address 10–14 hex —
Access — Reads only as 0’s.
Field description — All registers are reserved and read as 0’s.

5.1.6 Primary Bus Number/Secondary Bus Number/Subordinate Bus

Number/Secondary Master Latency Timer Register
This section describes the primary bus number/secondary bus number/subordinate bus
number/secondary master latency timer register.

31 24 23 16 15 08 07 00

18h Sec. MLT Subord. Bus No. Sec. Bus No. Pri. Bus No.

LJ-03245.AI4

Table 5-6. Primary Bus Number/Secondary Bus Number/Subordinate Bus Number/Secondary

Master Latency Timer
Address 18 hex —
Access <31:27> Read/write.
<26:24> Read only as 0.
<23:0> Read/write.
Master Latency Timer for secondary interface. Designates the maximum
number of PCI clock cycles from the assertion of s_frame_l until the
Field description <31:24>
expiration of the timer. The lower 3 bits are read only, giving a granularity of
eight PCI clock cycles. If 0, the timer is not used. Reset to 0.
The subordinate bus number. Defines the inclusive upper limit of a range of
<23:16> bus numbers. This range determines whether configuration accesses are to
be forwarded across the 21050 to the secondary bus. Reset to 0.
The secondary bus number. Enables accesses to configuration space of a
hierarchical PCI bus. If matched to a number driven during the Type 1
<15:8> address cycle on the primary bus, the access is for a device on the
secondary bus. Also provides the non-inclusive lower limit for the bus
number range described above. Reset to 0.
Primary bus number. Designates the primary bus. Used to decode Type 1
<7:0> configuration cycles initiated on the secondary bus intended for special
cycle generation on the primary bus. Reset to 0.

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5.1.7 I/O Base Address/I/O Limit Address/Secondary Status Register

This section describes the I/O base address/I/O limit address/secondary status register.

31 16 15 08 07 00

1Ch Secondary Status I/O Lim. Address I/O Base Address

LJ-03247.AI4

Table 5-7. I/O Base Address/I/O Limit Address/Secondary Status Registers (Sheet 1 of 2)
Address 1C hex —
Access <31:27> Read/write-1-to-clear.
<26:25> Read only.
<24> Read/write-1-to-clear.
<23> Read only.
<22:16> Read only as 0.
<15:12> Read/write.
<11:8> Read only as 0.
<7:4> Read/write.
<3:0> Read only as 0.
Field description <31> Detected Parity Error on secondary bus.
<30> Detected System Error on secondary bus – s_serr_l detected asserted.
<29> Received Master Abort on secondary bus.
<28> Received Target Abort on secondary bus.
<27> Signaled Target Abort on secondary bus.
s_devsel_l timing for the 21050 acting as target on secondary bus. Set to
<26:25>
01b to designate medium timing.
Data Parity Detected. Set when the 21050 is acting as a master on the
secondary bus, and s_perr_l is detected as asserted, or a parity error is
<24>
detected on secondary bus, and the Secondary Parity Response bit is set in
the 21050 control register.
Fast back-to-back capable. Reads only as 1 to indicate that the 21050 can
<23>
respond to fast back-to-back transactions on the secondary bus.

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Table 5-7. I/O Base Address/I/O Limit Address/Secondary Status Registers (Sheet 2 of 2)
<22:16> Reserved.
Contains bits <15:8> of the I/O limit address, or upper limit (inclusive), which
defines an address range used to determine whether to forward I/O
transactions from the primary to the secondary bus. Since the minimum
<15:8> I/O space is 4 kilobytes, the least-significant 4 bits are read only as 0h. The
16 most-significant bits of the address are assumed to be 0. The 12
least-significant bits of the address are assumed to be FFF hex. The
writable bits are reset to 0.
Contains bits <15:8> of the I/O base address, or lower address limit, which
defines an address range used to determine whether to forward I/O
transactions from one PCI bus to the other. Because the minimum I/O
<7:0>
space is 4 kilobytes, the least-significant 4 bits are read only. Both the 16
most-significant address bits and 8 least-significant address bits are
assumed to be 0. This register is reset to 0.

5.1.8 Memory Base Address/Memory Limit Address Register

This section describes the memory base address/memory limit address register.

31 16 15 00

20h Memory Limit Address Memory Base Address

LJ-03246.AI4

Table 5-8. Memory Base Address/Memory Limit Address Register

Address 20 hex —
Access <31:20> Read/write.
<19:16> Read only as 0.
<15:4> Read/write.
<3:0> Read only as 0.
Defines the most-significant 12 bits of the upper limit (inclusive) of the
memory address range. The minimum memory address range is 1 MB. The
least-significant 4 bits are reserved and read only as 0. The 20
Field description <31:16> least-significant bits of the memory limit address should be assumed to be
FFFFFh. For memory read transactions, the 21050 does not prefetch data
in this address range, and memory read transactions are limited to one data
burst. The writable bits are reset to 0.
Indicates the upper 12 bits of the base address, or lower address limit, of a
memory address range. This range is used to determine whether to forward
memory accesses across the 21050. The minimum memory address range
is 1 megabyte. The least-significant 4 bits are reserved and read only as 0.
<15:0>
The 20 least-significant bits of the memory base address should be
assumed to be 00000h. For memory read transactions, the 21050 does not
prefetch data in this address range, and memory read transactions are
limited to one data burst. This register is reset to 0.

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5.1.9 Prefetchable Memory Base Address/Prefetchable Memory Limit

Address Register
This section describes the prefetchable memory base address/prefetchable memory limit address
register.

31 16 15 00

24h Prefetchable Memory Limit Address Prefetchable Memory Base Address

LJ-03283.AI4

Table 5-9. Prefetchable Memory Base Addr./Prefetchable Memory Limit Addr. Register
Address 24 hex —
Access <31:20> Read/write.
<19:16> Read only as 0.
<15:4> Read/write.
<3:0> Read only as 0.
Define the most-significant 12 bits of the upper limit (inclusive) of the
memory address range. The minimum memory address range is 1
megabyte. The least-significant 4 bits are reserved and read only as 0.
Field description <31:16>
The 20 least-significant bits of the memory limit address should be
assumed to be FFFFFh. The 21050 prefetches data in this address
range. The writable bits are reset to 0.
Indicates the upper 12 bits of the base address, or lower address limit,
of a memory address range. This range is used to determine whether
to forward memory accesses across the 21050. The minimum memory
<15:0> address range is 1 megabyte. The least-significant 4 bits are reserved
and read only as 0. The 20 least significant bits of the memory base
address should be assumed to be 00000h. The 21050 prefetches data
in this address range. This register is reset to 0.

5.1.10 Reserved Registers (28-38 Hex)

This section describes the reserved registers (28-38 hex).

31 00

28h Reserved
:
: :
: :
: :
: :
: :
:
38h Reserved

LJ-03249.AI4

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Table 5-10. Reserved Registers (28–38 Hex)

Address 28h -- 38h —
Access — Read only as 0.
Field description — These registers are reserved and read only as 0’s.

5.1.11 Interrupt Pin/Bridge Control Register

This section describes the interrupt pin/bridge control register.

31 16 15 08 07 00

3Ch Bridge Control Interrupt Pin Reserved

LJ-03250.AI4

Table 5-11. Interrupt Pin/Bridge Controller Register (Sheet 1 of 2)

Address 3Ch —
Access <31:24> Reserved.
<23:21> Read/write.
<20> Read only as 0.
<19:16> Read/write.
<15:0> Read only.
Field description <31:26> Reserved. Read only as 0.
Fast back-to-back control. Reads only as zero to indicate that the 21050 will
<23>
not perform fast back-to-back accesses to targets on the secondary bus.
Secondary Bus Reset. When set high, the 21050 tristates secondary bus
outputs and immediately terminates any transactions involving the
secondary interface. The s_rst_l signal is asserted until this bit is cleared by
<22>
a configuration write. The primary bus interface is still active and the 21050
responds to accesses to its internal configuration state. The configuration
state is not cleared. All write buffers will be cleared.
Master Abort mode. When set, the 21050 signals a target abort to the
initiator when a master abort is detected for reads and non-posted writes. If
<21>
0, reads return FFFFFFFFh, and write data is transferred to the 21050 and
discarded. Reset to 0.
<20> Reserved. Read only as 0.
VGA Enable. When set, allows the 21050 to forward transactions
downstream directed at a VGA device (to memory addresses A0000h
through BFFFFh and to I/O addresses 03B0h through 03DFh except
<19>
3BCh–3BFh). These addresses are independent of the memory and
I/O ranges described by the memory base and address registers. Reset to
0.
ISA Enable for I/O transactions. When set, makes the 21050 ISA-aware.
When set, the 21050 blocks any forwarding of transactions addressing the
<18>
last 768 bytes in each 1-kilobyte chunk of I/O address space. Applicable to
I/O space within the I/O base and limit address registers only. Reset to 0.
s_serr_l forward enable. If high, allows forwarding of s_serr_l on secondary
<17>
address parity errors to the primary bus via assertion of p_serr_l. Reset to 0.

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Table 5-11. Interrupt Pin/Bridge Controller Register (Sheet 2 of 2)

Parity Error Response. When low, disables parity checking on the
<16>
secondary bus interface. Reset to 0.
Interrupt pin. Designates which interrupt signal the device uses. Reads only
<15:8>
as a 00h, because the 21050 does not generate an interrupt.
<7:0> Reserved. Read only as 0.

5.2 Implementation-Specific 21050 Register Descriptions

This section offers a detailed description of implementation-specific configuration registers.

5.2.1 Chip Control/Diagnostic Control/Burst Limit Counter/serr Disable

Register
This section describes the chip control/diagnostic control/burst limit counter/serr disable register.

31 16 15 00

40h SErr Disable Burst Counter Diag. Control Chip Control

LJ-03251.AI4

Table 5-12. Chip Control/Diagnostic Control/Burst Limit Counter/serr Disable Register (Sheet 1 of 2)
Address 40h —
Access <31:0> Read/write.
serr disable. When set, the following bits prevent p_perr_l from being
Field description <31:24>
asserted for the following conditions:
Bits Description
<31:29> Reserved
<28> Master abort on posted write
<27> Target abort during posted write
<26> Unable to deliver posted write data
<25> Bad data parity on target bus for posted write
<24> Reserved
Burst Limit Counter. Specifies the maximum number of data transfers that
can occur during any transaction. The top 2 bits are hard-wired to be 0,
<23:16>
leaving a maximum burst range from 1 to 64 data transfers. If 0, no burst
limits are applied. Reset to 0.
<15:13> Reserved. Read only as 0.
p_serr_l diagnostic mode assertion control. When set to 1, the 21050
<12> asserts the p_serr_l signal in response to all address phases on the primary
PCI bus. This bit should be used for diagnostic purposes only. Reset to 0.
s_perr_l diagnostic mode assertion control. When set to 1, the 21050
asserts the s_perr_l signal in response to all write data phases on the
<11>
secondary bus intended for the 21050 or a primary bus device. This bit
should be used for diagnostic purposes only. Reset to 0.

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Table 5-12. Chip Control/Diagnostic Control/Burst Limit Counter/serr Disable Register (Sheet 2 of 2)
p_perr_l diagnostic mode assertion control. When set to 1, the 21050
asserts the p_perr_l signal in response to all write data phases on the
<10>
primary bus intended for the 21050 or a secondary bus device. This bit
should be used for diagnostic purposes only. Reset to 0.
Test mode. Used for chip test. When set to 1, all counters greater than 4 bits
<9>
will be sub-divided into parallel 4 bit chunks by forced carry signals. Reset to 0.
Chip Reset. When set, the 21050 performs a chip reset. All configuration
registers are returned to their reset state and the 21050 must be
<8>
reconfigured. This bit is cleared by the chip upon completion of reset.
s_rst_l is asserted until the secondary reset bit is cleared.
<7:5> Reserved. Reads as 0.
Secondary bus prefetch disable. If not set, memory read transactions
initiated on the secondary bus use prefetching. If set, memory read
<4> transactions are disconnected after one data transfer. Memory read lines
and memory read multiple transactions always use prefetching and may
consist of multiple data transfers. Reset to 0.
Request mask timer. Designates the maximum value of the request mask
<3:2> timer, which is enabled after the 21050 issues a target retry to a master on
the secondary bus. Reset to 0.
00b—mask timer not used
01b—16 PCI clock cycles
10b—32 PCI clock cycles
11b—64 PCI clock cycles
Disable Posting Enable. If set, posting is disabled while s_dispst_l is
<1>
asserted. Reset to 0.
Secondary PCI bus arbitration mode select. When set, selects rotating
priority between all secondary bus requests. If not set, arbitration is also
<0>
rotating priority, except that the 21050 has highest priority on alternate
arbitration cycles. Reset to 0.

5.2.2 Primary Target Wait Timer/Secondary Target Wait Timer Register

This section describes the primary target wait timer/secondary target wait timer register.

31 16 15 08 07 00

44h Reserved Sec. Tar. Wait Tmr. Pri. Tar. Wait Tmr.

LJ-03248.AI4

Table 5-13. Primary Target Wait Timer/Secondary Target Wait Timer Register (Sheet 1 of 2)
Address 44h --
Access <31:16> Read only as 0’s.
<15:0> Read/write.

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Table 5-13. Primary Target Wait Timer/Secondary Target Wait Timer Register (Sheet 2 of 2)
Field
<31:16> Reserved. Read only as 0’s.
descriptions
Secondary interface target wait timer. A programmable register which
indicates the maximum number of PCI cycles that the 21050 waits to gain
access to the target (primary) bus for a transaction initiated on the
<15:8> secondary bus. If the timer expires before the 21050 receives a grant for the
primary bus, the 21050 issues a target retry to the initiator on the secondary
bus and deasserts its primary bus request. If 0, the 21050 waits indefinitely.
Reset to 0.
Primary interface target wait timer. A programmable register which indicates
the maximum number of PCI cycles that the 21050 waits to gain access to the
target (secondary) bus for a transaction initiated on the primary bus. If the
<7:0>
timer expires before the 21050 receives a grant for the secondary bus, the
21050 issues a target retry to the initiator on the primary bus and deasserts its
secondary bus request. If 0, the 21050 waits indefinitely. Reset to 0.

5.2.3 Secondary Write Attempt Counter Register

This section describes the secondary write attempt counter register.

31 00

Secondary Write Attempt Counter

LJ-03430-TI0

Table 5-14. Secondary Write Attempt Counter Register

Address 48h —
Access — Read only
A read-only register which shows the number of attempts that have been
Field description — made to empty data in the downstream write buffer. Used for diagnostic
purposes. Reset to 0.

5.2.4 Primary Write Attempt Counter Register

This section describes the primary write attempt counter register.

31 00

4Ch Primary Write Attempt Counter

LJ-03431.AI4

Table 5-15. Primary Write Attempt Counter Register

Address 4Ch —
Access — Read only
A read-only register which shows the number of attempts that have been
Field description — made to empty data in the upstream write buffer. Used for diagnostic
purposes. Reset to 0.

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5.2.5 Reserved Registers (50h-FFh)

This section describes the reserved registers (50h-FFh).

31 00

50h Reserved
:
: :
: :
: :
: :
: :
:
FFh Reserved

LJ-03252.AI4

Table 5-16. Reserved Registers (50h – FFh)

Address 50h - FFh —
Access — Read only as 0.
Field description — Reserved and read only as 0’s.

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6.0 Diagnostics and Test Mechanisms

This chapter provides testing and diagnostics information.

6.1 Test Pins and Nand Tree Implementation

The 21050 implements two pins for testing purposes.
• The goz_l pin, when asserted, tristates all bidirectional pins.
• The nand_out pin is the output of a serial Nand tree connecting all chip inputs, except p_clk and
s_clk. A pattern can be applied to chip inputs, and the nand_out pin verifies input pin interconnect.

When using the Nand tree test mechanism, all bidirectional signals must first be tristated by
assertion of goz_l. The goz_l signal should remain asserted for the duration of this test.

Note: Any inputs tied high or low, s_cfn_l for example, should be connected to power or ground through
a resistive device to allow use of the Nand tree feature.

The Nand tree begins at the s_dispst_l input and runs clockwise to p_rst_l, and then is output at
nand_out.

The suggested Nand tree test sequence is:

1. Drive goz_l low.
2. Drive each input and bidirectional pin high, with the possible exception of p_clk and s_clk.
(p_clk and s_clk are not included in the Nand tree).
3. Starting with pin 90 (s_dispst_l), individually drive each pin low; nand_out should toggle with
each pin. Proceed clockwise, driving each subsequent pin low.
4. Turn off tester drivers.
5. Drive goz_l high.
6. Reset chip before proceeding with further testing.

6.1.1 Diagnostic Control Register

The 21050 implements three bits for xperr_l and p_serr_l control in the Diagnostic Control
register, which exists in 21050 configuration space.

Note: These bits should never be set during normal chip operation or initialization.

When the xperr_l control bit is set, the 21050 returns xperr_l to the master of any write transaction
occurring on that bus. The 21050 asserts p_perr_l in response to all write transaction data phases
initiated on the primary bus and directed to or across the 21050 when the p_perr_l control bit is set.
Similarly, when the s_perr_l control bit is set, the 21050 asserts s_perr_l in response to all write
transaction data phases initiated on the secondary bus and directed across the 21050 chip.

When the p_serr_l control bit is set, the 21050 returns p_serr_l to the master in response to any
address phase occurring on the primary bus. The 21050 continues to respond to transactions, unless
a real address parity error is detected.

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 21050 PCI-to-PCI Bridge

The 21050 also implements a test mode bit in the Diagnostic Control register to facilitate chip fault
test. When set, all counters in excess of 8 bits are broken up into 4-bit chunks by a forced carry
signal. The 4-bit chunks of any particular counter will count in parallel when the chip is in test
mode. The test mode bit should not be set unless all 21050 state machines are idle, that is, there are
no transactions in progress across the 21050 chip.

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 21050 PCI-to-PCI Bridge

7.0 21050 Specifications

This chapter describes the mechanical and electrical specifications of the 21050.

7.1 Mechanical Specifications

The following sections describe the mechanical specifications of the 21050.

7.1.1 21050 Package

The 21050 PCI chip is packaged in a 208-pin PQFP. Table 7-1 lists the mechanical specifications,
and Figure 7-1 shows the package dimensions of the 21050.

Table 7-1. Lead Counts and Dimensional Attributes

Symbol Limit Dimensions in Millimeters

LL REF 1.3
e BSC 0.5
L MIN 0.5
L MAX 0.75
A MAX 4.2
A1 MIN 0.25
A2 MIN 3.17
A2 MAX 4.25
b MIN 0.17
b MAX 0.27
c MIN 0.09
c MAX 0.2
ccc — 0.08
ddd — 0.08
ttt — 0.2
D BSC 30.6
D1 BSC 28
E BSC 30.6
E1 BSC 28
R MIN 0.08
R MAX 0.25

Preliminary Datasheet 87

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 21050 PCI-to-PCI Bridge

Figure 7-1. Package Dimensions

-A-
D
D1

PIN 1

208-Pin PQFP B E1 E -B-

4x
N/4 Tips
ttt C A B 4x 0.2 H A B A2 A
// 0.13 C
-H-
Datum Plane

-C-
5¡ - 16¡ Seating Plane
0.40 Min. A1
ccc C
0¡ - 10¡
A

L
0.25
79% Scaled
ddd M C A S B S LL
0¡ - 7¡ c LJ-03911.AI4

7.1.2 Absolute Maximum Ratings

This section lists the absolute maximum ratings for the 21050. Stressing the device beyond the
absolute maximum ratings may cause permanent damage. These are stress ratings only. Operating
beyond the functional operating range is not recommended and extended exposure beyond the
functional operating range may affect reliability.

Table 7-2. Absolute Maximum Ratings

Parameter Minimum Maximum
Supply voltage VCC — 5.5 V
Junction temperature, Tj — 125°C
Maximum voltage applied to signal pins — 5.5 V
Maximum power, PWC — 1.7W
Storage temperature range, Tstg –55°C 125°C

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 21050 PCI-to-PCI Bridge

Table 7-3. Functional Operating Range

Parameter Minimum Maximum
Operating ambient temperature, Ta 0°C 40°C
Junction temperature, Tj — 100°C
Supply voltage VCC 4.75 V 5.25 V

7.2 Electrical Specifications

Table 7-4 defines the dc parameters met by all 21050 signals under the conditions of the functional
operating range.

Table 7-4. DC Specifications

Symbol Parameter Condition Minimum Maximum Units
Vih Input high voltage — 2.0 VCC + 0.5 V V
Vil Input low voltage — –0.5 0.8 V
Input high leakage
Iih Vin = 2.7 V — 70 µA
current1
Input low leakage
Iil Vin = 0.5 V — –70 µA
current1
Voh Output high voltage Iout = –2 mA 2.4 — V
Iout = 3 mA,
Vol Output low voltage2 — 0.55 V
6 mA
Cin Input pin capacitance — — 10 pF
CIDSEL p_idsel pin capacitance — — 8 pF
p_clk, s_clk pin
Cclk — 5 12 pF
capacitance

1. Input high leakage current and input low leakage current include Iozl or Iozh leakage current for bidirectional signals. The leak-
age tests are run at VCC=5.0 V, which is the normal operating level for VCC.
2. Most output low voltage signals have 3 mA current. The following output low voltage signals have 6 mA low output current:
p_frame_l, p_trdy_l, p_irdy_l, p_devsel_l, p_stop_l, p_serr_l, p_perr_l, p_lock_l, s_frame_l, s_trdy_l, s_irdy, s_devsel_l,
s_stop_l, s_perr_l, s_lock_l

7.3 Interface Signal AC Electrical Specifications

Table 7-5 lists output parameters for all 21050 shared signals under the conditions of the functional
operating range:

Table 7-5. Shared Signal Output Parameters

Symbol Parameter Condition Minimum Maximum Units
0 < Vout ≤ 1.4 –44 — µA
Ioh (AC) Switching current high1
1.4 < Vout ≤ 2.4 2 3
µA
Test point Vout = 3.1 V — –142 µA
Vout ≥ 2.2 95 — µA
Iol (AC) Switching current low1
4
2.2 > Vout > 0.55 Vout / 0.023 µA
Test point Vout = 0.71 V — 206 µA

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 21050 PCI-to-PCI Bridge

Table 7-5. Shared Signal Output Parameters

Symbol Parameter Condition Minimum Maximum Units
5
Icl Low clamp current –5 < Vin –1 — µA
Unloaded output rise
tr 0.4 V to 2.4 V 1 — V/ns
time
Unloaded output fall
tf 0.4 V to 2.4 V 1 — V/ns
time

1. See V/I curves in the PCI Specification.

2. –4.4 + (Vout – 1.4)/0.024
3. 11.9 * (Vout – 5.25) * (Vout + 2.45) for VCC > Vout > 3.1 V
4. 78.5 * (Vout * (4.4 – Vout) for 0 V < Vout > 0.71 V
5. –25 + (Vin + 1) / 0.015

7.3.1 Interface Signal AC Timing Specifications

Table 7-6 and Figure 7-2 show the p_clk and s_clk ac timing.

Table 7-6. p_clk and s_clk AC Timing

Symbol Parameter Minimum Maximum Units Notes

Tcyc xclk cycle time 30 – ns –

@1.5 V and
Thigh xclk high time 12 – ns
@1 V/ns
xclk low time 12 – ns @1.5 V and
Tlow @1 V/ns
Slew rate 1 4 V/ns 0.4 to 2.4 V
Delay from p_clk to
Tskew 0 7 ns @ 1.5 V
s_clk
p_clk rising to
Tsclkr 0 5 ns @1.5 V1
s_clk_o<6:0> rising
p_clk falling to
Tsclkf 0 5 ns @1.5 V1
s_clk_o<6:0> falling

1. Measured with 30pF lumped load.

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Figure 7-2. p_clk and s_clk AC Timing

T
cyc

2.0 V
1.5 V T T
high low
0.8 V
p_clk T
T f
r
T T
r f
2.0 V
T T
1.5 V high low
0.8 V
s_clk

T T
skew skew

T
cyc LJ-03253.AI4

7.3.2 Input Signal AC Timing Specifications

Table 7-7 and Figure 7-3 show the input signal ac timings.

Table 7-7. Input Signal AC Timings

Symbol Parameter Minimum Maximum Units

xclk-to-xsignal valid
Tval 2 11 ns
delay—bused signals1, 2, 3
xclk-to-xsignal valid
Tval (ptp) 2 12 ns
delay—point-to-point1, 2, 3
Ton Float-to-active delay1 2 — ns
Toff Active-to-float delay1 — 28 ns
Input setup time to xclk—
Tsu 7 — ns
bused signals1, 3
Input setup time to
Tsu (ptp) 10, 12 — ns
xclk—point-to-point1, 3
Th Input signal hold time from xclk1 0 — ns

1. All primary interface signals are used by p_clk and all secondary interface signals are used by s_clk.
2. Minimum times measured with 0-pF equivalent load. Maximum times measured with 50-pF equivalent load.
3. Point-to-point signals are p_req_l, s_req_l<7:0>, p_gnt_l, s_gnt_l<7:0>, s_dispst_l, s_bufne_l, and s_cfn_l.
All other PCI signals are shared.
All xgnt_l signals, s_dispst_l, and s_cfn_l have a setup time of 10 ns.
xreq_l has a setup time of 12 ns.

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 21050 PCI-to-PCI Bridge

Figure 7-3. AC Timing Waveforms

xclk 1.5 V
T T
val inval
Output Valid
T T
on off

Input Valid
T
su
T
h
LJ-03254.AI4

Table 7-8 shows the timing specifications for xrst_l.

Table 7-8. xrst_l Timing Specifications

Symbol Parameter Minimum Maximum Units

p_rst_l active time after power

Tprst 1 — µS
stable
p_rst_l active time after p_clk
Tprst–clk 100 — µS
stable
p_rst_l active to output float
Tprst–off — 40 ns
delay
s_rst_l active after p_rst_l
Tsrst — 40 ns
assertion
s_rst_l active time after s_clk
Tsrst–on 100 — µS
stable
s_rst_l active to secondary
Tsrst–off — 40 ns
output float delay

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Copies of documents that have an ordering number and are referenced in this document, or other
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