SHARED-BUS OPERATION

Dr. Gargi Alavani

Department of CS & IS

1
SHARED-BUS OPERATION

● A system that performs more than one task is called a multitasking system.
● In a distributed, multiprocessing, multitasking environment, each
microprocessor accesses two buses:
(1) The local bus
(2) The remote or shared bus

2
Types of Buses
Local Bus
● Resident to the microprocessor.
● Contains the resident or local memory and I/O.
● The local memory and local I/O are accessed by the microprocessor that is directly
connected to them.

Shared Bus
● Connected to all microprocessors in the system.
● Used to exchange data between microprocessors in the system.
● May contain memory and I/O devices that are accessed by all microprocessors in the
system.
● Access to the shared bus is controlled by some form or arbiter that allows only a single
microprocessor to access the system’s shared bus space.

3
4
• 8284 provides the clock to the
system.
• 8088 places address/data/status
signals on the bus.
• 8288 (Bus Controller) decodes
status and generates control signals.
• Address is latched via ‘373.
• Data flows via ‘245 transceivers to
either the local or shared bus.
• 8289 (Bus Arbiter) ensures the
correct device controls the shared
bus using arbitration logic.
• Signals like RDY, AEN, CEN, and
RESB ensure smooth and conflict-
free operation.
5
The Bus Arbiter 8289

● The 8289 bus arbiter controls the interface of a bus master to a shared bus.
● Each bus master or microprocessor requires an arbiter for the interface to the
shared bus
● Intel calls the Multibus
● IBM calls the Micro Channel.
● The shared bus is used only to pass information from one microprocessor to
another; otherwise, the bus masters function in their own local bus modes by
using their own local programs, memory, and I/O space.
● Microprocessors connected in this kind of system are often called parallel or
distributed processors because they can execute software and perform tasks in
parallel.

6
8289 Architecture

7
8289 Architecture
• CPU sends status and control signals
to 8289.
• The State Generator decodes
processor status.
• The Control block interprets requests
and coordinates internal operations.
• If the processor needs to access the
shared bus, the Arbitration block
requests it.
• Once granted, the Multibus Interface
sends appropriate command signals.
• The Local Bus Interface connects
local data to/from the shared system
bus.

8
8289 Architecture

• The 8289 controls the shared bus by causing the READY input to the
microprocessor to become a logic 0 (not ready) if access to the shared bus is denied.
• The blocking occurs whenever another microprocessor is accessing the shared bus.
• As a result, the microprocessor requesting access is blocked by the logic 0 applied to
its READY input.
• When the READY pin is a logic 0, the microprocessor and its software wait until
access to the shared bus is granted by the arbiter. In this manner, one
microprocessor at a time gains access to the shared bus.
• No special instructions are required for bus arbitration with the 8289 bus arbiter
because arbitration is accomplished strictly by the hardware

9
Pin Definitions

10
Pin Definitions

11
Pin Definitions

12
Pin Definitions

13
8289 Modes of Operation

14
8289: Three Basic Modes of Operation
1. I/O Peripheral-Bus Mode
• All local bus devices = I/O
• Memory accesses → Shared Bus
• I/O accesses → Local Bus

2. Resident-Bus Mode
• Both memory & I/O accessed via:
• Local Bus
• Shared Bus

3. Single-Bus Mode
• Microprocessor interfaces only with Shared Bus
• No local memory or I/O
• Used to define a Shared-Bus Master 15
System-Level Role Distribution

One microprocessor → Shared-Bus Master

● Operates in Single-Bus Mode
● Controls system via shared memory & I/O

Other microprocessors → Resident or I/O Peripheral-Bus Masters

● Perform independent tasks
● Report results via Shared Bus

16
 Single-Bus and Resident-
Bus Connections.

Bus Master A (Single-Bus Mode)

• Contains an 8088 microprocessor,
bus controller (8288), address
latches (74LS373), and buffers
(74LS245).
• All address/data/control lines
connect directly to the shared
buses:
• Shared Data Bus, Shared Address
Bus ,Shared Control Bus
• No local memory, relies on shared
memory & I/O (like CRT).
• Manages global tasks like
program execution and
coordination.

17
Single-Bus and Resident-
Bus Connections.

Bus Slave B (Resident-Bus Mode)

• Also contains an 8088, 8288, and
8289 (bus arbiter), along with its
own local memory and I/O (e.g.,
Telephone interface).
• Data flow is controlled by:
➢ 74LS245 (bidirectional buffer for
data bus)
➢ 74LS244 (unidirectional buffer)
➢ 74LS373 (address latch)
➢ 74LS04 (inverter for control logic)
• Can work independently using its
local memory.
• Uses the 8289 bus arbiter to
request and gain control of the
shared bus when data exchange
with shared memory is needed.
18
Single-Bus and Resident-
Bus Connections.

Bus Slave C (Resident-Bus Mode)

• Same architecture as Bus Slave
B.
• Connected to Printer, Disk, and
Local Memory. Operates as a
print spooler: collects data from
shared memory into local memory,
and then prints it.
• Uses the same 8288 + 8289 + 74-
series support chips.

19
 Single-Bus and Resident-
Bus Connections.

Shared Bus Arbitration (8289 +

Priority Resolver)
• 8289 Bus Arbiter: Each resident
processor has an 8289 chip that
controls access to the shared bus.
• A Parallel Priority Resolver
receives Bus Request (BRQ)
signals and issues Bus Grant (BG)
signals.
• The BUSY signal ensures only
one processor owns the shared
bus at a time.

20
 Single-Bus and Resident-
Bus Connections.

• Bus Master A runs programs and

interacts with CRT and shared
memory.
• Bus Slave B handles telephone
I/O, stores/transfers data via its
local memory.
• Bus Slave C manages printing
tasks independently.Slaves only
use the shared bus when needing
to transfer data to/from shared
memory.
• Bus arbitration logic (8289 +
priority resolver) ensures no
conflict on shared buses.

21
 Single-Bus and Resident-
Bus Connections.

• Bus Master A runs programs and

interacts with CRT and shared
memory.
• Bus Slave B handles telephone
I/O, stores/transfers data via its
local memory.
• Bus Slave C manages printing
tasks independently.Slaves only
use the shared bus when needing
to transfer data to/from shared
memory.
• Bus arbitration logic (8289 +
priority resolver) ensures no
conflict on shared buses.

22
Single-Bus and Resident-
Bus Connections.

• Bus Master A runs programs and

interacts with CRT and shared
memory.
• Bus Slave B handles telephone
I/O, stores/transfers data via its
local memory.
• Bus Slave C manages printing
tasks independently.Slaves only
use the shared bus when needing
to transfer data to/from shared
memory.
• Bus arbitration logic (8289 +
priority resolver) ensures no
conflict on shared buses.

23
 Single-Bus and Resident-
Bus Connections.

• Bus Master A runs programs and

interacts with CRT and shared
memory.
• Bus Slave B handles telephone
I/O, stores/transfers data via its
local memory.
• Bus Slave C manages printing
tasks independently.Slaves only
use the shared bus when needing
to transfer data to/from shared
memory.
• Bus arbitration logic (8289 +
priority resolver) ensures no
conflict on shared buses.

24
25
THANK YOU

26