PCB Interface User's Guide

Release X-ENTP VX.2.8

Document Revision 6
Unpublished work. © Siemens 2020

This document contains information that is confidential and proprietary to Mentor Graphics Corporation, Siemens
Industry Software Inc., or their affiliates (collectively, "Siemens"). The original recipient of this document may
duplicate this document in whole or in part for internal business purposes only, provided that this entire notice
appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable effort
to prevent the unauthorized use and distribution of the confidential and proprietary information.

This document is for information and instruction purposes. Siemens reserves the right to make changes in
specifications and other information contained in this publication without prior notice, and the reader should, in all
cases, consult Siemens to determine whether any changes have been made.

The terms and conditions governing the sale and licensing of Siemens products are set forth in written agreements
between Siemens and its customers. End User License Agreement — You can print a copy of the End User
License Agreement from: mentor.com/eula.

No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give
rise to any liability of Siemens whatsoever.

SIEMENS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY.

SIEMENS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, CONSEQUENTIAL OR
PUNITIVE DAMAGES, LOST DATA OR PROFITS, EVEN IF SUCH DAMAGES WERE FORESEEABLE, ARISING
OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF SIEMENS
HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

LICENSE RIGHTS APPLICABLE TO THE U.S. GOVERNMENT: This document explains the capabilities of
commercial products that were developed exclusively at private expense. If the products are acquired directly or
indirectly for use by the U.S. Government, then the parties agree that the products and this document are
considered "Commercial Items" and "Commercial Computer Software" or "Computer Software Documentation," as
defined in 48 C.F.R. §2.101 and 48 C.F.R. §252.227-7014(a)(1) and (a)(5), as applicable. Software and this
document may only be used under the terms and conditions of the End User License Agreement referenced above
as required by 48 C.F.R. §12.212 and 48 C.F.R §227.7202. The U.S. Government will only have the rights set forth
in the End User License Agreement, which supersedes any conflicting terms or conditions in any government order
document, except for provisions which are contrary to applicable mandatory federal laws.

TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Siemens or
other parties. No one is permitted to use these Marks without the prior written consent of Siemens or the owner of
the Marks, as applicable. The use herein of third party Marks is not an attempt to indicate Siemens as a source of a
product, but is intended to indicate a product from, or associated with, a particular third party. A list of Siemens'
trademarks may be viewed at: www.plm.automation.siemens.com/global/en/legal/trademarks.html and
mentor.com/trademarks.

The registered trademark Linux® is used pursuant to a sublicense from LMI, the exclusive licensee of Linus
Torvalds, owner of the mark on a world-wide basis.

Support Center: support.sw.siemens.com

Send Feedback on Documentation: support.sw.siemens.com/doc_feedback_form
 Revision History ISO-26262

Revision Changes Status/Date

6 Modifications to improve the readability and comprehension of the Released
content. Approved by Regis Krug. November
All technical enhancements, changes, and fixes listed in the 2020
Xpedition Enterprise Flow Release Notes for this product are
reflected in this document. Approved by Mike Bare.
5 Modifications to improve the readability and comprehension of the Released
content. Approved by Regis Krug. March 2020
All technical enhancements, changes, and fixes listed in the
Xpedition Enterprise Flow Release Notes for this product are
reflected in this document. Approved by Mike Bare.
4 Modifications to title page to reflect the latest product version Released
supported. Approved by Regis Krug. September
All technical enhancements, changes, and fixes listed in the 2019
Xpedition Enterprise Flow Release Notes for this product are
reflected in this document. Approved by Mike Bare.
3 Modifications to title page to reflect the latest product version Released
supported. Approved by Regis Krug. February
All technical enhancements, changes, and fixes listed in the 2019
Xpedition Enterprise Flow Release Notes for this product are
reflected in this document. Approved by Mike Bare.

Author: In-house procedures and working practices require multiple authors for documents. All
associated authors for each topic within this document are tracked within the Mentor Graphics
Technical Publication’s source. For specific topic authors, contact Mentor Graphics Technical
Publication department.

Revision History: Released documents include a revision history of up to four revisions. For
earlier revision history, refer to earlier releases of documentation on Support Center.

PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
4 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Table of Contents

Revision History ISO-26262

Chapter 1
Overview of PCB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Basic Design Workflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Creating a PCB Netlist File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Creating a PCB Netlist File From a Command Line Script . . . . . . . . . . . . . . . . . . . . . . . . 12
Error Handling in the Schematic Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pass the Netlist File to a PCB Layout Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Back Annotating Layout Changes to Xpedition Designer . . . . . . . . . . . . . . . . . . . . . . . . . 15
Design Constraint Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Updating the Default Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Creating Net Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Creating Class Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Creating Component Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Creating Differential Pair Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Chapter 2
PCB Interface Configuration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Creating a Custom Configuration File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Basic Configuration File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Basic Configuration File Format Sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AlsRules Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AttPassList Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ChkRules Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
ErrorRules Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
General Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
NewPkgRules Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
TrnRules Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Chapter 3
Supported Vendor’s PCB Layout Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Generic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PADS Layout Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Data Transfer to PADS Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Data Transfer from PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
PADS Keywords and Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Pin Mapping for PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Package Pin Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Pin Order File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Pin Order Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Symbol Preparation for PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

PCB Interface User's Guide, X-ENTP VX.2.8 5

 Table of Contents

Pin Swapping with PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Gate Swapping in PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Group Pin Swapping with PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PADS Layout Design Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Automatically Creating a New PADS Layout Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Manually Creating a New PADS Layout Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Compare the Schematic to the PADS Layout Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Comparing Designs Automatically. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Comparing Designs Manually . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PADS Layout Forward and Back Annotation Processes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Automatically Forward Annotating to PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Manually Forward Annotating to PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Automatically Back Annotating from PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Manually Back Annotating from PADS Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Xpedition Layout Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Data Transfer to Xpedition Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Data Transfer from Xpedition Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Required Xpedition Layout Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Swapping Pins Within Xpedition Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Forward and Back Annotation with Xpedition Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
RINF Layout Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Data Transfer to RINF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Data Transfer from RINF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Keywords Specific to RINF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Symbol Preparation for RINF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Group Pin Swapping with RINF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Visula VDP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Allegro PCB Layout Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Data Transfer Files To Allegro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Data Transfer Files From Allegro. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Allegro Keywords and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Device File Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Creating an Alternate Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Symbol Preparation for Allegro. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Group Pin Swapping with Allegro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Passing Pin Attributes to Allegro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Allegro Netlist File Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Allegro Forward and Back Annotation Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Creating Allegro Forward Annotation Files Automatically . . . . . . . . . . . . . . . . . . . . . . . . 108
Creating Allegro Forward Annotation Files Semi-Automatically . . . . . . . . . . . . . . . . . . . 109
Creating Allegro Forward Annotation Files Manually. . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Creating Allegro Back Annotation Files Automatically. . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Allegro Import and Export Scripts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
view2a.pl File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
a2view.pl File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

6 PCB Interface User's Guide, X-ENTP VX.2.8

Table of Contents

Chapter 4
Heterogeneous Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Common (Shared) Device Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Declaring Heterogeneous Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Defining HETERO Devices for Power Schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Heterogeneous Device Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Chapter 5
Design Reuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Design Reuse Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Design Reuse Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Creating a Reuse Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Chapter 6
Component and Design Level Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Component Level Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Design Level Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Preserve Packaging for Off-Board Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Chapter 7
PCB Interface Tool GUI Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
PCB Interface Dialog Box - Basic Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
PCB Interface Dialog Box - Advanced Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
PCB Interface Dialog Box - Constraints Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
PCB Interface Dialog Box - Results Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Xpedition Designer To PADS Layout Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Library Import Options Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
ECO Compare Options Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
PADS Layout To Xpedition Designer Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
PCB Interface PADS Layout Script. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Index
End-User License Agreement
with EDA Software Supplemental Terms

PCB Interface User's Guide, X-ENTP VX.2.8 7

 Table of Contents

8 PCB Interface User's Guide, X-ENTP VX.2.8

 Chapter 1
Overview of PCB Interface

Use the Xpedition Designer PCB Interface tool to export and import design data between
Xpedition Designer and a PCB layout system from several vendors (including Mentor
Graphics®). The PCB Interface tool specifies the design and the configuration parameters for
export or import, and then performs the data conversion.
Note
Refer to “Supported Vendor’s PCB Layout Interfaces” on page 53 for the list of supported
vendors of PCB layout systems.

The PCB Interface tool contains a default configuration (.cfg) file that provides configurable
packaging control options to meet standard PCB vendor design requirements. These options
control how components on a schematic are bundled into physical packages. In general, this
process involves the assignment of reference designators and physical pin numbers to schematic
components according to physical device definitions.

The PCB Interface tool performs component packaging while honoring existing package
assignments and checking for packaging conflicts. You can choose to manually assign
packaging parameters to some components and allow the vendor’s PCB layout tool to handle
the rest of the assignments. Refer to “Component and Design Level Packaging” on page 127 for
more information.

You can pre-select a Process to Run option to be in effect when you invoke the PCB Interface
tool. For more information on customizing the Tools menu, refer to “Customizing the Tools
Menu” in the Xpedition Designer User's Guide.

Basic Design Workflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Creating a PCB Netlist File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Creating a PCB Netlist File From a Command Line Script . . . . . . . . . . . . . . . . . . . . . . . . 12
Error Handling in the Schematic Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pass the Netlist File to a PCB Layout Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Back Annotating Layout Changes to Xpedition Designer . . . . . . . . . . . . . . . . . . . . . . . . . 15
Design Constraint Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Updating the Default Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Creating Net Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Creating Class Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Creating Component Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Creating Differential Pair Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PCB Interface User's Guide, X-ENTP VX.2.8 9

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Overview of PCB Interface
Basic Design Workflow

Basic Design Workflow

In general, a basic design workflow sequence consists of creating a configuration file, and then
using the configuration file to export and import design data between Xpedition Designer and
the vendor’s PCB layout tool.
Tip
You can follow the procedures listed below to familiarize yourself with the basic design
workflow by creating a simple design of a few components and taking the design through
the process, then making some small changes to the design in layout so that you can observe
back annotating those changes to the Xpedition Designer tool.

Creating a PCB Netlist File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Creating a PCB Netlist File From a Command Line Script . . . . . . . . . . . . . . . . . . . . . . 12
Error Handling in the Schematic Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pass the Netlist File to a PCB Layout Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Back Annotating Layout Changes to Xpedition Designer . . . . . . . . . . . . . . . . . . . . . . . . 15

Creating a PCB Netlist File

In a netlist workflow, you use the PCB Interface tool to create a netlist so that you can package
and exchange data between Xpedition Designer and layout tools.
Prerequisites
• You must have created an Xpedition Designer netlist flow.
Procedure
1. In the Xpedition Designer tool, choose the Setup > Settings menu item, Project
(category).
2. In the Project pane, do the following:
a. Select the vendor’s layout tool from the Layout Tool dropdown list.
b. (Optional) Select Use Custom Constraints file, and specify the location of your
custom constraints file .cns in the Constraints Definition text box.
c. (Optional) Select Use Custom Configuration file, and specify the location of your
custom configuration file (.cfg) in the PCB Configuration text box.
d. Click OK to close the Settings dialog box.
3. Choose the Tools > PCB Interface menu item to open the PCB Interface dialog box.
4. Click the Basic tab to open the “PCB Interface Dialog Box - Basic Tab” on page 133.

10 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Overview of PCB Interface
Creating a PCB Netlist File

Note
The design entry tool automatically adds the default design name and the
configuration file path to the fields in the PCB Interface dialog box.

a. Select Assign Reference Designators (REFDES) to create a generic (basic from-to

format) netlist file.
b. Select Create Netlist for Layout (Forward to Layout) to create the PCB netlist file.
c. Select Use Component Labels to use component labels instead of component UIDs
in the netlist file and any error messages.
d. Type the property level of the design hierarchy data in the Netlist-Design to Level
(Space Delimited) text box. You can have multiple LEVEL properties, for example:
Level1 Level2.
e. (Optional) Select “Run command line to process” to activate the vendor’s standard
command line script. The command line script displays in the text box.
f. (Optional) Select “Use custom cmd line” to specify a user-defined script, and type
the custom command line script in the text box. Refer to “Design Constraint Rules”
on page 18.

Note
Do not click the OK button if you want to automatically back annotate changes to
the schematic.

5. Click the Advanced tab to open the “PCB Interface Dialog Box - Advanced Tab” on
page 136.
a. Select Preserve Previous REFDES Assignments (Forward to Layout) to keep the
reference designator assignments for layout designs that contain manually assigned
reference designators.
b. Select Preserve Gaps in REFDES Numbering Assignments to keep breaks (gaps) in
sequences of reference designator assignments.
c. Select Automatically Add Spare Gates to Schematic to create an additional
Xpedition Designer schematic sheet with all unused gates (slots) instantiated.
d. Select Preserve Case to keep the case sensitivity of the reference designators in the
configuration file when back annotating.
e. In the First Number for REFDES Assignments text box, type the start number for
reference designators. The PCB layout tool uses this number when assigning
reference designator values.
f. Select Automatically Back Annotate Changes to Schematic to back annotate the
layout information from your PCB layout tool to the netlist design.

PCB Interface User's Guide, X-ENTP VX.2.8 11

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Overview of PCB Interface
Creating a PCB Netlist File From a Command Line Script

6. Click the Constraints tab to open the “PCB Interface Dialog Box - Constraints Tab” on
page 140.
a. Define the pin, net, and component constraints you want to include in the
configuration file.
7. Click the Results tab to open the PCB Interface Dialog Box - Results Tab.
a. View the Console window for any packaging errors, warnings or notes. Refer to
“Error Handling in the Schematic Files” on page 14.
8. Click Save Pcb Configuration to save your changes to a local configuration file, or
click OK to update the default configuration file.

Note
The Save Pcb Configuration button displays only if you made changes on the
Advanced tab.

Results
The PCB Interface tool packages the schematic and creates a netlist file, which you can now
pass to your layout tool.
Related Topics
Basic Configuration File Format
Design Constraint Rules

Creating a PCB Netlist File From a Command Line

Script
Use the PCB Interface tool to create an .eco file from a command line script to automate
forward annotating design data from an Xpedition Designer schematic to the vendor’s PCB
layout tool.
Forward annotation compares data from a recent Xpedition Designer schematic to an older
layout design file, and then updates the layout design to match the schematic design.

Prerequisites
• Xpedition Designer and your layout tool must be installed on the same system.
Procedure
1. In the Xpedition Designer tool, choose the Setup > Settings menu item to open the
Settings dialog box.
2. Click the Project tab to open the Project tab.
a. Select the vendor’s layout tool from the Layout Tool dropdown list.

12 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Overview of PCB Interface
Creating a PCB Netlist File From a Command Line Script

b. (Optional) Select “Use Custom Constraints file”, and specify the location of your
custom constraints (.cns) file in the Constraints Definition text box.
c. (Optional) Select “Use Custom Configuration file”, and specify the location of your
custom configuration (.cfg) file in the PCB Configuration text box.
d. Click Apply or OK to close the Settings dialog box.
3. Choose the Tool > PCB Interface menu item to open the PCB Interface dialog box.
4. Click the Advanced and Constraints tabs to set the required design options.
5. Click the Basic tab to open the “PCB Interface Dialog Box - Basic Tab” on page 133.

Note
The software automatically adds the default design name and the configuration file
path to the fields in the PCB Interface dialog box.

a. Select “Create Netlist for Layout” (Forward to Layout) to create the PCB netlist file.
b. Type the property level of the design hierarchy data in the Netlist-Design to Level
(Space Delimited) text box. You can have multiple LEVEL properties, for example:
Level1 Level2.
c. Select “Run command line to process” to activate the vendor’s standard command
line script. The command line script displays in the text box.
d. Select “Use custom cmd line” to specify a user-defined script, and type the custom
command line script in the text box. Refer to Design Constraint Rules.
6. Click OK.
Results
• For the Xpedition Layout tool, the software creates the new .pcb file, adds the
Xpedition Designer parts into the selected library, and imports the selected netlist. Refer
to Xpedition Layout Interface.
• For the Zuken Visula RinF and Zuken Visula RinF VDP tools, the software creates the
files necessary for the netlist. Refer to the Zuken Visula RinF documentation for
information on updating the RinF Layout with the changes. Refer to “RINF Layout
Interface” on page 89.
• For the Cadence Allegro PCB Layout tool, the software imports the Allegro netlist and
device files into the Allegro board database. Refer to “Allegro Forward and Back
Annotation Processes” on page 108.
Related Topics
Basic Design Workflow
Creating a PCB Netlist File

PCB Interface User's Guide, X-ENTP VX.2.8 13

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Overview of PCB Interface
Error Handling in the Schematic Files

Design Constraint Rules

Error Handling in the Schematic Files

Error Handling in the Schematic Files

Running the PCB Interface tool generates a pcb.err file, which contains messages for all of the
errors found in the design.
Note
During initial runs of the PCB Interface tool, you can select to exclude error messages in the
“PCB Interface Dialog Box - Advanced Tab” on page 136, and this serves as a convenient
way to minimize messages while running through your PCB netlisting cycle.

It is strongly recommended that you disable any exclusions before producing a final netlist file.

The Xpedition Designer Output Window also displays error, warning or note messages, as
shown in Figure 1-1, and provides hypertext links to design elements within the
Xpedition Designer tool.

An error file in the design project’s /LogFiles directory indicates corrections that need to be
made to the schematic. If you feel an indicated correction is in error, you can modify the .cfg file
to accommodate the detected condition.

Figure 1-1. Conflicts Shown Within the Xpedition Designer Message Window

The pcb.err file reports the following types of error conditions:

• Library issues.
• Single or zero pin nets.
• Totally floating connections or subnets.
• Unnamed dangling connections (one end floating).

14 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Overview of PCB Interface
Pass the Netlist File to a PCB Layout Tool

• Power and Ground symbols used on nets with different names from the default name on
the symbol.
• Multiple subnet nets where one or more subnets has a missing an off-page symbol.
• Single subnet nets with an off-page symbol (lonely subnet warning).
• User named subnets that have no visible net name label.
Related Topics
Basic Configuration File Format
ErrorRules Section
ChkRules Section
Design Constraint Rules

Pass the Netlist File to a PCB Layout Tool

Once you have successfully created a PCB netlist file without errors, you are ready to pass the
netlist file to the vendor’s PCB layout tool.
In situations where you cannot use the automated back annotation process, for instance when
the vendor’s PCB layout tool is not installed on the system where you created the PCB netlist
file, you can use the manual back annotation process to use the files generated by the vendor’s
PCB layout tool and update your Xpedition Designer schematic.

Related Topics
Creating a Custom Configuration File
Error Handling in the Schematic Files
Allegro Forward and Back Annotation Processes
RINF Layout Interface
Xpedition Layout Interface
PADS Layout Forward and Back Annotation Processes

Back Annotating Layout Changes to

Xpedition Designer
Use the PCB Interface tool to set options in the configuration file and a command line script to
automate back annotating PCB layout data to the Xpedition Designer schematic.

PCB Interface User's Guide, X-ENTP VX.2.8 15

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Overview of PCB Interface
Back Annotating Layout Changes to Xpedition Designer

Prerequisites
• The Xpedition Designer tool and the vendor’s PCB layout tool must be installed on the
same system.
• You must copy the back annotation files from the vendor’s PCB layout tool to your
Xpedition Designer project directory.
Procedure
1. In the Xpedition Designer tool, choose the Setup > Settings menu item, Project
(category).
2. In the Project pane, do the following:
a. Select the vendor’s layout tool from the Layout Tool dropdown list.
b. (Optional) Select Use Custom Constraints file, and specify the location of your
custom constraints file .cns) in the Constraints Definition text box.
c. (Optional) Select Use Custom Configuration file, and specify the location of your
custom configuration file (.cfg) in the PCB Configuration text box.
d. Click OK to close the Settings dialog box.
3. Choose the Tools > PCB Interface menu item to open the PCB Interface dialog box.
4. Click the Advanced and Constraints tabs to set the required design options.
5. Click the Basic tab to open the “PCB Interface Dialog Box - Basic Tab” on page 133.

Note
The software automatically adds the default design name and the configuration file
path to the fields in the PCB Interface dialog box.

6. Select “Back Annotate Information From Layout To Schematic”.

a. Select “Run command line before processing” to activate the PCB layout tool
vendor’s standard command line script.
The command line script displays in the text box.
b. Select “Use custom cmd line” to specify a user-defined script, and type the custom
command line script in the text box.
Refer to “Design Constraint Rules” on page 18.
7. Click OK.
For more information on the effects of back annotating layout changes from a specific
layout tool:
• If you are working with Xpedition Layout, refer to Automatically Back Annotating
from PADS Layout.

16 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Overview of PCB Interface
Back Annotating Layout Changes to Xpedition Designer

• If you are working with Xpedition Layout, refer to “Forward and Back Annotation
with Xpedition Layout” on page 88.
• If you are working with Cadence Allegro, refer to “Creating Allegro Back
Annotation Files Automatically” on page 111.
• If you are working with Visual or Visual VDP, refer to “RINF Layout Interface” on
page 89.
8. Click Finish.
Results
The software updates the schematic with the layout design changes and creates a pcb.err file in
the project’s ../LogFiles directory. This file contains information about the data changes. You
should review this file and make any necessary changes. If errors occur, review the error file.
Related Topics
Creating a Custom Configuration File
Basic Configuration File Format
Error Handling in the Schematic Files

PCB Interface User's Guide, X-ENTP VX.2.8 17

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Overview of PCB Interface
Design Constraint Rules

Design Constraint Rules

You can pass certain design rules bi-directionally between the Xpedition Designer and the
vendors’ layout tool, and you can edit and add constraints to your design using the Constraints
window in Xpedition Designer.
Tip
You should copy the master .cns file from the ..\SDD_HOME\standard folder and put the
copy in your project folder. Then, in the Xpedition Designer Project Settings, Constraints
Definition check box, point to the local version of the file. For example: type .\<filename>.cns
where <filename> is the latest version of the .cns file that you copied from the standard folder.

Updating the Default Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Creating Net Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Creating Class Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Creating Component Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Creating Differential Pair Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Updating the Default Rules

The default constraints file (.cns), contains preset default rules. You can update the default rules
by changing the values in the Constraints window and saving them as the default PCBCLASS.
Prerequisites
• Make sure you have a copy of the master .cns file within your project folder and have set
it to be used in the Xpedition Designer (choose Setup > Settings dialog box, Project
window).
Procedure
1. In Xpedition Designer, select any net in the schematic design.
2. Open the Constraints window (choose View > Other Windows > Constraints).
3. In the Constraints window, choose any of three categories of design rules tabs — High
Speed, Route, or Clearance.

Note
Undock the Constraints window to view the properties.

4. Review the values for constraints, and if necessary, edit the values for any of the
constraints.
5. At the bottom of the Constraints window, click Create New Class from Settings.

18 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Overview of PCB Interface
Creating Net Rules

6. In the Save Values as Class dialog box, select Save settings as the default class, then
click OK.
7. Click OK in the message box to overwrite the .cns file, because you have copied a local
.cns file into your design.
Results
When you click on any other net in the design, the default set of constraints for that net displays
with the new value and applies them to the default PCBCLASS.
Related Topics
Creating Net Rules
Creating Class Rules
Creating Component Rules
Creating Differential Pair Rules

Creating Net Rules

You can create Net rules by simply changing any of the default constraint values of a net.
Procedure
1. Select any net in the schematic design.
2. Open the Constraints window (choose View > Other Windows > Constraints).
3. In the Constraints window, at the bottom, select any of the three categories of design
rules tabs: High Speed, Route, or Clearance.

Tip
Undock the Constraints window to view the properties.

4. Change the values for any of the constraints in that category.

Tip
To see a description of a constraint, right-click a constraint row and then choose the
Constraint Information popup menu item.

Results
There are two ways to check whether you have created a Net rule.
• When you hover over the value of the changed constraint, the hover text reads “Net
Value = <n>?”. When you hover over a default value, the hover text reads, “Default
Value.”

PCB Interface User's Guide, X-ENTP VX.2.8 19

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Overview of PCB Interface
Creating Class Rules

• At the bottom of the Constraints window, click Show/Hide Detailed Information. This
expands the bottom of the Constraints window to display three fields: Default, Value,
and Instance Value. When you select the constraint that you changed to a net level, the
net level displays in the Value field, and the value of the default rule level displays in the
Default field.
Related Topics
Updating the Default Rules
Creating Class Rules
Creating Component Rules
Creating Differential Pair Rules

Creating Class Rules

You can create Class rules by setting constraints, creating a Class name and adding additional
nets to the Class. Unlike the other rules, new Class names cannot be back annotated from the
vendor’s PCB tool, and you can only delete class rules in Xpedition Designer.
Note
Class rules values can pass between Xpedition Designer and the vendor’s PCB tool
bidirectionally.

Procedure
1. Use a net to create the Class constraint values and create the Class name.
a. Select any net in the schematic design that you intent to use in the Class rule.
b. Open the Constraints window (choose View > Other Windows > Constraints).
c. In the Constraints window, at the bottom, select any of the three categories of design
rules tabs: High Speed, Route, or Clearance.

Tip
Undock the Constraints window to view the properties.

d. Change the values for any of the constraints in that category.

e. At the bottom of the Constraints window, click Create New Class from Settings.
f. In the Save Values as Class dialog box, type a name for the new class in the New
class name box. Do not select the “Save settings as the default class” check box.
g. Click OK.
2. Add other nets to the new class.

20 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Overview of PCB Interface
Creating Component Rules

a. Select another net in the design.

b. In the Constraints dialog box, in the PCBCLASS row, click the Default value and in
the list, select your new Class.
Related Topics
Updating the Default Rules
Creating Net Rules
Creating Component Rules
Creating Differential Pair Rules

Creating Component Rules

You can create Component rules by changing any of the default constraint values of a
component.
Procedure
1. Select one or more symbols in the schematic design.
2. Open the Constraints window (choose View > Other Windows > Constraints).

Tip
Undock the Constraints window to view the properties.

3. Change the values for any of the constraints.

Tip
To see a description of a constraint, right-click a constraint row and then choose the
Constraint Information popup menu item.

Related Topics
Updating the Default Rules
Creating Class Rules
Creating Net Rules
Creating Differential Pair Rules

Creating Differential Pair Rules

You can create Differential Pair rules by selecting two nets to make them a differential pair and
then set their differential pair constraints.

PCB Interface User's Guide, X-ENTP VX.2.8 21

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Overview of PCB Interface
Creating Differential Pair Rules

Procedure
1. Select any two nets in the schematic design.
2. Open the Constraints window (choose View > Other Windows > Constraints).

Tip
Undock the Constraints window to view the properties.

3. At the bottom of the Constraints window, click Make Differential Pair ( ).

Results
The two nets become a differential pair. When you change the value of one of the nets, the other
net of the differential pair changes automatically. A new Differential Pair category tab appears
at the bottom of the Constraints window and becomes active.
Related Topics
Updating the Default Rules
Creating Class Rules
Creating Component Rules
Creating Net Rules

22 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Chapter 2
PCB Interface Configuration Files

The PCB Interface tool uses configuration files to manage the backward and forward annotation
between Xpedition Designer and the PCB layout tool.
For data transfer into a PCB layout tool, each supported PCB layout interface has its own
vendor-specific configuration (.cfg) file. The vendor specific configuration (.cfg) file specifies
particular settings for each vendor and contains the correct default settings for each interface.
The SDD_HOME/standard directory for Xpedition Designer contains default configuration
(.cfg) files for each supported PCB layout system.
Table 2-1. Vendor Specific Configuration Files
Vendor Configuration Filename
Generic (Vendor-independent) generic.cfg
Mentor Graphics Xpedition Layout expedition.cfg
Mentor Graphics Xpedition Layout pads100.cfg
Zuken Visula RINF rinf.cfg
Zuken Visula RINF VDP rinf_vdp.cfg
Cadence Allegro allegro14.cfg
allegro15.cfg
allegro16.cfg

Creating a Custom Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Basic Configuration File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Basic Configuration File Format Sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AlsRules Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AttPassList Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ChkRules Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
ErrorRules Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
General Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
NewPkgRules Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
TrnRules Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Creating a Custom Configuration File

You can modify a configuration file to control the netlisting information and formatting to
match your corporate standards. You can then save these changes and not overwrite your master

PCB Interface User's Guide, X-ENTP VX.2.8 23

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
Creating a Custom Configuration File

.cfg file by creating a user-defined configuration file. For design environments where multiple
users pass data to a particular layout tool, you should establish one central copy of the
configuration file.
Default configuration files reside in the ..\SDD_HOME\standard directory.

The process involves making modifications to a copy of the appropriate .cfg file (keeping the
original version as a backup), and then making the file available in one of two ways.

Prerequisites
Consult the “Basic Configuration File Format” on page 25 section to learn the formatting
requirements for section delimiters, keyword syntax, case sensitivity, and comment characters.

Procedure
1. Edit a copy of the default configuration file for your target layout tool (<vendor>.cfg).
2. Save a copy of the customized file to the location that corresponds to the scope you want
it to control. Be sure to save it under the original name, <vendor>.cfg.
• For installations where Xpedition Designer resides on the network, place the new
configuration file (.cfg) file in the \\<network_install_dir>\standard directory.
o Each user must modify their WDIR environmental variable to specify the
directory path to the “golden” .cfg file.
o The directory path must be specified before the directory path to the
Xpedition Designer installation. For example: SET WDIR=<dir_with_golden
_file>,C:\<install_dir>\standard
• For installations where Xpedition Designer resides on individual user's computers,
store the configuration file (.cfg) file in a central accessible location, and then
distribute copies of the corporate-approved “golden” .cfg file to all users.
o To control only one project, place it in the project directory.
3. Enable the use of the custom configuration file:
a. In the Xpedition Designer tool, choose the Setup > Settings menu item, Project
(category).
b. Select the Use Custom Configuration File checkbox, then enter the custom file
name, or browse to the custom file you created.
If you do not specify a custom configuration file, the PCB Interface tool searches for
the default <vendor>.cfg file in the following order:
1. From the location you entered in the Project tab.
2. In the local project.
3. In the WDIR search path (up to the \standard directory).

24 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Configuration Files
Basic Configuration File Format

Related Topics
Basic Configuration File Format
Basic Configuration File Format Sections
Supported Vendor’s PCB Layout Interfaces

Basic Configuration File Format

Input for: The PCB Interface tool
Use the ASCII configuration file (.cfg) to control the backward and forward annotations
between Xpedition Designer and the vendor’s PCB layout tool.
The section order can vary between Layout configuration files, but the LayoutID must appear at
the top of the file, followed by the ErrorRules section. Mentor Graphics delivers a default
configuration file in the SDD_HOME/standard directory.

Note
Any keywords with filename values can use double quotes (“ ”) to default to the project
name.

A configuration file is a text file that must conform to the following formatting and syntax rules:

• The LayoutID keyword must appear at the top of the file.

• Begin and End section delimiters contain the keywords, apart from General
Functionality keywords, which may appear in any configuration file sections.
• File content keywords are case-sensitive, apart from the Yes or No values.
• The vertical bar ( | ) must be used to indicate comment text.
Figure 2-1. Example of a Section in a Configuration File

Related Topics
Creating a Custom Configuration File
System Property Definitions [Xpedition Designer and Xpedition System Designer Properties

PCB Interface User's Guide, X-ENTP VX.2.8 25

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
Basic Configuration File Format

Glossary]
Supported Vendor’s PCB Layout Interfaces

26 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Configuration Files
Basic Configuration File Format Sections

Basic Configuration File Format Sections

The .cfg files are ASCII files that uses standard XML formatting. The content of the
configuration files are divided into major sections.
AlsRules Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AttPassList Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ChkRules Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
ErrorRules Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
General Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
NewPkgRules Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
TrnRules Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

AlsRules Section
The AlsRules (Alias Rules) section of the configuration file maps property names into
corresponding names for the different target layout systems.
This section can also map attribute=value pairs into different attribute=value pairs for the target
layout systems. In effect, this creates an alias between Xpedition Designer names and layout
system names. Typical uses of the AlsRules section include:

• Resolving mapping of property values between the Xpedition Designer standard parts
libraries and the layout system.
• Generating mixed case or lowercase properties for the layout system.
• Using an alternate property rather than an originally configured specific attribute.
• Helping import third-party schematics. For example, if the third-party schematic uses
SHAPE=8PDIP, and Xpedition Designer uses PKG_TYPE=DIP8.

AlsRules Section Example

BeginAlsRules
PKG CLASS=DIODE CLASS=ANALOG
PIN PINTYPE=OUT PINTYPE=S
PKG PKG_TYPE=8PDIP PKG_TYPE=DIP8
NET CHAR_Z char_Z |The layout system sees mixed case
COM UNIQUE_PART_NUMBER DEVICE |Use UNIQUE_PART_NUMBER rather than DEVICE
EndAlsRules

Table 2-2. AlsRules Keywords

AlsRules Keywords Description
PIN Component pin properties.

PCB Interface User's Guide, X-ENTP VX.2.8 27

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
AttPassList Section

Table 2-2. AlsRules Keywords (cont.)

AlsRules Keywords Description
PKG Xpedition Designer component properties that belong to the
layout system’s packages.
NET Xpedition Designer net properties.
COM Component properties.
Table 2-3 contains syntactical examples that you can use in the ALSRules section
Table 2-3. Syntactical Examples
Syntax Aliases Example
Alias the attribute=value combination as the PKG PKG_TYPE=14PDIPPKG_TYPE=“ ”
property name by substituting empty
quotation marks for the value.
Alias to mixed case. COM VALUE Value
Insert spaces in the alias. Aliases containing PKG PKG_TYPE “PKG TYPE”
spaces must be enclosed in quotation marks.
Insert quotation marks in the alias by NET MAX_LEN 14\“ produces MAX_LEN 14”
preceding them with a backslash (\)
Alias the name=value combination as just PKG PKG_TYPE=14PDIP PKG_TYPE=“ ”
the property name by substituting double
quotes for the value.
Alias the net property WIDTH to NET WIDTH TRACEWIDTH
TRACEWIDTH of the layout system.

Related Topics
Basic Configuration File Format
Creating a Custom Configuration File
System Property Definitions [Xpedition Designer and Xpedition System Designer Properties
Glossary]
Supported Vendor’s PCB Layout Interfaces

AttPassList Section
The forward annotation (pcbfwd) and back annotation (pcbbck) functions use the AttPassList
(Attribute Pass List) section to identify which properties from the Xpedition Designer database
to load into internal memory.

28 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Configuration Files
AttPassList Section

Note
The AttPassList section contains an additional section and two additional keywords. The
DoOATs section General and Specific keywords.

Refer to Additional Keywords and Section within the AttPassList Section

AttPassList Example Section

BeginAttPassList
|pcbfwd and pcbbck use this section to determine which properties from the
|Xpedition Designer database to load into internal memory.
Specific | These properties are referred to specifically by interface code
|to meet particular syntactical requirements.
PIN PINTYPE
COM PINSWAP
COM PKG_LOCK
COM NC
‘
‘
PKG PKG_TYPE
BeginOatAtts | Attributes following this keyword are treated as
|Occurrence Attributes (OATS) for the new hierarchy functionality. If you
|are using this new functionality you must uncomment this keyword.
PIN #
COM REFDES
COM $OBJNAME | Used internally
COM GEN_ID | Maintains layout system name
NET $OBJNAME | Used internally
NET GEN_ID | Maintains layout system name
EndOatAtts | This keyword turns off the listing of the OATS properties.
General | These properties are passed to the layout system in
|syntactically general way. Not implemented for GENERIC.
|PKG C_TEMPERATURE | DontBackAnno | Optionally prevents back annotation of
|this attribute
NET DIFFP_PRIMARY_GAP
NET DIFFP_NECK_GAP
NET DIFFP_MIN_SPACE
‘
EndAttPassList

Table 2-4 lists the AttPassList Keywords.

Table 2-4. AttPassList Keywords
AttPassList Keywords Description
PIN Component pin properties.
COM Component properties.
BOARD Board-level properties.
NET Xpedition Designer net properties.
PKG Xpedition Designer component properties that belong to the
layout system’s packages.

PCB Interface User's Guide, X-ENTP VX.2.8 29

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
AttPassList Section

Table 2-4. AttPassList Keywords (cont.)

AttPassList Keywords Description
PPN Xpedition Designer component pin properties that describe
the layout system’s package pins.
DontBackAnno Prevents the back annotation of new or changed properties.
Table 2-5 lists the additional keywords and addition section.
Table 2-5. Additional Keywords and Section within the AttPassList Section
Additional Section and Usage
Keywords
General and Specific — The General and Specific keywords do not have Begin or End
delimiters, and when present within the AttPassList section, they toggle each other on or
off from the top down.
Specific The PCB Interface interface code uses the properties after
this keyword to meet particular syntactical requirements
when passing data to the layout system. For example, to
preserve the packaging of a component or symbol, you
would enter COM PKG_LOCK.
The Specific keyword uses either a Begin <keyword>
delimiter, or a General keyword as its delimiter.
General The PCB Interface interface code uses the properties within
this keyword to meet general syntactical requirements when
passing data to the layout system.
The General keyword uses either a Begin <keyword>
delimiter, or a Specific keyword as its delimiter.
BeginOatAtts/EndOatAtts — Use the OATS (Occurrence Attributes) properties within this
section of the AttPassList main section for hierarchy functionality.
The OATS section may appear multiple times within the Specific and General subsections.
BeginOatAtts Attributes that follow this keyword are occurrence
properties.
Uncomment this keyword if DoOats equals Yes.
EndOatAtts Attributes that precede this keyword are occurrence
properties.
Uncomment this keyword if DoOats equals Yes.

Related Topics
Basic Configuration File Format
Creating a Custom Configuration File
System Property Definitions [Xpedition Designer and Xpedition System Designer Properties

30 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Configuration Files
ChkRules Section

Glossary]

ChkRules Section
The ChkRules (Check Rules) section of the configuration file specifies the types of error
checking. The PCB Interface tool looks for conditions, and if the particular condition is
encountered; it checks the resulting severity, and then decides the action (if any) to be taken.
A short description of the error condition appears next to each rule in the Check Rules section.
If the tool encounters an error, it does not save or modify the data from the original netlist file,
however, if it encounters only warnings or notes, the interface attempts to complete its run. To
suppress a particular rule, remove the line from the configuration file or precede the line with a
comment character ( | ).

ChkRules Example
To suppress a particular rule, comment the particular check line in the configuration file by
preceding the line with a pipe character ( | ).

BeginChkRules
CHKVAL _NAME_CHK SYMCOM DEVICE ERR 0 "~{}*,.`
\t\n\r@" "" 1 16
CHKVAL _NAME_CHK NET TRACEWIDTH ERR 0 "0-9" ""
1 3
CHKBRD _DUPL_ATTR ERR 0 | Duplicate attribute
CHKBRD _BAD_SLOTCNT ERR 0 | Conflicting number of slots
CHKBRD _DUPL_PINS ERR 0 | SIGNAL, NC, # conflicts
CHKBRD _ILL_PINSWAP WRN 0 | Illegal pin swap
CHKBRD _BAD_PINSWAP ERR 0| Bad PINSWAP attribute
CHKBRD _BAD_PIN_NUM ERR 1| Component pin # not on symbol, 1=repack
.
.
.
EndChkRules

Supported Check Rules

Table 2-6. ChkRules Keywords
ChkRules Keywords Description
ALLOW_DUPL <object_type> <attr_name>
Allows duplicates of an attribute, or multiple values, so
that CHKBRD _DUPL_ATTR does not report errors.
Normally only SIGNAL properties should have
duplicates.
Error Messages: none.

PCB Interface User's Guide, X-ENTP VX.2.8 31

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
ChkRules Section

Table 2-6. ChkRules Keywords (cont.)

ChkRules Keywords Description
CHKBRD _BAD_HETERO <error_severity> <fixcode>
Checks for bad heterogeneous package definitions.
Fixcode: 0 (none supported)
Error Messages: 6091, 6092
CHKBRD _BAD_PINSWAP <error_severity> <fixcode>
Checks for bad PINSWAP properties.
Fixcode: 0 (none supported)
Error Messages: 6117, 6118, 6119, 6120
CHKBRD _BAD_PIN_NUM <error_severity> <fixcode>
Checks for Xpedition Designer component pin
numbers not on the Xpedition Designer symbol.
Fixcode: 0
No fixup: 1 — Repackages the gate
Error Messages: 6047, 6088
CHKBRD _BAD_SIG_NUM <error_severity> <fixcode>
Checks for Xpedition Designer component SIGNAL
or NC pin numbers not on the Xpedition Designer
symbol.
Fixcode: 0
No fixup: 1 — Treats the pin as a normal SIGNAL or
NC pin
Error Messages: 6006, 6007
CHKBRD _BAD_SLOTCNT <error_severity> <fixcode>
Checks for conflicting number of slots as indicated by
Xpedition Designer symbol pin numbers.
Fixcode: 0 (none supported)
Error Messages: 6087
CHKBRD _BUS_PIN <error_severity> <fixcode>
Checks for bus pins not being expanded.
Fixcode: 0 (none supported)
Error Messages: 6084

32 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Configuration Files
ChkRules Section

Table 2-6. ChkRules Keywords (cont.)

ChkRules Keywords Description
CHKBRD _COMM_PIN1 <error_severity> <fixcode>
Checks for common pins which are both connected and
unconnected on the schematic for the same package
pin.
Fixcode: 0
No fixup: 1 — Repackages the gates
Error Messages: 6050, 6069, 6070
CHKBRD _COMM_PIN2 <error_severity> <fixcode>
Checks for common pins connected to different nets
for the same package pin.
Fixcode: 0
No fixup: 1 — Repackages the gates
Error Messages: 6050, 6069, 6070
CHKBRD _COMM_PIN3 <error_severity> <fixcode>
Checks for common pins which have different
properties for the same package pin.
Fixcode: 0
No fixup: 1 — Repackages the gates
Error Messages: 6045, 6066
CHKBRD _COMM_PIN4 <error_severity> <fixcode>
Checks for common pins which have an explicit
connected net overriding a SIGNAL for the same
package pin.
Fixcode: 0
No fixup: 1 — Repackages the gates
Error Messages: 6050, 6069, 6070
CHKBRD _DEV_CONFL <error_severity> <fixcode>
Checks for conflicting devices for Xpedition Designer
components with the same reference designator.
Fixcode: 0
No fixup: 1 — Repackages the gates
Error Messages: 6046, 6067, 6068

PCB Interface User's Guide, X-ENTP VX.2.8 33

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
ChkRules Section

Table 2-6. ChkRules Keywords (cont.)

ChkRules Keywords Description
CHKBRD _DUPL_ATTR <error_severity> <fixcode>
Checks for duplicate properties.
Fixcode: 0 (none supported)
Error Messages: 6053
CHKBRD _DUPL_FNAME1 <error_severity> <fixcode>
Checks for duplicate Xpedition Designer component
names.
Fixcode: 0 (none supported)
Error Messages: 6052
CHKBRD _DUPL_FNAME2 <error_severity> <fixcode>
Checks for Xpedition Designer component names
which duplicate reference designators.
Fixcode: 0 (none supported)
Error Messages: 6052
CHKBRD _DUPL_NNAME <error_severity> <fixcode>
Checks for duplicate net names.
Fixcode: 0 (none supported)
Error Messages: 6052
CHKBRD _DUPL_RNAME <error_severity> <fixcode>
Checks for Xpedition Designer reference designator
duplicates.
Fixcode: 0 (none supported)
Error Messages: 6052
CHKBRD _DUPL_PINS <error_severity> <fixcode>
Checks for conflicting pin numbers as indicated by
Xpedition Designer SIGNAL, NC, and # properties.
Fixcode: 0 (none supported)
Error Messages: 6051
CHKBRD _DUPL_SLOT <error_severity> <fixcode>
Checks for duplicate slots.
Fixcode: 0
No fixup: 1 — Repackages the gates
Error Messages: 6049, 6054

34 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Configuration Files
ChkRules Section

Table 2-6. ChkRules Keywords (cont.)

ChkRules Keywords Description
CHKBRD _EXTRA_PI <error_severity> <fixcode>
Checks for extra pins in Xpedition Designer symbol
compared with previously evaluated symbol of the
same name.
Fixcode: 0 — (none supported)
Error Messages: 6082
CHKBRD _ILL_PINSWAP <error_severity> <fixcode>
Checks for illegal pin swaps based on PINSWAP
properties.
Fixcode: 0
No fixup: 1 — Adds a PINSWAP attribute
Error Messages: 6074, 6090
CHKBRD _MISSING_PIN <error_severity> <fixcode>
Checks for pins missing from Xpedition Designer
symbol compared with previously evaluated symbol of
the same name.
Fixcode: 0 (none supported)
Error Messages: 6077
CHKBRD _MIXED_SLOT <error_severity> <fixcode>
Checks for pins from different slots on the same gate.
Fixcode: 0
No fixup: 1 — Repackages the gate
Error Messages: 6048, 6089
CHKBRD _PIN_SHORTED <error_severity> <fixcode>
Checks for shorted pins on gates. Excludes SIGNAL
pins from checking.
Fixcode: 0 (none supported)
Error Messages: 6093
CHKBRD _REF_CONFL <error_severity> <fixcode>
Checks for conflicting properties on
Xpedition Designer components with the same
reference designator.
Fixcode: 0
No fixup: 1 — Repackages the gates
Error Messages: 6045, 6066

PCB Interface User's Guide, X-ENTP VX.2.8 35

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
ChkRules Section

Table 2-6. ChkRules Keywords (cont.)

ChkRules Keywords Description
CHKBRD _SGL_PIN_NET <error_severity> <fixcode>
Checks for single pin nets.
Fixcodes:
• 0 — Pass single pin nets to netlist
• 1 — Filter all single pin nets from netlist
• 2 — Filter single pin nets with the NET NC
attribute from netlist
Error Messages: 6083, 6116
CHKBRD _UNCON_PIN <error_severity> <fixcode>
Checks for unconnected pins.
Fixcode: 0 (none supported)
Error Messages: 6094
CHKBRD _UNUSED_SLOT <error_severity> <fixcode>
Checks for unused slots.
Fixcode: 0 (none supported)
Error Messages: 6085
See Also: Configuration CreateSpareGates option
CHKBRD _VDVP_ATT <error_severity> <fixcode>
Checks for conflicting properties for the same package
or package pin in Xpedition Designer.
Fixcode: 0
No fixup: 1 — Updates with Xpedition Designer data
Error Messages: 6058, 6064, 6066, 6072
CHKVAL _DUMMY_CHK <object_type> <attr_name> <error_severity>
<fixcode>
Do not perform any default checking on this attribute.
Fixcode: 0 (none supported)
Error Messages: none

36 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Configuration Files
ChkRules Section

Table 2-6. ChkRules Keywords (cont.)

ChkRules Keywords Description
CHKVAL _ENUM_CHK <object_type> <attr_name> <error_severity>
<fixcode> <value1> <value2>...
Checks property values against an enumerated set of
values.
Fixcode: 0 (none supported)
Error Messages: 6039, 6055, 6056, 6057, 6060, 6061,
6062
See Also: GENVAL
CHKVAL _FND_CHAR <object_type> <attr_name> <error_severity>
<fixcode> <required_char>
Checks property values for a required character.
Fixcode: 0
No fixup: 1 — Appends the required character
Error Messages: 6040, 6055, 6056, 6057, 6060, 6061,
6062
See Also: GENVAL
CHKVAL _LIST_CHK <object_type> <attr_name> <error_severity>
<fixcode> <legal_chars> <replacement_chars>
<min_length> <max_length>
Checks property values which contain a list of values
for illegal characters and length violations.
Arguments — Same arguments as for _NAME_CHK.
The minimum and maximum length apply to each
value in the list, not to the entire list.
Fixcode: 0 (none supported)
Error Messages: 6034, 6035, 6036, 6037, 6038, 6055,
6056, 6057

PCB Interface User's Guide, X-ENTP VX.2.8 37

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
ChkRules Section

Table 2-6. ChkRules Keywords (cont.)

ChkRules Keywords Description
CHKVAL _NAME_CHK <object_type> <attr_name> <error_severity>
<fixcode> <legal_chars> <replacement_chars>
<min_length> <max_length>
Checks property values for illegal characters and
length violations, allowing character replacement and
truncation as possible fixups.
Arguments:
• <legal_chars> — a string of all legal characters. If
the list begins with ~, the string contains only the
illegal characters.
The entire string may be double-quoted.
Uses the Backslash as the literal character.
Ranges may be specified using the - character (e.g.
A-Z). If the range character appears first or last in
the string, it is interpreted literally.
• <replacement chars> may be a single character or
the null string.
Used to automatically replace illegal characters if it
encounters fixups.
Fixcodes:
• 0 — No fixup
• 1 — Tries character replacement
• 2 — Tries truncation
• 3 — Tries both character replacement and
truncation
Error Messages: 6034, 6035, 6036, 6037, 6055, 6056,
6057, 6060, 6061, 6062
See Also: GENVAL

38 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Configuration Files
ChkRules Section

Table 2-6. ChkRules Keywords (cont.)

ChkRules Keywords Description
CHKVAL _REG_EXP <object_type> <attr_name> <error_severity>
<fixcode> <illegal_chars> <replacement_chars>
<min_length> <max_length> <reg_exp>
Checks property values against a regular expression,
allowing illegal character replacement and truncation
as possible fixups.
Arguments:
• <illegal_chars> — a string of all illegal characters.
• <replacement_chars> — a string of all the
corresponding replacement characters to use, if
any, if fixups are enabled.
Fixcodes:
• 0 — No fixup
• 1 — Tries character replacement
• 2 — Tries truncation
• 3 — Tries both character replacement and
truncation
Error Messages: 6005, 6036, 6037, 6055, 6056, 6057,
6060, 6061, 6062
See Also: GENVAL and the Regular Expression
Syntax section
CHKVAL _SIG_CHK <object_type> <attr_name> <error_severity>
<fixcode>
Checks a SIGNAL property value. Apply NET
$OBJNAME checking to the net name portion and
PPN $OBJNAME checking to the pin number portion
of the value.
Fixcode: 0 (none supported)
Error Messages: 6041, 6055, 6056, 6057
FIRST_REFDES <n>
Begins new reference designator assignments with the
specified number, <n>.
FIX_SEVERITY <error_severity>
Sets the severity for messages which report automatic
fixups.

PCB Interface User's Guide, X-ENTP VX.2.8 39

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
ChkRules Section

Table 2-6. ChkRules Keywords (cont.)

ChkRules Keywords Description
GENVAL _DFLT_VAL <object_type> <attr_name> <default_value>
Generates a new property value when necessary using
the specified default value.
Error Messages: 6060, 6061, 6062
GENVAL _UNIQ_NUM <object_type> <attr_name> <prefix>
Generates a new property value when necessary by
using the specified prefix and appending the next
available unique number.
Error Messages: 6060, 6061, 6062
REQUIRE <object_type> <attr_name> <error_severity>
<fixcode>
Requires an property to exist.
Fixcodes:
• 0 — No fixup
• 1 — Creates a new attribute
Error Messages: 6074

ChkRules Object Types and Additional Attributes

The ChkRules section supports the following check rules in the configuration file.

You can use the following values when specifying an object type for a particular checking
feature.
Table 2-7. ChkRules Objects and Additional Attributes
Object Types and Description
Additional Attributes
Object Types — You can concatenate multiple object types into a single value, such as
SYMCOM.
COM Xpedition Designer component.
NET Xpedition Designer net.
PIN Xpedition Designer component pin.
PKG Xpedition Designer component.
PPN Xpedition Designer component pin.
SPN Xpedition Designer symbol pin.
SYM Xpedition Designer symbol.

40 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Configuration Files
ChkRules Section

Table 2-7. ChkRules Objects and Additional Attributes (cont.)

Object Types and Description
Additional Attributes
ANY All of the above.
Additional Attributes — In addition to regular property names (for example, REFDES),
special values may be used to specify a property name for a particular checking feature.
$OBJNAME Checks the object name.
$ATTNAME Checks the property name (not the property value).
$ANY Checks every property value.
$DEFAULT Checks every unchecked property value.

Pattern Matching Syntax

The ChkRules section of the configuration file uses special characters and syntax for pattern
matching.
Table 2-8. ChkRules Pattern Matching Syntax
Special Character Definition
* Matches zero or more occurrences of any character.
? Matches a single occurrence of any characters.
[chars] Matches a single occurrence of a character given inside the
brackets. You can specify a range of characters by using a
hyphen (-).
Special characters lose their meaning inside brackets. For
example, if a hyphen appears first inside the brackets, the
software reads it as just another character.
Note: Because the tool performs bus expansion before
pattern expansion, the tool supports the bus notation for bus
signals within brackets, for example [<msb>:<lsb>].
[^not_chars] Matches a single occurrence of any character except the ones
inside the brackets (not_chars).
Note: The caret (^) character maintains its meaning, only if it
follows the opening bracket ([^).

PCB Interface User's Guide, X-ENTP VX.2.8 41

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
ChkRules Section

Table 2-8. ChkRules Pattern Matching Syntax (cont.)

Special Character Definition
char{repetition_factor} Matches the char for the given number of times by the
repetition_factor.
char — single character
repetition_factor — one of the following:
• Single number — exact number for which the character has
to be repeated.
• Two numbers separated by hyphen — acceptable range of
repetitions.
• Single number followed by hyphen — repetitions more
than that number of times.
• * — zero or more repetitions of this character.
• + — one or more repetitions of this character.
“string” Provides one or more characters, including delimiters, their
literal meaning; such as white space, parentheses, semicolon,
angle brackets, and equals sign enclosed in quotation marks (“”).
The string does not remove the meaning of special characters.
Note: You must use quotation marks to quote the full string.
/ Removes the special meaning of any special character
immediately following the forward slash (/).
If the slash appears before a non-special character, then it stands
for itself.
To match a slash before a special character, add another slash (//
).
Note: Use the forward slash character instead of the
backslash (\) character.

Pattern Matching Syntax Examples

The following examples expand upon the pattern matching syntax information for the ChkRules
section of the configuration file:
Table 2-9. Pattern Matching Syntax Examples
Pattern Matching Description
Syntax
ab* Matches any string starting with ab.
?xyz Matches any string of four characters ending with xyz.
? Matches any string of two characters starting with an alphabetic character.
[^0-9]* Matches any string not starting with a digit.

42 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Configuration Files
ErrorRules Section

Table 2-9. Pattern Matching Syntax Examples (cont.)

Pattern Matching Description
Syntax
ab{3} Matches the string abbb only.
{1-3} Matches any string of one to three digits.
az{*} Matches any string starting with a and having zero or more occurrences of
z.
“ax;\za” Matches the string ax;\za literally.
abc/*z Matches the string abc*z.
xy//* Matches any string starting with xy/.

Related Topics
Basic Configuration File Format
Creating a Custom Configuration File
System Property Definitions [Xpedition Designer and Xpedition System Designer Properties
Glossary]

ErrorRules Section
The ErrorRules section controls the level of error messages and warnings produced by PCB
Interface.
This section enables you to exclude specific errors, warnings or notes by their particular
numbers, or to exclude an entire class of messages (for example, exclude all messages that are
of type Note).
Table 2-10. ErrorRules Keywords
ErrorRules Keywords Description
DoSummary Controls whether pcbfwd or pcbbck prints a summary
of the total number of messages. Assign a value of Yes
or No.
Errorfile Identifies the error filename. Assign filename .err as
the value.
Exclude Excludes error messages from the output by severity
level. There are seven severity levels: Error, Warning,
Status, Note, Failure, Fatal, and Internal. Only assign
keyword values to Warning, Status, or Note.
ExcludeNums Excludes specific error messages by error message
number.

PCB Interface User's Guide, X-ENTP VX.2.8 43

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
General Rules

ErrorRules Example
BeginErrorRules
DoSummary Yes
| Errorfile pcb.err
| Exclude Note
| ExcludeNums 1234 5678
EndErrorRules

Note
Exclude error messages carefully — you can lose important information. Only suppress
repetitive and familiar warnings and messages. Turn them back on before creating the final
netlist file.

Related Topics
Basic Configuration File Format
Creating a Custom Configuration File
System Property Definitions [Xpedition Designer and Xpedition System Designer Properties
Glossary]

General Rules
General keywords may appear in any of the defined file sections. General keywords do not have
a Begin or End section.

Table 2-11. General Rules

General Rule Keywords Description
BackExt Extension of the third-party back-annotation file.
Default value: .bck.
BackFileName Identifies the name of the third party annotation file.
BackNetFileExt Specifies the filename extension of the property back annotation
netlist file.
BackNetlistFileName Specifies the filename of the property back annotation netlist
file.
BackPlaceFileExt Identifies the file extension for the back annotation placement
file.
Default value: .bpl.
BackPlaceFileName Identifies the filename of the back annotation placement file.

44 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Configuration Files
General Rules

Table 2-11. General Rules (cont.)

General Rule Keywords Description
CreateSpareGates Yes — Automatically adds spare gates to the schematic on a
new sheet.
Default: No.
DeviceFileExt Extension of device files.
Default: .dvf.
DeviceFileName Overrides the default output filename for pcbfwd for the library
device descriptions.
Default: design.dvf.
Note: You must include the extension when changing the
default filename.
DoCompLabel Controls whether component UIDs or component labels appear
in the netlist file and the error messages.
Yes — The netlist file requires component labels.
You must also set the $OBJNAME name check to make the '$'
character illegal.
No — Default value.
DoOats Yes — Turns on OATs functionality.
You must also remove the comment lines from BeginOatAtts
and EndOatAtts in the AttrPassList section.
DoPacking Yes — Default. Assigns reference designators for all
components in the design.
No — Checks the design, based on the rules set up in the
configuration file.
DriverId Indicates the format in which pcbfwd writes the output.
For generic.cfg, the value is GENERIC. Other interface
configuration files indicate the specific PCB CAD system (for
example, PADS Layout, RINF, ALLEGRO).
DumpDict Controls name mapping functionality in conjunction with the
SuppressIDBackAnno keyword.
Yes — Default. Controls the reading and writing of dictionary
files to the project directory.
No — Prevents using dictionary files.
EvalParamAtts Yes — Default. Controls whether Xpedition Designer evaluates
parameterized properties when netlisting.

PCB Interface User's Guide, X-ENTP VX.2.8 45

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
General Rules

Table 2-11. General Rules (cont.)

General Rule Keywords Description
FindHeterosInSameLibrary Yes — Default. Prevents the HETERO property from using a
library alias for any of the DEVICE fields in its value. All the
symbols referenced by the HETERO property must be in the
same library.
No — The system searches multiple libraries for each device.
FuncDictExt Identifies the function dictionary file extension
Default: .fdc.
FuncDictFileName Identifies the function dictionary filename.
FwdExt Provides the extension of the netlist file produced by pcbfwd.
Default: .fwd.
GenericEnable Enables the use of PKT files to transform generic symbols into
unique components, and to back annotate this information to the
schematics.
Grounds Lists net names attached to a ground.The interface writes these
nets into the device file.
LayoutId Indicates the format in which the PCB Interface tool writes the
output.
For example, if you create a generic netlist file using the
generic.cfg file, the LayoutId keyword has the value of
GENERIC.
Each supported vendor’s PCB layout tool has a specific value
for this keyword. For example, if the LayoutID keyword value
equals PADS9, it would indicate that the compatible output file
format equals PADS Layout.
Levels An alternate way of specifying how far down the design
hierarchy the pcbfwd and pcbbck commands should netlist.
Default value — STD.
NetDictExt Identifies the net dictionary file extension.
Default: .ndc.
NetDictFileName Identifies the net dictionary filename.
NetlistFileName Overrides the default output filename for the netlist file
produced by the pcbfwd command.
Default filename — design.net.
You must include the extension when changing the default
filename.

46 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Configuration Files
General Rules

Table 2-11. General Rules (cont.)

General Rule Keywords Description
OneDeviceFile Controls whether the device file information is written into a
single file, or into separate files for each device.
Yes — Produces only one device file.
No — Produces separate files for each device.
OutLen Controls the maximum line length for all output files except the
error file. You can assign an integral value.
Default — 80 characters.
OverrideCompAttr Yes — The SIGNAL and NC properties on the symbol overrides
the SIGNAL and NC properties on the component.
No — Default.
ParamAttFile Specifies an optional file containing additional
Xpedition Designer parameterized property definitions.
Default: .var extension.
PartFileName Overrides the default output filename for the partslist file
produced by the pcbfwd command.
Default filename — design.pkg.
You must include the extension when changing the default
filename.
PinMapEnable Yes — Updates pin labels on components using the labels in the
PINMAP section of the PKT file.
No — Leaves component pin labels at the symbol value.
PkgSkip Yes — Ignores deleted or omitted reference designators to
preserve gaps in REFDES numbering assignments.
No — Default.
PlaceFileExt Identifies the file extension for the forward placement file.
Default: .fpl.
PlaceFileName Identifies the filename of placement file.
PlacementScale Specifies a unit conversion factor for placement information.
You can assign a floating point number.
Powers Identifies the nets attached to a power source. The interface
writes these nets into the device file.
Precision Defines the number of decimal places when writing placement
and trace width floating point values.
Default — 0.

PCB Interface User's Guide, X-ENTP VX.2.8 47

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
General Rules

Table 2-11. General Rules (cont.)

General Rule Keywords Description
PreservePrevPack Controls whether to preserve or reassign existing reference
designator and pin number assignments.
Yes — Default. Preserves the existing values when possible.
SignalStyle Dictates whether the pcbfwd command writes the
Xpedition Designer SIGNAL property values to the netlist file.
pkgpin — Default. Writes all Xpedition Designer SIGNAL
property values to the netlist file.
strip — excludes SIGNAL property values.
SpareInputSignal Use this keyword when automatically adding spare gates to the
schematic.
Defines the net to be automatically connected to the input
PINTYPEs defined by SpareInputTypes.
To leave all the input pins disconnected, do not specify any
SpareInputTypes.
Default — GND.
SpareInputTypes Use this keyword when automatically adding spare gates to the
schematic.
Defines the input PINTYPEs to be automatically connected to
the SpareInputSignal.
Default — None.
SuppressIdBackAnno Controls name mapping functionality in conjunction with the
DumpDict keyword.
Back annotates translated names to the schematic.
Yes — Default. Blocks translated names being back annotated
to the schematic.
Note: You must also set the DumpDict keyword to Yes to
block the back annotation. If set to No, back annotation
No — Enables translated names to be back annotated to the
schematic.
TPEnable Yes —Indicates that testpoint components added to the top level
of a design have hierarchical netnames attached.
To preserve these names, add the HIER_NAMES_ALLOWED
keyword to the global netlist file.
Note: The TPEnable (Test Point Enable) functionality does
not support inverted labels.

48 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Configuration Files
NewPkgRules Section

Table 2-11. General Rules (cont.)

General Rule Keywords Description
WriteBaf Yes — Blocks the pcbbck command from automatically
updating your schematic with any changes made to the design
while it was in the layout system or if a .baf file exists.
No — Default. Back annotation automatically updates your
schematic with any changes made to the design while it was in
the layout system, or if a .baf file exists.
WriteDeviceInfo Yes — Instructs the pcbfwd command to create a separate part
type file.
No — Default.
WriteVbf Yes — The pcbbck command automatically updates your board
with any changes made in the layout tool, or creates a .vbf file.
No — Default.

Related Topics
Basic Configuration File Format
Creating a Custom Configuration File
System Property Definitions [Xpedition Designer and Xpedition System Designer Properties
Glossary]

NewPkgRules Section
The NewPkgRules (New Package Rules) section of the configuration file specifies the
Xpedition Designer symbols to use when automatically updating the design with new
components added during the layout phase.
Note
See Pattern Matching Syntax section for more information.

NewPkgRules Example
BeginNewPkgRules
REFDES res R*
REFDES res R[0-9]*
DEVICE my74ls00 74LS00
EndNewPkgRules

NewPkgRule Interpretation
You only need to define rules for device types added during layout which were not previously
used on the schematic. For example, if the device CAP10R was not previously used on the

PCB Interface User's Guide, X-ENTP VX.2.8 49

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
TrnRules Section

schematic but was added during layout, you must specify the Xpedition Designer symbol to be
used for the CAP10R device.

The PCB Interface tool follows specific rules when parsing the DEVICE and REFDES
information in the NewPkgRules section.

• When processing device information to be added, the PCB Interface tool processes the
entries in the NewPkgRules section from top to bottom.
• If DEVICE information exists, and a DEVICE rule triggers a match, then the PCB
Interface tool uses the indicated symbol.
• If REFDES information exists, and a REFDES rule triggers a match, then the PCB
Interface tool uses the indicated symbol.
• If both DEVICE and REFDES information exists, the PCB Interface tool performs the
DEVICE check, followed by the REFDES check.
Table 2-12 lists the possible combinations of the DEVICE and REFDES keywords, along with
the resulting action to be taken by the PCB Interface tool.
Table 2-12. DEVICE and REFDES Keyword Combinations
Rule Keyword Layout DEVICE Layout REFDES Keyword Active?
DEVICE "" U1 No
DEVICE 74LS00 U1 Yes
DEVICE 74LS00 "" Yes
REFDES "" U1 Yes
REFDES 74LS00 U1 Yes
REFDES 74LS00 "" No

Related Topics
Basic Configuration File Format
Creating a Custom Configuration File
System Property Definitions [Xpedition Designer and Xpedition System Designer Properties
Glossary]

TrnRules Section
The TrnRules (Translation Rules) section of the configuration file creates new
Xpedition Designer properties to contain the values of any net, component name, or property
value that may have incompatible syntax between Xpedition Designer and the target PCB
place-and-route system.

50 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Configuration Files
TrnRules Section

Table 2-13. TrnRules Keywords

TrnRules Keywords Description
Levels Determines how far down the design hierarchy the
pcbfwd and pcbbck commands should netlist.
Default value — STD.
NetDictExt Identifies the net dictionary file extension.
Default — .ndc.
NetDictFileName Identifies the net dictionary filename.
NetlistFileName Overrides the default output filename for the netlist file
produced by the pcbfwd command.
Default filename — design.net.
You must include the extension when changing the
default filename.
PIN Component pin properties.
COM Component properties.
NET Xpedition Designer net properties.
PKG Xpedition Designer component properties that belong
to the layout system packages.
PPN Xpedition Designer component pin properties that
describe the layout system’s package pins.

Example TrnRules Section

BeginTrnRules
|For visibility,n = only property name visible, v = property name and
|value visible, vv = only property value visible, i - property name and
|value invisible)
NET $OBJNAME GEN_ID v
COM $OBJNAME GEN_ID vv
COM ONE TWO v
EndTrnRules

$OBJNAME Keyword
Specifying $OBJNAME in the TrnRules section, enables the TrnRules section to control the
name and visibility of the NET and COM properties. These property values contain the layout
system name generated during the checking phase of netlisting. These properties are typically in
the format of *_ID, and may be back annotated onto the schematic. This information also
appears in the dictionary files.

If the first entity after the object type keyword is a property name that appears on the schematic,
and the value for this name has caused a translation during the checking phase, then the line

PCB Interface User's Guide, X-ENTP VX.2.8 51

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Configuration Files
TrnRules Section

specifies a new property name which is back annotated onto the schematic with the translated
value.

Examples
In the example, ChkRules detected an illegal A character and used the truncation fix-up.

• If the Translation Rules section contains:

COM ONE TWO v

• and the Check Rules section contains:

CHKVAL _NAME_CHK COM ONE WRN 1 B-Z 1 79

• and a component on the schematic contains:

ONE=ABCD | A is illegal

• then the PCB back annotates the following:

TWO=BCD | truncated name

Related Topics
Basic Configuration File Format
Creating a Custom Configuration File
System Property Definitions [Xpedition Designer and Xpedition System Designer Properties
Glossary]

52 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Chapter 3
Supported Vendor’s PCB Layout Interfaces

The Xpedition Designer PCB Interface supports multiple vendor PCB layout tool interfaces.
Generic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PADS Layout Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Data Transfer to PADS Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Data Transfer from PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
PADS Keywords and Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Pin Mapping for PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Package Pin Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Pin Order File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Pin Order Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Symbol Preparation for PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Pin Swapping with PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Gate Swapping in PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Group Pin Swapping with PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PADS Layout Design Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Automatically Creating a New PADS Layout Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Manually Creating a New PADS Layout Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Compare the Schematic to the PADS Layout Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Comparing Designs Automatically. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Comparing Designs Manually . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PADS Layout Forward and Back Annotation Processes . . . . . . . . . . . . . . . . . . . . . . . . . 76
Automatically Forward Annotating to PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Manually Forward Annotating to PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Automatically Back Annotating from PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Manually Back Annotating from PADS Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Xpedition Layout Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Data Transfer to Xpedition Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Data Transfer from Xpedition Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Required Xpedition Layout Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Swapping Pins Within Xpedition Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Forward and Back Annotation with Xpedition Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
RINF Layout Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Data Transfer to RINF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Data Transfer from RINF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Keywords Specific to RINF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Symbol Preparation for RINF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

PCB Interface User's Guide, X-ENTP VX.2.8 53

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Generic Interface

Group Pin Swapping with RINF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Visula VDP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Allegro PCB Layout Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Data Transfer Files To Allegro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Data Transfer Files From Allegro. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Allegro Keywords and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Device File Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Creating an Alternate Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Symbol Preparation for Allegro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Group Pin Swapping with Allegro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Passing Pin Attributes to Allegro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Allegro Netlist File Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Allegro Forward and Back Annotation Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Creating Allegro Forward Annotation Files Automatically . . . . . . . . . . . . . . . . . . . . . . . . 108
Creating Allegro Forward Annotation Files Semi-Automatically . . . . . . . . . . . . . . . . . . . 109
Creating Allegro Forward Annotation Files Manually. . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Creating Allegro Back Annotation Files Automatically. . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Allegro Import and Export Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
view2a.pl File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
a2view.pl File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Generic Interface
The Generic PCB Interface produces general vendor-independent netlists. When you specify
Generic as the vendor in Xpedition Designer, the REFDES utility automatically runs on the
specified design to ensure the design properly updates with reference designators.
Note
The Generic interface is used only in “To Layout” mode.

The “To Layout” mode provides the following operations:

• Creation of a generic netlist (.net)

• Creation of package file (.pkg)
• Optional creation of device files (.dev)
• Function and Net Dictionary files (.fdc, .ndc)

Table 3-1. Generic Interface Input Files

Input Filename Description
generic.cfg Configuration file

54 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Generic Interface

Table 3-1. Generic Interface Input Files (cont.)

Input Filename Description
\wir\design_name.* Design wire files (connectivity data)

Table 3-2. Generic Interface Output Files

Output Filename Description
design_name.net Netlist file
design_name.pkg Package file
design_name.dvf Device file (optional)
design_name.baf Back annotation file produced if the .cfg file contains the
keyword WRITEBAF YES
pcb.err Error file
design_name.fdc Function dictionary file
design_name.ndc Net dictionary file

Related Topics
Creating a PCB Netlist File

PCB Interface User's Guide, X-ENTP VX.2.8 55

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
PADS Layout Interface

PADS Layout Interface

The PCB Interface tool for PADS Layout enables design and device information to be passed
between the Xpedition Designer and PADS Layout tools.
The PADS Layout interface supports the following features in addition to the general PCB
Interface supported features:

• Creation of a netlist file with optional placement data and optional property passing.
• Optional creation of all part types using a .p file to import part data into the PADS
Layout library.
• Detection of net or component deletions and electrical changes.
• Back annotation of gate swaps, pin swaps, reference designator renumbering, decal
changes (the PKG_TYPE property updates, but does not support alternate decals). For
supported design rule information, refer to Design Constraint Rules.
• Optional forward and back annotation of design rules. For supported design rule
information, refer to Design Constraint Rules.
Data Transfer to PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Data Transfer from PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
PADS Keywords and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Data Transfer to PADS Layout

The Xpedition Designer to PADS Layout data transfer process uses various input and output
files for forward annotation.

Table 3-3. PADS Forward Annotate Input and Output Files

Input / Filename Description
Output
Input Files pads100.cfg Configuration file.
\wir\design_name.* Design wire files (connectivity data).

56 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Data Transfer from PADS Layout

Table 3-3. PADS Forward Annotate Input and Output Files (cont.)
Input / Filename Description
Output
Output Files design_name.asc Netlist file created using the pcbfwd command.
design_name.p File containing all part type information for
importing into a PADS library.
pcb.err Error file which you can load into ViewNavigator
for automatic searching of errors.
design_name.ndc Net dictionary file which controls bidirectional
translation of names when annotating information to
and from PADS Layout.
Use only when the netlister finds an invalid net or
instance name in the design, and you set the
configuration file to continue with a new net name
(new net name could have an illegal character
replaced or removed).
design_name.fdc Function dictionary file containing definitions of
component names and properties. Similar to the net
dictionary (.ndc) file.
design_name.pxr Cross-probing file that identifies all objects. This
file is used by the PADS-Designer Link and the
Cross Prober, which provides real-time
communication between Xpedition Designer and
the PADS Layout tools.

Related Topics
Data Transfer from PADS Layout

Data Transfer from PADS Layout

The Xpedition Designer-PADS Layout data transfer process uses various input and output files
for back annotation.
Note
Before you back annotate design data, copy the input files to the designated
Xpedition Designer project directory. This overwrites the original netlist file used for PADS
Layout, so rename the original netlist file in Xpedition Designer to retain a backup copy.

PCB Interface User's Guide, X-ENTP VX.2.8 57

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
PADS Keywords and Properties

Table 3-4. PADS Forward Annotate Input and Output Files

Input / Filename Description
Output
Input Files design_name.asc Exported PADS Layout netlist file that examines
Xpedition Designer schematics to ensure the .eco
file created by the PADS Layout tool contains all
the required changes.
Used because the Xpedition Designer tool cannot
read the format of a .pcb file.
design_name.eco Incremental ECO change file that contains a list of
all changes made.
Created and saved in the same directory as the
native PADS Layout .pcb file.
Output File design_name.baf Back annotation file that contains the comparison
between the Xpedition Designer schematics .asc
and .eco files.
Only created if the configuration file contains the
WRITEBAF YES keyword.

Related Topics
Data Transfer to PADS Layout

PADS Keywords and Properties

You can specify the unique, required, conditional, recommended and optional properties PADS
Layout keywords in the configuration file.
The table of optional properties provides only a partial list; it does not list properties used for
simulation or DFT.
Table 3-5. PADS Layout Specific Keywords
Keyword Description
CADLibrarySignals Determines whether the .asc file from the PCB Interface tool
includes default signals from the PADS Layout part type
library.
Valid values: Yes / No.
Yes: PADS Layout reads the default signals from the PADS
Layout part type library when reading the .asc file.
No: (default), PADS Layout does not read the default signals.

58 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
PADS Keywords and Properties

Table 3-5. PADS Layout Specific Keywords (cont.)

Keyword Description
DeviceFormat Specifies an alternate format for the device string in the
PART section of the .asc file. The device string needs to
include Xpedition Designer properties and must be delimited
by dollar signs ($).
Example: DeviceFormat $DEVICE$
Grounds Lists net names attached to a ground. The Xpedition Designer
tool writes these nets into the netlist file using
SignalTraceWidth instead of NormalTraceWidth.
NetFileHeader Indicates the header that the PCB Interface tool places on
each .asc file.
NormalTraceWidth Sets the default trace width.
Default width: 12.
PassBoardOutline Creates a separate LINES section in the .asc file.
No: Inhibits the creation of a LINES section.
Note: The LoadPlacementData keyword must be set to
Yes.
Powers Identifies the nets attached to a power source. The
Xpedition Designer tool writes these nets into the .asc file
using SignalTraceWidth instead of NormalTraceWidth.
SignalTraceWidth Sets the default trace width for signal, power, and ground
nets. Any net that is connected to non-signal pins writes as
SignalTraceWidth.
Default value: 50.

Table 3-6. PADS Layout Required Properties

Required Properties Description
PKG_TYPE Maps to the PADS Layout PCB decal (footprint).
# Provides component pin numbers.
Note: For symbols with common groups of pins, PADS
Layout does not create the individual functions.
REFDES Defines the component reference designator in the PADS
Layout tool.

PCB Interface User's Guide, X-ENTP VX.2.8 59

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
PADS Keywords and Properties

Table 3-6. PADS Layout Required Properties (cont.)

Required Properties Description
DEVICE Defines the PADS Layout part type description in the library
file (.p file).
If you do not use the .p file, then the DEVICE property must
map directly to the name of the part type you use in the PADS
Layout library. This is used as the Default to the symbol name
if you do not specify DEVICE.

Table 3-7. PADS Layout Conditional Properties

Conditional Properties Description
PARTS Required only when multiple symbols make up one package.
These symbols are all equal in function and are called
homogeneous parts. When the symbols that make up a
package are not all functionally identical, they are called
heterogeneous parts.
Note: The HETERO property is required when using the
PADS Layout PARTS property (refer to Heterogeneous
Device Support).
HETERO Required on heterogeneous parts and identifies the symbols
which make up the single package. The HETERO property
requires specific syntax for different situations.
SIGNAL Hides nets on the schematic. You can hide power and ground
pins on your symbols if you are confident with the design, and
it is understood that power and ground pins exist.
For multiple pins of the same signal, use commas to separate
the pins.
For example: SIGNAL=VCC;4,8.
Required when you use an implicit pin connection to a
specific net.
PKGORDER Specifies alphanumeric pin mapping to numerics when using
the .p file to automatically generate PADS Layout part types
during netlisting.
Alternatively, you can use a pin file (.ppn) to specify the
alphanumeric mapping to numeric pins.
Required when mapping alphanumerics to a PADS decal
which uses numeric pin numbers.

60 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
PADS Keywords and Properties

Table 3-7. PADS Layout Conditional Properties (cont.)

Conditional Properties Description
NC Identifies unconnected external package pins, by adding the
unattached property to components to indicate unconnected
pins on the package.
If you use the NC property, the specified No-Connect pin
must not be explicitly drawn on the symbol.
For example, for multiple NC pins use NC=2,4,5. (Important
for certain types of packages, such as the FK versus J
package).
GATESWAP Accepts a Boolean value which enables or inhibits gate
swapping in the library file (.p file).
LEVEL Prevents netlisting of underlying schematics for composite
symbols, as well as underlying Verilog or VHDL of module
symbols.

Table 3-8. PADS Layout Recommended Properties

Recommended Properties Description
PINTYPE Identifies the individual pins type (IN, OUT, BI, and so on).
The PADS Layout tool uses the PINTYPE property to
automatically rearrange the topology of net connections to
one of several useful patterns.
CLASS Maps to the PADS Layout logic family of the part type and
ensures you get the correct prefix for all your reference
designators.
PINSWAP Identifies swappable pins in PADS Layout. You must specify
the swappable pin labels. For example:
PINSWAP=(1,2),(3,7).
PADS Layout automatically and manually swaps both pins
and gates based on the minimum net length.
Note: PADS Layout does not support group pin
swapping. You must split a component using HETERO 4
packaging to implement this functionality (refer to
Heterogeneous Device Support).

PCB Interface User's Guide, X-ENTP VX.2.8 61

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
PADS Keywords and Properties

Table 3-8. PADS Layout Recommended Properties (cont.)

Recommended Properties Description
GEOMETRY.HEIGHT Used to indicate the height of the part, and enables PADS
Layout to prevent the component from being placed in a
height restricted area of the PCB.
PADS Layout passes the property to mechanical tools for use
in 3D simulations to determine whether the part meets spatial
requirements.
In addition to the value, use one of the following to indicate
the unit of measure:
• Use the quotation symbol (") for inches. The PADS
Layout Attribute Dictionary specifies the following limits
of acceptable values: Min=0.00000", Max=25.00000".
Example: GEOMETRY.HEIGHT=3.26548”
• Use the abbreviation mil in upper or lower case. The
PADS Layout Attribute Dictionary specifies the following
limits of acceptable values: Min=0.00mil,
Max=25000.00mil
Default unit of measure, if you do not assign the UNIT
property.
Example: GEOMETRY.HEIGHT=12654.83mil
• Use the abbreviation mm in upper or lower case. The
PADS Layout Attribute Dictionary specifies the following
limits of acceptable values: Min=0.00000mm,
Max=635.00000mm.
Example: GEOMETRY.HEIGHT=123.21348mm
Note: We recommend that you use a unit of measure in
the property value in order to use different units for your
components.
UNIT An unattached property added to the first schematic sheet to
indicate a different unit of measure for the layout design.

Table 3-9. PADS Layout Optional Properties

Optional Properties Description
TOLERANCE Specifies the tolerance of a discrete component.
VALUE Specifies the numeric value of a discrete component.

62 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Pin Mapping for PADS Layout

Pin Mapping for PADS Layout

Although PADS Layout enables alphanumeric pin numbers on PCB decals, you can map a
Xpedition Designer symbol with alphanumeric pin numbers to a PADS Layout decal with
numeric numbers.
This enables you to reuse decals for various manufacturer devices, each with its own set of
logical pin numbers. For example, you could reuse an SOT23 or TO-39 decal with logical
devices with pin numbers such as E,B,C; G,D,S; or A,K.

Package Pin Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Pin Order File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Pin Order Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Package Pin Order

Use the PKGORDER property to define the order of pins on the package. As property values
have character limits, you should limit the use of the PKGORDER property to symbols with
fewer pins.
If using a heterogeneous device, you must attach the PKGORDER property to each of the
symbols that comprise the heterogeneous device.

Usage example—You have a transistor with pin numbers labeled E, B, and C. But the PADS
Layout decal uses pin numbers 1, 2, and 3. You add the pin number values to the property value
in the exact sequential order of the package. If the Emitter pin is pin 2, the Base pin is pin 3, and
the Collector pin is pin 1, you would use the following property and value: PKGORDER=C,E,B

Related Topics
PKGORDER [Xpedition Designer and Xpedition System Designer Properties Glossary]
Pin Order File
Pin Order Processing
Heterogeneous Device Support

Pin Order File

The pin order text file (.ppn) contains unlimited pin numbers (not pin labels) in the appropriate
pin order. Separate pin numbers with a space, or place them on separate lines. The software
looks in the /sym directory of the project for this file.

PCB Interface User's Guide, X-ENTP VX.2.8 63

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Pin Order Processing

Note
You must make sure that the decals in the PADS library have the appropriate pin numbers,
or the software generates errors when forward annotating.

Related Topics
PKGORDER [Xpedition Designer and Xpedition System Designer Properties Glossary]
Package Pin Order
Pin Order Processing

Pin Order Processing

When creating the wire list file, the tool processes pin order information according to the
following rules.
• The Xpedition Designer tool looks for a PKGORDER property. If found, this property
defines the pin order.
• If the Xpedition Designer tool does not find a PKGORDER property, it looks for a pin
order (.ppn) file. If found, it uses this file to define the pin order.
• If the Xpedition Designer tool does not find a pin order file, it assumes that the PADS
Layout decal has matching pin numbers and does not need to create a pin mapping.

Tip
Use the PKGORDER property whenever you have different pin numbers on the symbol
compared to the decal.

If you have previously used alphanumeric pin numbers without a PKGORDER property or .ppn
file, the pin order would have been random. If the decal has numeric pin numbers, use the
PKGORDER property or if it has a large number of pins, create a .ppn file and save the file
using the Device name for the Hetero symbol in order to generate the pin order output.

Note
If you update associated decals to have alphanumeric pin numbers, you must remove the
PKGORDER property, or delete the associated .ppn file.

Related Topics
PKGORDER [Xpedition Designer and Xpedition System Designer Properties Glossary]
Package Pin Order

64 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Symbol Preparation for PADS Layout

Symbol Preparation for PADS Layout

Attributes assign non-graphical data to individual components in your schematic. The PCB
Interface uses the translation information in the configuration file for PADS Layout to interpret
the netlist file and property data.
Figure 3-1 shows an example of a symbol that has all the appropriate properties for optimum
placement in the PADS Layout tool.

Figure 3-1. Symbol Properties for PADS Layout

Pin Swapping with PADS Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Gate Swapping in PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Group Pin Swapping with PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Pin Swapping with PADS Layout

The PINSWAP property generates detailed pin swapping information. When specifying the
pins to be swapped, use parentheses to contain groups that the interface can swap, and brackets
to contain groups that the interface cannot swap.
Note
You cannot specify discrete groups of pins to swap with other discrete groups of pins. If you
attempt to do this by using square brackets, the PCB Interface tool ignores all pin swap
information.

PCB Interface User's Guide, X-ENTP VX.2.8 65

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Gate Swapping in PADS Layout

Within the PADS Layout tool, use the following syntax to specify individual pins that can be
swapped using the PINSWAP attribute:

PINSWAP=(A,B,C, ... )

where A, B, C, and so on, can all be swapped with each other.

You can also use the syntax:

(A,B),(C,D), ...

where A can be swapped with B, C can be swapped with D, and so on.

Related Topics
Basic Configuration File Format
Pin Order File
Group Pin Swapping with PADS Layout

Gate Swapping in PADS Layout

In order for the PADS Layout tool to recognize a common pin format for gate swapping, you
must use heterogeneous packaging. This enables pins to be grouped together, and instead of
doing a pin swap, the PADS Layout tool performs a gate swap (which is equivalent to group pin
swapping).The PCB Interface tool correctly identifies these pins during the layout process
Figure 3-2 and Figure 3-3 show how to implement heterogeneous packages (common pins are
not included on the swappable symbol on a simple SIP resistor pack and a package of Octal Bus
transceivers and registers.

Figure 3-2. Simple SIP Resistor Pack

66 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Group Pin Swapping with PADS Layout

Figure 3-3. Package of Octal Bus Transceivers and Registers

Related Topics
Pin Swapping with PADS Layout
Group Pin Swapping with PADS Layout
Defining HETERO Devices for Power Schemes

Group Pin Swapping with PADS Layout

To implement group pin swapping in the PADS Layout tool, you must create a heterogeneous
package, in two representations: a schematic/graphical and a board/layout representation. This
enables you to group pins together, and instead of performing a pin swap in PADS Layout, you
perform a gate swap (equivalent to group pin swapping.).
The important properties to note are DEVICE and HETERO. The DEVICE property uses the
same value (74HC652) to tie the symbols together in the library (.lib) file. The HETERO
property defines the package of the components to be passed to layout.

PCB Interface User's Guide, X-ENTP VX.2.8 67

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Group Pin Swapping with PADS Layout

Figure 3-4. Group Pin Swapping in PADS Layout

In Figure 3-4, the HETERO property specifies the 74HC652.1 symbol in parentheses to indicate
only a schematic graphical representation. The 74HC652A.1 symbol contains all the relevant
board/layout information, (not specified in parentheses). Therefore, 74HC652A.1 enables you
to perform gate swaps in layout and to back annotate this information to the schematic. You can
use either symbol in the design schematic.

Note
74HC652A.1 does not necessarily have to be on the schematic, but it must reside in the
library search path for proper integration.

Related Topics
Heterogeneous Device Support

68 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Group Pin Swapping with PADS Layout

Gate Swapping in PADS Layout

PCB Interface User's Guide, X-ENTP VX.2.8 69

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
PADS Layout Design Creation

PADS Layout Design Creation

You can create a new PADS Layout design from a Xpedition Designer schematic using the
following methods.
Automatically Creating a New PADS Layout Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Manually Creating a New PADS Layout Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Automatically Creating a New PADS Layout Design

Use the Xpedition Designer PCB Interface to set options in the configuration file and run a
command line script to automatically import the Xpedition Designer schematic into PADS
Layout.
Prerequisites
• Xpedition Designer and PADS Layout tools must be installed on your computer.
• You must have performed steps 1 through 6 of “Creating a PCB Netlist File” on
page 10.
• In Step 2 of the Basic Flow, you must have chosen PADS VX from the Layout Tool
dropdown list.
Procedure
1. In the PCB Interface Dialog Box - Basic Tab, select the “Run command line after
processing” check box.
2. Click OK.
Result: The PCB Interface creates the netlist files and the Xpedition Designer To PADS
Layout dialog box appears.
3. In the Xpedition Designer To PADS Layout Dialog Box:
a. Click Create New PCB design.
b. If you want to use a template, select Start with Template PCB Design and type the
path name for your PCB design in the Template PCB Design Filename (*.pcb) text
field, or use the browse button to search for a PCB design.
c. Click Next.
4. In the Library Import Options Dialog Box:
a. Select Update Part Types in Library to transfer part types from Xpedition Designer
to PADS Layout, or uncheck the option to skip transferring part types and click
Next.

70 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Manually Creating a New PADS Layout Design

b. If the Part Type ASCII file (.p) does not display, use the browse button. The PCB
Interface tool creates the .p file, along with the rest of the netlist files, and places the
file in your Xpedition Designer Project folder prior to running the script.
c. Select the PADS Layout library to which you want to add the Xpedition Designer
parts.

Tip
You can click New Library to create a new PADS library. By default, libraries
reside in the ..\<latest_release>PADS\SDD_HOME\Libraries directory. The
new library appears at the bottom of the library list and search order.

d. Set the Import Mode for Library Parts.

5. Click Finish.
Results
The software creates the new .pcb file, adds the Xpedition Designer parts into the selected
library, and imports the selected netlist.
Related Topics
Manually Creating a New PADS Layout Design

Manually Creating a New PADS Layout Design

Use the Xpedition Designer PCB Interface to set options in the configuration file and output
netlist files to manually create a PADS layout design. Use this method when you do not have
PADS Layout installed on your system, and you must send the files to the layout designer.
Prerequisites
• You must have performed steps 1 through 6 of Creating a PCB Netlist File.
• In Step 2 of the Basic Flow, you must have chosen PADS VX from the Layout Tool
dropdown list.
Procedure
1. In the PCB Interface Dialog Box - Basic Tab, select Create Netlist for Layout (Forward
to Layout).
2. Clear “Run command line after processing” check box.
3. Click OK.
Result: The PCB Interface creates the following netlist files:*.asc, *.fdc, *.ndc, *.p,
*.db.

PCB Interface User's Guide, X-ENTP VX.2.8 71

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Manually Creating a New PADS Layout Design

4. In the PADS Layout window, choose File > Library. The Xpedition EDM Librarian
dialog box displays.
5. In the Xpedition EDM Librarian dialog box, select a library from theLibrary menu.
6. Click the Parts button.
7. Click Import. The Library Import File dialog box displays.
8. In the Library Import File dialog box, browse for the .p file and click Open.
9. Close the Xpedition EDM Librarian dialog box.
10. In the PADS Layout window, choose File > Import menu item. The File Import dialog
box displays.
11. In the File Import dialog box, browse for the .asc file and click Open.
Results
All component decals (footprints) appear in PADS Layout stacked on the origin. If this process
generated errors, an ascii.err file appears in your default text editor. You will need to resolve all
of the errors before proceeding. The software reports the following types of error conditions in
the ascii.err file:
• Library issues.
• Single or zero pin nets.
• Totally floating connections or subnets.
• Unnamed dangling connections (one end floating).
• Power and Ground symbols used on nets whose name differs from the default name on
the symbol.
• Multiple subnet nets where one or more subnets do not have an off-page symbol.
• Single subnet nets with an off-page symbol (lonely subnet warning).
• User named subnets that have no visible net name label.
Related Topics
PADS Layout Forward and Back Annotation Processes
Automatically Creating a New PADS Layout Design

72 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Compare the Schematic to the PADS Layout Design

Compare the Schematic to the PADS Layout

Design
Automatically or manually compare a Xpedition Designer schematic to a PADS layout using
the Xpedition Designer PCB Interface, and generate a differences report.
Comparing Designs Automatically. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Comparing Designs Manually . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Comparing Designs Automatically

Use the Xpedition Designer PCB Interface script to compare a Xpedition Designer schematic
design to a PADS Layout design, and generate a differences report.
Prerequisites
• Xpedition Designer and PADS Layout must both be installed on your computer.
• You must have performed steps 1 through 6 of Creating a PCB Netlist File.
• In Step 2 of the Basic Flow, you must have chosen PADS VX from the Layout Tool
dropdown list.
Procedure
1. In the PCB Interface Dialog Box - Basic Tab, select the “Run command line after
processing” check box.
2. Click OK.
Result: The PCB Interface creates the netlist files and the command line script runs.
3. In the Xpedition Designer To PADS Layout Dialog Box:
a. Select Compare Schematic with existing PCB design.
b. If your design pathname does not appear in the PCB Design Filename (*.pcb) text
field, type the pathname or browse for your PCB design.
c. Select Generate Differences Report, and uncheck the Update check boxes.
d. Click Next.
4. In the Library Import Options Dialog Box:
a. Select Update Part Types in Library to transfer part types from Xpedition Designer
to PADS Layout, or deselect the box to skip transferring part types and click Next.
b. If a file does not appear in the Part Type ASCII (*.p) text field, type the pathname or
browse to the file location. The PCB Interface tool creates the .p file, and places it
into the project folder prior to running the script.

PCB Interface User's Guide, X-ENTP VX.2.8 73

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Comparing Designs Manually

c. Select the PADS Layout library to add the Xpedition Designer parts.

Tip
Click New Library to create a new library in the SDD_HOME\Libraries
directory.

d. Select the Import Mode for Library Parts.

e. Click Next.
5. In the ECO Compare Options Dialog Box, set the options needed to meet your design
requirements.
6. Click Finish.
Results
The software creates the following files in the Xpedition Designer project folder:
• A differences (powerpcb.rep) file that reports the differences between the schematic and
layout design files.
• An error report (ecogen.err) file. You must resolve all of the errors before proceeding,
then follow the steps in this procedure to regenerate the PCB netlist file.
• An Engineering Change Order (*.eco) file. The forward and back annotation processes
use this file to synchronize the layout design and the schematic files.
Related Topics
Comparing Designs Manually

Comparing Designs Manually

Use the Xpedition Designer PCB Interface to set options in the configuration file and output
netlist files, and the PADS Layout Compare/ECO Tools options to compare designs and create
a differences report. Use this method when you do not have PADS Layout installed on your
system.
Prerequisites
• You must have performed steps 1 through 6 of Creating a PCB Netlist File.
• In Step 2 of the Basic Flow, you must have chosen PADS VX from the Layout Tool
dropdown list.
Procedure
1. In the PCB Interface Dialog Box - Basic Tab, clear the “Run command line after
processing” check box.
2. Click OK.

74 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Comparing Designs Manually

Result: The PCB Interface creates the following netlist files: *.asc, *.fdc, *.ndc, *.p,
*.db.
3. In PADS Layout window, choose Tools > Compare/ ECO menu item.
4. In the Compare/ECO Tools dialog box, select the Documents tab.
5. If you know the name of the original design, and newer design name, choose the
appropriate design (the original, older design) in the Original Design to Compare and
Update and New Design with Changes sections. If you do not know the name of the
original design, or newer design name, use the Original Design to Compare and Update
section to browse for the .asc netlist file in your Xpedition Designer project directory

Tip
Change the file type from PADS Layout Files (*.pcb) to ASCII Files (*.asc).

6. In the Output Options section, select Generate Differences Report and clear the other
options.
7. On the Comparison tab, set the comparison options.
8. On the Update tab, select the Update Options and Library check boxes.
9. Click Run.
10. In the Process Status dialog box, click Show Report.
Results
The software creates files in the PADS Layout working folder:
• Differences file (layout.rep) that reports the differences between the schematic and
layout design files.
• Log file (layout.log).

Note
You must provide the generated netlist files to the layout designer to generate the
differences report.

Related Topics
PADS Layout Forward and Back Annotation Processes
Comparing Designs Automatically

PCB Interface User's Guide, X-ENTP VX.2.8 75

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
PADS Layout Forward and Back Annotation Processes

PADS Layout Forward and Back Annotation

Processes
The automated forward annotation process compares data from a newer Xpedition Designer
schematic to an older PADS Layout design file, and updates the PADS Layout design to match
the schematic design. The software generates an .eco file which you would then import into
PADS Layout.
There may be situations where you may be unable to use the automated back annotation
process; for example, you may not have access to the automation scripts. In addition, your
PADS Layout and Xpedition Designer software may be located at different sites, such that they
do not have access to each others' applications and data. In this case, use the manual back
annotation process, and then provide netlist files to the layout designer who must generate the
.eco file of design changes and import it into PADS Layout.

The automated back annotation process automatically back annotates Allegro ECO changes and
net property data to the Xpedition Designer schematic.

Tip
To avoid unexpected changes during forward or back annotation, compare
Xpedition Designer to PADS Layout before you forward/back annotate design data (refer to
“Compare the Schematic to the PADS Layout Design” on page 73).

Automatically Forward Annotating to PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Manually Forward Annotating to PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Automatically Back Annotating from PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Manually Back Annotating from PADS Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Automatically Forward Annotating to PADS Layout

Use the Xpedition Designer PCB Interface to set options in the configuration file and a
command line script to automate forward annotating design data from an Xpedition Designer
schematic to the PADS layout.
Prerequisites
• Xpedition Designer and PADS Layout must be installed on the same system.
• You must have performed steps 1 through 6 of Creating a PCB Netlist File.
• In Step 2 of the Basic Flow, you must have chosen PADS VX from the Layout Tool
dropdown list.

76 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Automatically Forward Annotating to PADS Layout

Procedure
1. In the PCB Interface Dialog Box - Basic Tab, select the “Run command line after
processing” check box.
2. Click OK.
Result: The PCB Interface creates the netlist files and the Xpedition Designer To PADS
Layout dialog box appears.
3. In the Xpedition Designer To PADS Layout Dialog Box:
a. Click Compare Schematic with existing PCB design.
b. If your design pathname does not appear in the PCB Design Filename (*.pcb) text
field, type the pathname or browse for your PCB design.
c. Set the remaining options to meet your design requirements.
d. Click Next.
4. In the Library Import Options Dialog Box:
a. Select “Update Part Types in Library” to transfer part types from
Xpedition Designer to PADS Layout, or uncheck the box to skip transferring part
types, then click Next.
b. If the Part Type ASCII file (.p) does not display, use the browse button. The PCB
Interface tool creates the .p file, along with the rest of the netlist files, and places the
file in your Xpedition Designer Project folder prior to running the script.
c. Select the PADS Layout library to which you want to add the Xpedition Designer
parts.

Tip
Click New Library to create a new PADS library. By default, libraries reside in
the ..\<latest_release>PADS\SDD_HOME\Libraries directory. The new library
appears at the bottom of the library list and search order.

d. Set the Import Mode for Library Parts.

e. Click Next.
5. In the ECO Compare Options Dialog Box, set the options needed to meet your design
requirements.
6. Click Finish.
Results
The software generates an .eco file, and imports the file into PADS Layout. If this process
generated errors, an ascii.err file appears in your default text editor. You will need to resolve all

PCB Interface User's Guide, X-ENTP VX.2.8 77

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Manually Forward Annotating to PADS Layout

of the errors before proceeding. The software reports the following types of error conditions in
the ascii.err file
• Library issues.
• Single or zero pin nets.
• Totally floating connections or subnets.
• Unnamed dangling connections (one end floating).
• Power and Ground symbols used on nets whose name differs from the default name on
the symbol.
• Multiple subnet nets where one or more subnets has a missing an off-page symbol.
• Single subnet nets with an off-page symbol (lonely subnet warning).
• User named subnets that have no visible net name label.
Related Topics
PADS Layout Forward and Back Annotation Processes

Manually Forward Annotating to PADS Layout

Forward annotation compares data from a newerXpedition Designer schematic to an older
PADS Layout layout design, and updates the layout design to match the schematic design. Use
this method when you do not have PADS Layout installed on your system.
Prerequisites
• You must have performed steps 1 through 6 of Creating a PCB Netlist File.
• In Step 2 of the Basic Flow, you must have chosen PADS VX from the Layout Tool
dropdown list.
Procedure
1. In the PCB Interface Dialog Box - Basic Tab, clear the “Run command line after
processing” check box.
2. Click OK.
Result: The PCB Interface creates the following netlist files: *.asc, *.fdc, *.ndc, *.p,
*.db.
3. In PADS Layout window, choose Tools > Compare/ECO menu item.
4. In the Compare/ECO Tools dialog box, select the Documents tab.
5. In the New Design with Changes section, clear Use Current PCB Design. Browse for the
.asc netlist file in your Xpedition Designer project directory.

78 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Manually Forward Annotating to PADS Layout

Tip
Change the file type from PADS Layout Files (*.pcb) to ASCII Files (*.asc).

6. In the Original Design to Compare and Update section, select Use Current PCB Design.
7. In the Output Options section, select Generate ECO File and clear the other options.
8. On the Comparison tab, set the options according to your design needs.
9. On the Update tab, select Update Original Design in the Update Options section.

Tip
If you do not use this option, import the .asc file after you update the library with the
.p file.

10. In the Library section, select Update Part Types in Library. In the Part Type ASCII File
text field, browse for the .p netlist file in your Xpedition Designer project directory.

Note
If you do not use this option, import the .p file into the library using the
Xpedition EDM Librarian.

11. Select the PADS Layout library to which you want to add the Xpedition Designer parts.

Tip
Click New Library to create a new PADS library. By default, libraries reside in the
..\<latest_release>PADS\SDD_HOME\Libraries directory. The new library appears
at the bottom of the library list and search order.

12. ClickOK.
Results
The software generates an .eco file, and imports the file into PADS Layout. If this process
generated errors, an ascii.err file appears in your default text editor. You will need to resolve all
of the errors before proceeding. The software reports the following types of error conditions in
the ascii.err file
• Library issues.
• Single or zero pin nets.
• Totally floating connections or subnets.
• Unnamed dangling connections (one end floating).
• Power and Ground symbols used on nets whose name is different from the default name
on the symbol.
• Multiple subnet nets where one or more subnets is missing an off-page symbol.

PCB Interface User's Guide, X-ENTP VX.2.8 79

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Automatically Back Annotating from PADS Layout

• Single subnet nets with an off-page symbol (lonely subnet warning).

• User named subnets that have no visible net name label.
Related Topics
PADS Layout Forward and Back Annotation Processes

Automatically Back Annotating from PADS Layout

Use the Xpedition Designer PCB Interface to set options in the configuration file and a
command line script to automate back annotating design data from the PCB layout to a
Xpedition Designer schematic. Back annotation compares data from an older
Xpedition Designer schematic to a newer PADS Layout design file, and updates the
Xpedition Designer schematic to match the layout design.
Caution
Before you re-number the reference designators, record the .eco file to maintain discrete
relationships.

Prerequisites
• Xpedition Designer and PADS Layout must be installed on your computer.
• You must have performed steps 1 through 6 of Creating a PCB Netlist File.
• In Step 2 of the Basic Flow, you must have chosen PADS VX from the Layout Tool
dropdown list.
Procedure
1. In the PCB Interface Dialog Box - Basic Tab, select Back Annotate Information From
Layout to Schematic.
2. [Optional] If additional modifications to the configuration file are needed, open a text
editor and update the file.
3. Select the “Run command line after processing” checkbox.
4. Click OK.
5. In the PADS Layout To Xpedition Designer Dialog Box, make sure that your .pcb file
displays in the PCB Design Filename (*.pcb) text field.
a. If your design pathname does not appear in the PCB Design Filename (*.pcb) text
field, type the pathname or browse for your PCB design.
6. Define the ECO Options.
a. Select Use an Existing ECO file, and type the pathname or browse for the .eco file,
then click Finish.

80 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Manually Back Annotating from PADS Layout

or
b. Select Create ECO File Using Netlist Comparison, and choose the options for the
.eco file, then click Next.
c. In the ECO Compare Options Dialog Box, define the options needed to meet your
design requirements.
d. Click Finish.
Results
The script generates the .asc and .eco files required for back annotation, and the PCB Interface
tool back annotates the files to the Xpedition Designer tool.
Related Topics
PADS Layout Forward and Back Annotation Processes

Manually Back Annotating from PADS Layout

There may be situations where you may be unable to use the automated back annotation
process. In this case, use the manual back annotation process to use the files generated by the
PADS Layout tool and update your Xpedition Designer schematic. Use this method when you
do not have PADS Layout installed on your system.
Prerequisites
You must acquire the .asc and .eco file from the layout designer before you can import them
into Xpedition Designer.

Procedure
1. In a PADS Layout window, choose the Tools > Compare/ECO menu item.
2. In the Compare/ECO Tools dialog box, select the Documents tab.
3. Select Use Current PCB Design.
4. Clear Use Current PCB Design and browse for the original .asc netlist file output from
your Xpedition Designer design.

Tip
Change the file type from PADS Layout Files (*.pcb) to ASCII Files (*.asc).

5. Select Generate ECO File, and type a file pathname or browse for the file location.
6. Select Generate ASCII File for Back Annotation to Schematic, and type a file pathname
or browse for the file location.
7. On the Comparison tab, set the options according to your design needs.

PCB Interface User's Guide, X-ENTP VX.2.8 81

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Manually Back Annotating from PADS Layout

8. On the Update tab, clear Update Part Types in Library.

9. Click Run.
10. In the Process Status dialog box, click Close.
11. Move the .asc and .eco files to the Xpedition Designer project directory and verify that
the filenames match the Xpedition Designer project name.

Tip
Rename the original schematic .asc file, to stop it being overwritten by the file being
used for back annotation.

12. In the Xpedition Designer tool, choose the Setup > Settings menu item to open the
Settings dialog box.
13. Click the Project tab to open the Project tab.
a. Select PADS VX from the Layout Tool dropdown list.
b. (Optional) Select Use Custom Constraints file, and specify the location of your
custom constraints (.cns) file in the Constraints Definition text box.
c. (Optional) Select Use Custom Configuration file, and specify the location of your
custom configuration (.cfg) file in the PCB Configuration text box.
d. Click OK to close the Settings dialog box.
14. Choose the Tools > PCB Interface menu item to open the PCB Interface dialog box.
15. On the PCB Interface Dialog Box - Advanced Tab, select Automatically Back Annotate
Changes to Schematic.
16. On the Advanced and PCB Interface Dialog Box - Constraints Tab tabs, set the options
needed to meet your design requirements.
17. Click the Basic tab to open the PCB Interface Dialog Box - Basic Tab.

Note
The software automatically adds the default design name and the PADS Layout file
path to the fields in the PCB Interface dialog box.

18. Select Back Annotate Information From Layout to Schematic.

19. Clear the “Run command line after processing” check box.
20. Click OK.
Related Topics
PADS Layout Forward and Back Annotation Processes

82 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Xpedition Layout Interface

Xpedition Layout Interface

The Xpedition Designer to Xpedition interface enables design and device information to be
passed between Xpedition Designer and Xpedition Layout, occurring through importing and
exporting netlist files. It also provides back annotation of pin swaps, gate swaps, and reference
designator changes.
Data Transfer to Xpedition Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Data Transfer from Xpedition Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Required Xpedition Layout Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Swapping Pins Within Xpedition Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Forward and Back Annotation with Xpedition Layout . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Data Transfer to Xpedition Layout

The Xpedition Designer to Xpedition Layout data transfer process uses a variety of input and
output files for forward annotation.

Table 3-10. xPCB Layout Forward Annotate Input and Output Files
Input / Filename Description
Output
Input Files expedition.cfg Configuration file.
\wir\design_name.* Design wire files (connectivity data).

PCB Interface User's Guide, X-ENTP VX.2.8 83

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Data Transfer to Xpedition Layout

Table 3-10. xPCB Layout Forward Annotate Input and Output Files (cont.)
Input / Filename Description
Output
Output Files comps.fwd Component forward annotation file.
gates.fwd Gate forward annotation file.
nets.fwd Net forward annotation file
pins.fwd Pin forward annotation file
pcb.err Error file.
design_name.ndc Net dictionary file which controls bidirectional
translation of names when annotating information to
and from xPCB Layout.
Use only when the netlister finds an invalid net or
instance name in the design, and you set the
configuration file to continue with a new net name
(new net name could have an illegal character
replaced or removed).
design_name.fdc Function dictionary file containing definitions of
component names and properties. Similar to the net
dictionary (.ndc) file.
design_name.tfn Flat net definition file.
design_name.tna Flat net alias file.
design_name.tnp Net property file.
design_name.tpa Path definition file.
design_name.tpd Property definition file.
design_name.tpn Symbol pin file.
design_name.tpp Symbol pin property file.
design_name.tsh Sheet definition file.
design_name.tsp Symbol property file.
design_name.txt ASCII parts database (PDB) file.
design_name.tsy Symbol file.
pdb.hkp Design specific PDB data file.

Related Topics
Data Transfer from Xpedition Layout
Required Xpedition Layout Properties

84 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Data Transfer from Xpedition Layout

Data Transfer from Xpedition Layout

The Xpedition Designer to Xpedition Layout data transfer process uses a variety of input and
output files for back annotation.
Note
Before you back annotate design data, copy the input files to your project directory.

Table 3-11. Xpedition Layout Back Annotate Input and Output Files
Input / Filename Description
Output
Input Files design_name.tfn Flat net definition file.
design_name.tnp Net property file.
design_name.tpd Property definition file.
design_name.tpn Symbol pin file.
design_name.tpp Symbol pin property file.
design_name.tsp Symbol property file.
design_name.tsy Symbol file.
Output Files design._namebaf The PCB Interface tool produces this back
annotation file if the .cfg file contains the keyword
WRITEBAF YES.
Otherwise the PCB Interface tool back annotates
information to the schematic itself.
comps.bck Component back annotation file.
gates.bck Gate back annotation file
nets.bck Net back annotation file
pins.bck Pin back annotation file.

Related Topics
Data Transfer to Xpedition Layout
Required Xpedition Layout Properties

Required Xpedition Layout Properties

You can specify the required properties keywords in the configuration file.

PCB Interface User's Guide, X-ENTP VX.2.8 85

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Swapping Pins Within Xpedition Layout

Table 3-12. Xpedition Layout Required Properties

Required Attribute Description
DEVICE All components must have a DEVICE property at either the
symbol or component level. The PCB Interface tool uses this
property to create entries for each part type in the .txt file.
Generally, you would specify the DEVICE property on the
symbol, however, if you want a different entry for each set of
resistors that have a particular VALUE and TOLERANCE
attribute, you should not attach the DEVICE property on the
symbol.
PIN TYPE The value of this property results in the %TOPCELL entry in
the .txt file.
PINTYPE Each symbol pin in Xpedition Designer should have a
PINTYPE property with one of the following values: IN,
OUT, BI, TRI, ANALOG, OCL, OEM.

DEVICE Property on Resistors Example

Each resistor with the same VALUE property has the same DEVICE property. This results in
separate entries for RES1K, RES2K and RES100K in the .txt file.

You use the Databook tool to group properties belonging to a particular DEVICE. When using
the Xpedition Layout interface, ensure that the Databook tool database contains the DEVICE
property for each entry in the database.

Figure 3-5. Resistors with Different Properties

Related Topics
Swapping Pins Within Xpedition Layout

Swapping Pins Within Xpedition Layout

The PINSWAP property generates detailed pin swapping information. Use this property to
specify the gate and pin swapping information that the Xpedition Layout Interface writes to the
Xpedition Layout ASCII PDB file.

86 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Swapping Pins Within Xpedition Layout

When specifying the pins to be swapped, use parentheses to contain groups that the interface
can swap, and brackets to contain groups that the interface cannot swap.

Note
You cannot specify discrete groups of pins to swap with other discrete groups of pins. If you
attempt to do this by using square brackets, the PCB Interface tool ignores all pin swap
information.

Use the following syntax to specify individual pins that can be swapped using the PINSWAP
attribute:

PINSWAP=(A,B,C, ... )

where A, B, C, and so on, can all be swapped with each other.

You can also use the syntax:

(A,B),(C,D), ...

where A can be swapped with B, C can be swapped with D, and so on.

You can swap groups of pins with other groups of pins using the following syntax:

PINSWAP=([A, B], [C, D], ...)

where the interface can swap A and B, as a group, with C and D, as a group.

More complex syntax is also supported:

PINSWAP=([(A, B), C], [(D, E), F])

where the interface can swap A and B with each other, but not with C, and it can swap D and E
with each other, but not with F. The interface can also swap the group A, B, C with the group D,
E, F.

Related Topics
Required Xpedition Layout Properties
System Property Definitions [Xpedition Designer and Xpedition System Designer Properties
Glossary]

PCB Interface User's Guide, X-ENTP VX.2.8 87

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Forward and Back Annotation with Xpedition Layout

Forward and Back Annotation with

Xpedition Layout
Use the Xpedition Designer PCB Interface tool to set options in the configuration file and a
command line script to automate forward and back annotation of design data from an
Xpedition Designer schematic to the Xpedition Layout layout.
Note
Refer to the Xpedition documentation for more information about forward and back
annotation operations.

Related Topics
Data Transfer to Xpedition Layout
Data Transfer from Xpedition Layout
Required Xpedition Layout Properties

88 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
RINF Layout Interface

RINF Layout Interface

The RINF interface enables design and device information to be passed between
Xpedition Designer and the standard Visula or Visula VDP from Racal-Redac®, which reads
and writes RINF file format. The interface also enables back annotation of pin swaps (using
HETERO 4), gate swaps, and reference designator changes, changes in placement and package
type.
Note
Contact Zuken for more information about forward and back annotation operations.

RINF does not support the PINSWAP property. Use HETERO 4 as a workaround for group pin
swapping (refer to Figure 4-1 and Figure 4-2 for different representations of the same device).

The RINF interface supports the following Visula features in addition to the General PCB
Interface-supported features.

• PCB Interface to Visula

o Creates a netlist file with optional property passing. The netlist file extension (.frs)
for both a RINF and a Visula VDP netlist.
o Optional outputs placement data.
• PCB Interface from Visula
o Supports back annotation of properties, placement, changes to package type,
component & net renames and pin & gate swaps. File extensions for RINF and
Visual VDP (RINF (.irp), Visula VDP (.erp)).
o Supports detection of net or component deletions and electrical changes.

Note
Back annotation requires an incremental netlist file. Contact Zuken for more
information.

Data Transfer to RINF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Data Transfer from RINF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Keywords Specific to RINF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Data Transfer to RINF

The Xpedition Designer - RINF data transfer process uses the following input and output files
for forward annotation.

PCB Interface User's Guide, X-ENTP VX.2.8 89

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Data Transfer from RINF

Table 3-13. To RINF Input Data Files

Input Filename Description
rinf.cfg Configuration file.
\wir\design_name.* Design wire files which contain connectivity data.

Table 3-14. To RINF Data Output Files

Output Filename Description
design_name.frs Netlist file (full RINF output).
pcb.err Error file which you can load into ViewNavigator for
automatic searching of errors.
design_name.fdc Function dictionary file. Similar to the net dictionary (.ndc)
file. Contains definitions of component names and properties.
design_name.ndc Net dictionary file. Used only when the netlister finds an
invalid net or instance name in the design and the
configuration file is set to continue with a new net name (new
net name could have an illegal character replaced or removed).
Controls bidirectional translation of names when annotating
information to and from PADS Layout.
design_name.baf Back annotation file produced if the .cfg file contains the
WRITEBAF YES keyword.

Related Topics
Data Transfer from RINF
Keywords Specific to RINF

Data Transfer from RINF

The Xpedition Designer - RINF data transfer process uses the following input and output files
for back annotation.
Note
Before you back annotate design data, copy the input files to your project directory.

Table 3-15. From RINF Data Input Files

Input Filenames Description
design_name.irp Third-party back annotation file (incremental RINF).

90 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Keywords Specific to RINF

Table 3-15. From RINF Data Input Files (cont.)

Input Filenames Description
design_name.erp Third-party back annotation file (incremental RINF) VDP
version.

Table 3-16. From RINF Data Output File

Output Filename Description
design_name.baf Back annotation file produced if the .cfg file contains the
WRITEBAF YES keyword.

Related Topics
Data Transfer to RINF
Keywords Specific to RINF

Keywords Specific to RINF

You can specify the following unique RINF keywords in the RINF configuration file.

Table 3-17. RINF Unique Keywords

RINF Unique Keywords Description
LongFile Use for compatibility with Racal Redac tools that cannot
interpret the default format
Yes — Modifies the netlist file format to generate the file with
refdes and pin numbers in a column.
Default: No.
OutputPac Yes — Outputs the .PAC statement
Default: No.

The following properties must be present on the symbols:

Table 3-18. RINF Required Keywords
RINF Required Keywords Description
DEVICE and/or.
PART_TYPE PART_TYPE has priority.
P/D_NUM If not present, the field is left blank in the .frs file.
PKG PKG_TYPE Must be included in the AttPassList section of the
configuration file.

PCB Interface User's Guide, X-ENTP VX.2.8 91

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Keywords Specific to RINF

Table 3-18. RINF Required Keywords (cont.)

RINF Required Keywords Description
PKG P/D_NUM Must be included in the AttPassList section of the
configuration file.
PKG PART_TYPE Must be included in the AttPassList section of the
configuration file.
The following required attributes must be present on the symbols.
Table 3-19. RINF Required Attributes
RINF Required Attributes Description
# (Pin) Assigned to the pin and are used to map pins to the physical
device.
DEVICE Identifies the RINF part type name for a
Xpedition Designer symbol. Use this property if the RINF
layout system part type name is different from the
Xpedition Designer symbol name. The value of the
DEVICE property must match a value of the Part key in the
Visula database.
PARTS Identifies the number of component (slots) in a package.
The number of parts must match the number of pins listed
for each # property on the symbol.
For example, if PARTS=4, each # property must specify
four pin numbers. The default value if this property is not
specified is PARTS=1.
REFDES Defines the component name in RINF.

The following optional attributes may be present on the symbols.

Table 3-20. RINF Optional Attributes
RINF Optional Attributes Description
HETERO Used for implementing heterogeneous package functionality
(refer to Heterogeneous Device Support).
LEVEL Prevents netlisting of underlying schematics for composite
symbols.
NC Identifies unconnected external package pins. If used, the
specified No-connect pin must not be explicitly drawn on the
symbol.
For example, for multiple NC pins, use NC=2,4,5. Required
for certain types of packages (such as the FK package versus
J package).

92 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Keywords Specific to RINF

Table 3-20. RINF Optional Attributes (cont.)

RINF Optional Attributes Description
P/D_NUM Used to identify the unique part number in the Visula Central
Database.
PKG_TYPE Identifies which package symbol alternate to use. This
property needs to be in the AttPassList section of the RINF
configuration file.
PINTYPE Identifies the individual pin types (IN, OUT, BI, and so on).
SIGNAL Identifies an implicit pin connection to a specific net. For
multiple pins of the same signal, use commas to separate the
pins.
For example: SIGNAL=VCC;4,8

Related Topics
Data Transfer from RINF
Data Transfer Files To Allegro

PCB Interface User's Guide, X-ENTP VX.2.8 93

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Symbol Preparation for RINF

Symbol Preparation for RINF

Attributes assign non-graphical data to individual components in your schematic. The PCB
Interface uses the translation information in the rinf.cfg file to interpret the netlist file and
property data for use by Visula RINF.
Figure 3-6 shows an example of a symbol that has all the appropriate properties for optimum
placement in Visula RINF.

Figure 3-6. Symbol Attributes for RINF

Group Pin Swapping with RINF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Visula VDP Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Group Pin Swapping with RINF

To implement group pin swapping in Visula RINF, you must create a heterogeneous package in
two representations: a schematic/graphical and a board/layout representation. This enables you
to group pins together, and instead of performing a pin swap in Visula RINF, you perform a gate
swap (equivalent to group pin swapping.)
The important properties to note are DEVICE and HETERO. The DEVICE property uses the
same value (74HC652) to tie the symbols together in the library (.lib) file. The HETERO
property defines the package of the components to be passed to layout.

94 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Group Pin Swapping with RINF

Figure 3-7. Group Pin Swapping in RINF

In Figure 3-7, the HETERO property specifies the 74HC652.1 symbol in parentheses to indicate
only a schematic graphical representation. The 74HC652A.1 symbol contains all the relevant
board/layout information, (not specified in parentheses). Therefore, 74HC652A.1 enables you
to perform gate swaps in layout and to back annotate this information to the schematic. You can
use either symbol in the design schematic.

Note
74HC652A.1 does not necessarily have to be on the schematic, but it must reside in the
library search path for proper integration.

PCB Interface User's Guide, X-ENTP VX.2.8 95

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Visula VDP Interface

Related Topics
Heterogeneous Device Support
Symbol Preparation for RINF
Visula VDP Interface

Visula VDP Interface

Visula VDP enables designs to be partitioned or broken down into subcircuits.
Note
Contact Zuken for more information about forward and back annotation operations.

In the Xpedition Designer environment, the software treats these subcircuits as standalone
designs, and checks and packages them individually. Xpedition Designer represents subcircuits
as a special case of a hierarchical, or composite block. After packaging, the software instantiates
these blocks on the top-level design. The design may also contain standard hierarchical blocks.

Note
Visula VDP cannot span VDP subcircuits. All components that you want to be in the same
package must be placed in the same subcircuit.

When using the Visula VDP Interface, review the following restrictions when using subcircuits
in the Xpedition Designer environment:

• You must also have OATs enabled in the rinf_vdp.cfg file.

• You must place the SUBCIRCUIT property on all composite symbol blocks that you
want be used as VDP subcircuits. Do not place this property on the instantiated
component. The software treats any composite blocks that do not have the
SUBCIRCUIT property at the symbol level as a standard hierarchical component.
• You must run Check Project and Refdes on each subcircuit before instantiating it at the
top level. The pcbfwd command then runs on each subcircuit from the bottom up.
• Whenever you make a change to a subcircuit in layout, you must run pcbbck on this
subcircuit. Then you must run pcbfwd again on the changed subcircuit, on any parent
subcircuit of the changed subcircuit, and on the top level. This guarantees consistency
across the top level design and its subcircuits.
Related Topics
Heterogeneous Device Support
Symbol Preparation for RINF

96 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Allegro PCB Layout Interface

Allegro PCB Layout Interface

The Allegro layout interface enables design and device information to be passed between
Xpedition Designer and the Allegro PCB system. It also enables back annotation of pin swaps,
gate swaps, and reference designator changes.
The Allegro layout interface supports the following layout mode features.
Table 3-21. Allegro PCB Layout To and From Layout Modes
Mode Description
To Layout Mode • Creation of a netlist file with optional property (attribute) passing.
• Optional creation of placement files.
• Optional creation of device files.
From Layout Mode • Back annotation of properties, placement and changes to package
types, reference designators, and pin and gate swaps.
• Optional generation of delay table (.dtb) files from the output of the
Allegro tldelay program.

Note
It is extremely important to save the board under a different name each time you read
Xpedition Designer design data into Allegro (due to the method Allegro uses to write its
third-party back annotation format).

Data Transfer Files To Allegro. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Data Transfer Files From Allegro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Allegro Keywords and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Device File Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Creating an Alternate Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Data Transfer Files To Allegro

The following files are part of the Xpedition Designer-Allegro data transfer process:

Table 3-22. Allegro Forward Annotate Input and Output Files

Input / Filename Description
Output
Input Files allegro1n.cfg Configuration file.
\wir\design_name.* Design wire files (connectivity data).

PCB Interface User's Guide, X-ENTP VX.2.8 97

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Data Transfer Files From Allegro

Table 3-22. Allegro Forward Annotate Input and Output Files (cont.)
Input / Filename Description
Output
Output Files device.txt Device file, one for each device in the design.
design_name.plc Placement file (optional).
design_name.tel1 Allegro netlist file.
pcb.err Error file.
design_name.fdc Function dictionary file.
design_name.ndc Net dictionary file.
design_name.baf Back-annotation file produced if the configuration
file contains the WRITEBAF YES keyword.
1. Copy the design_name.tel, device.txt, and design.plc files to your Allegro project directory and read the
data into the Allegro design using the Allegro Netin command.

Related Topics
Data Transfer Files From Allegro
Device File Properties

Data Transfer Files From Allegro

The following files are part of the Allegro - Xpedition Designer data transfer process.
Note
Before back annotating design data, copy the input files to your project directory.

Table 3-23. Allegro Back Annotate Input and Output Files

Input / Filename Description
Output
Input Files design_name.abk Allegro third-party back annotation file. You must
rename this file manually from the design.baf file
produced by Allegro to avoid conflict with the
DxDesigner.baf file.
design_name.dtb Timing delay file (optional).
design_name.ipn Optional output files of the Allegro tldelay program
(optional).
design_name.tl2 Netlist file.

98 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Allegro Keywords and Attributes

Table 3-23. Allegro Back Annotate Input and Output Files (cont.)
Input / Filename Description
Output
Output File design_name.baf Back annotation file produced if the configuration
file contains the WRITEBAF YES keyword.

Related Topics
Data Transfer Files To Allegro
Device File Properties

Allegro Keywords and Attributes

You can specify the following Allegro keywords in the General Information section of the
configuration file.
To identify component properties that belong to Allegro device files as properties, the DEV
keyword may be specified in the AttPassList section of the configuration file.
Table 3-24. Allegro Keywords
Keyword Description
AllegroQuoteTrigger C programming syntax for specifying triggers.
CmpAttInDvf Yes — the PCB Interface tool passes the component property in
the device file.
DelayScale Scales the transmission line delay numbers from the Allegro
tldelay program, to a scale appropriate for a DxDesigner.dtb file
by multiplying the tldelay numbers by the number indicated
after the keyword.
DelayUnits Specifies the units string for output into the DxDesigner.dtb file
when the OutPinDelay keyword equals Yes.
DoAllegroQuote Controls use of quotes for Allegro. Accepts Yes or No as its
value.
InPinExt Identifies the file extension for the tldelay input file (default
value is .ipn).
InPinFNme Identifies the input filename of Allegro tldelay file.
OutPinDelay Controls whether the PCB Interface creates a timing delay file
from the results of Allegro's tldelay program. Accepts Yes or No
as its value.
OutPinExt Identifies the output file extension for the delay table file.
Default value: .dtb.
OutPinFnme Identifies the output filename of the Allegro delay table file.

PCB Interface User's Guide, X-ENTP VX.2.8 99

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Allegro Keywords and Attributes

Table 3-24. Allegro Keywords (cont.)

Keyword Description
DoPinAttributes Yes (default value) — the PCB Interface tool passes pin
properties to Allegro.
PinFileName Identifies the filename (without an extension) that contains the
$PINS data in. To use the default filename (design name),
comment out this keyword.
PinFileExt Identifies the extension of the file that the PCB Interface places
the $PINS data in.
Default extension: .pin.
The Allegro PCB layout tool requires that certain attributes/properties be in the configuration
file to assist in a successful data transfer.
Table 3-25. Required Allegro Properties
Property Name Description
PKG_TYPE Maps to the Allegro package symbol.
PARTS, # Defines the individual functions in the Allegro device file (.txt file).
REFDES Defines the reference designator in Allegro.

The Allegro PCB layout tool does not require that you add optional attributes/properties in the
configuration file. However, if these properties exist in the configuration file, Mentor Graphics
recommends you add as much information as possible to clearly define their use.

Tip
Standard Xpedition Designer library parts have many of these properties already defined.

Table 3-26. Optional Allegro Properties

Property Name Description
ALT_SYMBOLS Specifies alternate Allegro layout symbols which may be called
during layout.
For specific notation regarding the appropriate value for this
attribute, refer to the Allegro documentation.
You should check the property value syntax by adding the
appropriate line to the CHKVAL section in the configuration file.
Note: To pass this property to Allegro, your configuration file
must have the DEV ALT_SYMBOLS entry specified in the
General > BeginAttPassList section.
DEVICE Defines the name of the Allegro device file (.txt file).
Default: symbol name.

100 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Allegro Keywords and Attributes

Table 3-26. Optional Allegro Properties (cont.)

Property Name Description
CLASS Identifies a device family for the symbol.
HETERO Implements heterogeneous package functionality. There are
different types of heterogeneous packages (see “Heterogeneous
Device Support” on page 117).
LEVEL Prevents netlisting of underlying schematics for composite
symbols.
NC Identifies unconnected external package pins.
If using the NC property, the specified no-connect pin must not be
explicitly drawn on the symbol.
Refer to TI Data Book, device SN54HC00, for examples on using
unconnected pins.
PINSWAP Identifies swappable pins in Allegro. You must specify the pin
labels which are swappable.
Note: Allegro does not support group pin swapping. You must use
HETERO 4 packaging to implement this functionality (refer to
“Heterogeneous Device Support” on page 117).
PINTYPE Identifies the individual pins type (such as IN, OUT, BI).
SIGNAL Indicates an implicit pin connection to a specific net. For multiple
pins of the same signal, use commas to separate the pins. For
example: SIGNAL=VCC;4,8.
TOLERANCE Specifies the tolerance of a discrete component.
VALUE Specifies the numeric value of a discrete component.
Table 3-27 shows the correspondence between the Xpedition Designer configuration file
keyword and the keyword equivalent in the notes subsection of the Allegro netlist file.
Table 3-27. Allegro Attributes
Xpedition Designer .cfg File Allegro Netlist Keyword
Keyword
NET = Allegro $NETS property
COM = Allegro $FUNCTIONS property
PKG = Allegro $PACKAGES property
DEV = Allegro device file pro

Related Topics
Data Transfer Files From Allegro
Data Transfer Files To Allegro

PCB Interface User's Guide, X-ENTP VX.2.8 101

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Device File Properties

Device File Properties

Device File Properties

Previously, Xpedition Designer symbol properties which were configured as DEV properties in
the AttPassList would appear in the device files as device properties. By setting the
CmpAttInDvf keyword to Yes, the PCB Interface changes how it assigns device file properties
to Allegro device files from the Xpedition Designer schematic.
Note
Mentor Graphics does not recommend using this functionality. By default, $PACKAGES
(PKG in the Attribute Pass List) comes from the component and can override symbol device
file properties.

Setting CmpAttInDvf to Yes, enables the component property value to appear in the device file.
If using multiple identical packages, the particular instance from which CmpAttInDvf extracts
the component property cannot be specified (except for different component properties), and the
following warning appears:

pcb: Warning: 6286: Device property name=value being overridden with value
from package due to CmpAttInDvf

Related Topics
Data Transfer Files From Allegro
Data Transfer Files To Allegro
Allegro Keywords and Attributes

Creating an Alternate Package

Use this procedure if you want the PCB Interface tool to use an alternate package for a given
instance of a part and then call the alternate package into the Allegro layout tool.
Procedure
1. Add the following lines to the General section of the Allegro configuration file:
DoAlternates yes | [no] | Enables the ALTs processing

2. In the BeginAttPassList section of the configuration file, add the following lines:
PKG ALT_PKG
PKG ALT_DEV
PKG ALT_TAG

102 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Creating an Alternate Package

3. In the BeginChkRules section of the configuration file, modify or add the following
lines:
CHKBRD _REF_CONFL WRN 1 | REFDES has conflicting properties,
1=repack
CHKVAL _NAME_CHK COM ALT_TAG ERR 0 "a-zA-Z0-9" " " 1 *
CHKVAL _NAME_CHK COM ALT_PKG ERR 0 "a-zA-Z0-9" " " 1 *
CHKVAL _NAME_CHK COM ALTDEV ERR 0 "a-zA-Z0-9" " " 1 *

4. Add the ALT_TAG, ALT_PKG, and ALT_DEV properties to the components.

Results
After making these changes to the Allegro configuration file, the software generates an .adc file
after running the PCB Interface tool.
Related Topics
Device File Properties
Basic Configuration File Format

PCB Interface User's Guide, X-ENTP VX.2.8 103

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Symbol Preparation for Allegro

Symbol Preparation for Allegro

Attributes are used to assign non-graphical data to individual components in your schematic.
The PCB Interface tool uses the translation information in the allegro<version>.cfg file to
interpret the netlist file and property data so that it can be used by Allegro.
Figure 3-8 shows an example of a symbol that has all the appropriate properties for optimum
placement in Allegro.

Figure 3-8. Symbol Attributes for Allegro

Group Pin Swapping with Allegro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Passing Pin Attributes to Allegro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Allegro Netlist File Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Group Pin Swapping with Allegro

To implement group pin swapping in Allegro, you must specify a heterogeneous package,
which enables pins to be grouped together. Instead of doing a pin swap in Allegro you perform
a gate swap, (equivalent to group pin swapping).
The important properties to note are the DEVICE property and the HETERO attribute. The
DEVICE property now ties the two symbols together in the Allegro device (.txt) files. The
HETERO property defines the package of the components to be passed to Allegro.

Heterogeneous packaging, provides a schematic/graphical representation and a board/layout

representation (see Different Representations of the Same Device).

104 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Group Pin Swapping with Allegro

In Figure 3-9, the HETERO property specifies the 74HC652.1 symbol in parentheses to indicate
only a schematic graphical representation. The 74HC652A.1 symbol contains all the relevant
board/layout information, (not specified in parentheses). Therefore, 74HC652A.1 enables you
to perform gate swaps in layout and to back annotate this information to the schematic. You can
use either symbol in the design schematic.

Note
74HC652A.1 does not necessarily have to be on the schematic, but it must reside in the
library search path for proper integration.

Figure 3-9. Group Pin Swapping in Allegro

PCB Interface User's Guide, X-ENTP VX.2.8 105

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Passing Pin Attributes to Allegro

Related Topics
System Property Definitions [Xpedition Designer and Xpedition System Designer Properties
Glossary]

Passing Pin Attributes to Allegro

The Allegro PCB Interface tool supports the passing of pin properties to the Allegro PCB layout
tool.
Note
The initial upload of Allegro does not process the $PINS section in the .tel file, but the PCB
Interface tool can write the $PINS section to a second file, which can then be read in as an
incremental netlist file.

Procedure
1. Open the allegro<version>.cfg file in a text editor.
2. Set the DoPinAttributes keyword to Yes.
3. Set the PinsFileName keyword to the name of the file (without the extension) to which
the PCB Interface tool writes the $PINS data. By default, the name of the file is the
design name.
4. Set the PinsFileExt keyword to the file extension of the file to which the PCB Interface
writes the $PINS data. By default, the file extension is .pin.
5. Add the property to the General portion of the AttPassList section with 115 an object
type of PPN.
6. In Allegro, read the initial netlist (.tel) file.
7. Read the .pin file with Set Supersede All Logical Data flag set to False in the Allegro
Netlist-In dialog box.
Results
The Allegro PCB tool reads the new pin netlist file (*.pin), that you just created into Allegro
PCB layout.
Related Topics
Creating an Alternate Package
Group Pin Swapping with Allegro

106 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Allegro Netlist File Scheduling

Allegro Netlist File Scheduling

The Allegro layout system supports scheduling of nets in its netlist file. Scheduling enables the
ordering of the pins and pin routing for a particular net.
You assign the SCHED property to each pin on a net that you want to have scheduled in the
Allegro netlist file. Though it is a Xpedition Designer attribute, the SCHED property performs
no direct function within Xpedition Designer. It simply identifies nets in a Xpedition Designer
design that are to be scheduled in Allegro.

The syntax for Allegro scheduling starts with a net name, followed by a series of pin groups,
separated by a semicolon, and each pin in each group separated by a comma. The netlist file
appears as follows:

$SCHEDULE
1N25 ; U1.3 U1.6 U1.8 U2.3 ; U2.3 U2.6 U2.11, U2.8 U3.3 ; U1.6 U1.12 ; U3.3
U1.13

The following syntax defines the value for each instance of a SCHED property:

SCHED=(order_in_group), group_#,second_group

The order_in_group argument must appear in parentheses and can use the optional argument
second_group.

Note
Consult your Cadence Allegro documentation for a more in-depth discussion of scheduling
syntax.

Related Topics
Device File Properties

PCB Interface User's Guide, X-ENTP VX.2.8 107

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Allegro Forward and Back Annotation Processes

Allegro Forward and Back Annotation

Processes
The Allegro to Forward and Back Annotation can be done in three different ways; Automatic,
Semi-Automatic or manually.
The automated forward annotation process generates Allegro netlist and device files, then uses
them to update the Allegro board file.When you use the automated forward process, the pcbfwd
command generates the netlist file, updates the Allegro board, and saves all the files you need to
edit and back annotate the board. The automated back annotation process automatically back
annotates Allegro ECO changes and net property data to the Xpedition Designer schematic.

You would use semi-automatic if you install and maintain Xpedition Designer and Allegro in
exclusive environments. In this case, you can still copy the automated scripts into the Allegro
environment, and also run scripts from the command line:

There may be situations where you may be unable to use the automated back annotation
process; for example, you may not have access to the automation scripts. In addition, your
Allegro and Xpedition Designer software may be located at different sites, such that they do not
have access to each others' applications and data. In this case, use the manual back annotation
process to generate the Allegro ECO file and update your Xpedition Designer schematic.

Creating Allegro Forward Annotation Files Automatically . . . . . . . . . . . . . . . . . . . . . . 108

Creating Allegro Forward Annotation Files Semi-Automatically . . . . . . . . . . . . . . . . . 109
Creating Allegro Forward Annotation Files Manually . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Creating Allegro Back Annotation Files Automatically . . . . . . . . . . . . . . . . . . . . . . . . . 111

Creating Allegro Forward Annotation Files

Automatically
The automated forward annotation process generates Allegro netlist and device files, then uses
them to update the Allegro board file.When you use the automated forward process, the pcbfwd
command generates the netlist file, updates the Allegro board, and saves all the files you need to
edit and back annotate the board.
Caution
The automated forward process overwrites the target Allegro board database without
warning — the automated forward process ignores any file locking that may be done by
Allegro. If you are sharing board databases with other designers, be sure you do not overwrite
their work.

• You must have performed steps 1 through 6 of Creating a PCB Netlist File.

108 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Creating Allegro Forward Annotation Files Semi-Automatically

• In Step 2 of the Basic Flow, you must have chosen Allegro<version> from the Layout
Tool dropdown list.
Procedure
1. In the PCB Interface Dialog Box - Basic Tab, select the “Run Command Line after
Processing” check box to activate the automated Allegro import script.
The command line for the script appears as view2a <design_name>.tel
<design_name>.brd. This command runs after pcbfwd has successfully completed.
2. Click OK.
Results
The forward process creates the following files, and then imports the Allegro netlist and device
files into the Allegro board database.
• <design_name>_sav.brd — Backup copy of the board before import.
• <design_name>_baf.brd — Updated board after import, used for back annotation.
• <design_name>.brd — Working copy of the board.
Related Topics
Allegro Forward and Back Annotation Processes

Creating Allegro Forward Annotation Files Semi-

Automatically
Use this procedure to create an Allegro netlist and device files, and generate files for Cadence
Allegro to update the Allegro board database.
• You must have performed steps 1 through 6 of Creating a PCB Netlist File.
• In Step 2 of the Basic Flow, you must have chosen Allegro<version> from the Layout
Tool dropdown list.
Procedure
1. In the PCB Interface Dialog Box - Basic Tab, select Create Netlist for Layout
(Forward to Layout).
2. Click OK.
The pcbfwd function creates the Allegro netlist <design_name>.tel and the Allegro
device files.

PCB Interface User's Guide, X-ENTP VX.2.8 109

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Creating Allegro Forward Annotation Files Manually

3. To generate the Allegro netlist and device files:

a. Place the Allegro netlist (<design_name>.tel) and device files (*.txt) in the same
directory as the Allegro board database corresponding to the Xpedition Designer
design.
b. In a command window, type: view2a <design_name>.tel <design_name>.brd
Results
The software generates the following files:
• <design_name>_sav.brd — Backup copy of the board before import.
• <design_name>_baf.brd — Updated board after import, used for back annotation.
• <design_name>.brd — Working copy of the board.
Related Topics
Allegro Forward and Back Annotation Processes
view2a.pl File Format

Creating Allegro Forward Annotation Files

Manually
There may be situations where you may be unable to use the automated forward process. For
example, you may not have access to the automation scripts. Or perhaps your Allegro and
Xpedition Designer software are located at a different site, so that they do not have access to
each other. In this case, use the manual forward process to generate the Allegro netlist and
device files, and update your Allegro board file.
Prerequisites
• You must have performed steps 1 through 6 of Creating a PCB Netlist File.
• In Step 2 of the Basic Flow, you must have chosen Allegro<version> from the Layout
Tool dropdown list.
Procedure
1. In the PCB Interface Dialog Box - Basic Tab, select Create Netlist for Layout (Forward
to Layout).
2. Click OK.
The pcbfwd command creates the Allegro netlist <design_name>.tel file and the
Allegro device files.
3. In the Allegro environment, make a backup copy of the present state of your board
database and name it <design_name>_sav.brd.

110 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Creating Allegro Back Annotation Files Automatically

4. Place the Allegro Netlist (<design_name>.tel) and device file (<design_name>.txt) in

the same directory as the Allegro board database corresponding to the
Xpedition Designer design.
5. In the Allegro PCB tool, open the most recent Allegro board database corresponding to
the Xpedition Designer design.
6. Choose File > Import > Logic to open the netin param dialog box and select the
following parameters:
• Third Party logic type
• Save Drawing Before Execution
• Supersede All Logic Data
• Append Device File Log
• Allow Etch Removal during ECO
• Always Place Changed Component in Design
7. Click Import.
8. Choose File > Save As and name the file <design_name>_baf.brd.
9. When you have finished working on the imported board, choose File > Save As and
name the files <design_name>. brd.

Note
The Back annotation to Xpedition Designer commands uses these two files to update
the schematic.

Related Topics
Allegro Forward and Back Annotation Processes

Creating Allegro Back Annotation Files

Automatically
The automated back annotation process automatically back annotates Allegro ECO changes and
net property data to the Xpedition Designer schematic.
Prerequisites
• You should make a back-up copy of your Xpedition Designer schematic
• You must have copied the <design_name>_baf.brd file (the unedited forward-annotated
board database) and the <design_name>.brd file that contains all your edits to the
corresponding Xpedition Designer project.

PCB Interface User's Guide, X-ENTP VX.2.8 111

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
Creating Allegro Back Annotation Files Automatically

• You must make sure that the keyword DoAttBackann yes appears in the Allegro
configuration file (.cfg).
• You must have performed steps 1 through 6 of “Creating a PCB Netlist File” on
page 10.
• In Step 2 of the Basic Flow, you must have chosen Allegro<version> from the Layout
Tool dropdown list.
Procedure
1. In the “PCB Interface Dialog Box - Basic Tab” on page 133, select Back Annotate
Information (Back from Layout).
2. Select Run Command Line Before Processing to activate the automated Allegro export
script (a2view <design_name>.brd). This command runs first before the pcbback
function.
3. Click OK.
Results
The a2view command creates Allegro ECO back annotation <design_name>.abk and back
annotation netlist <design_name>.tl2 files from the board files. PCBBACK back annotates the
ECO changes and the property data to update the Xpedition Designer schematic.
Related Topics
Allegro Forward and Back Annotation Processes
a2view.pl File Format

112 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
Allegro Import and Export Scripts

Allegro Import and Export Scripts

The software provides scripts for forward- and back- annotation with the Allegro PCB
Interface.
You can run these scripts from a command prompt or as part of the automated forward- and
back annotation processes.

Note
You must have Perl5 installed and configured in your environment to use these scripts.

view2a.pl File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

a2view.pl File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

PCB Interface User's Guide, X-ENTP VX.2.8 113

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
view2a.pl File Format

view2a.pl File Format

Input for: Allegro Forward Annotation
The view2a.pl script updates an Allegro board database with a netlist file generated by the
Xpedition Designer PCB Interface tool.
Format
The view2a.pl file must conform to the following formatting and syntax rules:

• Lines starting with # are treated as comments.

view2a.pl [-c] [-f <config file>] [-p <place file>][-t <technology
file>] [-o <new board>] [<netlist>] <current board>

Parameters
• [-c}
Runs the draw_check and checks package symbols required for the updated board netlist.
• [-f <config file>]
An optional argument specifying a configuration file to use for file naming defaults. This
checks for the relative path for the file and if not found, checks for the WDIR path. These
options override the configuration file settings.
• [-p <place file>]
Runs the Allegro plctxt script to import placement from the Xpedition Layout tool. Defaults
to the configuration file settings for “PlaceFileName” and “PlaceFileExt” if
“LoadPlacementData =yes”.
• [-t <technology file>]
An optional argument specifying the Allegro technology file to be exported from Allegro.
• [-o <new board>]
An optional argument that saves the update to the specified new board name. Default
overwrites the <current board>.
• <netlist>
Required argument that specifies the Allegro netlist file to use to update the board database.
Default filename extension is .tel.
• <current board>
Required argument which specifies the Allegro board database to read as a baseline for
netlist file update. Should correspond to the most recently edited board.
Related Topics
a2view.pl File Format

114 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Supported Vendor’s PCB Layout Interfaces
a2view.pl File Format

a2view.pl File Format

Input for: Allegro Back Annotation
The a2view.pl script extracts and formats files from Allegro for back annotation to
Xpedition Designer.
Format
The a2view.pl file must conform to the following formatting and syntax rules:

• Lines starting with # are treated as comments.

a2view.pl [-f <config file>] [-l <was-is comparison board>] [-c
<extract command file>] [-e <extract report>][-o <tl2 file>] [-b<ECO
baf file>] [-p <placement file>] [-u] [-s <back schedule filename>]
[-t <technology file>] <allegro board>

Parameters
• [-f <config file>]
An optional argument specifying a configuration file to use for file naming defaults. This
checks for the relative path for the file and if not found, checks for the WDIR path. These
options override the configuration file settings.
• [-l <was-is comparison board>]
An optional argument that specifies the comparison board for input to the Allegro baf
command. Default is <allegro board>_baf.brd.
• [-c <extract command file>]
An optional argument which specifies command file for Allegro extract. This file
determines which net properties get extracted from the Allegro board for back annotation.
Default is $WDIR/anetprops.cmd.
• [-e <extract report>]
An optional argument that specifies the Allegro extract report file to be written. Default is
<allegro board>.axt.
• [-o <tl2 file>]
An optional argument that specifies the Allegro back annotation netlist file to be written.
This name should match the PCB Interface configuration file “BackNetlistFileName” and
“BackNetlistFileExt” settings. Default is <allegro board>.tl2.
• [-b <ECO baf file>]
An optional argument that specifies the Allegro ECO baf filename. Default is <allegro
board>.abk.
• [-u]
An optional argument which retains the design unit suffixes added to some net property
values by Allegro. As a default, you should remove this suffix, if not specified on the

PCB Interface User's Guide, X-ENTP VX.2.8 115

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Supported Vendor’s PCB Layout Interfaces
a2view.pl File Format

schematic. For example, if you specified MIN_LINE_WIDTH 100 on the schematic, Allegro
extracts this as MIN_LINE_WIDTH 100 MIL.
• [-p <back place filename>]
Runs the Allegro plctxt script to import placement from the PADS Layout tool. Defaults to
the configuration file settings for “PlaceFileName” and “PlaceFileExt” if
“LoadPlacementData =yes”.
• [-s <back schedule filename> ]
Extracts back annotation schedule information from Allegro for the PADS Layout tool.
Defaults to the schedback.txt file.
• [-t]
An optional argument specifying the Allegro technology file to be exported from Allegro.
• <allegro board>
Required argument which specifies the current Allegro board database for back annotation.
This board must have a netlist file matching the source Xpedition Designer schematic, aside
from possible pin, gate, and component swaps and net property additions/changes.
Related Topics
view2a.pl File Format

116 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Chapter 4
Heterogeneous Device Support

You can define a heterogeneous device as a physical package represented by at least two non-
equivalent symbols on an Xpedition Designer schematic.
These symbols may differ in logic function, pin count, pin labels, attributes, and number of
slots. The different symbols collectively correspond to a single physical device type for layout,
and sometimes correspond to a single model for simulation.

Adding identical DEVICE and HETERO property values on each of the non-equivalent
symbols implements heterogeneous device support for the PCB Interface. The value of the
HETERO property binds the different symbols together.

Figure 4-1 shows the components for a single 1488 device: one with three 2-input NAND gates
and one with a NOT gate.

Figure 4-1. Different Components within Same Device: HETERO Symbol

Figure 4-2 shows a NAND gate without drawn signal pins and a NAND gate with the signal
pins drawn, both represent a 74LS00 device. Either representation can be used for any of the
device slots.

PCB Interface User's Guide, X-ENTP VX.2.8 117

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Heterogeneous Device Support

Figure 4-2. Different Gates within Same Device: HETERO Symbol

Any implementation of heterogeneous devices requires information that binds together all the
involved symbols. For “different representations of the same device” (Figure 4-3) and “split
integrated circuit” (Figure 4-4) heterogeneous types, you need to provide information which
distinguishes the view on the schematic and the view seen by the layout system (schematic
versus layout view). These requirements are fulfilled by the HETERO property.

For “split integrated circuit” heterogeneous types, put the symbols that are the schematic view
in parentheses.

Note
Do not include the symbol for layout view in parentheses because only one symbol can be
sent to layout.

Figure 4-3. Different Representations of Same Device: HETERO Symbol

Figure 4-4 shows a large 240-pin IC split into three different components each containing 80
pins.

118 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Heterogeneous Device Support
Common (Shared) Device Pins

Figure 4-4. Split Integrated Circuits (IC)s: HETERO Symbol

Common (Shared) Device Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Declaring Heterogeneous Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Defining HETERO Devices for Power Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Heterogeneous Device Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Common (Shared) Device Pins

You can represent common pins (pins shared by more than one function in a physical package)
on Xpedition Designer symbols in several ways.
• SIGNAL Property — A common pin can be represented as a SIGNAL property and
not as a graphical pin. All Xpedition Designer applications support this frequently used
methodology.
• Graphically — A common pin can be represented graphically. The pin number (#)
property shows the common pin slots. For example: #=1,1,1,1,19,19,19,19.
• Implicit Connections — A common pin can be used to connect one slot of a component
with others which share the common pin to provide implicit connections for this pin.
You assign the component with the unconnected pin the same REFDES as an explicitly
connected component. You can attach any other unique property name=value pair to
the group of components that you want to share the same signal on their common pins.
Be sure to add the property name=value property in the AttPassList Section of your
configuration file, and comment out the CHKBRD_COMMON_PIN1 line in the .cfg file.
Related Topics
Heterogeneous Device Support
Declaring Heterogeneous Devices
Defining HETERO Devices for Power Schemes

PCB Interface User's Guide, X-ENTP VX.2.8 119

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Heterogeneous Device Support
Declaring Heterogeneous Devices

Heterogeneous Device Simulation

Declaring Heterogeneous Devices

Different types of heterogeneous devices exist. You can use the same method for declaring your
part as a heterogeneous device for all types.
The binding of different symbols together to form a heterogeneous device introduces the
problem of what to do with property differences between the involved symbols. The PCB
Interface tool attempts to merge attributes from the various symbols into a consistent set of
attributes for the layout view of the device, and it also detects and reports inconsistencies.

For example, both the 74LS244A and 74LS244B heterogeneous devices should have the same
PKG_TYPE property value.

Note
It is important to follow the methodology for specifying heterogeneous devices, particularly
the testing phase of placing the heterogeneous symbols on a test sheet and running it
through a PCB Interface. This can save significant debug time and effort when generating a
PCB netlist file for an entire board.

Procedure
1. Examine the devices in Figure 4-1, Figure 4-2, Figure 4-3, and Figure 4-4 to determine
which type you need.
2. Determine the syntax of the HETERO property value from the appropriate example.
3. Add an identical HETERO property to all involved symbols that contains a value that
matches the form of the value from the example.
4. Make sure that all symbols (not instances) have the same DEVICE property value.
5. Make sure that the # (pin number) attributes on each symbol indicate the number of slots
that the specific symbol occupies in the device.
6. Make sure the # property refers only to package pin numbers that the slot occupies.
7. Create a prototype schematic using these symbols connected to nets.
8. Run your schematic completely through a PCB Interface, and examine the netlist and
optional device files to evaluate the results.
Related Topics
Heterogeneous Device Support
Common (Shared) Device Pins
Defining HETERO Devices for Power Schemes

120 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Heterogeneous Device Support
Defining HETERO Devices for Power Schemes

Heterogeneous Device Simulation

Defining HETERO Devices for Power Schemes

A typical application for HETERO is to bind together symbols with either implicit or explicit
power pins, or to create packages that contain both types of symbols.
• Implicit symbols have no pins for power visible on the symbol. When you use implicit
power symbols, the corresponding packages get their power nets from the SIGNAL
attribute.
• Explicit symbols have pins for power visible on the symbol. When you use explicit
power symbols, the corresponding packages get their power nets from their power pin
connections.
Prerequisites
• You must have HETERO devices in your schematic.
• All symbols contained in the HETERO device must have the SIGNAL attribute.
• You must decide whether or not to use explicit symbols, or a combination of explicit and
implicit symbols. Your power scheme can consist of explicit symbols only or mixed
explicit/implicit symbols. It cannot contain implicit symbols only.
• If you include implicit symbols, you must set the REFDES values of all gates in the
package to the same value.
Procedure
1. In the Xpedition Designer tool, double-click the HETERO device to which you want to
add the property.
2. In the Properties window:
a. Click REFDES and select the check box if you want REFDES visible.
b. In the REFDES Value field, enter the REFDES value assigned to all gates in the
package.
3. Modify the ChkRules section in the configuration file to change CHKBRD
_DUPL_PINS from an error to a warning. This enables pin conflicts, and does not
repackage when different nets or attributes override the SIGNAL attribute.
4. (Optional) Set the CreateSpareGates keyword to Yes in the configuration file, if you
want the symbol corresponding to the layout-only slot to be added to the schematic.

PCB Interface User's Guide, X-ENTP VX.2.8 121

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Heterogeneous Device Support
Heterogeneous Device Simulation

Tip
The layout-only symbol is enclosed in parentheses in the HETERO property value.
For example, given HETERO = 74LS00,(74LS00P), 74LS00P refers to the layout-
only symbol.

Related Topics
Heterogeneous Device Support
Common (Shared) Device Pins
Declaring Heterogeneous Devices
Heterogeneous Device Simulation
ChkRules Section
General Rules

Heterogeneous Device Simulation

Each Xpedition Designer symbol for a heterogeneous device requires its own independent
simulation model, unless the MODEL property is used for primitives. For interdependent
symbols, such as split ICs, each multiple-symbol instance of the device requires a new copy of
the symbols and simulation model with new global net names. Interdependent heterogeneous
symbols must be packaged manually to ensure that the right pieces are packaged together.
This means that pieces of a large split IC, or a small optoisolator, cannot easily be modeled for
simulation if the pieces are interdependent.

Related Topics
Heterogeneous Device Support
Common (Shared) Device Pins
Declaring Heterogeneous Devices
Defining HETERO Devices for Power Schemes

122 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Chapter 5
Design Reuse

The Xpedition Designer and PCB Interface tools work together with PCB layout tools to create
logical and physical PCB reusable blocks of circuitry for use in a single or multiple host
designs.
Design Reuse Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Design Reuse Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Creating a Reuse Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Design Reuse Overview

A reusable block contains schematic, constraint (optional), layout data, and the corresponding
reusable block cell (editable in the layout tool) that provides physical attributes of the reusable
block, and enables the use of verified circuitry with the ease of placing a single block in a
design.
You can nest reusable blocks, following these rules.

• You must process each level of nesting independently. You must process the levels from
the bottom up, to resolve packaging conflicts and concatenate the prefixes.
• If you use nested REFDES_PREFIXs, the PCB Interface tool concatenates the prefixes
when processing each reuse block.
Table 5-1. You create a PCB reuse block using one of two strategies.
Strategy Description
Independent PCB Reuse Block
Advantages Enables definition of reusable blocks at the beginning of the
design process.
Enables gate and pin swaps for packaging and routing
optimization to be back annotated to the schematic reuse block.
All the designs that use the reuse block inherit these gate and
pin swaps.
Enables you to define logical and physical design constraints
for the reuse block.
Enables you to send portions of the design to PCB layout
regardless of the state of the top level design.

PCB Interface User's Guide, X-ENTP VX.2.8 123

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Design Reuse
Design Reuse Requirements

Table 5-1. You create a PCB reuse block using one of two strategies. (cont.)
Strategy Description
Disadvantages Requires advanced knowledge that the design is a reuse block.
Requires you to maintain separate PCB layouts for reuse blocks
and top level designs.
From Portions of a Design
Advantages Does not require you to maintain separate PCB layouts for reuse
blocks and top level designs.
Disadvantages Does not allow gate and pin swaps for packaging and routing
optimization to be back annotated to the schematic reuse block.
They are stored as top level design OATs.

Related Topics
Reusable Block Overview and Configuration [Reusable Blocks Process Guide]
Placing a Logical-Physical Reusable Block Into a Host Design [Reusable Blocks Process Guide]

Design Reuse Requirements

You must enable some requirements in the PCB netlist file in order to successfully package the
netlist for design reuse in the vendor’s PCB layout tool.
• PKG PKG_GRP — Located in the PCB configuration file for the vendor’s layout tool
(choose Property Pass List > Specific section).
• PreservePrevPack — Located in the PCB configuration file (and set to Yes) for the
vendor’s layout tool.
• DoOats — Set to Yes in the PCB configuration file for the vendor’s layout tool.
• OATs— Enabled in the Xpedition Designer tool (choose Project > Settings > Project).
Related Topics
Reusable Block Overview and Configuration [Reusable Blocks Process Guide]

Creating a Reuse Block

Reusable blocks are sections of circuitry that are reused in multiple designs. When you create a
reuse block, you design a subcircuit schematic that can be included in other schematics as a
hierarchical component.
Use this hierarchical subcircuit to create a corresponding PCB layout reuse block that can be
included in other PCB layouts.

124 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Design Reuse
Creating a Reuse Block

Tip
Whenever possible, define the reuse block schematic as an independent Xpedition Designer
project; then include the block as a read-only library available to other projects.

Prerequisites
• You must have created a schematic design that defines a reusable subcircuit.
• You must have assigned reference designators and slots to the appropriate vendor’s PCB
Interface PCB design and created a PCB netlist file.
• You must have created a composite symbol for the defined subcircuit schematic and
included all interface signals as hierarchical I/O pins.
• You must have moved the schematic project that contains the schematic design and the
reuse block symbol to the project directory or to a library that is included in the project
Search Order list. This enables instantiation of the reuse block into other schematics.
Procedure
1. Place the composite component for the reuse block on the schematic.
2. Add a REUSE_BLOCK component property to the component instance. This property
does not require a property value.
3. Add a REFDES_PREFIX component property to the component instance to use
reference designator optional prefixes. Assign an alphanumeric value to this property.

Note
The PCB Interface tool preserves packaging if you do not use Reference Designator
prefixes. Use the REFDES_PREFIX keyword if you want path information as part
of the REFDES string.

4. Run packaging at the top-level schematic to package the entire design. Packaging
preserves all slots and packaging within the reuse block.
5. Open the PCB Interface tool, and then generate a netlist file (refer to Creating a PCB
Netlist File).
Related Topics
Reusable Block Overview and Configuration [Reusable Blocks Process Guide]

PCB Interface User's Guide, X-ENTP VX.2.8 125

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Design Reuse
Creating a Reuse Block

126 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Chapter 6
Component and Design Level Packaging

The PCB Interface tool provides configurable packaging control options that allow you to
control how components on a schematic are processed into physical packages. This process
involves the assignment of reference designators and physical pin numbers to schematic
components according to physical device definitions.
The role of the PCB Interface tool is to package components while honoring existing package
assignments and checking for packaging conflicts. You can choose to manually assign
packaging parameters to some components, such as connectors that may require mandatory
packaging assignments, and then let the PCB Interface tool handle the rest of the assignments.

Note
Adding a comment line to the PreservePrevPack keyword in the PCB configuration file
enables all parts in the design to be repackaged. This can be useful in the initial stages of
design, where you want to test the schematic and layout packaging.

You should always remove the comment line from the PreservePrevPack keyword immediately
after repackaging to preserve the resulting packaging.

To accommodate different packaging assignment priorities, the PCB Interface tool offers two
levels of packaging control; component and design.

Component Level Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Design Level Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Preserve Packaging for Off-Board Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Component Level Packaging

You control packaging on a component-by-component basis with the PKG_LOCK property.
Components and symbols with the PKG_LOCK property take the highest priority for REFDES
and slot assignment, and are not repackaged.
Table 6-1 and Table 6-2 describe how PKG_LOCK and the configuration file control
packaging.
Table 6-1. Forward Annotation Packaging Assignments
REFDES PKG_LOCK Forward Annotation Actions
Assigned Property
No No Assigns next unused REFDES and slot.

PCB Interface User's Guide, X-ENTP VX.2.8 127

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Component and Design Level Packaging
Design Level Packaging

Table 6-1. Forward Annotation Packaging Assignments (cont.)

REFDES PKG_LOCK Forward Annotation Actions
Assigned Property
Yes No Preserves the existing REFDES and slot according to the
PCB packaging check configuration.
No Yes Preserves slot and assigns next unused REFDES.
Yes Yes Unconditionally preserves existing REFDES and slot.

Table 6-2. Forward Annotation Packaging Conflict Handling

Packaging Conflict Between: PCB Check Result
Configuration
Two components without WRN 0 Ignores any conflicts.
PKG_LOCK property Note: Not recommended — may
produce an invalid netlist file.
ERR 1 or WRN 1 Repacks both components and reports a
warning.
ERR 0 Reports an error and fail
Two components, one with ERR 1 or WRN 1 Repacks the component without
PKG_LOCK, and one without PKG_LOCK and reports a warning.
PKG_LOCK
ERR 0 Reports an error and fails.
Two components with ERR 1 or WRN1 Reports an error and fails.
PKG_LOCK
ERR 0 Reports an error and fails.

Related Topics
ChkRules Section
Design Level Packaging
Basic Configuration File Format
PKG_LOCK

Design Level Packaging

At the design level, you configure the PCB Interface tool to automatically resolve or report
errors for different types of packaging conflicts using the vendor’s individual configuration file.
Each time you package your design, you must decide whether to preserve previously assigned
packaging or to repackage all components in the design. You use the PreservePrevPack
keyword in the PCB configuration file to control packaging preservation.

128 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Component and Design Level Packaging
Preserve Packaging for Off-Board Connectors

Table 6-3. PreservePrevPack Keyword Conditions

Condition Description
Yes Preserves packaging of all components according to the packaging checks
and PKG_LOCK properties.
No Enables repackaging of all components that do not have the PKG_LOCK
property assigned.

In the initial stages of creating a schematic, you may want to allow the PCB Interface tool to
assign packaging arbitrarily rather than wasting time on unnecessary manual packaging
assignments. There may be only a handful of components that require mandatory manual
packaging, while the rest can be unrestricted.

In the final stages of creating a schematic, or if a physical board design already exists, you can
preserve all component packaging to keep the schematic and board packaging assignments
synchronized. To accomplish this, set the fix keyword flags in the configuration file to 0 (zero).
This prevents repacking due to package conflicts and produces error messages allowing the
conflicts to be manually corrected.

To resolve any packaging conflict, the software renumbers one of the REFDES values
according to the following rules. The component that gets changed depends on its hierarchical
level, page and ID.

• REFDES values at higher hierarchical levels (top being the highest) have priority over
those in lower hierarchical levels.
• REFDES values on earlier pages at the same hierarchical level have priority over those
on latter pages.
• REFDES values on components with lower ID numbers have priority over components
with greater ID numbers on the same page.
Related Topics
ChkRules Section
Component Level Packaging
Basic Configuration File Format
PKG_LOCK

Preserve Packaging for Off-Board Connectors

Designers often model connectors as single pin symbols. Off-board connector parts usually
have a pre-determined reference designator and pin to signal mapping. This requires the
designer to pre-assign these packaging parameters manually.

PCB Interface User's Guide, X-ENTP VX.2.8 129

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
Component and Design Level Packaging
Preserve Packaging for Off-Board Connectors

Procedure
1. In Xpedition Designer, add the PKG_LOCK property to the connector symbol at the
symbol level.
2. Assign slots and signals to the connector symbols on the schematic.
3. If you have multiple instances of the same connector type in the design, assign unique
reference designators to the connector components to differentiate between each
connector.
Results
Packaging does not repackage any off-board connectors with the attached PKG_LOCK
property.
Related Topics
ChkRules Section
Component Level Packaging
Basic Configuration File Format
PKG_LOCK

130 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Chapter 7
PCB Interface Tool GUI Reference

PCB Interface tool provides a graphical user interface to set up forward and backward
annotation to a PCB layout tools.
When you exit PCB Interface tool, the Windows registry stores your selections, and reuses them
as default values for subsequent uses of the PCB Interface tool.

Also see “PCB Interface PADS Layout Script” on page 147.

Table 7-1. PCB Interface Tool Dialog Boxes
PCB Interface Dialog Boxes Description
PCB Interface Dialog Box - Basic Tab Use the Basic tab to specify the processes
required to create a netlist, back annotate
information from the vendor’s PCB layout tool
to the schematic, or run scripts to define the
selected vendor’s data comparison reports.
PCB Interface Dialog Box - Advanced Tab Use the Advanced tab to specify processing
information when creating a PCB netlist file.
PCB Interface Dialog Box - Constraints Tab Use the Constraints tab to move available
physical constraint design rules to the layout
tool.
PCB Interface Dialog Box - Results Tab Use the Results tab to review errors, warnings or
notes based on the settings in the configuration
file.
Xpedition Designer To PADS Layout Dialog Use this dialog box to create a new PCB design,
Box or compare the current schematic with an
existing PCB design.
Library Import Options Dialog Box Use this dialog box to update
Xpedition Designer part types in the PADS
Layout library and set the import options.
ECO Compare Options Dialog Box Use this dialog box to compare design objects
between the schematic and the layout tool.
PADS Layout To Xpedition Designer Dialog Use this dialog box to generate ECO report files,
Box or reuse an existing ECO file to automate the
back annotation process.

PCB Interface User's Guide, X-ENTP VX.2.8 131

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Tool GUI Reference

Table 7-1. PCB Interface Tool Dialog Boxes (cont.)

PCB Interface Dialog Boxes Description
PCB Interface PADS Layout Script In the PCB Interface, use the ppcb2007.vbs
icscript to automatically export and import
design data between Xpedition Designer and
PADS Layout. When you select the latest PADS
Layout version in the Layout Tool list in the
Xpedition Designer Settings - Project category,
the script automatically appears on the command
line with the correct syntax for the direction of
the design information (forward or back).

132 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Tool GUI Reference
PCB Interface Dialog Box - Basic Tab

PCB Interface Dialog Box - Basic Tab

To access:
• Xpedition Designer Main toolbar, PCB Interface button , Basic tab

• Xpedition Designer Tools > PCB Interface menu item, Basic tab
Use the Basic tab to specify the processes required to create a netlist, back annotate information
from the vendor’s PCB layout tool to the schematic, or run scripts to define the selected
vendor’s data comparison reports.
Figure 7-1. PCB Interface Dialog Box - Basic Tab

PCB Interface User's Guide, X-ENTP VX.2.8 133

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Tool GUI Reference
PCB Interface Dialog Box - Basic Tab

Fields
Table 7-2. PCB Interface Dialog Box - Basic Tab Contents
Fields Description
Design Name Specifies the name of the open schematic.
Choose a design from the dropdown list.
CFG file Displays the PCB Configuration File to configure the output to
the PCB layout software.
Note: Displays the configuration path and filename you
entered in Xpedition Designer Setup > Settings menu item,
Project (category).
Process to Run
Assign Reference Selected, assigns reference designators (applying conditions
Designators (REFDES) specified in the “PCB Interface Dialog Box - Advanced Tab” on
page 136), and creates a generic (basic from-to format) netlist
file.
Create Netlist for Layout Selected, creates a PCB netlist file.
(Forward to Layout) Unassigned reference designators automatically assigned (by
applying conditions specified in the “PCB Interface Dialog Box -
Advanced Tab” on page 136).
Note: You can invoke a PCB Interface with pre-selected
forward or backward options.
Back Annotate Information Selected, the software brings layout information from your PCB
From Layout to Schematic layout tool back to your schematic. Information includes changes
(Back from Layout) in pin swaps and gate swaps.
Consult the documentation from the vendor for a list of
supported back annotation changes, or refer to “Supported
Vendor’s PCB Layout Interfaces” on page 53.
Note: You can invoke a PCB Interface with a vendor’s pre-
selected forward or backward options.
Processing Options
Use Component Labels Checked, the software uses component labels instead of
component UIDs in the netlist file and error message entries.
Netlist Design to Level Defines the number of LEVEL properties to determine the
(Space-Delimited) degree of design hierarchy data.
You can add multiple LEVEL properties, delimited by a space.
For example: Level1 Level2.

134 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Tool GUI Reference
PCB Interface Dialog Box - Basic Tab

Table 7-2. PCB Interface Dialog Box - Basic Tab Contents (cont.)
Fields Description
Run command line before/ Checked, enables you to use automated forward and back
after processing annotation scripts, and displays the default icscript.vbs command
line file in the text box.
Note: If you have PADS Layout installed on your system,
click OK to open a wizard to define the options to
automatically transfer your parts and design file.
Use custom cmd line Checked, enables you to enter a custom command line script in
place of the default script.
Tip: Available only if you select the “Run command line after/
before processing” option.
Displays only when you select to exclude error messages on the
Advanced tab.
Save PCB Configuration Click to save changes in a local copy of the .cfg file.
Note: Active only after you make changes on the Advanced
or Constraints tabs.

Related Topics
PCB Interface Dialog Box - Advanced Tab
PCB Interface Dialog Box - Constraints Tab
PCB Interface Dialog Box - Results Tab

PCB Interface User's Guide, X-ENTP VX.2.8 135

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Tool GUI Reference
PCB Interface Dialog Box - Advanced Tab

PCB Interface Dialog Box - Advanced Tab

To access:
• Xpedition Designer Main toolbar PCB Interface button , Advanced tab

• Xpedition Designer, the Tools > PCB Interface menu item, Advanced tab
Use the Advanced tab to specify processing information when creating a PCB netlist file.
Figure 7-2. PCB Interface Dialog Box - Advanced Tab

136 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Tool GUI Reference
PCB Interface Dialog Box - Advanced Tab

Fields
Table 7-3. PCB Interface Dialog Box - Advanced Tab Contents
Fields Description
Message Handling
File Name for Errors, Warnings Defines the filename for writing error, warning and note
and Notes (Located in Project information.
Directory) Updates the Errorfile keyword in the ErrorRules Section of
the configuration file.
Exclude Messages by Class Checked, excludes classes of messages.
(Errors, Warnings, Notes) Updates the Exclude keyword in the ErrorRules Section of
the configuration file.
Exclude Message by Number Defines error message numbers (separated by a space) to be
(Space-Delimited) excluded when processing.
Updates the ExcludeNums keyword in the ErrorRules
Section of the configuration file.
REFDES Processing/Optimization
Preserve Previous REFDES Checked, preserves existing assigned REFDES values for
Assignments (Forward to Layout) components on the physical board.
Unchecked, the software reassigns REFDES values to
optimize device or gate usage. This may minimize the
number of physical devices required for multi-slot devices.
Updates the PreservePrevPack keyword in the General
Rules section of the configuration file.
Preserve Gaps in REFDES Checked, preserves breaks in sequences of reference
Numbering Assignments (Ex: U1, designator assignments, and updates the PkgSkip keyword
U3, U4,…) in the General Rules section of the configuration file.
Used when REFDES values are intentionally unassigned
because they are reserved for future use.
Unchecked, utilizes unassigned REFDES values for
components needing assignments and fills in numbering
gaps.

PCB Interface User's Guide, X-ENTP VX.2.8 137

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Tool GUI Reference
PCB Interface Dialog Box - Advanced Tab

Table 7-3. PCB Interface Dialog Box - Advanced Tab Contents (cont.)
Fields Description
Automatically Add Spare Gates to Checked, creates an additional Xpedition Designer
Schematic schematic sheet with all unused gates (slots) instantiated,
and updates the CreateSpareGates keyword in the General
Rules section of the configuration file.
Useful for utilizing multi-slotted components (such as 7400
series discrete gates, flip flops, and so on) in large designs.
Note: In subsequent netlisting runs, if you delete any
gates from your design (whether used or unused), the
PCB Interface tool creates an additional sheet in your
design for that particular gate. It does not update any
previously created “spare gates” sheets.
Preserve Case Checked, keeps the case of the REFDES when back
annotating.
Unchecked, maps the configuration property names into
corresponding names for the different vendor layout
systems.
Refer to the “AlsRules Section” on page 27 of the
configuration file.
First Number for REFDES Defines the start number when assigning REFDES values.
Assignments Updates the FIRST_REFDES keyword in the ChkRules
Section of the configuration file.
Note: Does not affect reference designators already
assigned.
Back Annotation Control
Automatically Back Annotate Checked, automatically updates the schematic with changes
Changes to Schematic made in the PCB Interface, and updates the WriteBaf
keyword in the General Rules section of the configuration
file.
Unchecked, the software writes changes to a back
annotation (.baf) file.
Save Pcb Configuration Enables you to save changes to the .cfg file.
Note: Active only after you make changes in this tab, or
in the Constraints tab.

Related Topics
PCB Interface Dialog Box - Basic Tab
PCB Interface Dialog Box - Constraints Tab
PCB Interface Dialog Box - Results Tab

138 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Tool GUI Reference
PCB Interface Dialog Box - Advanced Tab

Basic Configuration File Format

PCB Interface User's Guide, X-ENTP VX.2.8 139

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Tool GUI Reference
PCB Interface Dialog Box - Constraints Tab

PCB Interface Dialog Box - Constraints Tab

To access:
• Xpedition Designer Main toolbar, PCB Interface button , Constraints tab

• Xpedition Designer Tools > PCB Interface menu item, Constraints tab
Use the Constraints tab to move available physical constraint design rules to the layout tool.
Fields
Table 7-4. PCB Interface Dialog Box - Constraints Tab
Fields Description
Project Displays the name of the currently active project.
CNS file Displays the path to the .cns constraints file.
Refer toCreating or Modifying Constraintsin the Constraint
Editor System (CES) User’s Manual.
Pin, Net, Component (Pkg) • Available — Displays all the pin/net/component
Constraints constraints available for this project. To pass an available
constraint to the layout, click Add.
• Being Passed to Layout — Displays the pin/net/
component constraints being passed to layout. To remove
a constraint from the list of constraints being passed to the
layout, click Remove.
Save Pcb Configuration Click to save changes in the .cfg file.
Note: Active only after you make changes in this tab, or in
the Advanced tab.

Related Topics
PCB Interface Dialog Box - Basic Tab
PCB Interface Dialog Box - Advanced Tab
PCB Interface Dialog Box - Results Tab

140 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Tool GUI Reference
PCB Interface Dialog Box - Results Tab

PCB Interface Dialog Box - Results Tab

To access:
• Xpedition Designer Main toolbar: Click PCB Interface button ( ), click Results tab

• Xpedition Designer: Choose Tools > PCB Interface menu item, click Results tab
Use the Results tab to review errors, warnings or notes based on the settings in the
configuration file.
Note
If there are conflicts within the configuration file, and they do not display in the window of
this tab, the Xpedition Designer Output Window also displays error, warning or note
messages and provides hypertext links. Refer to Error Handling in the Schematic Files.

Fields
Table 7-5. PCB Interface Dialog Box - Results Tab Contents
Fields Description
Results Window Displays errors, warnings or messages as hyperlinks,
which you can use to cross probe to the source of the
problem.
Displays only when you select to exclude error
messages on the Advanced tab.
Clear Summary Click to clear all the displayed entries.

Related Topics
PCB Interface Dialog Box - Basic Tab
PCB Interface Dialog Box - Advanced Tab
PCB Interface Dialog Box - Constraints Tab

PCB Interface User's Guide, X-ENTP VX.2.8 141

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Tool GUI Reference
Xpedition Designer To PADS Layout Dialog Box

Xpedition Designer To PADS Layout Dialog

Box
To access: From Xpedition Designer, the Tools > PCB Interface menu item, Basic tab, then
select Create Netlist for Layout and then select “Run command line after processing”
Use this dialog box to create a new PCB design, or compare the current schematic with an
existing PCB design.
Fields
Table 7-6. Xpedition Designer to PADS Layout Dialog Box Contents
Fields Description
Create New PCB Design Selected, creates a new PADS Layout design.
Start with Template PCB Checked, enables you to type, or use the Browse button, to
Design specify the location and filename of an existing .pcb file to use
as the starting point for the new design.
Compare Schematic with Selected, enables you to type, or use the Browse button, to
existing PCB design specify the location and filename of an existing .pcb file to
compare with the current schematic.
Generate Differences Report Checked, creates a report that shows the differences between
the schematic and layout design.
Update PCB Design with Part, Checked, updates the layout design with differences in the
Net, and Attribute Differences parts, nets, and attributes.
Update PCB Design with Checked, updates the layout design with design rule changes.
Design Rules Differences

Related Topics
PADS Layout Design Creation
Compare the Schematic to the PADS Layout Design
PADS Layout Forward and Back Annotation Processes

142 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Tool GUI Reference
Library Import Options Dialog Box

Library Import Options Dialog Box

To access: Xpedition Designer: Choose Tools > PCB Interface menu item, click Basic tab,
select Create Netlist for Layout option, and then select “Run command line after
processing” option
Use this dialog box to update Xpedition Designer part types in the PADS Layout library and set
the import options.
Fields
Table 7-7. Library Import Options Dialog Box Contents
Fields Description
Update Part Types in Library Checked, updates the PADS Layout part type library.
Part Type ASCII File Enables you to type, or use the Browse button to specify the
location and filename of the ASCII netlist file (.p).
Import to Library Displays a dropdown list of PADS Layout libraries.
New Library — Opens the Save As dialog box, which
enables you to create a new library. The new library appears
at the bottom of the dropdown list of libraries.
Import Mode for Library Parts Defines options to use when importing library parts.
• Do not overwrite existing parts — Updates parts in the
library that have an earlier timestamp.
• Always Overwrite existing parts — Overwrites existing
parts in the library.
• Prompt for Each part information — Prompts you to
keep or overwrite parts that have differences.

Related Topics
PADS Layout Design Creation
Compare the Schematic to the PADS Layout Design
PADS Layout Forward and Back Annotation Processes
Xpedition Designer To PADS Layout Dialog Box

PCB Interface User's Guide, X-ENTP VX.2.8 143

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Tool GUI Reference
ECO Compare Options Dialog Box

ECO Compare Options Dialog Box

To access: Xpedition DesignerTools > PCB Interface menu item, click Basic tab, select Create
Netlist for Layout option, and then select “Run command line after processing” option
Use this dialog box to compare design objects between the schematic and the layout tool.
Fields
Table 7-8. ECO Compare Options Dialog Box Contents
Fields Description
Data Comparison • Compare only ECO Registered Parts — Excludes non-ECO-
Options Section registered parts. Non-ECO-registered parts may include mechanical or
non-electrical parts located in the PCB design, but not in the schematic
design.
Unchecked, includes all parts during the comparison.
• Compare only ECO Registered Attributes — Excludes non-ECO-
registered attributes.
Note: During the ECO process, via attributes cannot be added,
deleted, or changed.
• Compare Board, Part, Net, and Pin Attributes — Includes board,
part, net, and pin attributes.
• Compare Part Decals — Includes part decals.
• Compare Design Rules — Includes design rules.
Name Comparison • Compare Net Names and Reference Designators. Rename as
Options section Necessary — Compares differences between reference designators and
net names and is primarily used to minimize changes to routed traces.
May result in the positional swapping of parts. For example, to
minimize routed trace changes when swapping R1 and R12, the
software may simultaneously rename R12 to R1 and R1 to R12, and
then reconnect R1 and R12 to the original nets.
• Compare Net Names and Reference Designators. Prefer to Add or
Delete Parts Instead of Renaming — Compares differences between
reference designators and net names on the basis that few reference
designators have been renamed and nets have not been renamed.
Best used to minimize the positional swapping of parts, and the design
disruption that may result.
• Compare Connectivity and Topology (not names). Rename as
Necessary — Compares differences using other names, such as pin
names and part type names, instead of reference designators or net
names.
Best used to compare designs when parts and nets have been renamed,
and minimal interconnect changes have been performed.

144 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Tool GUI Reference
ECO Compare Options Dialog Box

Table 7-8. ECO Compare Options Dialog Box Contents (cont.)

Fields Description
Ignore the Unused Excludes the unused pin’s net in the original design.
Pins Net The unused pin’s net contains pins that have no logical net association. An
unused pin’s net may be created using other tools in the PCB design
process.
Caution: If you uncheck this option, and update the layout tool from a
schematic or previous PCB layout design, the unused pins net may be
deleted.
Net Name The name of the unused pins net. You can use any alphanumeric character
except curly braces { }, an asterisk, space, question mark, or comma.
Maximum net name length: 47 characters.

Related Topics
PADS Layout Design Creation
Compare the Schematic to the PADS Layout Design
PADS Layout Forward and Back Annotation Processes
Xpedition Designer To PADS Layout Dialog Box
Library Import Options Dialog Box

PCB Interface User's Guide, X-ENTP VX.2.8 145

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Tool GUI Reference
PADS Layout To Xpedition Designer Dialog Box

PADS Layout To Xpedition Designer Dialog

Box
To access: Xpedition Designer: Tools > PCB Interface menu item, click Basic tab, select Back
Annotate Information From Layout to Schematic option, select “Run command line before
processing”
Use this dialog box to generate ECO report files, or reuse an existing ECO file to automate the
back annotation process.
Objects
Table 7-9. PADS Layout To Xpedition Designer Dialog Box Contents
Option Description
PCB Design Filename (*.pcb) Enables you to type, or use the Browse button to specify the
location and filename of the .pcb file.
If you have the PADS Layout tool open, the currently opened
filename displays.
ECO File Options — If you are unsure which option to use, refer to “Renumbering Effects of
Back Annotation Methods” in the PADS Layout Concepts Guide.
Create ECO File Using Netlist Compares the newer layout design to the older schematic
Comparison design and generates an .eco file containing the design
changes.
• Generate Differences Report Creates a report file (..\
PADS Projects\ Layout.rep) containing a description of
the differences between the design versions.
• Update Schematic Design with Design Rules
Differences — Updates the schematic with general, net,
net class, and differential pairs rules from PADS Layout.
Use Existing ECO file Uses the .eco file you recorded in PADS Layout for back
annotation.
Tip: A recorded .eco file maintains the relationship
between your integrated circuits and discrete components
in the schematic (refer to “Renumbering Effects of Back
Annotation Methods” in the PADS Layout Concepts Guide).
ECO Filename (*.eco)— Type the pathname or browse for
the recorded .eco file. The PADS Layout tool, ECO Options
dialog box provides the pathname for the file.

Related Topics
PADS Layout Design Creation
Compare the Schematic to the PADS Layout Design

146 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 PCB Interface Tool GUI Reference
PCB Interface PADS Layout Script

PADS Layout Forward and Back Annotation Processes

Xpedition Designer To PADS Layout Dialog Box
Library Import Options Dialog Box

PCB Interface PADS Layout Script

In the PCB Interface, use the ppcb2007.vbs icscript to automatically export and import design
data between Xpedition Designer and PADS Layout. When you select the latest PADS Layout
version in the Layout Tool list in the Xpedition Designer Settings - Project category, the script
automatically appears on the command line with the correct syntax for the direction of the
design information (forward or back).

Prerequisites
• PADS Layout must be installed on the same system as Xpedition Designer

Syntax
ppcb2007.vbs -c <cfg_file> [-f|-b] <design_name>

-c Configuration file.
<cfg_name> Name of your PCB configuration file.
-f Flow to PADS Layout.
-b Flow from PADS Layout.
<design_name> Name of the PADS Layout design.

PCB Interface User's Guide, X-ENTP VX.2.8 147

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
PCB Interface Tool GUI Reference
PCB Interface PADS Layout Script

148 PCB Interface User's Guide, X-ENTP VX.2.8

Note - Viewing PDF files within a web browser causes some links not to function. Use HTML for full navigation.
 Index

—G—
Index

— Symbols — Gate swapping

.cfg, 9 PADS Layout, 66
#attribute, 120 Generic interface, 54
—A— —H—
a2view.pl, 115 HETERO attribute, 120
Allegro interface, 97 Heterogeneous device
—B— parts, 60
Back-annotate, 10 Homogeneous parts, 60
layout changes, 15
—I—
—C— Implicit symbols, 121
Comment character, 31 in design reuse, 124
Configuration (.cfg) file, 9 Installation
ChkRules, 31 local, 23
error rules, 43
—L—
NewPkgRules, 49 Layout
syntax, 41 adding devices, 50
Connectors, off-board, 129 aliasing names with design entry tool, 27
Create PCB Netlist back-annotating changes from, 15
forward annotation, 82 using heterogeneous devices in, 117
—D— using with xDX Designer, 9
DEVICE attribute, 50, 120 Local installation, 23

—E— —M—
ECO file Mapping
Allegro, 108, 115 property names, 27
PADS Layout, 58
—N—
Error Netlist
checking, 31 creating in xDX Designer, 10
messages, 43 passing to layout, 15
rules, 43
Expedition Enterprise Interface, 83 —O—
OATs, 124
—F— Off-board connectors, 129
Forward annotation
Allegro, 109, 110 —P—
Expedition, 88 Package, 117
PADS Layout interface, 56

PCB Interface User's Guide, X-ENTP VX.2.8 149

Pattern matching, 41
pcbbck command
control netlisting, 46, 51
print message summary, 43
update board, 49
update schematic, 49
Visula VDP, 97
pcbfwd command
Allegro, 108
control netlisting, 46, 51
control output format, 45
create part type file, 49
print message summary, 43
Visula VDP, 96
Pin swapping
Allegro, 104
PADS Layout, 67
RINF, 89, 94
PINSWAP attribute, 65, 87, 89
PKG_TYPE attribute, 120
—R—
Reuse
block, 124
RINF interface, 89
—S—
SIGNAL attribute, 121
Simulation model, 122
Symbols
explicit, 121
implicit, 121
Syntax
pattern matching, 41
—V—
Visula, 89
—X—
xDX Designer
symbol usage, 49

150 PCB Interface User's Guide, X-ENTP VX.2.8

 End-User License Agreement
with EDA Software Supplemental Terms
Use of software (including any updates) and/or hardware is subject to the End-User License Agreement together with the
Mentor Graphics EDA Software Supplement Terms. You can view and print a copy of this agreement at:

mentor.com/eula