Unit no:2 Combinational circuits

Minterm: When a Boolean function or logical expression is expressed in the

SOP (Standard Sum of Product) Form , then each term of the expression is
called a minterm.

OR

A product term of a logical expression in n variables, which contains each of

the n variables in its either complemented or un-complemented form is called
a minterm.

Maxterm: When a Boolean function or logical expression is expressed in the

SPOS (Standard Product of Sum) Form or , then each term of the expression
is called a maxterm.
OR

A sum term of a logical expression in n variables, which contains each of the

"n" variables in its either complemented or un-complemented form is called
a maxterm.
Minterm and maxterm for 3 variables

In Digital Electronics any logic circuit’s output is the function of digital

inputs and the relation between input and output can be represented
using logic table or boolean expressions.
This Boolean expression can be represented in two forms.
1. Sum of Product (SOP)
2. Product of Sum (POS)

SOP TERM Representation

The Sum of Product Form

In the sum of the product form , the Boolean expression are defined by
sum of product terms.This form consists of two or more AND terms that
are ORed together.Each AND term consistes of one or more variables
appearing in either complemented or uncomplemented form.
Example:
A.B, A.B
̅.C (example of product term)

n SOP sum refers to logical OR Operation. Therefore, in this sum of

product form of expression, we perform logical or operations on different
product terms. Therefore it is known as the Sum of Product form.
Product of sum(POS)

In product of sums,the Boolean expression are defined by the product of

sum terms.This form consists of two or more than OR term,which are
ANDed together.Each OR term term consists of one or more variables in
complemented or uncomplemented form.

Steps for Converting SOP to SSOP

Here are some of the steps that have to be followed to convert any logical
expression into standard SOP form:

• Find the missing literals or variables for each and every product term.
For example, C is the missing term from the three variable boolean
expressions' product term AB.
• Apply the OR operator between the missing literal and its
complement. For example, (C+C')
• Now join it with the product term through the AND operator. For
example, AB(C+C')
• Repeat all the above steps, that is, from step 1 to step 3, to apply to
all the product terms that have missing literals or variables.

Now let's take an example to understand it in a practical way to apply the

above steps:
F(A,B,C) = AB + AC' + BC

Here, the first term is AB, the second term is AC, and the third term is BC.
We have three product terms, each with one variable missing.

In the first, second, and third terms, the variables C, B, and A are missing,
respectively.

Now, to perform the conversion, follow the above steps for the conversion
purpose. After performing the above steps for all the product terms that
have a missing variable (here all the terms have a missing variable), initially
we will get the following expression:
F(A,B,C) = AB(C+C') + AC'(B+B') + BC(A+A')

Now simplify the above expression as given below:

= AB(C+C') + AC'(B+B') + BC(A+A')
= ABC + ABC' + ABC' + AB'C' + ABC + A'BC
= ABC + ABC' + AB'C' + A'BC

Therefore, in standard SOP form, the final function will be:

F(A,B,C) = ABC + A'BC + ABC' + AB'C'

POS to SPOS Conversion Steps

Here is a list of some rules that have to be followed for the conversion of
any boolean expression from POS to standard POS form:

• Find the missing literal for each sum term.

• Now join the missing literals (in uncomplemented form) and missing
literals (in complemented form) with AND operator, and then join this
term with the sum term using OR operator.
Or, in other words, OR each term combined with the term formed
by AND including the omitted literal and its complement.
• Repeat the process for all the sum terms that have missing literals.
• Simplify the expression to get the boolean expression in standard
POS form.

Let's use an example to put all of the above steps into practice and
understand how to convert any given logical expression into standard POS
form.

We have to convert the boolean expression.

F(A,B,C) = (A+B).(A+C).(A+C')

into its standard POS form.

We have C, B, and A, which are the three variables that are missing from
the first, second, and third sum terms, respectively.

Now OR each term with the missing variable and its complement. After
applying this rule, we get:
F(A,B,C) = (A+B+CC').(A+C+BB').(B+C'+AA')

Simplify the above boolean expression. Here is the simplification of the

boolean expression:
= (A+B+CC').(A+C+BB').(B+C'+AA')
= (A+B+C).(A+B+C').(A+C+B).(A+C+B').(B+C'+A).(B+C'+A')
= (A+B+C).(A+B+C').(A+B'+C).(A'+B+C)

Therefore, the logical expression is:

(A+B).(A+C).(B+C')

in standard POS form are:

(A+B+C).(A'+B+C).(A+B'+C).(A+B+C')

And finally, the function in standard POS is defined as:

F(A,B,C) = (A+B+C).(A'+B+C).(A+B'+C).(A+B+C')

Minterm Notation  f = A’BC + AB’C’ + AB’C + ABC’ +ABC;

(A’BC)(011)=m3,
(AB’C’)100=m4,
(AB’C)101=m5
( ABC’ )110=m6
(ABC)(111)=m7
The other way to represent f is: f (A,B,C) = m3 + m4 + m5 + m6 + m7
or f (A,B,C) = m(3,4,5,6,7)
Maxterm Notation f = (A+B+C)(A+B+C’)(A+B’+C)
(A+B+C)(000)=M0
(A+B+C’)(001)=M1
(A+B’+C) (010)=M2
f (A,B,C) = M0M1M2 or f (A,B,C) =  M (0,1,2)

Find the Minterm

f(a,b,c,d) = a’(b’+d) + acd’. = a’b’ +a’d + acd’
= a’b’(c+c’)(d+d’) + a’d(b+b’)(c+c’) + acd’(b+b’)
= a’b’c’d’ + a’b’c’d + a’b’cd’ +a’b’cd + a’bc’d + a’bcd + abcd’ +ab’cd’
= Σm(0,1,2,3,5,7,10,14)
Find the maxterm:
f(a,b,c,d) = a’(b’+d) + acd’
= (a’+cd’)(a +b’+d)
= (a’+c)(a’+d’)(a+b’+d);
=(a’+bb’+c+dd’)(a’+bb’+cc’+d’)(a+b’ +cc’+d)
=(a’+bb’+c+d)(a’+bb’+c+d’)(a’+bb’+ c+d’)(a’+bb’+c’+d’)(a+b’+cc’+d)
=(a’+b+c+d)(a’+b’+c+d)(a’+b+c+d’)(
a’+b’+c+d’)(a’+b+c’+d’)(a’+b’+c’+d’)(a+b’+c+d)(a+b’+c’+d)
=ΠM(4,6,8,9,11,12,13,15

Karnaugh Map (K-Map)?

Karnaugh map or K-map is a map of a function used in a technique used for
minimization or simplification of a Boolean expression. It results in less number
of logic gates and inputs to be used during the fabrication.
Minimize the following boolean function-
F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)

hus, minimized boolean expression is-

 F(A, B, C, D) = BD + C’D + B’D’

Minimize the following boolean function-

F(A, B, C, D) = Σm(1, 3, 4, 6, 8, 9, 11, 13, 15) + Σd(0, 2, 14)

Thus, minimized boolean expression is-

F(A, B, C, D) = AD + B’D + B’C’ + A’D’
 Don’t care condition

Minimize the following boolean function-

F(A, B, C) = Σm(0, 1, 6, 7) + Σd(3, 5)

Thus, minimized boolean expression is-

F(A, B, C) = AB + A’B’

Minimize the following boolean function-

F(A, B, C) = Σm(1, 2, 5, 7) + Σd(0, 4, 6)
Thus, minimized boolean expression is-
F(A, B, C) = A + B’
Minimize the following boolean function-
F(A, B, C, D) = Σm(0, 2, 8, 10, 14) + Σd(5, 15)

Thus, minimized boolean expression is-

F(A, B, C, D) = ACD’ + B’D’

Minimize the following boolean function-

F(A, B, C, D) = Σm(3, 4, 5, 7, 9, 13, 14, 15)
Thus, minimized boolean expression is-
F(A, B, C, D) = A’BC’ + A’CD + AC’D + ABC

Half-Adder
A half-adder is an arithmetic circuit block that can be used to add two bits. Such a circuit thus has two inputs that
represent the two bits to be added and two outputs, with one producing the SUM outputand the other producing
the CARRY. Figure 7.4 shows the truth table of a half-adder, showing all possible input combinations and the
corresponding outputs.
The Boolean expressions for the SUM and CARRY outputs are given by the equations

Truth table of a half-adder.

 the first one representing the SUM output is that of an EX-OR gate, the second one representing the CARRY
output is that of an AND gate.

Fig: LOGIC DIAGRAM OF HALF ADDER

Full Adder
A full adder circuit is an arithmetic circuit block that can be used to add three bits to
produce a SUM and a CARRY output.

The full adder adds the bits A and B and the carry from the previous column called the
carry in (Cin) and the outputs the sum bit (S) and the carry bit called the carry out (Cout).
The variable S gives the value of the least significant bit of the sum. The variable Cout
gives the outout carry

Fig: block diagram of full adder Truth table of full adder

Full Adder using Logic gates:

From the truth table, we make the following K-map.

From the above K-map,the logical simplified expression for carry out and sum are

Using the truth table and the above K-Map, the Boolean Expression of
Sum (S) output of a Full Adder can be derived as:

the K-Map for Carry output (COUT) of a Full Adder is shown below:
he simplified Boolean equation for COUT is:

COUT = A B + A CIN + B CIN

Fig: Logic diagram of Full adder

7.1.1 Half-Subtractor
A half-subtractor is a combinational circuit that can be used to subtract one binary digit from anotherto produce a
DIFFERENCE output and a BORROW output. The BORROW output here specifies whether a ‘1’ has been borrowed to
perform the subtraction.
Full Subtractor
A full subtractor performs subtraction operation on two bits, a minuend and a
subtrahend, and also takes into consideration whether a ‘1’ has already been
borrowed by the previous adjacent lower minuend bit or not. As a result, there
are three bits to be handled at the input of a full subtractor, namely the two bits
to be subtracted and a borrow bit designated as Bin. There are two outputs,
namely the DIFFERENCE output D and the BORROW output Bo. The
BORROW output bit tells whether the minuend bit needs to borrow a ‘1’ from
the next possible higher minuend bit.

the K-Map as shown for “difference” and “borrow”.

Fig:Logic diagram of Full substractor
Implementation of full substractor using two half- substractor

Necessity of Multiplexer

Multiplexer
A multiplexer or MUX, also called a data selector, is a
combinational circuit with more than one input line, one output line
and more than one selection line.
A multiplexer is a combinational circuit that has 2 n input lines and a single output line.
×
Simply, the multiplexer is a multi-input and single-output combinational circuit. The
binary information is received from the input lines and directed to the output line. On
the basis of the values of the selection lines, one of these data inputs will be connected
to the output.
Unlike encoder and decoder, there are n selection lines and 2n input lines. So, there is
a total of 2N possible combinations of inputs. A multiplexer is also treated as Mux.

Types of Multiplexer:
1. 2:1 MUX
2. 4:1 MUX
3. 8:1 MUX
4. 16:1 MUX

2:1 Multiplexer

Figure 8.4 (a) 2-to-1 multiplexer circuit representation, (b) 2-to-1 multiplexer truth table
and (c) 2-to-1 multiplexer logic diagram.

4:1 Mux
Figure 8.1 (a) 4-to-1 multiplexer circuit representation and (b) 4-to-1
multiplexer truth table.

8:1 mux
Truth Table:
 Logic diagram of 8:1 mux

Implement 8 ×1 multiplexer using 4×1 and 2×1 multiplexer

We can implement the 8×1 multiplexer using a lower order multiplexer. To implement
the 8×1 multiplexer, we need two 4×1 multiplexers and one 2×1 multiplexer. The 4×1
multiplexer has 2 selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only
1 selection line.

For getting 8 data inputs, we need two 4×1 multiplexers. The 4×1 multiplexer produces
one output. So, in order to get the final output, we need a 2×1 multiplexer. The block
diagram of 8×1 multiplexer using 4×1 and 2×1 multiplexer is given below.
16 to 1 Multiplexer
In the 16 to 1 multiplexer, there are total of 16 inputs, i.e., A 0, A1, …, A16, 4 selection
lines, i.e., S0, S1, S2, and S3 and single output, i.e., Y. On the basis of the combination of
inputs that are present at the selection lines S 0, S1, and S2, one of these 16 inputs will
be connected to the output. The block diagram and the truth table of the 16×1 mux.

Block Diagram
Truth table

The logical expression of the term Y is as follows:

Y=A0.S0'.S1'.S2'.S3'+A1.S0'.S1'.S2 '.S3+A2.S0'.S1'.S2.S3'+A3.S0'.S1 '.S2.S3+A4.S0'.S1.S2'.S3'+A

5.S0 '.S1.S2'.S3+A6.S1.S2.S3'+A7.S0 '.S1.S2.S3+A8.S0.S1'.S2'.S3'+A9 .S0.S1'.S2'.S3+Y10.S0.S1'.S
2.S3 '+A11.S0.S1'.S2.S3+A12
S0.S1.S2 '.S3'+A13.S0.S1.S2'.S3+A14.S0.S1 .S2.S3'+A15.S0.S1.S2'.S3
 Fig: logic diagram of 16:1 mux.

6×1 multiplexer using 8×1 and 2×1 multiplexer

We can implement the 16×1 multiplexer using a lower order multiplexer. To implement
the 8×1 multiplexer, we need two 8×1 multiplexers and one 2×1 multiplexer. The 8×1
multiplexer has 3 selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only
1 selection line.

For getting 16 data inputs, we need two 8 ×1 multiplexers. The 8×1 multiplexer
produces one output. So, in order to get the final output, we need a 2×1 multiplexer.
The block diagram of 16×1 multiplexer using 8×1 and 2×1 multiplexer is given below.
De-multiplexer
A De-multiplexer is a combinational circuit that has only 1 input line and 2 N output
lines. Simply, the multiplexer is a single-input and multi-output combinational circuit.
The information is received from the single input lines and directed to the output line.
On the basis of the values of the selection lines, the input will be connected to one of
these outputs. De-multiplexer is opposite to the multiplexer.

Unlike encoder and decoder, there are n selection lines and 2 n outputs. So, there is a
total of 2n possible combinations of inputs. De-multiplexer is also treated as De-mux.

there are various types of De-multiplexer which are as follows:

1×2 De-multiplexer:
In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y 0, and Y1, 1 selection
lines, i.e., S0, and single input, i.e., A. On the basis of the selection value, the input will
be connected to one of the outputs. The block diagram and the truth table of the 1×2
multiplexer are given below.
 Truth table

he logical expression of the term Y is as follows:

Y0=S0'.A
Y1=S0.A

Logical circuit of the above expressions is given below:

1×4 De-multiplexer:
In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y 0, Y1, Y2, and Y3, 2 selection
lines, i.e., S0 and S1 and single input, i.e., A. On the basis of the combination of inputs
which are present at the selection lines S 0 and S1, the input be connected to one of the
outputs. The block diagram and the truth table of the 1×4 multiplexer are given below.

Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

Y0=S1' S0' A
y1=S1' S0 A
y2=S1 S0' A
y3=S1 S0 A
Logical circuit of the above expressions is given below:

1×8 De-multiplexer
In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and
Y7, 3 selection lines, i.e., S0, S1and S2 and single input, i.e., A. On the basis of the
combination of inputs which are present at the selection lines S 0, S1 and S2, the input
will be connected to one of these outputs. The block diagram and the truth table of
the 1×8 de-multiplexer are given below.
Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

Y0=S0'.S1'.S2'.A
Y1=S0.S1'.S2'.A
Y2=S0'.S1.S2'.A
Y3=S0.S1.S2'.A
Y4=S0'.S1'.S2 A
Y5=S0.S1'.S2 A
Y6=S0'.S1.S2 A
Y7=S0.S1.S3.A

Logical circuit of the above expressions is given below:

1×8 De-multiplexer using 1×4 and 1×2 de-multiplexer

We can implement the 1×8 de-multiplexer using a lower order de-multiplexer. To
implement the 1×8 de-multiplexer, we need two 1×4 de-multiplexer and one 1×2 de-
multiplexer. The 1×4 multiplexer has 2 selection lines, 4 outputs, and 1 input. The 1×2
de-multiplexer has only 1 selection line.
For getting 8 data outputs, we need two 1×4 de-multiplexer. The 1×2 de-multiplexer
produces two outputs. So, in order to get the final output, we have to pass the outputs
of 1×2 de-multiplexer as an input of both the 1×4 de-multiplexer. The block diagram
of 1×8 de-multiplexer using 1×4 and 1×2 de-multiplexer is given below.

1 x 16 De-multiplexer
In 1×16 de-multiplexer, there are total of 16 outputs, i.e., Y 0, Y1, …, Y16, 4 selection lines,
i.e., S0, S1, S2, and S3 and single input, i.e., A. On the basis of the combination of inputs
which are present at the selection lines S 0, S1, and S2, the input will be connected to
one of these outputs. The block diagram and the truth table of the 1×16 de-
multiplexer are given below.
Block Diagram:
The logical expression of the term Y is as follows:

Y0=A.S0'.S1'.S2'.S3'
Y1=A.S0'.S1'.S2'.S3
Y2=A.S0'.S1'.S2.S3'
Y3=A.S0'.S1'.S2.S3
Y4=A.S0'.S1.S2'.S3'
Y5=A.S0'.S1.S2'.S3
Y6=A.S0'.S1.S2.S3'
Y7=A.S0'.S1.S2.S3
Y8=A.S0.S1'.S2'.S3'
Y9=A.S0.S1'.S2'.S3
Y10=A.S0.S1'.S2.S3'
Y11=A.S0.S1'.S2.S3
Y12=A.S0.S1.S2'.S3'
Y13=A.S0.S1.S2'.S3
Y14=A.S0.S1.S2.S3'
Y15=A.S0.S1.S2'.S3

Logical circuit of the above expressions is given below:

1×16 de-multiplexer using 1×8 and 1×2 de-multiplexer

We can implement the 1×16 de-multiplexer using a lower order de-multiplexer. To
implement the 1×16 de-multiplexer, we need two 1×8 de-multiplexer and one 1×2
de-multiplexer. The 1×8 multiplexer has 3 selection lines, 1 input, and 8 outputs. The
1×2 de-multiplexer has only 1 selection line.
Implement the product-of-sums Boolean function expressed by M1,2,5 by a suitable multiplexer.