A NOVEL TOPOLOGY OF FIFTEEN LEVEL

MULTILEVEL INVERTER WITH HARMOMNIC

ELIMINATION USING GA-SHE
A Project Report
Submitted in the partial fulfillment of the requirements for
the award of the degree of
Bachelor of Technology
in
Electrical & Electronics Engineering
By
CH.Revathi(Y16AEE412) G.Lokesh Naidu(Y16AEE434)
G.Bhaskar rao(L17AEE537) D.Siva sai kumar(Y15AEE432)
Under the guidance of
Mrs.D.Naga lakshmi, M.Tech
Asst.Professor

Department of Electrical and Electronics Engineering

Bapatla Engineering College
(Autonomous)
(Affiliated to AcharyaNagarjuna University)
BAPATLA – 522102, Andhra Pradesh, INDIA
June, 2020
 Declaration

The Thesis entitled “A Novel Topology of Fifteen Level Multilevel Inverter

With Harmonic Elimination Using GA-SHE “ is a record of bonafide work

carried out by me, submitted in partial fulfillment for the award of Bachelor of

Technology in Electrical and Electronics Engineering to the Jawaharlal Nehru

Technological University Kakinada. The results embodied in this thesis have not

been submitted to any other University or Institute for the award of any degree or

diploma.

Signature of the Student

 Department of Electrical and Electronics Engineering
Bapatla Engineering College
(Autonomous)
(Affiliated to Acharya Nagarjuna University)
BAPATLA – 522102, Andhra Pradesh, INDIA

Certificate

This is to certify that the thesis entitled “A Novel Topology of Fifteen Level
Multilevel Inverter With Harmonic Elimination Using GA-SHE” is being
submitted by
CH.Revathi(Y16AEE412) G.Lokesh Naidu(Y16AEE434)
G.Bhaskar rao(L17AEE537) D.Siva sai kumar(Y15AEE432)
in partial fulfillment for the award of Bachelor of Technology in Electrical and
Electronics Engineering to Bapatla Engineering College, Bapatla is a record of
bonafide work carried out under my guidance.
The results embodied in this project report have not been submitted to any
other University or Institute for the award of any degree or diploma.

Signature of HOD Signature of the Project Guide

Dr.N.Rama Devi Mrs.D.Naga Lakshmi
 ACKNOWLEDGEMENTS
I would like to express my sincere gratitude and appreciation to my project
guide Mrs.D.Naga Lakshmi, Professor, Bapatla Engineering college, Bapatla for
their guidance and assistance throughout the project work. The advice and constant
encouragement given by them is gratefully acknowledged. I would like to express
my gratitude Dr. N.Rama Devi. Professor and Head of EEE department, Bapatla
Engineering College, Bapatla for all his help and encouragement throughout this
work. I would like to express my sincere thanks to Dr.V.Damodhar Naidu,
Principal, Bapatla Engineering College, Bapatla. I am thankful to all the faculty
members and staff of the Department of Electrical Engineering is gratefully
acknowledged. Finally, I thank everyone who has directly or indirectly helped me
during the course of this work.

With Regards

CH.Revathi(Y16AEE412)
G.Lokesh Naidu(Y16AEE434)
G.Bhaskar rao(L17AEE537)
D.Siva sai kumar(Y15AEE432)
 ABSTRACT
Renewable energy sources such as fuel cell, solar, Magneto hydro
Dynamic (MHD), geothermal are the best alternatives to solve the
problem of environmental issue and increasing demand of energy.
The output of these resources is dc, therefore to connect these
resources to the grid, multilevel inverter is the key device. But the
output of multilevel inverter has power quality issues such as
harmonic generation and notching due to conversion of dc to ac and
high number of switch. Hence, this paper deals with harmonic
elimination using Genetic Algorithm based Selective Harmonic
Elimination (GA-SHE) techniques for asymmetric and symmetric
topology of MLI. In the present study, comparative study among
various multilevel inverters with reduced number of switches
topologies has been discussed. A novel topology of single phase 15-
level inverter which consists least number of switches has been
designed for a desired voltage level. Also, the comparison of Total
harmonic distortion (THD) developed in the proposed 15-level
inverter with output voltage generated by different topology at
different levels are discussed. The output of proposed topology
contains THD (<5%) as per IEEE 519 standard.
 CONTENTS

DESCRIPTION PAGE NO
TITLE PAGE i
CERTIFICATE ii
DECLARATION iii

ACKNOWLEDGEMENT iv

ABSTRACT v

CHAPTER 1: 1-2
1.1 INVERTER 1
1.2 WHY DO WE CONSIDER MULTILEVEL INVERTER INSTEAD OF AND
INVERTER 1
1.3 WHAT IS A MULTILEVEL INVERTER 2
CHAPTER 2: 3-12
2.1 TYPE OF MULTILEVEL INVERTER 3
2.1.1) DIODE CLAMPED MULTILEVEL INVERTER 4
2.1.2) FLYING CAPACITOR MULTILEVEL INVERTER 7
2.1.3) CASCADED H-BRIDGE MULTILEVEL INVERTER 10
CHAPTER 3: 13-18
3.1) MODULATION TECHNIQUE 13
3.2) PULSE WIDTH MODULATION (PWM) TECHNIQUES 15
3.3) GA-SHE TECHNIQUE 16
CHAPTER 4: 19-34
4.1)A 15- LEVEL ASYMMETRIC CASCADED H BRIDGE MULTILLEVEL
INVERTER 19
4.2) OPERATION A 15-LEVEL ASYMMETRIC CASCADED H–BRIDGE
MULTILEVEL INVERTER LESS NUMBER OF SWITCHES 20
CHAPTER 5: 35-38
5.1) SIMULATION DIAGRAM OF MATLAB (2014/b) 35
5.2) INPUT WAVE FORM 37
5.3) SIMULATION DIAGRAM OF MATLAB (2014/b) WITH GA-SHE 37

CHAPTER 6: 39-43
6.1) SIMULATION OUTPUT 39
6.2) COMPARISON OF THD 43
CONCLUSION 44
REFERENCES 45
 CHAPTER 1

1.1) Inverter

A device which convert DC power into AC power at desired out voltage and
frequency is called inverter

Fig1.1

 Operated in inverter mode are called line commutated inverter.

 But line commutated inverters require at the output terminals an
existing ac supply which is used for their commutation.
 Line commutated inverters can’t function as isolated ac voltage
source or as variable frequency generators with dc power input.
 Voltage level, frequency and wave form on the ac side of line
commutated inverters can’t be change.

1.2) why do we consider multilevel inverter instead of an inverter?

 Operating at high frequency mainly due to switching loss and

constraints of device rating.
 The semi-conductor switching. Device should be used in such a
manner as to avoid problem.
 Series-parallel combination that are necessary to obtain capability of
handing high voltage and current.
1.3) what is a multilevel inverter?
The high voltage with low harmonic without the use of transformer or
series- parallel connected synchronized switching device the number of
voltage level increase is known as multilevel inverter.

 The multilevel inverter have drawn tremendous interest in the power

industry
 It may be easier to produce a high power, high voltage inverter with
multilevel structure because of the way in which device voltage
stresses are controlled in the structure
 Multilevel voltage sources inverter allows them to reach high voltages
with low harmonics without the use of transformer or series connected
synchronized switching devices
 CHAPTER 2
2.1) Type of multilevel inverter

There are 3 type of multilevel inverter those are

1) Diode Clamped or Neutral Point clamped multilevel inverter.
2) Flying Capacitor multilevel inverter
3) Cascaded H-Bridge multilevel inverter
 Fig 2.1) classification of multilevel inverter

2.1.1) Diode Clamped multilevel inverter

The most commonly used multilevel topology is the diode clamped

inverter, in which the diode is used as the clamping device to clamp the dc
bus voltage so as to achieve steps in the output voltage. The neutral point
converter proposed by Nabae, Takahashi, and Akagi in 1981 was essentially
a three-level diode-clamped inverter.
A three-level diode clamped inverter consists of two pairs of switches and
two diodes. Each switch pairs works in complimentary mode and the diodes
used to provide access to mid-point voltage .In a three-level inverter each of
the three phase so of the inverter shares a common DC bus, which has been
sub divided by two capacitors into three levels. The DC bus voltage is split
into three voltage levels by using two series connections of DC capacitors,
C1 and C2. The voltage stress across each switching device is limited to V dc
trough the clamping diodes Dc1 and Dc2.It is assumed that the total dc link
voltage is Vdc and midpoint is regulated at half of the dc link voltage, the
voltage across each capacitor is Vdc /2 (Vc1=Vc2= Vdc /2). In a three level
diode clamped inverter, there are three different possible switching states
which apply the stair case voltage on output voltage relating to DC link
capacitor voltage rate. For a three-level inverter, a set of two switches is on
at any given time and in a five-level inverter, a set of four switches is on at
any given time and so on. Fig-2.2 shows the circuit for a diode clamped
inverter for a three-level and a five-level inverter. Switching states of the
three level inverter are summarized in table-1
 Table-2.1. Switching states in one leg of the three-level diode clamped
inverter

Fig 2.2: Topology of the diode-clamped inverter (a) three-level inverter, (b)
five -level inverter
2.1.1.2) Advantages and Disadvantages

Advantages:

1. All of the phases share a common dc bus, which minimizes the

capacitance requirements of the converter. For this reason, a back-to-

back topology is not only possible but also practical for uses such as

a high-voltage back-to-back inter-connection or an adjustable speed

drive.

2. The capacitors can be pre-charged as a group.

 3. Efficiency is high for fundamental frequency switching.

Disadvantages:

1. Real power flow is difficult for a single inverter because the

intermediate dc levels will tend to overcharge or discharge without

precise monitoring and control.

2. The number of clamping diodes required is quadratically related to the

number of levels [1], which can be cumbersome for units with a high

number of levels

2.1.2) Flying Capacitor multilevel inverter

The capacitor clamped inverter alternatively known as flying capacitor was

proposed by Meynardand Foch in 1992 [18].The structure of this inverter is

similar to that of the diode- clamped inverter except that instead of using

clamping diodes, the inverter uses capacitors in their place. The flying

capacitor involves series connection of capacitor clamped switching cells.

This topology has a ladder structure of dc side capacitors, where the voltage

on each capacitor differs from that of the next capacitor. The voltage
increment between two adjacent capacitor legs gives the size of the voltage

steps in the output waveform. Figure 2.3 shows the three-level and five-level

capacitor clamped inverters respectively.

In the operation of flying capacitor multi-level inverter, each phase node (a,

b, or c) can be connected to any node in the capacitor bank (V3, V2, V1).

Connection of the a-phase to positive node V3 occurs when S1 and S2 are

turned on and to the neutral point voltage when S2 and S1′ are turned on.

The negative node V1 is connected when S1′ and S2′are turned on. The

clamped capacitor C1 is charged when S1 and S1′ are turned on and is

discharged when S2 and S2′ are turned on. The charge of the capacitor can

be balanced by proper selection of the zero states.

Fig.2.3 Capacitor-clamped multilevel inverter circuit topologies, (a) 3-level

inverter (b) 5- level inverter.

2.1.2.1) Advantages and Disadvantages

Advantages:

i) Added clamping diodes are not needed.

ii) ii) It has switching redundancy within the phase, which can be

used to balance the flying capacitors so that only one dc source is

needed.

iii) The required number of voltage levels can be achieved without the

use of the transformer. This assists in reducing the cost of the

converter and again reduces power loss.

iv) Unlike the diode clamped structure where the series string of

capacitors share the same voltage, in the capacitor-clamped voltage

source converter the capacitors within a phase leg are charged to

different voltage levels.

v) Real and reactive power flow can be controlled.

Disadvantages:
 i) Converter initialization ie., before the converter can be modulated by

any modulation scheme the capacitors must be set up with the

required voltage level as the initial charge. This complicates the

modulation process and becomes a hindrance to the operation of the

converter.

ii) Control is complicated to track the voltage levels for all of the

capacitors.

iii) Pre charging all of the capacitors to the same voltage level and start

up are complex.

iv) Switching utilization and efficiency are poor for real power

transmission.

2.1.3) Cascaded H-Bridge multilevel inverter

Fig 2.4: Single phase structures of Cascaded inverter (a) 3-level, (b) 5level,

(c) 7-level

One more alternative for a multilevel inverter is the cascaded multilevel

inverter or series H-bridge inverter. The series H-bridge inverter appeared in

1975[14].

Cascaded multilevel inverter was not fully realized until two researchers, Lai

and Peng.
They patented it and presented its various advantages in 1997. Since then,

the CMI has been utilized in a wide range of applications. With its

modularity and flexibility, the CMI shows superiority in high-power

applications, especially shunt and series connected FACTS controllers.

The CMI synthesizes its output nearly sinusoidal voltage waveforms by

combining many isolated voltage levels.

2.1.3.1) Advantages and Disadvantages

Advantages:

i) The regulation of the DC buses is simple.

ii) Modularity of control can be achieved. Unlike the diode clamped and

capacitor clamped inverter where the individual phase legs must be

modulated by a central controller, the full-bridge inverters of a

cascaded structure can be modulated separately.

iii) Requires the least number of components among all multilevel

converters to achieve

iv) The same number of voltage levels.

v) Soft-switching can be used in this structure to avoid bulky and loss

resistor- capacitor-diode seubbers.

 Disadvantages:

i) Communication between the full-bridges is required to achieve the

synchronization of reference and the carrier waveforms.

ii) Needs separate dc sources for real power conversions, and thus its

applications are somewhat limited

Cascaded H-Bridges is a best

 It requires the least number of components to achieve the same

number of voltage levels.

 Optimized circuit layout and packaging are possible, (No extra

clamping diode or voltage –balancing capacitors).

 Soft-switching technique can be used to reduce switching loss and

device stresses.

CHAPTER 3

3.1) MODULATION TECHNIQUE

 Fig 3.1) modulation technique for inverter

The various pulse width modulation techniques are explained in this chapter

and list out their merits and demerits. After this discussion, the simple and

well established motor friendly sinusoidal modulation, delta modulation and

improved delta modulation techniques are explained. Their operation, the

circuit design procedure and their inherent characteristics are discussed. The

requirement of the V/F speed control method of induction motor drives is

highlighted. Also the reasons for selection of these modulation techniques

used to control the proposed soft switched PWM inverter fed induction

motor drives are highlighted in this chapter.

CLASSIFICATION OF MODULATION TECHNIQUES

There are many types, of modulation techniques available, to achieve simple

implementation and improved overall inverter efficiency in the practical

applications. Basically, they are classified into two major types, namely

carrier based modulation and carrier less modulation techniques.

The carrier based modulation technique is further classified as

Sinusoidal Pulse Width Modulation (SPWM)

Modified Pulse Width Modulation (MPWM)

Random Pulse Width Modulation (RPWM)

Third harmonic injection PWM

Space Vector Modulation (SVM)

Carrier less modulation technique is further classified as

Delta Modulation (DM)

Specific Harmonic Elimination (SHE)

Wavelet Modulation (WM) 35

The main aim of these modulation techniques is to enhance, the output of the

inverters. Various techniques are designed to control the PWM inverter

switches in order to shape up the PWM inverter output AC voltage or

current to be very close to sine waveform. The quality of these, PWM

techniques, depends on the amplitude of the fundamental component, the

harmonic content in the inverter output, the effect of harmonics on the

source, the switching losses, controllability and implementation.

3.2) PULSE WIDTH MODULATION (PWM) TECHNIQUES

The output voltage of a voltage source inverter, can be adjusted by various

methods such as external control of AC voltage on the output side of VSI,

external control of DC voltage on the input side of VSI and internal control

within the VSI. The most efficient method of internal control of VSI is by a

PWM control technique used within the inverter itself. In the PWM method,

a constant input DC voltage is applied to the inverter and a controlled AC

output voltage with frequency is obtained. It is accomplished by adjusting

the turn on and turn off periods of the inverter switching devices. 34

Because of the advances in power electronics devices and modern digital

control systems, the PWM inverters are used in various industrial

applications to convert DC to AC and deliver AC power with various

voltage and frequency levels to the load or motors. The energy that a PWM

inverter delivers to a motor is controlled by the train of PWM control signal

to the gates or the control terminal of the power electronics devices.

3.3) GA-SHE technique

GA-SHE full form is “Genetic algorithm selective harmonic elimination”.

The purpose of the SHE technique is to get rid of certain lower order

harmonics. Other than triple –n harmonics, the remaining order of harmonics

can be removed by means of proper filter. But the drawback in SHE is that it

cannot obtain solutions for nonlinear equations easily. Therefore, certain

optimization techniques have to be implemented. The model wave form for

the SHE method is shown below Fig3.2

 Fig 3.2) Model wave for selective harmonic elimination (SHE) method

Genetic Algorithm

This algorithm is usually used to reach a near global optimum solution. In

each iteration of the GA a new set of strings, which are called chromosomes,

with improved fitness is produced using genetic operators. A selection

operator, a crossover operator which acts on a population of strings to

perform the required reproduction and recombination, and a mutation

operator which randomly alters character values, usually with a very low

probability. They are generally solved by equating Fourier equations to zero

and then by obtaining switching angles. Fourier series expansion for

waveform is:
where, Vn is the amplitude of the harmonics. The angles are limited to

between zero and 90◦ (0 ≤ θ ≤ 90). Because of an odd quarter-wave

symmetric characteristic, the harmonics with an even order become zero.

Subsequently, Vn becomes:

For elimination of 5th, 7th harmonics, these three equations should be

solved
 CHAPTER 4

4.1) A 15- LEVEL ASYMMETRIC CASCADED H BRIDGE

MULTILLEVEL INVERTER

The asymmetric multilevel inverters are based on the voltage across the dc
link i.e., the voltages are not equal they are the multiple of basic given
voltage. In asymmetric cascaded h-bridge multilevel inverter the number of
switches and number of levels are represented

Nlevel =2(n-1)-1

Nmosfet =n+4

It main circuit has 7 switches, 3 sources and 3 diodes as shown in below

figure 4.1
4.2) Operation A 15-level asymmetric cascaded H–Bridge multilevel
inverter less number of switches

Form the diagram, how each step flow the current as shown below diagram
STEP1:

In positive cycle switches in on are T1, T2, T3, S1 and S2.The voltage
brought to bear across the load is +Vdc.

Fig 4.2) step 1 current flow diagram

STEP2:

In positive cycle switches in on are T2, T3, S1 and S2, then current flow via
Diode D1. The voltage brought to bear across the load is +(6/7)Vdc.

Fig 4.3) step 2 current flow diagram

STEP3:

In positive cycle switches in on are T1, T3, S1 and S2, then current flow via
Diode D2. The voltage brought to bear across the load is +(5/7)Vdc

Fig 4.4) step 3 current flow diagram

STEP4:

In positive cycle switches in on are T3, S1 and S2, then current flow via
Diode (D1&D2). The voltage brought to bear across the load is +(4/7)Vdc

Fig 4.5) step 4 current flow diagram

STEP5:

In positive cycle switches on are T1, T2, S1 and S2, then current flow via
Diode D3. The voltage brought to bear across the load is +(3/7)Vdc.

Fig 4.6) step 5 current flow diagram

STEP6:

In positive cycle switches on are T2, S1 and S2, then current flow via
Diodes (D3&D1). The voltage brought to bear across the load is +(2/7)Vdc.

Fig 4.7) step 6 current flow diagram

STEP7:

In positive cycle switches on are T1, S1 and S2, then current flow via
Diodes (D3&D2). The voltage brought to bear across the load is +(1/7)Vdc.

Fig 4.8) step7 current flow diagram

STEP8:

The Zero Output voltage level is produced by turning on switches

S1,S2,S3&S4 and remaining controlled switch are in off condition the
voltage is zero.

Fig 4.9) step8 current flow diagram

STEP9:
In Negative cycle switch on are T1,S3,and S4,then current flows via diodes
(D2&D3).The voltage brought to bear across the load is –(1/7) vdc.

Fig 4.10) step 9 current flow diagram

Step10:
In Negative cycle switch on are T2,S3,and S4,then current flows
via(D1&D3).The voltage brought to bear across the load is –(2/7) vdc.

Fig 4.11) step 10 current flow diagram

Step11:
In Negative cycle switch on are T2,T1,S3,and S4,then current flows via
D3.The voltage brought to bear across the load is –(3/7) vdc.

Fig 4.12) step 11 current flow diagram

Step12:
In Negative cycle switch on are T3,S3,and S4,then current flows
via(D1&D2).The voltage brought to bear across the load is –(4/7) vdc.

Fig 4.13) step 12 current flow diagram

Step13:
In Negative cycle switch on are T1, T3, S3 and S4, then current flows via
(D1&D3) The voltage brought to bear across the load is –(5/7)vdc.

Fig 4.14) step 13 current flow diagram

Step14:

In Negative cycle switch on are T2,T3,S3,and S4,then current flows via

D1.The voltage brought to bear across the load is –(2/7) vdc.

Fig 4.15) step 14 current flow diagram

Step15:
In Negative cycle switch on are T2,T1,T3,S3,and S4, The voltage brought to
bear across the load is –(1/7) vdc.

Fig 4.16) step 15 current flow diagram

CHAPTER 5
5.1) SIMULATION DIAGRAM OF MATLAB (2014/b)

A 15-level Asymmetric cascaded H-bridge multilevel inverter consist of 3

source,7 Mosfets controlled switches and 3 diodes. There Input dc source
vdc1=35, vdc2=75 and vdc3=140. PD-PWM (phase disposition pulse width
modulation technique) for the output. For Low switching all switch are
operated to 50Hz.For high switching ,s1,s2,s3 are operated to 2K Hz
remaining switches are operated to 50Hz.

Fig 5.1) simulation for 15 level ASCHMLI with reduced number of switches

5.1.1) inside subsystem2

It consist of one Sine Wave, Repeating Sequence needed is 15, relational
Operator needed is 15. To create steps we use logic gates in order to get
output and hence we use 8 NOT gates, 8 AND gates and 3 OR gates. For
Low switching case the switching frequency is 50Hz.For high switching,
s1,s2,s3 the frequency is 2K Hz and for remaining switches are of 50Hz.

Fig 5.2) inside subsystem

5.2) INPUT WAVE FORM

 Fig5.3) PD-PWM SWITCHING SINGAL GENERATION

Above diagram show sine wave form frequency is 50Hz.and triangle wave

form frequency is 2K Hz. This input is use for high switching if wanted you

give input of low switching just change the triangles wave from frequency is

50Hz.

5.3) SIMULATION DIAGRAM OF MATLAB (2014/b) WITH GA-SHE

Here we consider 7 sources. It need 18 switches, in which four are

unidirectional switches and remaining are bidirectional switches.

Unidirectional switches given to bridges and triggering values are given

on the basis of 1cycle time consisting 0.02msec of total time. For positive

cycle 0.01 is the time period where 2 switches are on using not gate and 2

Switches are in off position. With the help of Bidirectional switches, now

we plan to design a 15 level, for that we give triggering values in this

manner.

for positive cycle consist 7 level so 01-----07, less than 90.

01=0.556,02=(90/7)*01--------------07=(90/7)*06, 01=(20msec/360)

Fig 5.4) simulation for 15 level ASCHMLI with technique

 CHAPTER 6

6.1) SIMULATION OUTPUT

Simulation using with and without use of GA-SHE switching frequencies

6.1.1) with GA-SHE switching

With GA-SHE switching output waveform X-axis taken as time and Y-axis

is taken as voltage

Fig 6.1) output waveform by using GA-SHE switching for ASCHMLI

6.1.1.2) THD and FFT analysis with using GA-SHE for ASCHMLI

Fig 6.2) THD and FFT for with using GA-SHE

6.1.2) without GA-SHE switching

Without using GA-SHE switching output waveform X-axis is taken as time

and Y-axis is taken as voltage

Fig 6.3) output wave form for without using GA-SHE switching for

ASCHMLI
6.1.2.2) THD and FFT analysis without GA-SHE for ASCHMLI

Fig 6.3) THD and FFT for without using GA-SHE

6.2) COMPARISON OF THD

S.NO GA-SHE THD

1 WITH 6.29%

2 WITHOUT 15.73%
 CONCLUSION

Generally 15 level consisting a number of bridges =7, number of sources are

7 and switches present are 28. Our work carried out on the asymmetric

cascaded H-bridge multilevel inverter uses 3 sources, 1 H-bridge and

number of switches are 7. By GA-SHE technique we observe the THD

analysis values are reduced. We conclude the that GA-SHE is Best but it not

better because it is not less than 5% of the THD

 REFERENCE

1. THD analysis of cascaded h bridge multilevel inverter by Gurucharn

singh ;IEEE papers

2. A novel topology of fifteen level multilevel inverter reduced THD by

Rohit kumar; IEEE papers

3. 15 level Asymentrical cascded H bridge Multilevel inverter with less

number of switches by J.gowri shankar

4. A. Jain, N. Khatri, P. Shrivastav and A. Mahor “THD Analysis of

Cascaded H-bridge Multilevel Inverters in Fuel Cell Applications”

IEEE International Conference on Computer, Communication and

Control, 2015, pp 1-6

5. B. Rajesh and Manjesh “Comparison of Harmonics and THD

Suppression with Three and 5 Level Multilevel Inverter-Cascaded H-

bridge” IEEE International Conference on Circuit, Power and

Computing Technologies [ICCPCT], 2016, pp 1-6