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SN 7416

The document provides specifications for the SN5406, SN5416, SN7406, and SN7416 hex inverter buffers/drivers, which feature open-collector high-voltage outputs suitable for interfacing with high-level circuits and driving high-current loads. It outlines their electrical characteristics, recommended operating conditions, and packaging information. The devices are designed to convert TTL voltage levels to MOS levels and are compatible with most TTL circuits.

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0% found this document useful (0 votes)
20 views20 pages

SN 7416

The document provides specifications for the SN5406, SN5416, SN7406, and SN7416 hex inverter buffers/drivers, which feature open-collector high-voltage outputs suitable for interfacing with high-level circuits and driving high-current loads. It outlines their electrical characteristics, recommended operating conditions, and packaging information. The devices are designed to convert TTL voltage levels to MOS levels and are compatible with most TTL circuits.

Uploaded by

wyortiz75
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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SN5406, SN5416, SN7406, SN7416

HEX INVERTER BUFFERS/DRIVERS


WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
SDLS031A – DECEMBER 1983 – REVISED DECEMBER 2001

D Convert TTL Voltage Levels to MOS Levels SN5406, SN5416 . . . J OR W PACKAGE

D High Sink-Current Capability


SN7406 . . . D, N, OR NS PACKAGE
SN7416 . . . D OR N PACKAGE
D Input Clamping Diodes Simplify System (TOP VIEW)
Design
D Open-Collector Drivers for Indicator Lamps
1A
1Y
1 14 VCC
6A
2 13
and Relays
2A 6Y
D
3 12
Inputs Fully Compatible With Most TTL 2Y 4 11 5A
Circuits
3A 5 10 5Y
3Y 6 9 4A
description
GND 7 8 4Y
These TTL hex inverter buffers/drivers feature
high-voltage open-collector outputs for interfacing SN5406 . . . FK PACKAGE
with high-level circuits (such as MOS) or for (TOP VIEW)
driving high-current loads (such as lamps or

VCC
NC
1Y
1A

6A
relays), and also are characterized for use as
inverter buffers for driving TTL inputs. The
SN5406 and SN7406 have minimum breakdown 3 2 1 20 19
2A 4 18 6Y
voltages of 30 V. The SN5416 and SN7416 have NC 5 17 NC
minimum breakdown voltages of 15 V. The 2Y 6 16 5A
maximum sink current is 30 mA for the SN5406 NC 7 15 NC
and SN5416, and 40 mA for the SN7406 and 3A 8 14 5Y
SN7416. 9 10 11 12 13

3Y

4Y
6A
NC
GND
NC – No internal connection

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
Tube SN7406D
7406
Tape and reel SN7406DR
SOIC – D
Tube SN7416D
7416
0°C to 70°C Tape and reel SN7416DR
SN7406N SN7406N
PDIP – N Tube
SN7416N SN7416N
SOP – NS Tape and reel SN7406NSR SN7406
Tube SNJ5406J SNJ5406J
CDIP – J
Tube SNJ5416J SNJ5416J
–55°C to 125°C Tube SNJ5406W SNJ5406W
CDIP – W
Tube SNJ5416W SNJ5416W
LCCC – FK Tube SNJ5406FK SNJ5406FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  2001, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production
testing of all parameters. processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1


SN5406, SN5416, SN7406, SN7416
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
SDLS031A – DECEMBER 1983 – REVISED DECEMBER 2001

logic diagram (positive logic)

1A 1 2 1Y

2A 3 4 2Y

3A 5 6 3Y

4A 9 8 4Y

5A 11 10 5Y

6A 13 12 6Y

Y=A

schematic (each buffer/driver)


’06, ’16
VCC

6 kΩ 1.4 kΩ
1.6 kΩ
Output Y
Input A
2 kΩ

100 Ω

1 kΩ

GND

Resistor values shown are nominal.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Output voltage, VO (see Notes 1 and 2): SN5406, SN7406 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
SN5416, SN7416 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. This is the maximum voltage which should be applied to any output when it is in the off state.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


SN5406, SN5416, SN7406, SN7416
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
SDLS031A – DECEMBER 1983 – REVISED DECEMBER 2001

recommended operating conditions


SN5406 SN7406
SN5416 SN7416 UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
’06 30 30
VOH High level output voltage
High-level V
’16 15 15
IOL Low-level output current 30 40 mA
TA Operating free-air temperature –55 125 0 70 °C

electrical characteristics over recommended operating free-air temperature range (unless


otherwise noted)
SN5406 SN7406
PARAMETER TEST CONDITIONS† SN5416 SN7416 UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
VIK VCC = MIN, II = –12 mA –1.5 –1.5 V
IOH VCC = MIN, VIL = 0.8 V, VOH = § 0.25 0.25 mA
IOL = 16 mA 0.4 0.4
VOL VCC = MIN
MIN, VIH = 2 V V
IOL = ¶ 0.7 0.7
II VCC = MAX, VI = 5.5 V 1 1 mA
IIH VCC = MAX, VIH = 2.4 V 40 40 µA
IIL VCC = MAX, VIL = 0.4 V –1.6 –1.6 mA
ICCH VCC = MAX 30 48 30 48 mA
ICCL VCC = MAX 32 51 32 51 mA
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ VOH = 30 V for ’06 and 15 V for ’16.
¶ IOL = 30 mA for SN54’ and 40 mA for SN74’.

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)


FROM TO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH 10 15
A Y RL = 110 Ω
Ω, CL = 15 pF ns
tPHL 15 23

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3


SN5406, SN5416, SN7406, SN7416
HEX INVERTER BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
SDLS031A – DECEMBER 1983 – REVISED DECEMBER 2001

PARAMETER MEASUREMENT INFORMATION


VCC

RL
From Output
Test Point
Under Test
CL
(see Note A)

LOAD CIRCUIT

3V
Input 1.5 V 1.5 V
0V
tPLH tPHL
VOH
High-Level In-Phase
1.5 V 1.5 V 1.5 V 1.5 V
Pulse Output
VOL
tw tPHL tPLH

Low-Level VOH
Out-of-Phase
Pulse 1.5 V 1.5 V 1.5 V 1.5 V
Output
VOL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE WIDTHS PROPAGATION DELAY TIMES

NOTES: A. CL includes probe and jig capacitance.


B. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 7 ns, tf ≤ 7 ns.
D. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


PACKAGE OPTION ADDENDUM

www.ti.com 1-May-2025

PACKAGING INFORMATION

Orderable Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
part number (1) (2) (3) Ball material Peak reflow (6)
(4) (5)

JM38510/00801BCA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/
00801BCA
JM38510/00801BDA Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/
00801BDA
SN5406J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN5406J
SN5416J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN5416J
SN7406D Obsolete Production SOIC (D) | 14 - - Call TI Call TI 0 to 70 7406
SN7406DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU | NIPDAU Level-1-260C-UNLIM 0 to 70 7406
SN7406DRE4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 7406
SN7406DRG4 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU | NIPDAU Level-1-260C-UNLIM 0 to 70 7406
SN7406N Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 SN7406N
SN7406NSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 SN7406
SN7416D Obsolete Production SOIC (D) | 14 - - Call TI Call TI 0 to 70 7416
SN7416DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 7416
SN7416N Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU | NIPDAU N/A for Pkg Type 0 to 70 SN7416N
SN7416NSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 SN7416
SNJ5406FK Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ5406FK
SNJ5406J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ5406J
SNJ5406W Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ5406W
SNJ5416J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ5416J
SNJ5416W Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ5416W

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without
limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available
for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 1-May-2025

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the
finish value exceeds the maximum column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per
JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the
previous line and the two combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN5406, SN5416, SN7406, SN7416 :

• Catalog : SN7406, SN7416


• Military : SN5406, SN5416

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product


• Military - QML certified for Military and Defense Applications

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS


K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)


QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN7406DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN7406DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN7406DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN7406NSR SOP NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN7416DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN7416NSR SOP NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN7406DR SOIC D 14 2500 353.0 353.0 32.0
SN7406DRG4 SOIC D 14 2500 353.0 353.0 32.0
SN7406DRG4 SOIC D 14 2500 356.0 356.0 35.0
SN7406NSR SOP NS 14 2000 356.0 356.0 35.0
SN7416DR SOIC D 14 2500 356.0 356.0 35.0
SN7416NSR SOP NS 14 2000 356.0 356.0 35.0

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal


Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
JM38510/00801BDA W CFP 14 25 506.98 26.16 6220 NA
M38510/00801BDA W CFP 14 25 506.98 26.16 6220 NA
SN7406N N PDIP 14 25 506 13.97 11230 4.32
SN7406N N PDIP 14 25 506 13.97 11230 4.32
SN7406NE4 N PDIP 14 25 506 13.97 11230 4.32
SN7406NE4 N PDIP 14 25 506 13.97 11230 4.32
SN7416N N PDIP 14 25 506 13.97 11230 4.32
SN7416N N PDIP 14 25 506 13.97 11230 4.32
SNJ5406FK FK LCCC 20 55 506.98 12.06 2030 NA
SNJ5406W W CFP 14 25 506.98 26.16 6220 NA
SNJ5416W W CFP 14 25 506.98 26.16 6220 NA

Pack Materials-Page 3
PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1

8.75 2X
8.55 7.62
NOTE 3

7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE

0.25
0 -8 1.27 0.10
0.40

DETAIL A
TYPICAL

4220718/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.

www.ti.com
EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM


1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(R0.05)
TYP
(5.4)

LAND PATTERN EXAMPLE


SCALE:8X

SOLDER MASK METAL UNDER SOLDER MASK


METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN


ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK


DEFINED DEFINED

SOLDER MASK DETAILS

4220718/A 09/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.


7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(5.4)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4220718/A 09/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN


(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP


[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE


[0.38]

0 -15 14X .008-.014


TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE


NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)


[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX


(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
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