Name: Mukesh sah

Usn: 1EW21EE013

Can_id: CAN_33840330

College Name: East West institute of technology

Department: Electrical and Electronic Engineering

Date of Submission: 13/03/2025

Project: Design of an 8-bit Subtractor using Verilog/SystemVerilog/VHDL

Introduction
This report presents the RTL design and functional verification of an 8-bit Subtractor using
Verilog. The 8-Bit Subtractor is a digital circuit designed to perform subtraction on two 8-bit
inputs (A and B). It uses two's complement arithmetic to compute the difference (Diff) and
provides a borrow output (Borrow_out) to indicate unsigned overflow. This module is
essential for arithmetic operations in processors, ALUs, and other digital systems. Its
efficient design ensures accurate and reliable subtraction. The implementation was verified
using EDA Playground with Aldec Riviera-PRO simulator.

Truth table of 8-bit Subtractor

Below is the truth table for the 8-bit Subtractor:

Design Architecture
The architecture consists of two 8-bit inputs (A and B) and an optional borrow input
(Borrow_in). The subtrahend (B) is negated using two's complement (~B + 1). The
difference is computed by adding the minuend (A) and the negated subtrahend (B_comp). A
9-bit sum captures the borrow, and the final outputs are the 8-bit difference (Diff) and the
borrow flag (Borrow_out).

Block Diagram
Below is the block diagram of the 8-bit Subtractor:

RTL Code

`timescale 1ns / 1ps

module subtractor_8bit(
input [7:0] A, // 8-bit Minuend
input [7:0] B, // 8-bit Subtrahend
input Borrow_in, // Initial borrow (optional, usually 0)
output [7:0] Diff, // 8-bit Difference
output Borrow_out // Borrow output
);
wire [7:0] B_comp; // Two's complement of B
wire [8:0] Sum; // 9-bit sum to capture borrow

// Two's complement: B' = ~B + 1

assign B_comp = ~B + 1'b1; // Negating B

// Perform A - B using addition

assign Sum = {1'b0, A} + {1'b0, B_comp} + Borrow_in;

// Assign outputs
assign Diff = Sum[7:0];
assign Borrow_out = ~Sum[8]; // Borrow occurs when MSB is 0 (unsigned overflow)

endmodule
Testbench Code

`timescale 1ns / 1ps

module tb_subtractor_8bit;

// Inputs
reg [7:0] A;
reg [7:0] B;
reg Borrow_in;

// Outputs
wire [7:0] Diff;
wire Borrow_out;

// Instantiate the Unit Under Test (UUT)

subtractor_8bit uut (
.A(A),
.B(B),
.Borrow_in(Borrow_in),
.Diff(Diff),
.Borrow_out(Borrow_out)
);

// Testbench logic
initial begin
// Initialize inputs
A = 8'b00000000;
B = 8'b00000000;
Borrow_in = 0;

// Wait for global reset

#10;

// Test case 1: Simple subtraction (15 - 3)

A = 8'b00001111; // 15
B = 8'b00000011; // 3
Borrow_in = 0;
#10;
$display("Test Case 1: A = %b, B = %b, Borrow_in = %b, Diff = %b, Borrow_out = %b",
A, B, Borrow_in, Diff, Borrow_out);

// Test case 2: Subtraction with borrow (10 - 15)

 A = 8'b00001010; // 10
B = 8'b00001111; // 15
Borrow_in = 0;
#10;
$display("Test Case 2: A = %b, B = %b, Borrow_in = %b, Diff = %b, Borrow_out = %b",
A, B, Borrow_in, Diff, Borrow_out);

// Test case 3: Subtraction with initial borrow (20 - 10 + 1)

A = 8'b00010100; // 20
B = 8'b00001010; // 10
Borrow_in = 1;
#10;
$display("Test Case 3: A = %b, B = %b, Borrow_in = %b, Diff = %b, Borrow_out = %b",
A, B, Borrow_in, Diff, Borrow_out);

// Test case 4: Edge case (255 - 255)

A = 8'b11111111; // 255
B = 8'b11111111; // 255
Borrow_in = 0;
#10;
$display("Test Case 4: A = %b, B = %b, Borrow_in = %b, Diff = %b, Borrow_out = %b",
A, B, Borrow_in, Diff, Borrow_out);

// Test case 5: Edge case (0 - 1)

A = 8'b00000000; // 0
B = 8'b00000001; // 1
Borrow_in = 0;
#10;
$display("Test Case 5: A = %b, B = %b, Borrow_in = %b, Diff = %b, Borrow_out = %b",
A, B, Borrow_in, Diff, Borrow_out);

// Test case 6: Edge case (128 - 127)

A = 8'b10000000; // 128
B = 8'b01111111; // 127
Borrow_in = 0;
#10;
$display("Test Case 6: A = %b, B = %b, Borrow_in = %b, Diff = %b, Borrow_out = %b",
A, B, Borrow_in, Diff, Borrow_out);

// End simulation
$finish;
end
endmodule

Simulation & Verification

Testbench Setup:

Inputs and Outputs:

A is the 8-bit minuend.

B is the 8-bit subtrahend.

Borrow_in is the initial borrow (usually 0).

Diff is the 8-bit difference.

Borrow_out is the borrow output.

Simulation Results
Expected Output:

Test Case 1: A = 00001111, B = 00000011, Borrow_in = 0, Diff = 00001100, Borrow_out = 1

Test Case 2: A = 00001010, B = 00001111, Borrow_in = 0, Diff = 11111011, Borrow_out = 0
Test Case 3: A = 00010100, B = 00001010, Borrow_in = 1, Diff = 00001011, Borrow_out = 1
Test Case 4: A = 11111111, B = 11111111, Borrow_in = 0, Diff = 00000000, Borrow_out = 1
Test Case 5: A = 00000000, B = 00000001, Borrow_in = 0, Diff = 11111111, Borrow_out = 0
Test Case 6: A = 10000000, B = 01111111, Borrow_in = 0, Diff = 00000001, Borrow_out = 1

Simulated Input-Output Waveforms

Below are the simulated input-output waveforms:

Results and Discussion

The 8-bit Subtractor was successfully implemented and verified. The simulation results
matched the expected behavior, confirming the correctness of the design.

Evaluation Criteria for Block-Level Verification in UVM

Testbench Architecture (50%)
- Proper use of UVM components

- Adherence to the UVM factory and configuration mechanism.

- Proper use of virtual sequences and sequence layering if applicable.

Driver

class subtractor_8bit_driver extends uvm_driver #(subtractor_8bit_sequence_item);

`uvm_component_utils(subtractor_8bit_driver)
virtual subtractor_8bit_if vif;
subtractor_8bit_sequence_item item;

function new(string name = "subtractor_8bit_driver", uvm_component parent);

super.new(name, parent);
`uvm_info("subtractor_8bit_driver", "Inside constructor of subtractor_8bit_driver",
UVM_HIGH)
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
 `uvm_info(get_name(), "Inside build phase", UVM_HIGH)

if (!(uvm_config_db #(virtual subtractor_8bit_if)::get(this, "*", "subtractor_8bit_vif", vif)))

`uvm_error(get_name(), "Failed to get Virtual IF from database")
endfunction: build_phase

task run_phase(uvm_phase phase);

super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)

forever begin
this.item = uvm_object_registry#(subtractor_8bit_sequence_item,
"subtractor_8bit_sequence_item")::create("item");
seq_item_port.get_next_item(item);
drive(item);
seq_item_port.item_done();
end
endtask

task drive(subtractor_8bit_sequence_item item);

`uvm_info(get_name(), "Drive...", UVM_HIGH)
@(posedge vif.i_clk);
#5;
vif.A = item.A;
vif.B = item.B;
vif.Borrow_in = item.Borrow_in;
endtask
endclass: subtractor_8bit_driver

Monitor

class subtractor_8bit_monitor extends uvm_monitor;

`uvm_component_utils(subtractor_8bit_monitor)
virtual subtractor_8bit_if vif;
subtractor_8bit_sequence_item item;

uvm_analysis_port #(subtractor_8bit_sequence_item) mon_port;

function new(string name = "subtractor_8bit_monitor", uvm_component parent);

super.new(name, parent);
`uvm_info("subtractor_8bit_monitor", "Inside constructor of subtractor_8bit_monitor",
UVM_HIGH)
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)

mon_port = new("mon_port", this);

if (!(uvm_config_db #(virtual subtractor_8bit_if)::get(this, "*", "subtractor_8bit_vif", vif)))

`uvm_error(get_name(), "Failed to get Virtual IF from database")
endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)
forever begin
this.item = uvm_object_registry#(subtractor_8bit_sequence_item,
"subtractor_8bit_sequence_item")::create("item");
sample(item);
`uvm_info(get_name(), "Item received!!", UVM_HIGH)
mon_port.write(item);
end
endtask

task sample(subtractor_8bit_sequence_item item);

#5;
item.A = vif.A;
item.B = vif.B;
item.Borrow_in = vif.Borrow_in;
item.Diff = vif.Diff;
item.Borrow_out = vif.Borrow_out;
endtask
endclass: subtractor_8bit_monitor

Agent

class subtractor_8bit_agent extends uvm_agent;

 `uvm_component_utils(subtractor_8bit_agent)
subtractor_8bit_driver drv;
subtractor_8bit_monitor mon;
subtractor_8bit_sequencer seqr;

function new(string name="subtractor_8bit_agent",uvm_component parent);

super.new(name,parent);
`uvm_info("subtractor_8bit_agent", "Inside constructor of subtractor_8bit_agent",
UVM_HIGH)
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)

drv=subtractor_8bit_driver::type_id::create("drv",this);
mon=subtractor_8bit_monitor::type_id::create("mon",this);
seqr=subtractor_8bit_sequencer::type_id::create("seqr",this);

endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
drv.seq_item_port.connect(seqr.seq_item_export);
endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)
endtask

endclass: subtractor_8bit_agent

Environment

class subtractor_8bit_env extends uvm_env;

`uvm_component_utils(subtractor_8bit_env)

subtractor_8bit_agent agent;
subtractor_8bit_scoreboard scb;
// subtractor_8bit_coverage cov_subscriber; // Declare the coverage subscriber
 function new(string name = "subtractor_8bit_env", uvm_component parent = null);
super.new(name, parent);
`uvm_info("subtractor_8bit_env", "Inside constructor of subtractor_8bit_env",
UVM_HIGH)
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
agent = subtractor_8bit_agent::type_id::create("agent", this);
scb = subtractor_8bit_scoreboard::type_id::create("scb", this);
// cov_subscriber = subtractor_8bit_coverage::type_id::create("cov_subscriber", this); //
Instantiate the coverage subscriber
endfunction : build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
agent.mon.mon_port.connect(scb.scb_port);
// agent.mon.mon_port.connect(cov_subscriber.analysis_export); // Connect the
monitor to the coverage subscriber
endfunction : connect_phase

endclass : subtractor_8bit_env

Test

class subtractor_8bit_test extends uvm_test;

`uvm_component_utils(subtractor_8bit_test)

subtractor_8bit_env env;
// subtractor_8bit_main_seq main_seq;

function new(string name="subtractor_8bit_test",uvm_component parent);

super.new(name,parent);
`uvm_info("subtractor_8bit_test", "Inside constructor of subtractor_8bit_test",
UVM_HIGH)
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
 env=subtractor_8bit_env::type_id::create("env",this);
endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
endfunction
/*
task run_phase(uvm_phase phase);
super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)

phase.raise_objection(this);

// repeat(`TEST_COUNT) begin
// main_seq=subtractor_8bit_main_seq::type_id::create("main_seq");class
subtractor_8bit_test extends uvm_test;
`uvm_component_utils(subtractor_8bit_test)

subtractor_8bit_env env;
// subtractor_8bit_main_seq main_seq;

function new(string name="subtractor_8bit_test",uvm_component parent);

super.new(name,parent);
`uvm_info("subtractor_8bit_test", "Inside constructor of subtractor_8bit_test",
UVM_HIGH)
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
env=subtractor_8bit_env::type_id::create("env",this);
endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
endfunction
/*
task run_phase(uvm_phase phase);
super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)
 phase.raise_objection(this);

// repeat(`TEST_COUNT) begin
// main_seq=subtractor_8bit_main_seq::type_id::create("main_seq");
// main_seq.start(env.agent.seqr);
// end
wait(env.scb.test_cnt==`TEST_COUNT);

phase.drop_objection(this);

endtask
*/

endclass: subtractor_8bit_test

class subtractor_8bit_mul_test extends subtractor_8bit_test;

`uvm_component_utils(subtractor_8bit_mul_test)

// subtractor_8bit_env env;
subtractor_8bit_mul_seq mul_seq;

function new(string name="subtractor_8bit_mul_test",uvm_component parent);

super.new(name,parent);
`uvm_info("subtractor_8bit_mul_test", "Inside constructor of subtractor_8bit_mul_test",
UVM_HIGH)
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info(get_name(), "Inside build phase", UVM_HIGH)
// env=subtractor_8bit_env::type_id::create("env",this);
endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info(get_name(), "Inside connect phase", UVM_HIGH)
endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);
`uvm_info(get_name(), "Inside run phase", UVM_HIGH)

phase.raise_objection(this);
 repeat(`TEST_COUNT) begin
// forever begin
mul_seq=subtractor_8bit_mul_seq::type_id::create("mul_seq");
mul_seq.start(env.agent.seqr);
end
wait(env.scb.test_cnt==`TEST_COUNT);

phase.drop_objection(this);

endtask

endclass: subtractor_8bit_mul_test

Testbench

`include "uvm_macros.svh"
import uvm_pkg::*;

`define TEST_COUNT 200

`include "interface.sv"
`include "sequence_items.sv"
`include "sequencer.sv"
`include "sequence.sv"
`include "driver.sv"
`include "monitor.sv"
`include "scoreboard.sv"
`include "agent.sv"
`include "environment.sv"
`include "test.sv"
`timescale 1ns/1ns
`include "uvm_macros.svh"

module top;

// bit i_clk=0;
// bit i_rst;
 subtractor_8bit_if top_if();

subtractor_8bit dut(
.A (top_if. A),
.B (top_if.B),
.Borrow_in (top_if.Borrow_in),
.Diff (top_if.Diff),
.Borrow_out (top_if.Borrow_out)
);

// initial forever #0.5 i_clk =~i_clk;

initial begin
// i_rst = 1;
// #2 i_rst =0;
end

initial begin
uvm_config_db #(virtual subtractor_8bit_if) :: set(null,"*","subtractor_8bit_vif",top_if);
`uvm_info("TOP","Configured database for interface...",UVM_LOW)
end

initial begin
run_test("subtractor_8bit_test");
end

initial begin
$dumpfile("waveform.vcd");
$dumpvars;
end

initial begin
#10000000;
$finish();
end
endmodule
// TODO: Receiving items from monitor in scoreboard

Stimulus Generation
- Development of constrained-random and directed test sequences.
- Use of UVM sequences and transaction-based stimulus generation.

- Ability to generate different corner cases and invalid scenarios.

- Parameterization and reuse of sequences.

Sequence Item

class subtractor_8bit_sequence_item extends uvm_sequence_item;

// rand logic rst;

// randc logic [31:0] A;

// randc logic [31:0] B;
// logic [31:0] result;
// logic exception;
// logic overflow;
// logic underflow;
// logic done;

// randc logic [2:0] A; // 8-bit input data

// randc logic [2:0] shift_amount; // Shift amount (0 to 7)
// randc logic shift_direction; // Shift direction (0: left, 1: right)
// logic [7:0] data_out ; // 8-bit shifted output
//logic [7:0] Y ; // 8-bit shifted output
// `uvm_object_utils (subtractor_8bit_sequence_item)

// randc logic [7:0] D0, D1, D2, D3, D4, D5, D6, D7; // 8-bit inputs
// randc logic [2:0] S; // 3-bit select
// logic [7:0] Y ; // 8-bit output
// randc logic i_up_down; // Control signal: 1 for UP, 0 for DOWN
// logic [3:0] o_count ; // Parameterized width counter output

randc logic [7:0] A; // 8-bit Minuend

randc logic [7:0] B; // 8-bit Subtrahend
randc logic Borrow_in; // Initial borrow (optional, usually 0)
logic [7:0] Diff; // 8-bit Difference
logic Borrow_out; // Borrow output

function new(string name="subtractor_8bit_sequence_item");

super.new(name);
endfunction
/*
module subtractor_8bit(
input [7:0] A, // 8-bit Minuend
input [7:0] B, // 8-bit Subtrahend
input Borrow_in, // Initial borrow (optional, usually 0)
output [7:0] Diff, // 8-bit Difference
output Borrow_out // Borrow output
);

module shifter_8bit (
input [7:0] data_in, // 8-bit input data
input [2:0] shift_amount, // Shift amount (0 to 7)
input shift_direction, // Shift direction (0: left, 1: right)
output [7:0] data_out // 8-bit shifted output
);
reg [7:0] shifted_data; // Temporary register to hold shifted data
*/
//`uvm_object_utils_begin(subtractor_8bit_sequence_item)
// `uvm_field_int(A, UVM_ALL_ON)
// `uvm_field_int(B, UVM_ALL_ON)
// `uvm_field_int(result, UVM_ALL_ON)
// `uvm_object_utils_end

// input [2:0] A, // 3-bit input

// output reg [7:0] Y // 8-bit output (one-hot encoding)

endclass

Sequence

class subtractor_8bit_base_sequence extends uvm_sequence;

`uvm_object_utils(subtractor_8bit_base_sequence)
subtractor_8bit_sequence_item subtractor_8bit_item;

function new(string name = "subtractor_8bit_sequence");

super.new(name);
endfunction
endclass: subtractor_8bit_base_sequence

class subtractor_8bit_mul_seq extends subtractor_8bit_base_sequence;

`uvm_object_utils(subtractor_8bit_mul_seq)
subtractor_8bit_sequence_item item;
 function new(string name = "subtractor_8bit_mul_seq");
super.new(name);
endfunction

task body();
`uvm_info(get_name(), "Running main sequence...", UVM_HIGH);
this.item = uvm_object_registry#(subtractor_8bit_sequence_item,
"subtractor_8bit_sequence_item")::create("item");
start_item(item);
item.randomize();
finish_item(item);
endtask
endclass

Scoreboarding and Checking

- Implementation of functional and self-checking scoreboard.

- Use of predictive models and golden reference comparison.

- Effective use of UVM phases for checking.

Scoreboard

class subtractor_8bit_scoreboard extends uvm_scoreboard;

`uvm_component_utils(subtractor_8bit_scoreboard)

uvm_analysis_imp #(subtractor_8bit_sequence_item, subtractor_8bit_scoreboard)

scb_port;

subtractor_8bit_sequence_item item[$];
subtractor_8bit_sequence_item s_item;
int test_cnt = 0;
int test_valid = 0;
int test_invalid = 0;

virtual subtractor_8bit_if vif;

function new(string name = "subtractor_8bit_scoreboard", uvm_component parent);

super.new(name, parent);
`uvm_info("SCB_CLASS", "Inside Constructor!", UVM_HIGH)
if (!(uvm_config_db #(virtual subtractor_8bit_if)::get(this, "*", "subtractor_8bit_vif", vif)))
 `uvm_error(get_name(), "Failed to get Virtual IF from database")
endfunction: new

function void build_phase(uvm_phase phase);

super.build_phase(phase);
`uvm_info("SCB_CLASS", "Build Phase!", UVM_HIGH)
scb_port = new("scb_port", this);
endfunction: build_phase

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
`uvm_info("SCB_CLASS", "Connect Phase!", UVM_HIGH)
endfunction: connect_phase

function void write(subtractor_8bit_sequence_item rx_item);

item.push_front(rx_item);
endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);
forever begin
this.s_item = uvm_object_registry#(subtractor_8bit_sequence_item,
"subtractor_8bit_sequence_item")::create("s_item");
wait((item.size() != 0));
s_item = item.pop_front();
// s_item.print();
compare(s_item);
test_cnt++;
end
endtask

function void compare(subtractor_8bit_sequence_item item);

logic [7:0] ex_res;
logic ex_borrow;

subtractor_8bit_ref(
item.A, // 8-bit Minuend
item.B, // 8-bit Subtrahend
item.Borrow_in, // Initial Borrow
ex_res, // 8-bit Difference
ex_borrow // Borrow Output
);
 if ((ex_res == item.Diff) && (ex_borrow == item.Borrow_out)) begin
`uvm_info(get_name, $sformatf("[%0d/%0d] Test Passed", test_cnt, `TEST_COUNT),
UVM_HIGH);
test_analysis(item, ex_res, ex_borrow, 1);
test_valid++;
end else begin
`uvm_error(get_name, $sformatf("[%0d/%0d] Test failed", test_cnt, `TEST_COUNT));
test_analysis(item, ex_res, ex_borrow, 1);
test_invalid++;
end
endfunction

function void test_analysis(subtractor_8bit_sequence_item item, logic [7:0] ex_res, logic

ex_borrow, bit flag);
if (flag) begin
$display("--------------------------------------------------------------------------------");
$display("A = %0b, B = %0b, Borrow_in = %0b,
Diff = %0b, ex_res = %0b,
Borrow_out = %0b, ex_borrow = %0b,", item.A, item.B, item.Borrow_in, item.Diff, ex_res,
item.Borrow_out, ex_borrow);
end
endfunction

function automatic void subtractor_8bit_ref(

input logic [7:0] A, // 8-bit Minuend
input logic [7:0] B, // 8-bit Subtrahend
input logic Borrow_in, // Initial Borrow
output logic [7:0] Diff, // 8-bit Difference
output logic Borrow_out // Borrow Output
);
logic [8:0] Sum; // 9-bit sum to track borrow
logic [7:0] B_comp; // Two's complement of B

// Compute two's complement of B

B_comp = ~B + 1'b1;

// Perform subtraction using addition

Sum = {1'b0, A} + {1'b0, B_comp} + Borrow_in;

// Assign outputs
Diff = Sum[7:0];
Borrow_out = ~Sum[8]; // Borrow occurs when MSB is 0 (unsigned overflow)
endfunction
 function void report_phase(uvm_phase phase);
super.report_phase(phase);
`uvm_info(get_name, $sformatf("Total tests: %0d", test_cnt), UVM_LOW)
`uvm_info(get_name, $sformatf("Passed tests: %0d", test_valid), UVM_LOW)
`uvm_info(get_name, $sformatf("Failed tests: %0d", (test_invalid / test_cnt) * 100),
UVM_LOW)
endfunction
endclass

Debugging and Logs

- Effective use of UVM messaging and verbosity levels.

- Debugging skills and ability to interpret waveforms and logs.

- Error detection.

- Documentation of issues and resolutions.

Waveform (In Testbench)

initial begin
$dumpfile("dump.vcd");
$dumpvars();
end

UVM Report

Code Quality and Best Practices

- Consistency in naming conventions and coding style.

- Use of parameterized and reusable components.

- Proper comments and documentation within the code.

- Efficient and optimized coding practices.

EDA Link: https://edaplayground.com/x/D3AK

Generate GDS using OpenROAD tool

In this section, the layout of the RTL code has been generated using the OpenROAD software
tool.

Technology/Platform utilized: nangate45

Instructions of the config.mk

export DESIGN_NICKNAME = ripple_carry_adder_8bit

export DESIGN_NAME = ripple_carry_adder_8bit
export PLATFORM = gf180

export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$

(DESIGN_NICKNAME)/ripple_carry_adder_8bit.v))
export SDC_FILE =
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export CORE_UTILIZATION = 0.5

export PLACE_DENSITY = 0.1
export TNS_END_PERCENT = 100

Instructions of the constraint.sdc

current_design ripple_carry_adder_8bit
set clk_name v_clk
set clk_period 2.5
set clk_io_pct 0.2
create_clock -name $clk_name -period $clk_period

set non_clock_inputs [lsearch -inline -all -not [all_inputs]]

set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

Layout of the Design

Below is the layout of the 8-bit Subtractor:
Performance Analysis

Power Measurement:

Group Internal Switching Leakage Total

Power Power Power Power (Watts)
----------------------------------------------------------------
Sequential 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Combinational 7.97e-14 5.80e-14 5.80e-06 5.80e-06 100.0%
Clock 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 7.97e-14 5.80e-14 5.80e-06 5.80e-06 100.0%
0.0% 0.0% 100.0%

Area Measurement:
Design area 235 u^2 13% utilization.

Timing Information:

Startpoint: B[2] (input port)

Endpoint: Borrow_out (output port)
Path Group: unconstrained
Path Type: max

Delay Time Description

---------------------------------------------------------
0.00 0.00 v input external delay
 0.00 0.00 v B[2] (in)
0.03 0.03 v _149_/Z (BUF_X2)
0.11 0.14 v _151_/ZN (OR4_X2)
0.03 0.17 v _152_/Z (BUF_X8)
0.08 0.25 v _153_/ZN (OR3_X4)
0.06 0.31 v _214_/ZN (OR2_X1)
0.04 0.35 ^ _215_/ZN (AOI21_X1)
0.02 0.37 v _216_/ZN (NOR4_X2)
0.06 0.43 ^ _219_/ZN (AOI211_X2)
0.03 0.46 v _223_/ZN (OAI221_X1)
0.03 0.48 v output4/Z (BUF_X1)
0.00 0.48 v Borrow_out (out)
0.48 data arrival time
---------------------------------------------------------
(Path is unconstrained)

Clock frequency

Group Slack
--------------------------------------------

max slew

Pin Limit Slew Slack

------------------------------------------------------------
_187_/ZN 0.20 0.06 0.14 (MET)

max capacitance

Pin Limit Cap Slack

------------------------------------------------------------
_247_/ZN 10.47 1.65 8.82 (MET)

Generated GDS
Below is the generated GDS file:
Conclusions

In this report, the RTL code of 8-bit Subtractor has been designed in Verilog. The code is
successfully verified with the UVM with 100% test case pass. The design code is further
processed in the OpenROAD tool to generate its GDS using the nangate45 platform. There is
no setup and hold violations.