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Booth algorithm

The document describes the Booth algorithm implemented in Verilog for signed multiplication of two 8-bit numbers, producing a 16-bit product. It includes a module for the Booth multiplier, an ALU for addition and subtraction, and a test bench to validate the functionality with various test cases. The test bench initializes inputs and displays the product after each multiplication operation is completed.

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2 views4 pages

Booth algorithm

The document describes the Booth algorithm implemented in Verilog for signed multiplication of two 8-bit numbers, producing a 16-bit product. It includes a module for the Booth multiplier, an ALU for addition and subtraction, and a test bench to validate the functionality with various test cases. The test bench initializes inputs and displays the product after each multiplication operation is completed.

Uploaded by

prafullaenc
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Booth algorithm

module booth(prod, busy, mc, mp, clk, start);

output signed [15:0] prod;

output busy;

input signed [7:0] mc, mp;

input clk, start;

reg signed[7:0] A, Q, M;

reg Q_1;

reg [3:0] count;

wire signed [7:0] sum, difference;

always @(posedge clk)

begin

if (start) begin

A <= 8'b0;

M <= mc;

Q <= mp;

Q_1 <= 1'b0;

count <= 4'b0;

end

else begin

case ({Q[0], Q_1})

2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q};

2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q};

default: {A, Q, Q_1} <= {A[7], A, Q};

endcase
count <= count + 1'b1;

end

end

alu adder (sum, A, M, 1'b0);

alu subtracter (difference, A, ~M, 1'b1);

assign prod = {A, Q};

assign busy = (count < 8);

endmodule

//The following is an alu.

//It is an adder, but capable of subtraction:

//Recall that subtraction means adding the two's complement--

//a - b = a + (-b) = a + (inverted b + 1)

//The 1 will be coming in as cin (carry-in)

module alu(out, a, b, cin);

output signed[7:0] out;

input signed[7:0] a;

input signed[7:0] b;

input cin;

assign out = a + b + cin;

endmodule

Test Bench
module tbw_v;

reg signed [7:0] mc, mp;

reg clk, start;

wire signed [15:0] prod;


wire busy;

// Instantiate the booth multiplier module

booth uut (.prod(prod), .busy(busy), .mc(mc), .mp(mp), .clk(clk), .start(start));

// Clock generation

always #5 clk = ~clk;

initial begin

// Initialize signals

clk = 0;

start = 0;

mc = 0;

mp = 0;

// Apply test cases

#10 mc = 8'd7; mp = 8'd3; start = 1; // 7 * 3 = 21

#10 start = 0;

wait (!busy); // Wait for operation to complete

$display("Product: %d", prod);

#10 mc = -8'd4; mp = 8'd2; start = 1; // -4 * 2 = -8

#10 start = 0;
wait (!busy);

$display("Product: %d", prod);

#10 mc = -8'd6; mp = -8'd3; start = 1; // -6 * -3 = 18

#10 start = 0;

wait (!busy);

$display("Product: %d", prod);

#10 mc = 8'd15; mp = -8'd2; start = 1; // 15 * -2 = -30

#10 start = 0;

wait (!busy);

$display("Product: %d", prod);

#50 $finish;

end

endmodule

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