Booth algorithm
Booth algorithm
output busy;
reg signed[7:0] A, Q, M;
reg Q_1;
begin
if (start) begin
A <= 8'b0;
M <= mc;
Q <= mp;
end
else begin
endcase
count <= count + 1'b1;
end
end
endmodule
input signed[7:0] a;
input signed[7:0] b;
input cin;
endmodule
Test Bench
module tbw_v;
// Clock generation
initial begin
// Initialize signals
clk = 0;
start = 0;
mc = 0;
mp = 0;
#10 start = 0;
#10 start = 0;
wait (!busy);
#10 start = 0;
wait (!busy);
#10 start = 0;
wait (!busy);
#50 $finish;
end
endmodule