CASCADED H-BRIDGE FIVE LEVEL INVERTERS FOR

SINGLE PHASE APPLICATIONS

PROJECT REPORT

Submitted by

KRISHNAKANTH C TCR21EE080
KRISHNAPRIYA NG TCR21EE082
NANDINI SAJ P TCR21EE097
UDIT MAHESH TCR21EE127
SHERIN VI PKD21EE047

to
the APJ Abdul Kalam Technological University
in partial fulfillment of the requirements for the award of the Degree
of
Bachelor of Technology
in
Electrical and Electronics Engineering

Department of Electrical Engineering

Government Engineering College Thrissur
Thrissur - 680009
April 2025
 DECLARATION

We, hereby declare that the project report titled ” CASCADED H-BRIDGE FIVE
LEVEL INVERTERS FOR SINGLE PHASE APPLICATIONS ” submitted for
partial fulfillment of the requirements for the award of the degree of Bachelor of
Technology of the APJ Abdul Kalam Technological University, Kerala is a bonafide
work done by us under the supervision of Prof. Nevin Jacob K.
This submission represents our ideas in our own words, and where ideas or words
of others have been included, we have adequately and accurately cited and refer-
enced the sources. We also declare that we have adhered to the ethics of academic
honesty and integrity and have not misrepresented or fabricated any data, idea, fact,
or source in our submission.
We understand that any violation of the above will be a cause for disciplinary action
by the institute and/or the University and can also evoke penal action from sources
that have not been properly cited or from whom proper permission has not been
obtained. This report has not previously been used as the basis for the award of any
degree, diploma, or similar title at any other university.

Name of student : KRISHNAPRIYA NG Name of student : UDIT MAHESH

Signature of student : .................................... Signature of student : ....................................
Name of student : KRISHNAKANTH C Name of student : SHERIN VI
Signature of student : .................................... Signature of student : ....................................
Name of student : NANDINI SAJ P
Signature of student : ....................................

Place : Thrissur
Date : April 2025

2
 DEPARTMENT OF ELECTRICAL ENGINEERING
Government Engineering College Thrissur
Thrissur
680009

CERTIFICATE

This is to certify that the report entitled ” CASCADED H-BRIDGE FIVE LEVEL
INVERTERS FOR SINGLE PHASE APPLICATIONS ”submitted by
KRISHNAKANTH C (TCR21EE080) , KRISHNAPRIYA NG (TCR21EE082)
NANDINI SAJ P (TCR21EE097) , UDIT MAHESH (TCR21EE127) , SHERIN
VI ( PKD21EE047 ) to the APJ Abdul Kalam Technological University in partial
fulfillment of the requirements for the award of the Degree of Bachelor of Tech-
nology in Electrical and Electronics Engineering is a bonafide record of the project
work carried out by him/her under my/our guidance and supervision. This report
in any form has not been submitted to any other University or Institute for any
purpose.

Internal Supervisor Project Coordinator

Name : Prof. Nevin Jacob K Name : Prof. Dr. Lalgy Gopi
Signature : ................................... Signature : ................................

Project Coordinator Head of Department

Name : Prof. Dr. Jaison Mathew Name : Prof. Dr. Manju B
Signature : ............................. Signature : ...................................
 ACKNOWLEDGMENT

We wish to record our indebtedness and thankfulness to all who helped us prepare
this project report titled ” CASCADED H-BRIDGE FIVE LEVEL INVERTERS
FOR SINGLE PHASE APPLICATIONS ” and present it satisfactorily.
We are especially thankful to our guide and supervisor Prof. Nevin Jacob K in
the Department of Electrical Engineering for giving us valuable suggestions and
critical inputs in the preparation of this report. We would like to extend our sincere
gratitude to Prof. Dr. Lalgy Gopi and Prof. Dr. Jaison Mathew for the invaluable
support and guidance. We are also grateful to Prof. Dr. Manju B, the head of the
Department of Electrical Engineering for encouragement.
Our classmates have always been helpful, and we are grateful to them for patiently
listening to our presentations on the work related to the project.

KRISHNAKANTH C
KRISHNAPRIYA NG
UDIT MAHESH
NANDINI SAJ P
SHERIN VI
B. Tech. (Electrical and Electronics Engineering)
Department of Electrical Engineering
Government Engineering College Thrissur

i
 ABSTRACT

Multilevel inverters are designed to produce desired output voltages from different
DC sources. This includes high quality output voltage, reduction of voltage stress
on the switches, low common mode voltages, better harmonic content and reduction
in total harmonic distortion.
This project focuses on the simulation and hardware implementation of an 8-switch
five-level cascaded H-bridge (CHB) inverter for single-phase applications. The sys-
tem is designed to operate with resistive (R) and resistive-inductive (RL) loads, en-
suring its feasibility for practical applications such as renewable energy integration
and motor drives.
The simulation studies were conducted for both 6-switch and 8-switch CHB inverter
configurations, analyzing their performance in terms of output voltage quality, and
efficiency. Based on the findings, the hardware implementation is focused on the 8-
switch topology, which provides a balance between reduced component count and
improved output waveform quality.
This work contributes to the ongoing research in multilevel inverters by optimiz-
ing the switching strategy and circuit topology for efficient power conversion, with
potential applications in renewable energy systems and industrial drives.

ii
 CONTENTS

ACKNOWLEDGMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . i
ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Chapter 1.. .INTRODUCTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.5 Outline Of The Report . . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 2.. .LITERATURE
. . . . . . . . SURVEY
. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 3.. .METHODOLOGY
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Introduction to Multilevel Inverters . . . . . . . . . . . . . . . . 8
3.2 Selected Topology:Cascaded H-bridge Inverter . . . . . . . . . 9
3.2.1 Five Level Cascaded H-Bridge (CHB) inverter . . . . . . . . 10
3.3 PWM Control Strategy for 5-Level Cascaded H-Bridge Multi-
level Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.1 Sinusoidal Level-Shifted PWM (SPWM) for 8-Switch 5-Level
CHB-MLI: . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.2 Sinusoidal Level-Shifted PWM (LSPWM) for 6-Switch Re-
duced 5-Level CHB-MLI: . . . . . . . . . . . . . . . . . . . 12
Chapter 4.. .8-SWITCH
. . . . . . FIVE-LEVEL
. . . . . . . . CHB
. . . INVERTER
. . . . . . . . . . . . . . . . . 13
4.1 Introduction To Conventional 8 Switch Five Level Cascaded H
Bridge Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Working Of 8 Switch Five Level Cascaded H Bridge Inverter . . 13

iii
Chapter 5.. .6-SWITCH
. . . . . . FIVE-LEVEL
. . . . . . . . CHB
. . . INVERTER
. . . . . . . . . . . . . . . . . 16
5.1 Introduction To Six Switch Five Level Cascaded-H Bridge Inverter 16
5.2 Switching Sequence Of Six Switch Five Level Cascaded-H Bridge
Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 6.. .SIMULATION
. . . . . . . . STUDIES
. . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 Simulation Analysis Of Eight Switch Five Level Cascaded H-
Bridge (CHB) multilevel inverters . . . . . . . . . . . . . . . . 19
6.1.1 Simulation Diagram . . . . . . . . . . . . . . . . . . . . . . 19
6.1.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 Simulation Analysis Of Six Switch Five Level Cascaded H-Bridge
(CHB) multilevel inverters . . . . . . . . . . . . . . . . . . . . 22
6.2.1 Simulation Diagram . . . . . . . . . . . . . . . . . . . . . . 22
6.2.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 7.. .HARDWARE
. . . . . . . IMPLEMENTATION
. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2 Components And Specifications . . . . . . . . . . . . . . . . . 26
7.2.1 230V/9V Transformer . . . . . . . . . . . . . . . . . . . . . 26
7.2.2 Bridge Rectifier IC (DB107) . . . . . . . . . . . . . . . . . . 28
7.2.3 IRF840 N Chanel MOSFET . . . . . . . . . . . . . . . . . . 28
7.2.4 TLP250H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2.5 FD2103S . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2.6 DSPIC30F2010 . . . . . . . . . . . . . . . . . . . . . . . . 32
7.3 Algorithm of PWM Generation . . . . . . . . . . . . . . . . . . 33
7.4 Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5 Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.6 Hardware Result . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 8.. .CONCLUSIONS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2 Future Scope For Futher Developments : . . . . . . . . . . . . . 44
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

iv
 LIST OF TABLES

4.1 Switching sequence for 8 switch MLI . . . . . . . . . . . . . . . . 14

5.1 Switching Sequence Of Six Switch Five Level Cascaded-H Bridge

Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

v
 LIST OF FIGURES

3.1 Structure of Cascaded H-Bridge (CHB) inverter with Five levels . . 10

4.1 Circuit diagram of 8 Switch Five Level Cascaded H Bridge Inverter 14

4.4 Current path for -Vdc . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 Current path for -2Vdc . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Current path for +2Vdc . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Current path for +Vdc . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 Six Switch CHB MLI topology . . . . . . . . . . . . . . . . . . . . 17

5.2 Circuit diagram for various voltage levels . . . . . . . . . . . . . . 18

6.1 Block diagram for Eight switch cascaded H bridge five level in-
verter with R load . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Block diagram for Eight switch cascaded H bridge five level in-
verter with RL load . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 Gate pulses for 8-switch MLI using Sine PWM . . . . . . . . . . . 20
6.4 Voltage and Current Waveform when RL Load is connected . . . . 21
6.5 Voltage and Current Waveform when R Load is connected . . . . . 21
6.6 6 switch model for R load . . . . . . . . . . . . . . . . . . . . . . . 22
6.7 6 switch model for RL load . . . . . . . . . . . . . . . . . . . . . . 22
6.8 6 switch model for R load . . . . . . . . . . . . . . . . . . . . . . . 23
6.9 Output current waveform when RL load is connected . . . . . . . . 23
6.10 Output voltage waveform when RL load is connected . . . . . . . . 24
6.11 Voltage across each switches when RL Load is connected . . . . . . 24
6.12 Current across each switches when RL load is connected . . . . . . 25

7.1 230V/9V Four winding Transformer . . . . . . . . . . . . . . . . . 26

7.2 Bridge Rectifier Circuit . . . . . . . . . . . . . . . . . . . . . . . . 28

vi
7.3 IRF840 N Channel MOSFET . . . . . . . . . . . . . . . . . . . . . 29
7.4 TLP250H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.5 FD2103S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.6 DSPIC30F2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.7 Circuit diagram of Hardware Implementation . . . . . . . . . . . . 38
7.8 Hardware setup for R load . . . . . . . . . . . . . . . . . . . . . . 40
7.9 Hardware setup for RL load . . . . . . . . . . . . . . . . . . . . . 40
7.10 Output for R load . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.11 Output for RL load . . . . . . . . . . . . . . . . . . . . . . . . . . 41

vii
 Chapter 1

INTRODUCTION

1.1 BACKGROUND

The advancement of power electronic systems has significantly contributed to the

development of efficient and reliable energy conversion technologies. Inverters play
a crucial role in converting direct current (DC) into alternating current (AC) for var-
ious applications, including renewable energy integration, industrial automation,
and power distribution systems. Among different inverter topologies, multilevel in-
verters have gained prominence due to their ability to generate high-quality output
waveforms, reducing voltage stress on power devices and enhancing overall perfor-
mance.
This report investigates the conventional 8 switch 5-Level Cascaded H-Bridge In-
verter for single-phase applications, with a primary focus on analyzing voltage
waveforms, current waveforms, and switching behavior. The cascaded H-bridge
configuration enables multiple voltage levels, resulting in improved waveform qual-
ity and reduced harmonic content. This characteristic makes it well-suited for ap-
plications requiring stable and controlled AC power output.
This study provides a comprehensive understanding of switching characteristics,
voltage and current waveform behaviour, and system operation in cascaded mul-
tilevel inverters for single-phase applications. The findings contribute to the opti-
mization of inverter designs for enhanced performance in power conversion appli-
cations, particularly in renewable energy systems and industrial power control.
1.2 MOTIVATION

The rapid advancements in power electronics have led to an increasing demand

for efficient, high-performance inverter topologies. Traditional two-level inverters,
while widely used, face challenges such as high switching losses, increased volt-
age stress on semiconductor devices, and poor waveform quality. To overcome
these limitations, multilevel inverters, particularly cascaded H-bridge configura-
tions, have gained attention due to their ability to generate stepped waveforms that
closely resemble sinusoidal AC output.
This project focuses on the 8-Switch Conventional 5-Level Cascaded H-Bridge In-
verter for single-phase applications, with a key objective of analyzing voltage and
current waveforms, as well as switching behavior. The motivation behind this work
stems from several critical factors:

• Enhanced Output Waveform Quality:Multilevel inverters produce output

voltages with lower harmonic distortion, reducing the need for additional fil-
tering and improving power quality.

• Optimized Switching Performance: Understanding and refining the switch-

ing behavior in an 8-switch cascaded inverter helps minimize switching stress
and improve operational efficiency.

• Application in Renewable Energy Systems: Multilevel inverters are ex-

tensively used in solar and wind energy conversion, where high-quality AC
output is essential for grid integration and standalone applications.

• Scalability and Modularity: The 8-switch topology offers greater flexibility

and adaptability to different voltage and power levels, making it suitable for
a wide range of power conversion applications.

2
Unlike conventional studies that emphasize total harmonic distortion (THD), losses,
or efficiency, this project prioritizes the analysis of switching behaviour, voltage
waveforms, and current waveforms. By combining simulation and hardware imple-
mentation, this research bridges the gap between theoretical modeling and practical
application, contributing to the advancement of multilevel inverter technology for
modern power conversion systems.

1.3 OBJECTIVES

• To perform simulation-based analysis of load voltage and current waveforms

for R and RL loads in the given inverter topology.

• To investigate the switching behaviour of the inverter and its impact on wave-
form characteristics.

• To implement a hardware prototype integrating DSPIC30F2010 for PWM

control and TLP250H gate drivers for power stage isolation.

• To compare simulation and experimental results for validating the inverter’s

operational performance and waveform fidelity

1.4 PROBLEM STATEMENT

Conventional inverters face challenges like high switching losses and poor wave-
form quality. This project focuses on designing, simulating, and implementing an
8-Switch Conventional 5-Level Cascaded H-Bridge Inverter for single-phase ap-
plications, emphasizing switching behaviour, voltage, and current waveforms over
THD or efficiency. The study analyzes waveform performance on R and RL loads
through simulation and hardware implementation.

3
1.5 OUTLINE OF THE REPORT

The organization of this report is as follows.

As already seen, Chapter 1 presents background of the work on Five level cascaded
H-bridge Inverters .
Chapter 2 portrays the literature survey.
Chapter 3 presents the definition of the problem and solution methodology.Effectiveness
of the given method is also depicted.
Chapter 4 and 5 explains the working and switching sequence of 6 switch and 8
switch CHB MLI.
Chapter 6 shows the Simulation result.
Chapter 7 shows the hardware implementation strategies and chapter 8 brings out
the final conclusion and future scope of our project.}

4
 Chapter 2

LITERATURE SURVEY

1. ”Cascaded Multilevel Inverter with Reduced Switches ” by J.

Rodriguez, P. Correa, and H. Akagi

This paper presents an analysis of the Cascaded H-Bridge Multilevel Inverter (CHB-
MLI) with a reduced number of power switches to enhance efficiency and cost-
effectiveness. The conventional CHB-MLI topology is known for its modularity
and ease of expansion; however, it requires multiple isolated DC sources, increas-
ing system complexity. The proposed reduced-switch topology minimizes the num-
ber of power semiconductor devices while maintaining multilevel output voltage
quality. Simulation and experimental results demonstrate improved efficiency and
reduced switching losses, making it a viable alternative for renewable energy appli-
cations and motor drive systems.

2. ”Comparative Analysis of Five Level Cascaded Multilevel In-

verter by Level Shift & Phase Shift PWM Techniques” by Champa
P N, Abhay Deshpande A, K Venkatesha.

This paper explores the advantages of multilevel inverters over conventional two-
level inverters, particularly in reducing Total Harmonic Distortion (THD) and im-
proving power quality. The study focuses on a Cascaded H-Bridge (CHB) topol-
ogy, utilizing both Phase-Shifted Sinusoidal PWM (PS-SPWM) and Level-Shifted
Sinusoidal PWM (LS-SPWM) techniques for pulse generation. The authors ana-
lyze single-phase five-level, seven-level, and nine-level inverters, highlighting the
trade-off between complexity and performance. MATLAB-based simulations con-
firm that higher-level inverters achieve lower THD.

3)” Analysis of PWM techniques on multi level cascaded h bridge

inverter” by Hemanth Kumar and Makarand M. Lokhande.

This paper analyses various PWM techniques for multilevel cascaded H-bridge
three-phase inverters to evaluate their effects on harmonic distortion, switching
losses, and power quality. The study compared different PWM strategies, including
phase-shifted and level-shifted PWM, to determine their impact on inverter effi-
ciency. Their results showed that selecting an appropriate PWM method signifi-
cantly improves waveform quality and inverter performance. This work is relevant
to our project on an 8-Switch Conventional 5-Level Cascaded H-Bridge Inverter,
which utilizes DSPIC30F2010/SPG for PWM generation and TLP250 for driver
isolation. While the study primarily focuses on three-phase inverters, the PWM
techniques explored are applicable to our single-phase setup. The findings provide
insights into optimizing our switching scheme for improved voltage and current
waveforms.

4. ” ”A novel high energetic efficiency multilevel topology with

reduced impact on supply network ” by Y. Ounejjar and K. Al-Haddad.

This paper presents a novel multilevel inverter topology designed to improve en-
ergy efficiency and reduce stress on the supply network. The study introduces a
six-switch, five-level cascaded H-bridge multilevel inverter (MLI) and evaluates its
performance in terms of energy savings, harmonic reduction, and component opti-

6
mization. The authors focus on minimizing total harmonic distortion (THD) while
achieving a high-quality AC output. This work contributes to developing more
sustainable inverter designs that address the growing demand for efficient, reliable
power conversion in renewable energy and other applications.

5. ”Design and Hardware Implementation Considerations of

Modified Multilevel Cascaded H-Bridge Inverter for Photovoltaic
System” by by S. Shuvo, E. Hossain, T. Islam, A. Akib, S. Padmanaban, and M.
Z. R. Khan.

This paper focuses on the design and practical implementation of a modified mul-
tilevel cascaded H-bridge inverter (CHB MLI) specifically tailored for solar photo-
voltaic (PV) applications. The authors analyze the use of a six-switch, five-level in-
verter configuration, comparing it with more complex, higher-level inverter topolo-
gies. Their findings highlight how this configuration balances efficiency, compo-
nent count, and cost-effectiveness, making it suitable for renewable energy setups.
The study also addresses challenges in achieving stable voltage levels, reducing
harmonic distortion, and managing control complexity, which are crucial for real-
world applications in PV systems. This work emphasizes the practical feasibility
and reliability of six-switch MLIs in meeting PV system requirements.

7
 Chapter 3

METHODOLOGY

3.1 INTRODUCTION TO MULTILEVEL INVERTERS

Multilevel inverters can switch their input or output nodes (or both) between mul-
tiple voltage or current levels. As the number of levels increases towards infinity,
the total harmonic distortion (THD) in the output waveform reduces significantly,
approaching zero. However, the maximum number of achievable voltage levels
is restricted by several factors, including voltage imbalance issues, clamping re-
quirements, circuit layout and packaging limitations, control system complexity,
and overall capital and maintenance costs. There are three widely used multilevel
inverter topologies in industrial applications: the cascaded H-bridge inverter with
separate DC sources, the diode-clamped inverter, and the flying capacitor inverter.
While all these multilevel converter configurations provide the general advantages
of multilevel voltage source inverters (VSIs), their suitability varies based on struc-
tural differences and specific application requirements.
In a multilevel VSI, the DC-link voltage is supplied by any stable DC source. Typi-
cally, series-connected capacitors act as an energy reservoir for the inverter, offering
multiple connection points for different voltage levels. For simplicity, these capac-
itors are assumed to be voltage sources of equal value. The voltage across each
capacitor is determined by the expression:

Vdc
Vc =
n−1
3.2 SELECTED TOPOLOGY:CASCADED H-BRIDGE INVERTER

The cascaded H-bridge inverter consists of multiple H-bridge units connected in

series. In this configuration, H-bridges are cascaded within each phase, and the
overall output voltage is the sum of the individual bridge voltages. By adjusting the
switching pattern, a stepped voltage waveform is generated. As the number of H-
bridges increases, the output waveform becomes smoother and more sinusoidal. For
an n-level inverter, (n-1)/2 identical H-bridge units are required per phase, with each
H-bridge having its own independent DC source. This feature makes the topology
particularly suitable for integrating power from renewable energy sources such as
solar panels and fuel cells. The Cascaded H-Bridge (CHB) inverter has gained
significant popularity in high-power AC applications and adjustable-speed drives
due to its modular structure and efficient power conversion capabilities.
Each separate DC source is linked to a single-phase full-bridge inverter, and the AC
output terminals of multiple inverter levels are connected in series. By appropriately
switching the four power switches (S1-S4), each H-bridge unit can generate three
distinct voltage levels: +Vdc,-Vdc, and 0V. The overall output voltage of the CHB
inverter is formed by summing the voltage contributions of all connected H-bridges.
Unlike diode-clamped and flying capacitor inverters, the number of output voltage
levels (m) in a CHB inverter is given by the formula m = 2N + 1, where N repre-
sents the number of independent DC sources. For example, a seven-level cascaded
inverter consists of three DC sources and three H-bridge inverters.
Each H-bridge unit generates a quasi-square waveform, achieved by phase-shifting
the switching instances of the positive and negative phase legs. The switching de-
vices in this topology operate with 180° conduction, meaning each switch remains
on for half a cycle, ensuring uniform current stress across all devices.
The CHB inverter topology eliminates the need for additional clamping diodes or
voltage-balancing capacitors, simplifying the circuit design. By incorporating mod-

9
ular H-bridge inverter units, this configuration enhances manufacturability, reduces
production costs, and improves scalability. The low dv/dt characteristics of the
output voltage further contribute to improved system performance and reliability.

Figure 3.1: Structure of Cascaded H-Bridge (CHB) inverter with Five levels

3.2.1 Five Level Cascaded H-Bridge (CHB) inverter

The output voltage of a 5-level cascaded H-bridge inverter consists of five distinct
voltage levels, similar to other multilevel inverter topologies. This inverter is com-
posed of two cascaded H-bridge inverters, requiring a total of 8 switching devices
for proper operation.
Figure 3.2 illustrates a five-level cascaded H-bridge multilevel inverter. Each H-
bridge unit operates with a dedicated DC source, ensuring an independent power
supply for each stage. The inverter comprises 8 MOSFET switches, with each H-
bridge containing 4 MOSFET switches connected in series.
This switching sequence generates a staircase waveform at the output. As the
number of output levels increases, the requirement for additional DC sources and

10
switches also increases, leading to higher costs and greater circuit complexity. De-
spite these challenges, multilevel inverters are widely used in applications demand-
ing high power and improved power quality, such as uninterruptible power supplies
(UPS), photovoltaic power conversion systems, and hybrid power trains.

3.3 PWM CONTROL STRATEGY FOR 5-LEVEL CASCADED H-

BRIDGE MULTILEVEL INVERTER

This project utilizes sinusoidal level-shifted Pulse Width Modulation (SPWM) and
Level-Shifted PWM (LSPWM) techniques to regulate the operation of a 5-level
cascaded H-bridge multilevel inverter (CHB-MLI). These methods help improve
waveform quality, reduce harmonic distortion, and optimize switching efficiency
for enhanced power conversion performance.

3.3.1 Sinusoidal Level-Shifted PWM (SPWM) for 8-Switch 5-Level CHB-

MLI:

The SPWM technique is implemented for the 8-switch 5-level CHB-MLI, where a
sinusoidal reference signal is compared with four high-frequency triangular carrier
waves to generate switching pulses. This inverter configuration consists of two cas-
caded H-bridges, each powered by a separate DC source, allowing it to generate five
output voltage levels: +Vdc, +2Vdc, 0, -2Vdc, and -Vdc. The use of high-frequency
carrier signals minimizes total harmonic distortion (THD), resulting in an output
waveform that closely resembles a sinusoidal signal. This modulation technique
enhances power conversion efficiency, making it well-suited for applications such
as renewable energy systems, motor drives, and power electronics converters.

11
3.3.2 Sinusoidal Level-Shifted PWM (LSPWM) for 6-Switch Reduced 5-Level
CHB-MLI:

A 6-switch 5-level CHB-MLI is implemented using the level-shifted PWM (LSPWM)

technique, which reduces the number of switches while maintaining the same five-
level output voltage. In LSPWM, four triangular carrier signals are vertically shifted
and compared with a single sinusoidal reference waveform to determine the switch-
ing states. This technique ensures smooth voltage transitions while lowering switch-
ing losses. The six-switch topology simplifies the circuit and reduces costs while
maintaining high power quality. This project showcases two effective modulation
strategies that enhance inverter performance and improve efficiency using sinu-
soidal level-shifted PWM.

12
 Chapter 4

8-SWITCH FIVE-LEVEL CHB INVERTER

4.1 INTRODUCTION TO CONVENTIONAL 8 SWITCH FIVE LEVEL

CASCADED H BRIDGE INVERTER

The 8-Switch 5-Level Cascaded H-Bridge Multilevel Inverter is designed to provide

five distinct output voltage levels: +2Vdc, +Vdc, 0V, -Vdc, and -2Vdc. This allows
the inverter to generate a staircase-like output waveform with reduced harmonic
distortion, thus improving the overall efficiency and performance of the inverter. In
the conventional 8-switch configuration, each H-Bridge consists of four switches,
typically arranged in two pairs. The series connection of multiple H-Bridge units
allows the inverter to synthesize a waveform with more voltage levels than a conven-
tional 2-level inverter. By carefully controlling the switching states of the H-Bridge
units, different voltage levels are produced at the output, resulting in a smoother AC
output waveform.

4.2 WORKING OF 8 SWITCH FIVE LEVEL CASCADED H BRIDGE

INVERTER

Each of the five output voltage levels is achieved through specific switching states.
The table below summarizes the switching states required for generating each level:
1.+ Vdc Output:The upper H-bridge (H1) and lower H-bridge (H2) are fully turned
ON, summing both DC sources. Q1, Q4, Q5, and Q7 are turned ON while the
remaining switches are off.
2. +2Vdc Output: Only one H-bridge (H1) is active, applying half the voltage.Q1,
Q4, Q5, and Q8 are turned ON, while the rest are off.
3. 0V Output: Both H-bridges bypass the DC sources, resulting in zero voltage.This
is achieved by switching ON Q1,Q3,Q5 and Q7.
4. -VDC Output: One H-bridge (H2) is active in reverse, applying negative half the
voltage. Q3,Q2,Q5 and Q7 are ON, while others remain OFF
5. -2Vdc Output: Both H-bridges are switched in reverse mode, summing -2Vdc
across the load. Q3,Q2, Q7 and Q6 are turned ON while the remaining switches are
OFF.

Vo Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
+2V 1 0 0 1 1 0 0 1
+V 1 0 0 1 1 0 1 0
0 1 0 1 0 1 0 1 0
-V 0 1 1 0 1 0 1 0
-2V 0 1 1 0 0 1 1 0
Table 4.1: Switching sequence for 8 switch MLI

Figure 4.1: Circuit diagram of 8 Switch Five Level Cascaded H Bridge Inverter

14
Figure 4.4: Current path for -Vdc Figure 4.5: Current path for -2Vdc

Figure 4.2: Current path for +2Vdc Figure 4.3: Current path for +Vdc

15
 Chapter 5

6-SWITCH FIVE-LEVEL CHB INVERTER

5.1 INTRODUCTION TO SIX SWITCH FIVE LEVEL CASCADED-

H BRIDGE INVERTER

The 6-switch reduced five-level cascaded H-bridge (CHB) inverter is an improved

variation of the traditional CHB inverter, designed to produce a five-level voltage
output using fewer power switches. This reduction helps lower costs, decrease
switching losses, and simplify the control system.
Unlike conventional five-level CHB inverters that typically require 8 switches, this
design operates with only 6 switches, offering several benefits:

• Reduced switching losses, leading to higher efficiency.

• Simplified gate driver circuit, minimizing hardware complexity.

• Optimized control strategy, making it easier to implement with microcon-

trollers like the dsPIC30F2010.

• Lower overall system cost, as fewer components are needed.

This inverter is particularly suitable for renewable energy applications, motor drives,
and industrial power conversion, where a high-quality voltage waveform is essen-
tial. The switching pattern is carefully designed to ensure the correct operation of
the switches, maintain power balance, and generate the desired five-level output.
 Figure 5.1: Six Switch CHB MLI topology

5.2 SWITCHING SEQUENCE OF SIX SWITCH FIVE LEVEL CASCADED-

H BRIDGE INVERTER

Five level of output can be obtained through different switching patterns.

• Positive Voltage: To apply a positive voltage to the RL load, we turn on S11

and S22 ,conduction through body diode of S32 is utilized to obtain a +V
voltage . The switches S11 ,S22,S31 are turned on to obtain a +2V voltage .

• Negative Voltage: To apply a negative voltage to the RL load, we turn on

S12 and S21 ,conduction through body diode of S31 is utilized to obtain a -V
voltage . The switches S12,S21,S32 are turned on to obtain a -2V voltage

• Zero Voltage: To apply zero voltage to the RL load, we can either turn off
all the switches or turn on . This effectively disconnects the load from the
voltage sources. V: S11 and S22 are on, applying a positive voltage to RL.
-V: S12 and S21 are on, applying a negative voltage to RL. 2V: S11 ,S22,S31
are on. -2V:S12,S21,S32 are turned on.

17
 S11 S12 S21 S22 S31 S32 Vout
0 0 0 0 0 0 0
1 0 0 1 0 0 +V
1 0 0 1 1 0 +2V
0 1 1 0 0 0 -V
0 1 1 0 0 1 -2V
Table 5.1: Switching Sequence Of Six Switch Five Level Cascaded-H Bridge In-
verter

Figure 5.2: Circuit diagram for various voltage levels

18
 Chapter 6

SIMULATION STUDIES

In this Project simulations were conducted for both six-switch and eight-switch
five-level cascaded H-bridge (CHB) multilevel inverters (MLIs) with resistive (R)
and resistive-inductive (RL) loads. The switching frequency was set to 5 kHz, with
a resistive load of 24 ohms and an inductance of 5 mH for the RL load. The anal-
ysis focused on evaluating the output voltage and current waveforms, as well as
capturing the corresponding switching pulses.

6.1 SIMULATION ANALYSIS OF EIGHT SWITCH FIVE LEVEL

CASCADED H-BRIDGE (CHB) MULTILEVEL INVERTERS

6.1.1 Simulation Diagram

Figure 6.1: Block diagram for Eight switch cascaded H bridge five level inverter
with R load
Figure 6.2: Block diagram for Eight switch cascaded H bridge five level inverter
with RL load

6.1.2 Simulation Results

Figure 6.3: Gate pulses for 8-switch MLI using Sine PWM

20
Figure 6.4: Voltage and Current Waveform when RL Load is connected

Figure 6.5: Voltage and Current Waveform when R Load is connected

21
6.2 SIMULATION ANALYSIS OF SIX SWITCH FIVE LEVEL CAS-

CADED H-BRIDGE (CHB) MULTILEVEL INVERTERS

6.2.1 Simulation Diagram

Figure 6.6: 6 switch model for R load

Figure 6.7: 6 switch model for RL load

22
6.2.2 Simulation Results

Figure 6.8: 6 switch model for R load

Figure 6.9: Output current waveform when RL load is connected .

23
 Figure 6.10: Output voltage waveform when RL load is connected .

Figure 6.11: Voltage across each switches when RL Load is connected .

24
Figure 6.12: Current across each switches when RL load is connected .

25
 Chapter 7

HARDWARE IMPLEMENTATION

7.1 INTRODUCTION

The hardware implementation has only been carried out for the 8-switch CHB in-
verter since it has achieved the expected simulation result. The 6-switch model has
not met the expected result.

7.2 COMPONENTS AND SPECIFICATIONS

7.2.1 230V/9V Transformer

Figure 7.1: 230V/9V Four winding Transformer

In this 8-Switch, 5-Level Cascaded H-Bridge Multilevel Inverter (CHB-MLI), a 9V

step-down transformer with four secondary windings is used to power the TLP250H
gate driver circuits. Since the TLP250H optocoupler-based gate drivers require an
isolated +12V DC supply, this transformer provides the necessary low-voltage AC,
which is later rectified and regulated to the required voltage levels.
The power rating is selected based on the total current requirement of the gate driver
circuits. The output voltage is chosen to provide a rectified DC voltage slightly
higher than +15V, allowing proper regulation.The winding insulation and core ma-
terial are optimized for safe and efficient power conversion.
A 9V, 4-winding step-down transformer is used to provide isolated power for the
TLP250 gate driver circuits and the DSPIC30F2010 microcontroller unit (MCU).
Each H-Bridge in the 8-Switch, 5-Level Cascaded H-Bridge Multilevel Inverter
(CHB-MLI) is powered by two dedicated secondary windings of the transformer.
These windings supply the required isolated +15V DC to the TLP250 gate drivers
after rectification and regulation. The remaining secondary winding is connected
to a bridge rectifier, followed by a voltage regulator, to provide the necessary DC
power to the DSPIC30F2010 microcontroller, ensuring stable operation and control
signal processing. This configuration ensures proper electrical isolation, minimizes
ground loops, and enhances the reliability of the inverter system.
Specifications:

• Type: Step-down transformer

• Primary Voltage: 230V AC, 50 Hz (Standard mains input)

• Secondary Voltage: 9V AC per winding

• Number of Windings: 4 independent secondary windings

• Power Rating: 10VA - 20VA (depending on gate driver power requirements)

• Core Material: Laminated iron core (EI Core) for power applications.

• Insulation Class: Class B (130°C) or better for electrical safety

27
7.2.2 Bridge Rectifier IC (DB107)

Figure 7.2: Bridge Rectifier Circuit

DB107 IC is used in this project to convert 9V AC from the transformer’s secondary

windings into DC voltage required for the TLP250H gate driver circuits and the
DSPIC30F2010 microcontroller. It ensures a stable and regulated DC power sup-
ply for reliable operation of the 8-Switch, 5-Level Cascaded H-Bridge Multilevel
Inverter (CHB-MLI). Provides regulated +5V DC for the DSPIC30F2010, ensuring
reliable microcontroller operation. A large capacitor smooths out ripples, providing
unregulated DC voltage.

7.2.3 IRF840 N Chanel MOSFET

The IRF840 N-Channel MOSFET serves as the main switching device in the 8-
Switch, 5-Level Cascaded H-Bridge Multilevel Inverter (CHB-MLI). Its primary
function is to control power flow by switching ON and OFF according to the PWM
signals generated by the DSPIC30F2010 microcontroller. The IRF840 switches
on and off in response to PWM signals to generate the required multilevel voltage
output.
This creates different voltage levels for the five-level output waveform applied to the
load. By switching in different sequences, the H-Bridge controls the inverter output
voltage levels, ensuring proper synthesis of the AC waveform.Converts the low-

28
 Figure 7.3: IRF840 N Channel MOSFET

power PWM control signals from the DSPIC30F2010 into high-power switching
signals, enabling efficient power conversions.
Specifications :

• Type: N-Channel MOSFET

• Maximum Drain-Source Voltage (VDS): 500V

• Continuous Drain Current (ID): 8A at 25°C

• On-State Resistance (RDS(on)): 0.85 ohm (low conduction losses)

• Gate-Source Voltage (VGS): ±20V (compatible with common gate drivers)

• Total Power Dissipation (PD): 125W

29
7.2.4 TLP250H

Figure 7.4: TLP250H

The TLP250H is an optocoupler-based gate driver used in our 8-Switch, 5-Level

Cascaded H-Bridge Multilevel Inverter (CHB-MLI) to ensure proper and isolated
switching of the IRF840 MOSFETs. Since the DSPIC30F2010 microcontroller
outputs 0V–5V PWM signals, and the IRF840 MOSFETs require a +15V gate
drive, the TLP250H is necessary for signal amplification, level shifting, and elec-
trical isolation between the control and power circuits. The PWM outputs from
DSPIC30F2010 are connected to the input pins of the TLP250H through a current-
limiting resistor 1k. The TLP250H gate driver circuit is powered by a +15V DC
supply, derived from a bridge rectifier and voltage regulator connected to the trans-
former winding. The TLP250H output drives the IRF840 MOSFET gates with a
+15V signal, ensuring efficient switching in the H-Bridge. Specifications

• Input Threshold Current (IF): 5 mA(max)

• Supply Voltage (VCC): 10v-30v

• Supply Current (ICC): 3mA

• Output Peak Current (IO): +2 .5mA(max)

30
• Propagation Delay Time (tpLH ,tpHL): 500ns (max)

• Isolation Voltage: 3750Vrms (min)

7.2.5 FD2103S

Figure 7.5: FD2103S

The FD2103S is a high-speed half-bridge gate driver designed to generate comple-

mentary PWM signals with built-in dead-time control. In our 8-Switch, 5-Level
Cascaded H-Bridge Multilevel Inverter (CHB-MLI), it ensures that high-side and
low-side MOSFETs do not turn on simultaneously, preventing short circuits and
improving switching reliability. This is a half-bridge gate driver IC. It takes a logic-
level input signal and produces the necessary gate drive signals for a pair of MOS-
FETs in a half-bridge configuration. The ”LO” output inverts the input, indicating
it’s likely used for the low-side MOSFET in the bridge.
Specifications :

• Type: MOSFET Driver IC

• Package: SOP-8 (Small Outline Package)

• Gate Drive Voltage: 10V (Typically)

31
 • Input Voltage: 3.3V to 15V

• Output Voltage: 0 to VDD (rail-to-rail)

• Maximum Output Current:2A

• Source current: 2.5A

• Sink current: 4A

7.2.6 DSPIC30F2010

Figure 7.6: DSPIC30F2010

The DSPIC30F2010 is a digital signal controller (DSC) that combines the features
of a microcontroller (MCU) and a digital signal processor (DSP). It is widely used
in power electronics and motor control applications due to its high-speed process-
ing, PWM generation, and precise control capabilities. In our 8-Switch, 5-Level
Cascaded H-Bridge Multilevel Inverter (CHB-MLI), the DSPIC30F2010 plays a
critical role in generating PWM signals for MOSFET switching. It ensures proper
sequence, timing, and dead-time control, which are essential for the correct opera-
tion of the inverter.
The DSPIC30F2010 is powered by a regulated DC voltage derived from the bridge
rectifier circuit connected to a 9V step-down transformer The DSPIC generates pre-
cise Pulse Width Modulation (PWM) signals required for switching the MOSFETs

32
in the inverter circuit. It ensures correct timing and dead-time management to avoid
shoot-through faults.
The PWM signals from dsPIC30F2010 are sent to the TLP250H gate driver circuit,
which amplifies and isolates these signals before driving the IRF840 MOSFETs.

7.3 ALGORITHM OF PWM GENERATION

1. Initialization Phase (Main Function)

Step 1: System Setup

1. Initialize PWM Module by calling PWMINIT().

2. Set Initial Duty Cycle Values

PDC1 = fc * 2 * 0.60;

PDC2 = fc * 2 * 0.25;

PDC3 = fc * 2 * 0.30;

(These may be used for initial duty cycle settings.)

3. Enter Infinite Loop (while(1))

Keeps the microcontroller running indefinitely.

Calls delayms (10); to introduce a 10ms delay before the next loop iteration.

2. PWM Interrupt Service Routine (ISR)

Step 2: Fetch Next Sine Table Value

1. Read the next value from sinetable:

33
 duty = sinetable[sin1];

This represents a sampled sine wave amplitude for PWM control.

2. Increment the sine table index:

sin1 = sin1 + 1;

If sin1 exceeds 55, reset it to 0.

Step 3: Duty Cycle and H-Bridge Switching Logic

Compare duty against predefined threshold levels

Case 1:If duty >=7371 (Highest Voltage Level)

1. Compute duty cycle:

PDC2 = (duty - 7371) * 4;

2. Set OVDCON register to control switches:

Enable H-bridge leg 2 (POVD2) and turn off others:

OVDCONbits.POVD1L = 0;

OVDCONbits.POVD1H = 0;

OVDCONbits.POVD2L = 1;

OVDCONbits.POVD2H = 1;

OVDCONbits.POVD3L = 0;

OVDCONbits.POVD3H = 0;

34
3. Set H-bridge switch outputs:

OVDCONbits.POUT1L = 0;

OVDCONbits.POUT1H = 1;

OVDCONbits.POUT2L = 0;

OVDCONbits.POUT2H = 1;

OVDCONbits.POUT3L = 1;

OVDCONbits.POUT3H = 1;

Case 2: If 4914 <=duty<=7371 (Mid-Level Voltage)

1. Compute duty cycle:

PDC1 = (duty - 4914) * 4;

2. Set OVDCON to activate H-bridge leg 1 (POVD1):

OVDCONbits.POVD1L = 1;

OVDCONbits.POVD1H = 1;

OVDCONbits.POVD2L = 0;

OVDCONbits.POVD2H = 0;

OVDCONbits.POVD3L = 0;

OVDCONbits.POVD3H = 0;

3. Set H-bridge switch outputs:

35
 OVDCONbits.POUT1L = 0;

OVDCONbits.POUT1H = 0;

OVDCONbits.POUT2L = 0;

OVDCONbits.POUT2H = 1;

OVDCONbits.POUT3L = 1;

OVDCONbits.POUT3H = 1;

Case 3: If 2457 <=duty<=4914 (Lower Mid-Level)

1. Compute duty cycle:

PDC3 = (duty - 2457) * 4;

2. Set OVDCON to activate H-bridge leg 3 (POVD3L):

OVDCONbits.POVD1L = 0;

OVDCONbits.POVD1H = 0;

OVDCONbits.POVD2L = 0;

OVDCONbits.POVD2H = 0;

OVDCONbits.POVD3L = 1;

OVDCONbits.POVD3H = 0;

3. Set H-bridge switch outputs:

OVDCONbits.POUT1L = 1;

OVDCONbits.POUT1H = 0;

36
 OVDCONbits.POUT2L = 0;

OVDCONbits.POUT2H = 1;

OVDCONbits.POUT3L = 0;

OVDCONbits.POUT3H = 1;

Case 4:If duty <=2457(Lowest Voltage Level)

1. Compute duty cycle:

PDC3 = duty * 4;

2. Set OVDCON to activate H-bridge leg 3 (POVD3H):

OVDCONbits.POVD1L = 0;

OVDCONbits.POVD1H = 0;

OVDCONbits.POVD2L = 0;

OVDCONbits.POVD2H = 0;

OVDCONbits.POVD3L = 0;

OVDCONbits.POVD3H = 1;

3. Set H-bridge switch outputs:

OVDCONbits.POUT1L = 1;

OVDCONbits.POUT1H = 0;

OVDCONbits.POUT2L = 0;

OVDCONbits.POUT2H = 1;

OVDCONbits.POUT3L = 0;

37
 OVDCONbits.POUT3H = 1;

Step 4: Reset PWM Interrupt Flag

Clear interrupt flag (IFS2bits.PWMIF = 0;) to allow the next PWM cycle interrupt.

3. Loop Execution
Repeat Steps 2-4 continuously as new PWM cycles are generated.

7.4 CIRCUIT DIAGRAM

Figure 7.7: Circuit diagram of Hardware Implementation

The 8-switch, 5-level cascaded H-bridge multilevel inverter operates by using PWM
signals from the DSPIC30F2010 to control the switching of IRF840 MOSFETs in
the H-bridge configuration. The system integrates various components, including a

38
power supply, a microcontroller, gate drivers, and switching elements, to generate
the desired output waveform
A 9V step-down transformer is utilized to supply power to different sections of the
circuit. The transformer consists of four windings, Two windings supply the H-
bridge circuits, specifically for powering the TLP250H gate driver ICs. Another
winding is connected to the DSPIC30F2010 through a bridge rectifier, which con-
verts AC to DC and provides a regulated power source for the microcontroller.The
DSPIC30F2010 is set up with: A crystal oscillator along with capacitors to maintain
a stable clock frequency. Pull-down resistors to ensure proper logic level control.
The DSPIC30F2010 generates six PWM signals that dictate the switching of the
IRF840 MOSFETs.Additionally, two complementary PWM signals are created us-
ing the FD2103S gate driver IC, which ensures the correct timing between high-
side and low-side MOSFET switching.The generated PWM signals are fed into
TLP250H gate driver ICs, which provide electrical isolation and sufficient voltage
levels to switch the MOSFETs efficiently.
Each H-bridge unit consists of four IRF840 MOSFETs, forming a circuit that en-
ables multilevel voltage generation. Since high-side MOSFETs require a voltage
higher than the ground-referenced low-side MOSFETs, a bootstrap circuit consist-
ing of a capacitor and diode is employed. This technique ensures that the high-
side MOSFETs receive the necessary gate drive voltage through capacitor charging
when lower mosfets turns on , avoiding the need for multiple isolated power sup-
plies for each H-bridge.
The output terminals of the cascaded H-bridges combine to create a 5-level stepped
AC voltage that is supplied to the RL load. The waveform synthesis is achieved by
appropriately controlling the PWM signals to switch the MOSFETs in a predefined
sequence. As a result, the inverter produces an AC voltage output with multiple
levels, improving power quality and making it suitable for applications such as

39
renewable energy systems and motor drives.

7.5 HARDWARE SETUP

Figure 7.8: Hardware setup for R load

Figure 7.9: Hardware setup for RL load

40
7.6 HARDWARE RESULT

Figure 7.10: Output for R load

Figure 7.11: Output for RL load

In the implemented Hardware utilise two separate 12V DC sources as input to gen-
erate a five-level AC output voltage of 24V across the load. The measured output
waveform demonstrates the expected multilevel characteristics, with stepwise tran-
sitions forming discrete voltage levels: ±24V, ±12V, and 0V.
For both resistive (R) and inductive (RL) loads, the inverter successfully synthesizes

41
the desired stepped AC waveform. However, minor deviations from the ideal wave-
form are observed due to factors such as switching transients, non-ideal component
behavior, and driver circuit limitations

42
 Chapter 8

CONCLUSIONS

8.1 CONCLUSIONS

The project successfully explored the design, simulation, and hardware implemen-
tation of Cascaded H-bridge Multilevel Inverters (CHB MLI) for renewable energy
systems. We began by simulating two different topologies: a 6-switch reduced five-
level CHB MLI and an 8-switch conventional five-level CHB MLI, using resistive
(R) and inductive-resistive (RL) loads. These simulations provided valuable in-
sights into the system’s performance, including the voltage and current waveforms,
switching patterns, and overall efficiency. The comparison between the two topolo-
gies highlighted differences in system’s performance.
Following the simulation phase, we moved on to the hardware implementation
of the 8-switch conventional five-level CHB MLI. The DSPIC30F2010 microcon-
troller generated Pulse Width Modulation (PWM) signals to control the switches of
the inverter, with the TLP250H driver board providing isolation between the control
signals and the power devices. The hardware system was successfully tested, with
the inverter producing the desired output voltage and showing good agreement with
the simulated results in terms of current and voltage waveforms.
This project not only confirmed the accuracy of the theoretical models and sim-
ulations but also demonstrated the practicality of implementing these inverters in
real-world renewable energy systems. The PWM duty cycle adjustment mecha-
nism ensured optimal performance of the inverter. Ultimately, the work provides
valuable contributions to the design and control of multilevel inverters, offering a
reliable solution for efficient power conversion in renewable energy applications.

8.2 FUTURE SCOPE FOR FUTHER DEVELOPMENTS :

There are several potential avenues for further development and improvement in
this project. Future work could focus on the implementation of advanced control
techniques such as Model Predictive Control (MPC) or Fuzzy Logic Control (FLC),
which could enhance the inverter’s performance, particularly in dynamic or fluctu-
ating load conditions. These methods could help in minimizing harmonic distortion
and improving voltage regulation.
Another area for expansion is the integration of the cascaded H-bridge multilevel
inverter (CHB MLI) with energy storage systems like batteries or supercapacitors.
This would improve the stability and efficiency of renewable energy systems, partic-
ularly in off-grid scenarios, by effectively managing energy storage and balancing
load fluctuations.
To further improve the output quality, exploring advanced modulation strategies,
such as Space Vector Modulation (SVM) or Hybrid Pulse Width Modulation (HPWM),
could help reduce total harmonic distortion (THD). These techniques would en-
hance the quality of the inverter’s power output.
Additionally, scaling the system to handle higher power and voltage ratings would
be valuable for large-scale renewable energy applications. This would require fur-
ther advancements in switch selection, driver circuit design, and thermal manage-
ment for power devices.
Introducing fault detection and protection mechanisms, such as overcurrent or under-
voltage protection and thermal monitoring, would significantly improve the relia-
bility and safety of the inverter, especially in critical applications.
Another potential direction for future work involves integrating wireless communi-
cation for real-time monitoring and control. This would enable remote diagnostics

44
and performance tracking, which could simplify maintenance and enhance system
management.
Simulating other inverter topologies, such as 9-level or 11-level cascaded H-bridge
inverters, would provide valuable insights into efficiency improvements and scala-
bility for higher power applications.
Grid integration is another key area to explore. Future efforts could focus on ad-
dressing power quality issues such as voltage sags, harmonics, and reactive power
compensation, ensuring compliance with grid standards and improving the system’s
compatibility with the grid.
Finally, ongoing research into cost reduction and design optimization could help
make the technology more cost-effective, accessible, and suitable for large-scale
deployment in renewable energy systems. By enhancing component selection, im-
proving thermal management, and optimizing designs for mass production, the
overall system could become more affordable and efficient.

45
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[2] . Shuvo, E. Hossain, T. Islam, A. Akib, S. Padmanaban and M. Z. R.

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[3] B. S. Naik, Y. Suresh, J. Venkataramanaiah and A. K. Panda, ,”A

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[4] G. K ”Implementation of Five Level Multilevel Inverter with Reduced Leak-

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