A Project Report On

Improved Multicarrier PWM Technique for Harmonic Reduction by

using APOD method for cascaded H-bridge DC/AC converters.

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY

ANANTAPUR, ANANTHAPURAMU
In partial fulfillment of the requirements for the award of the degree of

BACHELOR OF TECHNOLOGY
In
ELECTRICAL AND ELECTRONICS ENGINEERING
Submitted by

P.B. CHARAN (22HR5A0206) C. BHASKAR REDDY (21HR1A0206)

M. SHAKTHI KUMAR (21HR1A0220) B. VIJAY KUMAR (21HR1A0204)
V. CHANDU (21HR5A0245)
Under the esteemed guidance of

Mr.K. JEEVAN REDDY,M.Tech.,

Assistant Professor, EEE Department

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

MOTHER THERESA INSTITUTE OF ENGINEERING &TECHNOLOGY

AN ISO 9001:2015 CERTIFIED INSTITUTION

(Approved by AICTE, New Delhi and Affiliated to JNTUA)
Melumoi (P), Palamaner, Chittoor (Dist.)-517408
2021-2025
 MOTHER THERESA INSTITUTE OF ENGINEERING & TECHNOLOGY
AN ISO 9001:2015 CERTIFIED INSTITUTION
(Approved by AICTE, New Delhi and Affiliated to J.N.T.U.A., Ananthapuramu)
Melumoi (Post), Palamaner-517 408, Chittoor (Dist), A.P.
Department of eLeCtrICaL eLeCtronICS anD engIneerIng

Certificate
This is to certify that the Project Report entitled
Improved Multicarrier PWM Technique for Harmonic Reduction by
using APOD method for cascaded H-bridge DC/AC converters.
is the bonafied work done and
Submitted by
P.B. CHARAN (22HR5A0206) C. BHASKAR REDDY (21HR1A0206)
M. SHAKTHI KUMAR (21HR1A220) B. VIJAY KUMAR (21HR1A0204)
V. CHANDU (21HR1A0245)

In the Department of ELECTRICAL AND ELECTRONICS ENGINEERING

Mother Theresa Institute of Engineering & Technology, Palamaner affiliated to J.N.T.U.A.,
Ananthapuramu in partial fulfillment of the requirements for the award of Bachelor of
Technology in Electrical and Electronics Engineering during Academic Year2024-2025.
Submitted on:

Project Guide Head of Department

Mr.K.Jeevan Reddy,M.Tech. Mr.K.Krishna Reddy,M.Tech ,(Ph.D).,
Assistant Professor Associate Professor

Internal Examiner External Examiner

 ACKNOWLEDGEMENT

Any achievement, be it scholastic or otherwise does not depend solely on the individual effort
but on the guidance, encouragement and cooperation of intellectuals, elders and friends. I would
like to take this opportunity to thank them all. I feel myself self-honored to place my warm salutation
to The Management of Mother Theresa Institute of Engineering & Technology, Palamaner,
which gave me the opportunity to obtain a strong base in B. Tech and profound knowledge. I express
our sincere thanks to Dr. M. LAKSHMIKANTHA REDDY, M.Tech, Ph.D., our beloved Principal
for his encouragement and suggestions during my course of study.

With deep sense of gratitude, I acknowledge Mr. K. KRISHNA REDDY,M.Tech,(Ph.D.)

Head of the Dept., Electrical & Electronics Engineering, for his valuable support and help in
completing our project successfully.
I express my sincere thanks to Project Co-Ordinator Mr. N.V. KISHORE KUMAR, M.Tech
Associate professor, for his valuable suggestions and guidance in completing the project
successfully. I whole-heartedly express my gratitude and esteemed regards to our Project Guide,
Mr. K. JEEVAN REDDY,MTech, Assistant Professor in Dept. of EEE, for providing me invaluable
gratitude and inspiration in carrying out our Project Work. His constant support and encouragement
enable us to complete this project work successfully.

Finally, I would like to express my sincere thanks to Faculty Members of E.E.E Department,
and Lab technicians, friends & family members one and all, who have helped us to complete this
project work successfully.

P. B. CHARAN (22HR5A0206)

C.BHASKAR REDDY (21HR1A0206)

M.SHAKTHI KUMAR (21HR1A0220)

B.VIJAY KUMAR (21HR1A0204)

V.CHANDU (21HR1A0245)
 CONTENT

S. No Chapter Title Page. No

Number
LIST OF FIGURES I
LIST OF ABBREVIATIONS III
1 INTRODUCTION
1.1 INTRODUCTION TO MULTI-LEVEL 12
INVERTER
1.2 OPERATION AND TOPOLOGIES OF 13
MULTILEVEL CONVERTERS
1
1.3 OPERATION ANALYSIS 19

1.4 MODULATION TECHNIQUES FOR 21

MULTILEVEL INVERTERS
1.5 COMPARISION 22

2 PULSE WIDTH MODULATION

TECHNIQUE
2.1 INTRODUCTION 23

2.2 PULSE WIDTH MODULATION 24

2 GENERATION
2.3 PARAMETERS OF PWM 25

2.4 TYPES OF PWM 26

2.5 APPLICATIONS 29

3 CASCADED H-BRIDGE INVERTER

3.1 INTRODUCTION 31
3.2 WORKING PRINCIPLE OF CASCADED H- 32
BRIDGE
3 3.3 OPERATION OF CHB INVERTER 33

3.4 REDUNDANCY AND FAULT TOLERANT 34

OPERATION
3.5 CHB DC/AC CONVERTER AND ITS 38
HARMONIC CHANGES
3.6 CHB INVERTER FOR GRID CONNECTED 41

APPLICATIONS
 4 ALTERNATIVE PHASE OPPOSITION AND
DISPOSITION

4.1 INTRODUCTION 43

4 4.2 APOD MODULATION STRATEGY 44

4.3 46
HARMONIC MITIGATION IN APOD SPWM

4.4 MATHEMATICAL ANALYSIS OF APOD 48

SPWM
4.5 ADVANTAGES OF APOD SPWM 53

4.6 APOD’s ROLE IN CHB INVERTERS 54

5 HARMONICS

5.1 INTRODUCTION 55

5 5.2 TOTAL HARMONIC DISTORTION (THD) 55

5.3 HARMONICS IN APOD SPWM 57

5.4 MATHEMATICAL DERIVATION OF THD 58

IN APOD SPWM
5.5 HARMONIC MITIGATION PROPERTY 59

5.6 HARMONIC MITIGATION ALGORITHM 60

5.7 HARMONIC SPECTRAL 62

CHARACTERISTICS
5.8 PROPOSED SYSTEM 66

6 6 SOFTWARE

6.1 MATLAB 70

6.2 SIMULINK 77

6.3 MATLAB AND SIMULINK WORKING 84

TOGETHER
7 7 SIMULATION RESULTS 86

8 8 CONCLUSION 90

9 9S REFERENCE 91
 Abstract

The conventional modulation schemes of the cascaded H-bridge DC/AC converter tend
to generate a higher percentage of low-frequency harmonics in the output voltage, leading to
discontinuous high-peak output current, which negatively impacts industrial motor drive systems.
To address this issue, this paper proposes an enhanced multicarrier pulse-width modulation
(MCPWM) technique utilizing the Alternative Phase Opposition Disposition (APOD) method.
The proposed technique effectively reduces harmonic content in the AC output voltage while
ensuring continuous output current with a reduced peak magnitude. A harmonic mitigation
algorithm is introduced, which adjusts the modulation index and switching frequency of the
semiconductor switches dynamically, based on the switching angles of the MCPWM pulse. The
main focus of this research is to mitigate the fifth, seventh, and eleventh-order harmonics from the
inverter's output voltage, by identifying a new range of switching angles that result in the lowest
possible amplitude for these specific harmonics. Additionally, the paper presents an innovative
approach to estimate the switching angles of the MCPWM pulse train in real-time operation,
without the need for solving complex nonlinear equations. This technique offers advantages such
as low-frequency harmonic mitigation, reduced processing time, and minimal hardware
requirements (using a medium-sized FPGA), providing an effective balance between design
complexity and performance. The feasibility and effectiveness of the proposed method are
demonstrated through comprehensive comparisons with recently reported techniques.
Furthermore, theoretical, simulation, and experimental results using an FPGA-based three-phase
cascaded H-bridge multilevel inverter prototype are provided to validate the suitability of the
proposed technique.
 LIST OF FIGURES

Fig.no Figure name Page no

1.1 Gate Triggering circuit 13

1.2 Topology of the Diode Clamped Inverter 14

1.3 Schematic of Capacitor Clamped Inverter 16

1.4 Schematic of Series H-bridge Inverter 18

1.5 Switching Pattern Produced using the APOD carrier based 19

PWM scheme
1.6 H-Bridge Inverter 20
2.1 PWM Signal Generator 23
2.2 Duty Cycle of PWM 24
2.3 Frequency of PWM 25

2.4 Single Pulse Width Modulation 26

2.5 Multiple Pulse Width Modulation 27

2.6 Sinusoidal Pulse Width Modulation 28

3.1 Basic circuit of CHB 32
3.2 Single Phase 5 and 7 level CHB 33

3.3 Bypassing H-Bridge with Faults 40

3.4 Voltage waveforms 42

3.5 Grid connected CHB Based Solar Inverter 44

4 Switching Pattern produced using the APOD carrier based 45

PWM Scheme
5.1 MCPWM Generated Five level staircase voltage 58
waveform
5.2 Harmonic Mitigation algorithm 59

5.3 Voltage amplitude deviation 64

5.4 21- Level Inverter 66

5.5 Input sequence of APOD method 67

5.6 MAT lab circuit 69

6 MAT lab images 74

7 Simulation results of the Voltage waveform of R-Phase 85

7.1 Simulation results of the Voltage waveform of Y-Phase 85

7.2 Simulation results of the Voltage waveform of B-Phase 86

7.3 Simulation results of the Three-Phase Voltage waveform 86

7.4 Simulation results of the Current waveform of R-Phase 87

7.5 Simulation results of the Current waveform of Y-Phase 87

7.6 Simulation results of the Current waveform of B-Phase 88

7.7 Simulation results of the Three-Phase Current waveform 88

 List of Abbreviations

MLI : MULTI-LEVEL INVERTER

MCPWM : MULTI-CARRIER PULSE WIDTH MODULATION

CHB : CASCADED H-BRIDGE

APOD : ALTERNATIVE PHASE OPPOSITION AND DISPOSITION

FPGA : FIELD PROGRAMMABLE GATE ARRAY

EMI : ELECTROMAGNETIC INTERFERENCE

VSI : VOLTAGE SOURCE INVERTER

NPC : NEUTRAL POINT CLAMPED

FC : FLYING CAPACITOR

SVPWM : SPACE VECTOR PULSE WIDTH MODULATION

SHE : SELECTIVE HARMONIC ELIMINATION

SHM : SELECTIVE HARMONIC MITIGATION

PV : PHOTOVOLTAIC

MI : MODULATION INDICES

THD : TOTAL HARMONIC DISTORTION

 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Chapter-01

Introduction

1.1 Introduction to Multilevel Inverters

Multilevel Inverters are the most preferred choices for electronic power conversion in
high-power applications, and it seeks increased attention in industry and research areas. It has
been accepted globally as a matured and proven technology and has been entrenched
successfully in electronic power conversion system. Currently, they are being utilized in
standard and customized products that enable power to a extensive range of applications, such
as compressors, extruders, fans, blast furnace blowers, gas turbine starters, mixers, grinding
mills, rolling mills, conveyors, crushers mine hoists, reactive power compensation, hydro
pumped storage, wind energy conversion, railway traction marine propulsion, high voltage
direct current (HVDC) transmission , and so on. Researchers over the entire world are trying
to further improve energy efficiency, simplicity, reliability, power density and cost of
multilevel converters, and enlarge their application field as they are competitive and attention
seeking than other topologies. Recently, many publications have presented multilevel inverter
technology and cited the growing importance of multilevel inverters for power quality and
high-power applications.
The unique structure of multilevel inverters allows them to achieve high voltages with
less harmonic content without transformers.
The general purpose of the multilevel inverter is to obtain a desired voltage from
several levels of DC voltages. The synthesized output waveform has more steps; as the number
of levels increases, the produced staircase wave that approaches the required waveform. As the
number of steps increase in the waveform, the harmonic distortion of the output wave
decreases, approaching zero. Multilevel inverter is structured such that no voltage-sharing
problems are encountered by the active devices. Some of the applications these inverters come
under the sections: static var compensation, drives for electric motors, back-to-back high-
voltage intertie, and adjustable speed drives (ASD). In static var compensation, only reactive
power flows between the converter and the system but in the case of motor drives, the converter
must handle bidirectional real power flow . Nowadays, industrial needs are demanding high
power handling equipments, which now reaches the megawatt level. In today's scenario, it is
difficult to connect a single power semiconductor switch directly to medium voltage grids (2.3,
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

3.3, 4.16, or 6.9 kV). Due to these reasons, a new group of multilevel inverters has emerged as
the solution for working with higher and medium voltage levels .
One of the major drawbacks of the topology is that larger number of power semiconductor
switches, which adds on to the complexity and cost of the system as each switch has a related
gate driver circuit. Great attention is being given on the studies to reduce the number of power
electronic switches thereby reducing the complexity of the circuit and the requirements of gate
triggering circuits.
Single phase leg of inverters with two and “n” numbers of levels, for which an ideal switch is
used to represent the action of the power semiconductors with several positions.

1.1.Gate Triggering Cicuits

The output voltage of a two level inverter would comprise of two values (levels) with respect
to the negative terminal of the capacitor, while the n-level inverter generates “n” voltage levels.
The number of steps in the voltage between two phases of the load k is given by (4.1), where
“m” is the number of steps of the phase voltage with reference to the negative terminal of the
inverter.
(4.1)k=2m+1.

1.2OPERATION AND TOPOLOGIES OF MULTILEVEL CONVERTERS

1.2.1 Diode-Clamped Multilevel Inverter

The most commonly used multilevel topology is the diode clamped inverter, in
which the diode is used as the clamping device to clamp the dc bus voltage so as to achieve
steps in the output voltage. the circuit for a diode clamped inverter for a three-level and a four-
level inverter. The key difference between the two-level inverter and the three-level inverter
are the diodes D1a and D2a. These two devices clamp the switch voltage to half the level of
the dc-bus voltage. In general, the voltage across each capacitor for an N level diode clamped
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

inverter at steady state is Although each active switching device is only required to block V dc
/ n − 1 V dc / n −1 . , the clamping devices have different ratings. The diode-clamped inverter
provides multiple voltage levels through connection of the phases to a series of capacitors.
According to the original invention, the concept can be extended to any number of levels by
increasing the number of capacitors. Early descriptions of this topology were limited to three-
levels [4] where two capacitors are connected across the dc bus resulting in one additional
level. The additional level was the neutral point of the dc bus, so the terminology neutral point
clamped (NPC) inverter was introduced [4]. However, with an even number of voltage 23
levels, the neutral point is not accessible, and the term multiple point clamped (MPC) is
sometimes applied [5]. Due to capacitor voltage balancing issues, the diode-clamped inverter
implementation has been limited to the three level. Because of industrial developments over
the past several years, the three level inverter is now used extensively in industry applications.
Although most applications are medium-voltage, a three-level inverter for 480V is on the
market. In general for a N level diode clamped inverter, for each leg 2 (N-1) switching devices,
(N-1) * (N-2) clamping diodes and (N-1) dc link capacitors are required. When N is sufficiently
high, the number of diodes and the number of switching devices will increase and make the
system impracticable to implement.

Figure 1.2: Topology of the diode-clamped inverter (I) two-level inverter, (II) three-level
inverter, (III) four-level inverter.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Though the structure is more complicated than the two-level inverter, the operation is
straightforward and well known [5]. In summary, each phase node (a, b, or c) can be connected
to any node in the capacitor bank (V3, V2, V1). Connection of the a phase to positive node, V3
occurs when S1ap and S2ap are turned on and to the neutral point voltage, when S2ap and S1an
are turned on and the negative node V1 is connected when S1an and S2an are turned on. There
are some complementary switches and in a practical implementation, some dead time is
inserted between the gating signals and their complements meaning that both switches in a
complementary pair may be switched off for a small amount of time during a transition.
However, for the discussion herein, the dead time will be ignored. From Figure 3.1 (II), it can
be seen that, with this switching state, the a-phase current Ia will flow into the junction through
diode D1a if the current is negative or out of the junction through diode D2a if the current is
positive. The dc currents I3, I2, and I1 are the node currents of the inverter. Extending the
diode-clamped concept to four levels results in the topology shown in Figure 3.1 (III). A pair
of diodes is added in each phase for each of the two junctions. The operation is similar to the
three-level. For practical implementation, the switching state needs to be converted into
transistor signals.

1.2.2 The capacitor clamped inverter

The capacitor clamped inverter alternatively known as flying capacitor was proposed
by Meynard and Foch. This is one of the alternative topology for the diode clamped inverter.
The flying capacitor involves series connection of capacitor clamped switching cells [8]. Figure
3.2 shows the three-level and the four level capacitor clamped inverter. This topology has
several unique and attractive features when compared to the diode-clamped inverter. One
feature is that added clamping diodes are not needed. Furthermore, the flying capacitor inverter
has switching redundancy within the phase, which can be used to balance the flying capacitors
so that only one dc source is needed. Figure 3.2 shows the three-level flying capacitor inverter.
The general concept of operation is that each flying capacitor is charged to one-half of the dc
voltage and can be connected in series with the phase to add or to subtract this voltage.

The major advantage is that the required number of voltage levels can be achieved
without the use of the transformer. This assists in reducing the cost of the converter and again
reduces power loss. Unlike the diode clamped structure where the series string of capacitors
share the same voltage, in the capacitor-clamped voltage source converter the capacitors within
a phase leg are charged to different voltage levels.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Figure 1.3: Schematic of Capacitor Clamped inverter (I) three-level inverter (II) four level
inverter.

To synthesize the phase voltage waveforms the various switches within the phase leg
are switched on to combine the various capacitor voltage levels with the constraint that no
capacitor is short-circuited and current continuity with the DC link is maintained for each
capacitor. Similar to the diode clamped inverter, the capacitor clamping requires a large number
of bulk capacitors to clamp the voltage. Provided that the voltage rating of each capacitor used
is the same as that of the main power switch, a N level converter will require a total of (N-1) *
(N-2) / 2 clamping capacitors per phase in addition to the N-1 main dc bus capacitors.

The topology also has several disadvantages that have limited its use. First one being
the converter initialization i.e., before the converter can be modulated by any modulation
scheme the capacitors must be set up with the required voltage level as the initial charge. This
complicates the modulation process and becomes a hindrance to the operation of the converter.
The capacitor voltages must also be regulated under normal operation in a similar way to the
capacitors of a diode clamped converter. Another major drawback of the topology is the rating
of the capacitors, since the capacitors have large fractions of the dc bus voltage across them.

In the operation of the converter, each phase node (a, b, or c) can be connected to any
node in the capacitor bank (V3, V2, V1). Connection of the a-phase to positive node V3 occurs
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

when S1ap and S2ap are turned on and to the neutral point voltage when S2ap and S1an are
turned and the negative node V1 is connected when S1an and S2an are turned on. The clamped
capacitor C1 is charged when S1ap and S1an are turned on and is discharged when S2ap and
S2an are turned on. The charge of the capacitor can be balanced by proper selection of the zero
states. In comparison to the three-level diode-clamped inverter, an extra switching state is
possible. In particular, there are two transistor states, which make up the level V3. Considering
the direction of the a-phase flying capacitor current Ia for 29 the redundant states, a decision
can be made to charge or discharge the capacitor and therefore, the capacitor voltage can be
regulated to its desired value by switching within the phase. As with the three-level flying
capacitor inverter, the highest and lowest switching states do not change the charge of the
capacitors. The two intermediate voltage levels contain enough redundant states so that both
capacitors can be regulated to their ideal voltages.

1.2.3 Series H-Bridge Multilevel Inverter

One more alternative for a multilevel inverter is the Series H-bridge inverter. The series
H-bridge inverter appeared in 1975 [7], but several recent patents have been obtained for this
topology as well. A series of single-phase full bridges makes up a phase for the inverter. Each
full bridge can switch between +Vdc, 0, -Vdc. Since this topology consists of series power
conversion cells, the voltage and power level may be easily scaled. The dc link supply for each
full bridge converter is provided separately, and this is typically achieved using diode rectifiers
fed from isolated secondary windings of a three-phase transformer. An apparent disadvantage
of this topology is the large number of isolated voltages required to supply each cell. However,
phase-shifted transformers can supply the cells in medium-voltage systems in order to provide
high power quality at the utility connection. 30 There are several advantages for this topology
that have made the application of the converter interesting. The main advantage is the
regulation of the DC buses described, while the other is concerning the modularity of control
that can be achieved. Unlike the diode clamped and capacitor clamped inverter where the
individual phase legs must be modulated by a central controller, the full-bridge inverters of a
cascaded structure can be modulated separately. Communication between the full-bridges is
required to achieve the synchronization of reference and the carrier waveforms. A two-cell
series H-bridge inverter is as shown in Figure 3.3. The inverter consists of familiar H-bridge
(sometimes referred to as full-bridge) cells in a cascade connection. Since each cell can provide
three voltage levels (zero, positive dc voltage, and negative dc voltage), the cells are themselves
multilevel inverters. Since the H-bridge cells can supply both positive and negative voltages
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

contributing to the line-to-ground voltage, a switching state is defined for H-bridge cells that
have negative values.

Figure 1.4: Schematic of series H-bridge inverter.

1.2.4 Alternate Phase Disposition (APOD)

In case of alternate phase disposition (APOD) modulation, every carrier waveform is in

out of phase with its neighbour carrier by 1800. Since APOD and POD schemes in case of
three-level inverter are the same, a five -level inverter is considered to discuss about the APOD
scheme. The rules for APOD method, when the number of level N = 5, are • The N – 1 = 4
carrier waveforms are arranged so that every carrier waveform is in out of phase with its
neighbor carrier by 1800. 39 • The converter switches to + Vdc / 2 when the reference is greater
than all the carrier waveforms. • The converter switches to Vdc / 4 when the reference is less
than the uppermost carrier waveform and greater than all other carriers. • The converter
switches to 0 when the reference is less than the two uppermost carrier waveform and greater
than two lowermost carriers. • The converter switches to - Vdc / 4 when the reference is greater
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

than the lowermost carrier waveform and lesser than all other carriers. • The converter switches
to -Vdc / 2 when the reference is lesser than all the carrier waveforms.

1.5: Switching pattern produced using the APOD carrier-based PWM scheme for a five-level
inverter: (a) Four triangles and the modulation signal (b) S1ap (c) S2ap (d) S3ap (e) S4ap.

1.3 Operation Analysis:

Multilevel inverters (MLIs) enhance the voltage levels by a factor of (n − 1) times compared
to conventional high-power two-level voltage source inverters (VSIs) through a series–parallel
combination of semiconductor switches, where n represents the number of output voltage levels
[1]. In comparison to traditional inverters of the same power rating, MLIs offer significant
advantages, such as reduced harmonic distortion, lower dv/dt stress on semiconductor switches,
and minimized electromagnetic interference (EMI) in the output voltage [2]. These benefits
make MLIs ideal for a wide variety of applications, including low-voltage and low-power
systems [3], medium-voltage and high-power systems [4]–[5], photovoltaic grid-connected
systems [6], [7], locomotive traction [8], and other specialized applications [9]. MLIs are
typically classified into three main configurations: neutral point clamped (NPC) [10], flying
capacitor (FC) [11], [12], and cascaded H-bridge (CHB) [13]–[26]. Among these, the cascaded
H-bridge topology has gained popularity due to its modularity and scalability. In order to
improve the performance of CHB inverters, modulation techniques such as Alternative Phase
Opposition Disposition (APOD) have been proposed to further reduce harmonic content and
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

enhance output voltage quality. These techniques are integral to achieving efficient and high-
quality voltage waveforms, especially in high-power and industrial applications.

1.6 H-Bridge Circuit

As the Neutral Point Clamped (NPC) topology involves a greater number of diodes and
capacitors, it requires a complex control technique to generate higher output voltage levels
[25]. In comparison, the Flying Capacitor (FC) topology uses the same number of circuit
components but results in increased volume due to the higher number of capacitors required.
On the other hand, the Cascaded H-Bridge (CHB) inverter consists of individual low-voltage
H-bridge modules connected to separate DC sources to generate multiple output voltage levels
(n), as illustrated in Fig. 1. The CHB inverter offers several advantages over the NPC and FC
topologies, which are listed below:The modular structure of the CHB topology provides a
scalable output due to identical H-bridge modules [14].

1. Soft-switching techniques make the CHB topology suitable for both higher and lower voltage
applications [3], [4].
2. The CHB topology generates less EMI by reducing dv/dt stress on the semiconductor switches
[2].
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

3. The number of output voltage levels can be easily increased by adding more H-bridge modules
to the topology [17].

With the development of MLI topologies, several pulse-width modulation (PWM)

techniques have been proposed to enhance inverter performance. These PWM techniques are
classified as either online or offline [15] and can be carrier-based or carrier-less [16], [17]. The
conventional carrier-based PWM technique uses a triangular carrier wave and a reference
sinusoidal wave to generate the PWM gate pulses. While this classical technique provides a
simple way to generate PWM pulses for industrial drive applications, it also produces low-
frequency harmonics at higher modulation indices (MI) and switching frequencies [27]. Space
Vector PWM (SVPWM) techniques represent the latest advancement in MLI control
techniques [15]. SVPWM directly controls all phase voltages and manages line voltages,
offering the ability to exploit the versatility of MLIs, such as reducing common-mode voltage
and switching state or voltage-level redundancy. As a result, SVPWM is a widely accepted
choice in the power electronics industry. Generalized 2-D and 3-D SVPWM algorithms for n-
level inverters have been reported in [18], and these algorithms typically involve selecting the
nearest voltage vectors, computing dwell times, and determining the switching sequence.
However, the practical implementation of these algorithms complicates the system, requiring
additional calculations to determine the switching angles.

1.4 Advantages

The multilevel converter has several advantages, that is:

1. Common Mode Voltage: The multilevel inverters produce common-mode voltage, reducing
the stress of the motor and don’t damage the motor.

2. Input Current: Multilevel inverters can draw input current with low distortion

3. Switching Frequency:The multilevel inverter can operate at both fundamental switching

frequencies that are higher switching frequency and lower switching frequency. It should be
noted that the lower switching frequency means lower switching loss and higher efficiency is
achieved.

4. Reduced harmonic distortion:Selective harmonic elimination technique along with the multi-
level topology results the total harmonic distortion becomes low in the output waveform
without using any filter circuit.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Chapter-02

PULSE WIDTH MODULATION TECHNIQUE

2.1 INTRODUCTION:

Pulse Width Modulation (PWM) is a widely used technique in electronics for controlling
power delivery using digital signals. Unlike Analog methods that vary voltage or current
continuously, PWM maintains a constant voltage level but modulates the time the signal is
active, known as the "on time," within each cycle. This modulation is expressed as a duty
cycle—the percentage of one period in which the signal is high (on). For example, a 100% duty
cycle means the signal is always on, delivering full power, while a 0% duty cycle means it is
always off, delivering no power. By adjusting the duty cycle, PWM allows for fine control over
devices such as motors, LEDs, and heating elements. It is especially useful in microcontroller
systems where precise control and high efficiency are required. PWM signals are typically
generated using timers or dedicated hardware modules within microcontrollers, and they can
operate at various frequencies depending on the application. Higher PWM frequencies are often
used for audio and visual applications to avoid perceptible flickering or noise. One of the key
advantages of PWM is its ability to deliver variable power with minimal energy loss, making
it an ideal method for modern electronics and embedded systems.
PWM, is a modulation method that changes the pulse signal's width in electrical systems
to regulate the average power supplied to a load. PWM is particularly helpful for effectively
regulating the output of audio amplifiers, the speed of motors, and the brightness of light. They
are frequently Used in microcontrollers and specialist PWM controller integrated
Circuits (ICs).
The PWM switching frequency can vary greatly depending on load and application. For
example, switching only has to be done several times a minute in an electric stove; 100 or
120 Hz (double of the utility frequency) in a lamp dimmer; between a few kilohertz (kHz) and
tens of kHz for a motor drive; and well into the tens or hundreds of kHz in audio amplifiers
and computer power supplies. Choosing a switching frequency that is too high for the
application may cause premature failure of mechanical control components despite getting
smooth control of the load. Selecting a switching frequency that is too low for the application
causes oscillations in the load. The main advantage of PWM is that power loss in the switching
devices is very low. When a switch is off there is practically no current, and when it is on and
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

power is being transferred to the load, there is almost no voltage drop across the switch. Power
loss, being the product of voltage and current, is thus in both cases close to zero. PWM also
works well with digital controls, which, because of their on/off nature, can easily set the needed
duty cycle. PWM has also been used in certain communication systems where its duty cycle
has been used to convey information over a communications channel.
In electronics, many modern microcontrollers (MCUs) integrate PWM controllers exposed to
external pins as peripheral devices under firmware control. These are commonly used for
DC motor control in robotics, switched-mode power supply regulation, and other applications.
2.2 Pulse Width Modulation Generation

A comparator is used to create a signal that modulates pulse width. One component of
the comparator's input is the modulating signal, while the other component is either a sawtooth
wave or a non-sinusoidal wave. The comparator creates an output waveform of a PWM signal
after comparing two signals.

One possible output of a monostable multivibrator is a PWM signal. When an external

trigger is applied, a monostable multivibrator will only produce one output pulse and have one
stable state. An operational amplifier comparator can be used to build a monostable
multivibrator circuit.

One portion of the input to the comparator is structured by the modulating signal, and
the other portion is wave formed non-sinusoidally. After analyzing two signals, the comparator
generates a PWM signal as the output waveform. The output is in a "High" condition when the
sawtooth or non-sinusoidal signal exceeds the modulating signal.

2.1 PWM Signal Generator

 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

The output signal is in a "High" condition if the sawtooth signal exceeds the modulating signal.
The comparator output, which establishes the pulse width produced at the output, is determined
by the magnitude value.

2.3 Parameters of PWM

2.3.1 Duty Cycle

Duty Cycle of PWM

The fraction of a second that a signal or system is operational is called a duty cycle. A duty
cycle is usually expressed as a percentage or ratio. The amount of time a signal takes to
complete an ON-OFF cycle is called a period. The proportion of time a digital signal is on
throughout a period of time or interval is precisely described by the percentage duty cycle.
The waveform's time is equal to its inverse frequency.
Duty Cycle: On Time / On Time + Off Time
We would say a digital signal has a 50% duty cycle and looks like a perfect square wave if it
is on for half of the time and off for the other half. The digital signal spends more time in the
high state than the low state if the percentage is greater than 50%, and vice versa if the duty
cycle is lower than 50%. Here is a graph depicting the three scenarios.:

2.2 Duty Cycle of PWM

 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

A 100% duty cycle is equivalent to a 5 volt (high) voltage setting. Grounding the signal would
be equivalent to 0% duty cycle. PWM duty cycle is the ratio of the conduction time to the
duration of the half AC cycle defined by the frequency of the AC line Voltage .Time that
a periodic signal or waveform spends in the active or high state compared to the total time of
one complete cycle. It is often expressed as a percentage and is a critical parameter in various
applications, from controlling the brightness of the LEDs to regulating motor speed in robotics.
Calculating the Duty Cycle

Duty Cycle (%) = (Active Time / Period) * 100

2.3.2 Frequency of PWM

The Speed at which something occurs over a specific time period is known as its
frequency. In another way, the rate at which a vibration occurs that result in a wave, such as
radio, light, or sound waves; this rate is usually measured in seconds. It is easy to define a
frequency or period for regulating a particular servo. Data is currently transmitted over
communication channels using PWM's duty cycle in an unambiguous communication
system. PWM serves as a technique for converting high-frequency pulses into low-frequency
output signals.

Frequency: 1 / Time Period

2.3 Frequency of PWM

The frequency of a Pulse Width Modulation (PWM) signal refers to how often the signal
switches between high and low states. It's measured in Hertz (Hz) and is the inverse of the
PWM period (the time it takes for one complete cycle). The appropriate PWM frequency
depends on the specific application, but it often falls within a range of a few hundred Hertz to
several kilohertz. For example, servo motors typically operate at a frequency of 50 Hz, while
LED brightness control might use a higher frequency like 500 Hz.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

2.4Types of PWM

 Single-Pulse Width Modulation

 Multiple-Pulse Width Modulation
 Sinusoidal Pulse Width Modulation

2.4.1 Single-Pulse Width Modulation

A single pulse is produced at each switching cycle in single-pulse width modulation. The
average power applied to the load is controlled by varying the pulse's width. Single-PWM is
straightforward and simple to use, although it could have a larger harmonic content and be
unsuitable for applications that need precision control at low power levels.

2.4 Single Pulse Width Modulation

Single Pulse Width Modulation (SPWM) is a PWM technique where a single pulse is used per
half-cycle of the output voltage waveform to control the inverter output voltage. This is
achieved by varying the width of the pulse to achieve the desired output voltage.
2.4.2 Multiple-Pulse Width Modulation
In this method of pulse-width modulation, the harmonic content can be reduced using several
pulses in each half-cycle of output voltage. By comparing a reference signal with a triangular
carrier wave, the gating signals are generated for turning. on and turning-off of a thyristor, as
shown in Fig.1(a). The carrier frequency, fc, determines the number of pulses per half-
cycle, m,m, whereas the frequency of reference signal sets the output frequency, f0f0.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

The modulation index controls the output voltage. This type of modulation is also known as
symmetrical pulse width modulation (SPWM). The number of pulses NpNp per half-cycle is
found from the expression
Np=fc2f0=mf2−−−−−(1)
Np=fc2f0=mf2−−−−−(1)
Where mf=fcf0mf=fcf0 is the frequency modulation ratio. The variation of modulation index
(M) from 0 to 1 varies the pulse width from 0 to π/Npπ/Np and the output voltage from 0 to E
dc. For SPWM, the output voltage for single-phase bridge inverters is shown in Fig.1(b).

2.5. Multiple -Pulse Width Modulation

If P is the width of each pulse, the RMS output voltage can be obtained from the following
expression,
The general expression for various harmonics in the output voltage is obtained by deriving an
expression for a general pair of pulses, such the positive pulse of duration PP starts
at ωt=αωt=α and the negative one of the same width starts at ωt =π+α. ωt=π+α. This is shown
in Fig.1(b). The effects of all pulses can be combined together to obtain the effective output
voltage.

2.4.3 Sinusoidal Pulse Width Modulation

In Sinusoidal Pulse Width Modulation triangular carrier signal is compared with sine wave.
Figure below explains the generation of a sinusoidal PWM signal, which finds more
applications in industries. The gating signal can be generated by comparing a sinusoidal
reference signal with a triangular carrier wave and the width of each pulse varied proportionally
to the amplitude of a sine wave evaluated at the center of the same pulse. The output frequency
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

(fo) of the inverter can be found by using the frequency of the reference signal (fr). The rms
output voltage (vo) can be controlled by modulation index M and in turn modulation index is
controlled by peak amplitude (Ar). The voltage can be calculated by VO =Vs (S1- S4). The
number of pulses per half cycle depends on the carrier frequency. The gating signal can be
produced by using the unidirectional triangular carrier wave.

2.6 Sinusoidal Pulse Width Modulation

The SPWM mainly is employed in industrial applications and based on the comparison of
modulation and carrier signals. A sine wave (modulation signal, vm) is compared with two
triangular waveforms (carrier signals, vc1 and vc2) to generate PWM signals as shown in Fig.
2.4. It should be mentioned that this modulation scheme is only represented for the phase “a.”
To generate switching signals for the other phases, modulation signals should be shifted 120°
according to each other while using the same carrier signals. The frequency of the modulation
signal determines the output voltage frequency while the frequency of the carrier signals
determines the switching frequency. Furthermore, the amplitude of the output voltage is
determined by the amplitude of the modulation signal.

2.5 Applications

1. Motor Control:

PWM is used to regulate the speed of DC and AC motors by adjusting the duty cycle of the
pulse signal, effectively controlling the power delivered to the motor.
This allows for precise speed control without the need for complex analog circuits.

2. Lighting Control:

PWM is used to dim LEDs and other light sources by varying the duty cycle, creating the
illusion of different brightness levels.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

This is a common feature in LED lighting systems and displays.

3. Temperature Control:

PWM can be used to regulate the power delivered to heating or cooling elements, enabling
precise temperature control in systems like HVAC.
By varying the duty cycle, the power can be adjusted to maintain a desired temperature range.

4. Power Conversion:

PWM is used in power converters like DC-DC converters and inverters to efficiently transform
and regulate electrical power.
This is crucial in renewable energy systems, UPS, and other applications where power
conversion is needed.

5. Audio Amplification:

Class D audio amplifiers use PWM to efficiently generate high-quality audio signals,
minimizing heat generation and increasing efficiency.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Chapter-03

Cascaded H-Bridge Inverter

3.1 Introduction

The Cascaded H-Bridge (CHB) multilevel inverter is a widely used topology in power
electronics, especially in medium to high-power applications. It offers a modular structure and
improved output waveform quality by synthesizing a staircase waveform with reduced
harmonic distortion. Each H-Bridge cell generates three voltage levels using a separate DC
source, and when connected in series, the output voltage levels increase, enabling higher
voltage applications without requiring transformers. CHB inverters are popular in industrial
motor drives, renewable energy integration, and power quality control. The working principle,
mathematical modelling , advantages, and challenges of cascaded H-Bridge inverters.

Although the diode clamped multilevel inverter is commonly discussed in the literature,
there has been considerable interest in the series connected or cascaded H-bridge inverter
topologies. The primary advantage of this structure is its simplicity and that fewer or more H-
bridge cells can be cascaded in order to decrease or increase the voltage and power level
respectively. The main disadvantage of this topology is that each H-bridge cell requires an
isolated dc source. The isolated sources are typically provided from a transformer/rectifier
arrangement, but may be supplied.

Multilevel inverters have gained significant attention in power electronics due to their
ability to produce high-quality voltage waveforms and operate at high voltages without using
bulky transformers. Among various multilevel inverter topologies—diode clamped, flying
capacitor, and cascaded H-Bridge—the Cascaded H Bridge (CHB) stands out for its modularity
and simple design.A single phase CHB inverter consists of multiple H-Bridge cells connected
in series, where each H-Bridge is powered by an independent DC voltage source. By
appropriately switching these H-Bridge cells, a stepped output voltage is generated that
approximates a sinusoidal waveform. The number of output voltage levels increases with the
number of H Bridge cells, reducing Total Harmonic Distortion (THD) and improving power
quality.

A cascaded H-bridge multilevel inverter is a power electronics circuit that generates a

multi-level output voltage from a series of H-bridges, each powered by a separate DC source.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

The formula for the number of output voltage levels, m, is given by m = 2s + 1, where 's' is the
number of DC sources. This topology offers advantages like high output voltage levels, reduced
harmonic distortion, and modularity, but also has drawbacks like increased complexity and the
need for multiple DC sources.

3.2 Working Principle of Cascaded H-Bridge:

The Cascaded H-Bridge (CHB) inverter works on the principle of combining the outputs
of multiple H-bridge inverter cells (each powered by separate DC sources) in series to produce
a stepped multilevel AC output voltage. The AC output voltage is synchronised with
accumulation of the voltage levels generated by the dissimilar H-bridge type cells. Every single
-phase H-bridge cells produce three level voltages are Vdc, 0,Vdc by concerning the DC source
level to AC output levels. Each H-bridge can independently generate three voltage levels:

• +Vdc

•0

• –Vdc

A Cascaded H-Bridge (CHB) block is a fundamental building block in

multilevel inverters, used to generate a stepped waveform that approximates a sinusoidal
output. It's achieved by cascading multiple H-bridge modules in series, each fed by a separate
DC source. This allows for the creation of multiple voltage levels, improving the quality of the
AC output and reducing harmonic distortion.

A conventional grid-connected solar Photovoltaic (PV) inverter consists of Two-

Level or Three-Level configuration is not suitable for very high Power ratings and the size of
AC side filter required is high to maintain the power quality as per the grid codes. It is
inefficient in extracting maximum power as the tracking of maximum power point is carried
out for entire PV arrays connected together instead of independent MPPT of each PV array.
With a conventional PV inverter, the utilization factor is also very less, since the system will
be in idle state during night times or when the irradiation is weak. Hence a conventional solar
inverter consists of Two-Level or Three-Level inverter suffers from the following drawbacks
(a) Not suitable for very high Power Ratings (b) High filter size (c) Inefficient in harvesting
maximum power (d) Less utilization factor.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

In this study, the need for the multilevel inverter (MLI) to minimize the drawbacks of
the conventional inverter is discussed. Cascaded H-Bridge (CHB) configuration which is more
preferred for solar power applications where isolated input DC sources are available and for
STATCOM. Number of Levels: L=2n+1L = 2n + 1L=2n+1 Where: • LLL: Number of output
voltage levels n: Number of H-bridge cells per phase Maximum Output Voltage: V out , max
=n ⋅V dc V out ,max= n⋅ V dc Where: • Vdc V: DC source voltage of each cell •n: Number of
cascaded H-bridges • Line-to-Line Voltage in 3-Phase System • V ab=Va−Vb• V line
,rms=3⋅Vphase,rms • Output Voltage: • V out(t)=k=1∑nVk(t) • Where Vk(t) is the output
voltage of the H-Bridge.

3.1 Basic circuit of CHB.

3.3 Operation of CHB Inverter:

A CHB inverter is built by cascading multiple H-bridges, which are fed from independent
DC sources. A Series connection of multiple H-bridges results in multiple levels in the AC
voltage. With a series of connection of Two H-Bridges, 5-level CHB MLI is built. This inverter
generates AC output with 5-levels i.e. +2 V; +1 V; 0; −1V and −2V. Similarly, Series connection
of three H-bridge modules is required to build a 7-level system.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

This inverter generates AC output with 7-levels i.e. +3 V; +2 V; +1 V; 0; −1V; −2V; −3V.
Maximum number of levels possible with a cascaded inverter (with H number of bridges per
phase) is equal to 2 H +1 which is always an odd number [33]. A comparison study on four
different levels of CHB inverters i.e. Five, Seven, Nine and Seventeen level CHB inverters is
carried out. THD improves with higher output levels, but the complexity of the system
increases. Authors discussed on CHB MLI with equal and unequal DC Sources, PWM
techniques and then discussed on a hybrid CHB inverter configuration which requires only one
DC source. The present work is focused on a standard CHB inverter fed from identical DC
sources. Cascaded H-Bridge (CHB) inverter consists of individual low-voltage H-bridge
modules connected to separate DC sources to generate multiple output voltage levels (n).

3.2(a) Single phase 5-level cascaded inverter; (b) Single phase 7-level cascaded inverter

3.4. Redundancy and fault tolerant operation

In the case of failure in one H-Bridge of a CHB inverter, the system can continue its
operation by bypassing that particular module through internal switches or by using a bypass
switch. To enhance the availability and to improve the reliability of a CHB based PV-inverter,
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

a Fault tolerant operation has been used. CHB MLI based STATCOM with fault-tolerant feature
is presented. Switching Strategy to Bypass failed H-Bridge module through internal switches
or through external bypass switch is explained in next subsections.

3.4.1 One Switch Opened on Fault

The bypassing method during one switch open on fault Condition. Consider switch S1 is
opened on Fault, then by Switching ON devices S2, S4 and by Keeping Switch S3 in OFF
State; the H-Bridge can be bypassed. Similarly, if the device S2 is opened on fault, then by
switching ON devices S1, S3 and by keeping switch S4 in OFF State, The H-Bridge can be
bypassed. Switching strategy to bypass the H-Bridge during only one Switch open on the fault
is presented in Table 3.

Fig 3.3 (a) Bypassing H-bridge when one Switch Opened on Fault; (b) Bypassing H-bridge
when Two Switches Opened on Fault; (c) Bypassing H-bridge when one Switch shorted on
Fault; (d) Bypassing H-bridge when Two Switches shorted on Fault.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Bypass
Condition S1 S2 S3 S4
Switch
S1 open on
Open ON OFF` ON OFF
Fault
S2 open on
ON Open ON OFF OFF
Fault
S3 open on
OFF ON Open ON OFF
Fault
S4 open on
ON OFF ON Open OFF
Fault
Table 3.4.1. Switch states to bypass faulty H-Bridge when One Switch Opened on Fault.

3.4.2 Two switches opened on fault

Switching strategy to bypass the H-Bridge during Two Switches opened on the fault is shown
in Table 3. If two top switches or two bottom switches open due to a fault, then the H-Bridge
can be bypassed by keeping other healthy switches in ON state as shown in Fig. 7(b). In
remaining cases bypass switch to be operated for bypassing the H-Bridge.

Bypass
Condition S1 S2 S3 S4
Switch
S1, S2 open
Open Open OFF OFF ON
on Fault
S3,S4 open
OFF OFF Open Open ON
on Fault
S1, S4 open
Open OFF OFF Open ON
on Fault
S2, S3 open
OFF Open Open` OFF ON
on Fault
S2, S4 open
ON Open ON Open OFF
on Fault
S1, S3 open
Open ON Open ON OFF
on Fault
Table 3.4.2 . Switch states to bypass faulty H-Bridge when Two switches opened on fault.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

3.4.3 One Switch shorted on fault

Fig. 7(c) shows, the bypass method during one Switch Shorted on fault Condition. Consider
Switch S1 is shorted on Fault, then by switching ON device S3 and by Keeping Switches S2,
S4 in OFF State; the H-Bridge can be bypassed. Switching strategy to bypass the H-Bridge in
the case of remaining cases also shown in Table 3.4.3.

Bypass
Condition S1 S2 S3 S4
Switch
S1 shorted
Shorted OFF ON` OFF OFF
on Fault
S2 shorted
OFF Shorted OFF ON OFF
on Fault
S3 shorted
ON OFF Shorted OFF OFF
on Fault
S4 shorted
OFF ON OFF Shorted OFF
on Fault

Table 3.4.3 . Switch states to bypass faulty H-Bridge when One Switch shorted on fault.

3.4.4 Two Switches shorted on fault

Switching strategy to bypass the H-Bridge during Two Switches Shorted on the fault
is shown in Table 3. If two Top switches or two bottom switches Shorted due to a fault, then
the H-Bridge can be bypassed through the failed Switches as shown in Fig. 7(d). In remaining
cases, Bypass switch needs to be switched ON for bypassing the faulty H-Bridge.Bypass
switching technique for a 7-Level CHB MLI is simulated and different types of faults are
simulated to verify the operation.

Number of levels is seven, when all three H-bridges are healthy. Simulated a fault on H-
Bridge-1 of CHB and the reference AC output voltage is maintained constant. Output voltage
waveforms of CHB MLI after bypassing H-Bridge-1 Module is shown in Fig. 8(b). When one
H-Bridge is faulty, then the output voltage levels are reduced to five but the system continues
to operate hence the availability of the system is improved.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Condition S1 S2 S3 S4 Bypass Switch

S1, S2 Shorted on
Shorted Shorted OFF OFF ON
Fault
S3,S4 Shorted on
OFF OFF Shorted Shorted ON
Fault
S1, S4 Shorted on
Shorted OFF OFF Shorted ON
Fault
S2, S3 Shorted on
OFF Shorted Shorted` OFF ON
Fault
S2, S4 Shorted on
OFF Shorted OFF Shorted OFF
Fault

S1, S3 Shorted on
Shorted OFF Shorted OFF OFF
Fault

Table 3.4.3 . Switch states to bypass faulty H-Bridge when Two Switches shorted on fault.

3.4 Voltage Waveforms of 7-Level Cascaded inverter when all three H-Bridges are Healthy;
(b) Voltage Waveforms of 7-Level cascaded inverter after bypassing Faulty H-Bridge.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

3.5 Cascaded H-Bridge DC/AC Converter and its Harmonic Challenges

3.5.1 Cascaded H-Bridge Inverter Topology

A Cascaded H-Bridge (CHB) inverter consists of multiple H-bridge cells connected in series,
each capable of producing a step of the output voltage. The output voltage levels are generated
by controlling the switching of each H-bridge cell, and each cell operates from its own
independent DC source. In practice, a multilevel CHB inverter can have multiple levels of
output voltage, leading to a waveform closer to the ideal sinusoidal form when compared to
two-level inverters.

While CHB inverters have the advantage of reducing the voltage stress on individual switching
devices and improving efficiency in high-power applications, they can still introduce
harmonics at the output. This happens due to the high number of voltage levels and switching
transitions that can create low-frequency harmonics.

3.5.2 Low-Frequency Harmonics in CHB Inverters

The key issue with CHB inverters lies in the creation of low-frequency harmonics, especially
when dealing with the DC bus ripple and the interleaving of carrier signals used in
modulation techniques. These harmonics result from the high-frequency switching, which
may not perfectly cancel out due to the phase displacement between the different H-bridge
cells. This leads to the creation of harmonics at low-frequency multiples of the fundamental
switching frequency.

These low-frequency harmonics can be problematic, especially in the context of motor drive
systems, as they can lead to:

 Torque Ripple: Harmonics in the output waveform lead to irregular torque generation in the
motor, resulting in reduced performance and efficiency.
 Voltage Fluctuations: The motor’s voltage input can fluctuate, leading to motor vibration,
reduced speed regulation, and other performance issues.
 Increased Heating: Harmonic distortion can result in additional power losses in the motor and
the inverter, leading to overheating and increased maintenance costs.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Furthermore, these harmonics can also induce high-peak current pulses in the system, leading
to discontinuous current at the output. This results in:

 Increased Motor Wear: The high-peak current can lead to increased thermal and mechanical
stress on the motor, reducing its lifespan.
 System Instabilities: Discontinuous current spikes can lead to voltage instability in the
inverter, causing unpredictable performance and possible failure of the system.

3.6 CHB inverter for grid connected applications

The CHB configuration is ideally suited for PV Inverter and STATCOM applications.
CHB requires independent DC links and it can be achieved in these two applications without
any additional cost. The control of power flow through an inverter is based on below principle.
When two AC sources with same frequency are connected together, then.
a) Source which is having a leading phase angle provides active power to the other source.

b) Source which is having higher voltage amplitude provides Reactive Power to the other
source.

In Grid connected applications, one AC source is Grid and the other AC source is the output
of the inverter. Phase angle difference between the sources is controlled to regulate the real
power through inverter, similarly to control reactive power through inverter, the magnitude of
inverter output is controlled depending on the reference powers.
Controller for Grid connected PV system applications is realized through the Real-
time Digital simulator and interfaced with a single-phase 11-level, Cascade multilevel inverter.
A comparative study of Symmetrical and asymmetrical CHB multi-level Inverters is presented
through simulation results. A fifteen level CHB based PV power conditioning system is
presented in Ref. [46]. The presented system eliminates output filter and transformer.
Advantages of this system are more efficiency, more reliability and the lesser cost but the
system has the disadvantage of non-uniform duty cycles among H-bridges due to the use of
step modulation technique. In Ref. [47], Authors presented a hybrid twenty-seven level MLI
based on the asymmetric CHB configuration, its suitability for photovoltaic systems.
Due to the availability of independent DC sources in PV plants, CHB MLI is more
suitable for large-scale systems. Output side filter size and cost are less in the case of CHB
MLI. Independent MPPT of each PV array can be achieved through this inverter
configuration. Fig. 9 shows a General Structure of a CHB MLI based solar power conditioning
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

system. This system comprises of multiple H-Bridges connected to independent PV Arrays

through independent DC Breakers based on the Power requirement. Whenever the solar power
is available the DC Breaker is closed and the active power available at the solar array is pumped
to the Grid. A thorough review of active power control techniques for CHB based PV Inverters
is presented in Section-4.

Fig 3.5 Grid Connected CHB based Solar Inverter.

3.6 Advantages and Disadvantages of CHB:

3.6.1 Advantages:

 Reduced Voltage Stress:

Each switching device in a cascaded H-bridge experiences lower voltage stress

compared to a traditional two-level inverter.

 Improved Output Power Quality:

Multilevel inverters, like the cascaded H-bridge, produce a staircase-like output

voltage, resulting in lower harmonic distortion and improved output voltage quality compared
to two-level inverters.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

 Suitability for Renewable Energy Integration:

The modular design and scalability of cascaded H-bridges make them well-suited for
interfacing renewable energy sources with the grid.

 Flexibility and Modularity:

The modular structure allows for easy reconfiguration and maintenance in case of
faults.

3.6.2 Disadvantages:

 Multiple DC Sources Required:

Each H-bridge module requires a separate DC source, which can limit applications where
multiple DC sources are not readily available.

 Unequal Current Stress:

While voltage stress is reduced, current stress can be unevenly distributed among the
switching devices.

 Potential for Higher Switching Frequency:

In some configurations, achieving desired output voltage levels may require higher
switching frequencies, leading to increased switching losses.

 Higher Component Count:

Compared to two-level inverters, cascaded H-bridges require a larger number of

components, including switching devices and capacitors, which can increase the cost and size
of the inverter.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Chapter-04
Alternative Phase Opposition and Disposition

4.1 Introduction

In case of alternate phase disposition (APOD) modulation, every carrier waveform is in

out of phase with its neighbour carrier by 1800. Since APOD and POD schemes in case of
three-level inverter are the same, a five-level inverter is considered to discuss about the APOD
scheme. The rules for APOD method, when the number of level N = 5, are • The N – 1 = 4
carrier waveforms are arranged so that every carrier waveform is in out of phase with its
neighbour carrier by 1800. 39 • The converter switches to + Vdc / 2 when the reference is
greater than all the carrier waveforms. • The converter switches to Vdc / 4 when the reference
is less than the uppermost carrier waveform and greater than all other carriers. • The converter
switches to 0 when the reference is less than the two uppermost carrier waveform and greater
than two lowermost carriers. • The converter switches to - Vdc / 4 when the reference is greater
than the lowermost carrier waveform and lesser than all other carriers. • The converter switches
to -Vdc / 2 when the reference is lesser than all the carrier waveforms.

4.1: Switching pattern produced using the APOD carrier-based PWM scheme for a five-level
inverter
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

4.2 APOD Modulation Strategy

The Alternative Phase Opposition Disposition (APOD) is a variant of carrier-based

PWM techniques that has been widely studied for reducing harmonic distortion in multilevel
inverters. In APOD, multiple triangular carrier waves are employed, each phase shifted by a
specific angle to improve the harmonic performance. Unlike other conventional PWM
techniques, the APOD strategy arranges the carrier waves such that they alternate between
positive and negative phases, creating a symmetrical pattern that helps in the cancellation of
certain low-order harmonics. This modulation method is particularly effective in reducing low-
frequency harmonics such as the fifth, seventh, and eleventh order, which are common in
multilevel inverter systems.

APOD is specifically designed to minimize the harmonics by ensuring that the

carriers are alternately in opposite phases, which helps in balancing the harmonic spectrum and
reducing peak current levels. This technique is well-suited for high power and medium
voltage applications, where harmonic distortion and current ripple are significant concerns.
The main benefit of APOD lies in its ability to generate lower total harmonic distortion (THD)
at a relatively high modulation index while maintaining an efficient switching sequence.

4.2.1 Alternative Phase Opposition Disposition (APOD) SPWM

In APOD SPWM, the carrier signals for each phase of a multilevel inverter are
alternately in opposition to each other. This means that the phase difference between each
carrier in a multilevel inverter is alternated, which helps to spread the harmonics over a wider
frequency spectrum, reducing the low-order harmonics.

A. Carrier Waveform and Modulated Signal

The carrier waveform can be represented as a triangular wave, and the modulating
sinusoidal waveform is used to determine the switching instants. The general equations for
these signals are:

 Carrier Signal:

 𝐶 (𝑡) = 𝐴 ⋅ sign sin(2𝜋𝑓 𝑡 + 𝜙 )

where: Ac is the amplitude of the carrier waveform,
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

 fc is the frequency of the carrier waveform,

 ϕk , is the phase shift of the carrier signal, with each carrier ϕk being adjusted according to the
APOD strategy.

Reference Signal (Modulating Signal):

𝑀 (𝑡) = 𝐴𝑚 ⋅ sin(2𝜋𝑓𝑚 𝑡)

where:

o Am is the amplitude of the modulating signal,

o fm is the frequency of the modulating signal.

B. Switching Decision

In APOD SPWM, the phase opposition is used in selecting the switching instances of the
inverter. For each carrier signal Ck(t) the switching times are determined when the modulating
signal M(t) intersects with the carrier.

For a given level k, the switching instants are determined by solving the equation:

𝑀(𝑡) = 𝐶 (𝑡)

where Ck(t) is the phase-shifted carrier waveform for each level. The output voltage waveform
is constructed by switching the inverter at these instants.

C. Carrier Phase Shift

The phase shift for the carrier signals in APOD is given by:

𝜙 =± ,where:

k is the index of the carrier signal (for each level in a multilevel inverter),

 N is the number of levels in the inverter (e.g., N=5N = 5N=5 for a 5-level inverter).
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

For example:

 For a 5-level inverter, the carrier phase shifts would be:

 𝜙 = 0, 𝜙 = +𝜋/5, 𝜙 = −𝜋/5, 𝜙 = +2𝜋/5, 𝜙 = −2𝜋/5

4.3 Harmonic Mitigation in APOD SPWM

A. Total Harmonic Distortion (THD)

The Total Harmonic Distortion (THD) is a common metric used to evaluate the harmonic
content of the output waveform. For a multilevel inverter, the THD is defined as:

∑ 𝑉
THD =
𝑉

where:

 V1 is the amplitude of the fundamental component of the output voltage,

 Vn is the amplitude of the n-th harmonic component of the output voltage.

B. Selective Harmonic Elimination (SHE)

Selective Harmonic Elimination (SHE) is a technique used to eliminate specific harmonic

components from the output waveform by appropriately adjusting the modulation angles. In
the context of APOD SPWM, SHE can be applied by solving a system of equations to eliminate
particular harmonics.

The general equation for harmonic elimination in SPWM is:

4𝐴 sin(𝑘 ⋅ 𝜃)
𝑉 =
𝜋 𝑘

where:

 Am is the amplitude of the modulation signal,

 θ is the switching angle for each harmonic component,
 n is the harmonic order.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

For the n-th harmonic:

4𝐴 sin(𝑘 ⋅ 𝜃 )
𝑉 = =0
𝜋 𝑘

By adjusting θn, the nth harmonic can be eliminated.

C. Harmonic Injection for Cancellation

Harmonic injection aims to cancel specific harmonic components by introducing additional

harmonic frequencies into the system. For a given harmonic order n, the injected harmonic is
given by:

𝑉injected = 𝐴inj ⋅ sin(2𝜋𝑓 𝑡 + 𝜙 )

where:

 A inj is the amplitude of the injected harmonic,

 fn is the frequency of the nth harmonic to be cancelled,
 ϕn is the phase shift for the injected harmonic.

You can cancel out unwanted low-order harmonics by properly tuning the injected harmonic's
amplitude and phase.

D. Switching Frequency Optimization

The switching frequency fs is related to the harmonic spectrum of the output. To optimize
switching frequency and reduce THD, the following equation is used to calculate the optimal
switching frequency:

𝑓 =𝑘⋅𝑓

where fm is the modulation frequency, and k is an integer that optimizes the THD by selecting
a frequency that avoids resonance with dominant harmonic frequencies.

By adjusting the switching frequency fs in relation to the modulation frequency fm, you can
effectively reduce harmonic distortion.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

E. Filter Design for Harmonic Mitigation

To further reduce harmonic content, filters are often used. For a basic low-pass LC filter, the
transfer function H(s) is:

𝐻(𝑠) = , where:
/

 R is the resistance,
 L is the inductance,
 s is the complex frequency variable s=jω (where ω is the angular frequency of the harmonic).

By carefully designing filters to target specific harmonic frequencies, you can attenuate the
unwanted harmonics in the inverter output.

4.4 Mathematical Analysis of APOD SPWM

In this section, we will delve into the mathematical analysis of the Alternative Phase
Opposition Disposition (APOD) Sinusoidal Pulse Width Modulation (SPWM) technique.
This includes deriving the equations for the carrier signal, modulating signal, the switching
condition, the phase shift in the APOD method, and the output waveform generated by the
modulation technique.

1. Carrier Signal Representation

The carrier signal in SPWM techniques is typically a triangular or sawtooth waveform. In the
APOD SPWM method, these carriers are modulated with specific phase shifts to produce a
smoother output waveform with reduced harmonic content.

2.Triangular Carrier Signal:

The triangular carrier signal, Ck(t), for the k-th carrier in the APOD technique can be
represented as:

𝐶 (𝑡) = 𝐴 ⋅ sign sin(2𝜋𝑓 𝑡 + 𝜙 )

Where:
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

 Ac is the amplitude of the carrier,

 fc is the frequency of the carrier (which is typically much higher than the modulating signal
frequency),
 ϕk is the phase shift applied to the k-th carrier,
 t is time.

The sign function outputs a waveform that alternates between +Ac and −Ac, creating the
triangular shape.

4.Carrier Phase Shift:

The carriers in APOD are phase-shifted to create phase opposition. The phase shifts alternate
between consecutive carriers to produce a symmetric waveform. For the k-th carrier, the phase
shift is given by:

𝑘𝜋
∅ =±
𝑁

Where:

 N is the total number of carriers (which depends on the number of levels in the inverter),
 k is the index of the carrier signal, which ranges from 1 to N.

Thus, for a 5-level inverter with 5 carriers, the phase shifts would be alternated as:

𝜙 = 0∘ ,

𝜋
𝜙 =+ ,
5

𝜋
𝜙 =− ,
5

2𝜋
𝜙 =+ ,
5

2𝜋
𝜙 =−
5
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

This results in a set of carriers with alternating phase shifts that are oppositely phased with
respect to one another.

4. Reference Signal Representation

The reference signal, also known as the modulating signal, is typically a sinusoidal
waveform that determines the desired output voltage. The modulating signal is compared with
the carrier signals to generate the PWM signal. The modulating signal M(t) can be expressed
as:

𝑀(𝑡) = 𝐴 ⋅ sin(2𝜋𝑓 𝑡)

Where:

 Am is the amplitude of the modulating signal (typically determined by the desired output
voltage),
 fm is the frequency of the modulating signal (which is the desired output frequency of the
inverter),
 t is time.

The amplitude and frequency of the modulating signal control the characteristics of the output
waveform, with the modulating signal essentially shaping the envelope of the output.

5.Switching Condition for APOD SPWM

The switching condition for the APOD SPWM technique determines the moments when the
inverter switches between different voltage levels. In the standard SPWM technique, the
switching points occur when the modulating signal intersects the carrier signal. Similarly, in
APOD SPWM, the switching points are determined by the intersections between the phase-
shifted carriers and the modulating signal.

6.Condition for Switching:

A switching event occurs whenever the modulating signal M(t) intersects the carrier signal
Ck(t). Mathematically, this is represented as:

𝑀(𝑡) = 𝐶 (𝑡)
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Substituting the expressions for M(t) and Ck(t):

𝐴𝑚 ⋅ sin(2𝜋𝑓𝑚 𝑡) = 𝐴𝑐 ⋅ sign sin(2𝜋𝑓𝑐 𝑡 + 𝜙𝑘 )

This equation represents the condition for the inverter to switch from one voltage level to
another.

Analysis of Intersections:

 The intersections occur when the modulating sine wave intersects the triangular carrier wave
at specific instants in time. The phase shift ϕk changes the location of these intersections for
each carrier signal.
 For example, if the modulating signal intersects the carrier at a specific time t1, the inverter
will switch to a particular voltage level corresponding to the carrier signal’s state at that time.

7. Carrier Phase Shift in APOD

The carrier phase shift is the key feature of the APOD method that distinguishes it from other
modulation techniques. By alternating the phase shifts of the carriers, the APOD method aims
to spread the harmonic content over a broader range of frequencies, thereby reducing low-
order harmonic distortion.

8. Derivation of the Phase Shift:

The phase shift for the k-th carrier in the APOD method can be expressed as:

𝑘𝜋
∅ =±
𝑁

Where k is the index of the carrier, ranging from 1 to N, and N is the number of carriers used
for modulation (which is typically equal to the number of levels in the inverter).

This alternating phase shift ensures that the carrier signals are oppositely phased, thus
reducing harmonic content by spreading the switching events across a wider frequency range.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

The result is a smoother, more sinusoidal output waveform with lower total harmonic distortion
(THD).

9. Mathematical Derivation of the Output Waveform

The output voltage waveform of a multilevel inverter is determined by the switching instants,
which are, in turn, determined by the intersections between the modulating signal and the
carrier signals. To calculate the output voltage Vout(t) for a multilevel inverter, we need to
account for the voltage levels corresponding to each carrier’s state at the switching times.

9.1 Output Voltage Expression

The output voltage waveform for a multilevel inverter using APOD SPWM can be expressed
as:

𝑉𝑜𝑢𝑡 (𝑡) = 𝑉𝑘 ⋅ 𝐻 𝑀 (𝑡) − 𝐶𝑘 (𝑡)

𝑘=1

Where:

 Vk is the voltage corresponding to the k-th carrier (which is determined by the inverter’s DC
voltage and the number of levels),
 H(x) is the Heaviside step function, which is 1 if x>0 and 0 otherwise, representing the
switching logic,
 M(t) is the modulating signal,
 Ck(t) is the k-th carrier signal.
 Since the switching condition is determined by the intersection between the modulating signal
and the carrier signals, the output voltage is a step-wise function where the voltage level
corresponds to the state of the carrier at the moment of intersection.

10. Harmonic Analysis of the Output Waveform:

 The output waveform produced by APOD SPWM contains harmonics, which are a result of
the periodic switching events. To analyze the harmonic content, we typically use Fourier series
expansion. The fundamental component of the output is the desired sinusoidal waveform, but
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

higher-order harmonics arise due to the discrete nature of the switching transitions.By carefully
selecting the number of carriers and their phase shifts, the APOD technique reduces the low-
order harmonics, leading to a lower THD compared to traditional SPWM methods.

4.5 Advantages of APOD SPWM

The APOD SPWM technique offers several advantages, particularly in terms of harmonic
mitigation, voltage quality, and efficiency:

4.5.1 Reduced Harmonics:

 APOD reduces the amplitude of low-order harmonics, which are typically the most problematic
in terms of power quality. This is achieved by alternating the phase opposition between
adjacent carrier signals, which spreads the harmonic energy over a wider frequency range.
 The harmonic spectrum of an APOD-modulated inverter is shifted, and the lower-order
harmonics are significantly reduced compared to standard SPWM or carrier-based PWM
methods.

4.5.2 Improved Voltage Quality:

 The output waveform generated by APOD SPWM is smoother and closer to a pure sinusoidal
waveform compared to traditional modulation methods. This is because the phase opposition
spreads out the switching transitions, reducing the sharpness of voltage changes and
minimizing the ripple.
 This leads to higher-quality output voltage, reducing the need for additional filtering and
improving the overall performance of the inverter.

Higher Efficiency:

 By reducing the low-order harmonics, APOD SPWM minimizes the need for large passive
filters, which can consume power and reduce overall system efficiency.
 The technique also enhances the effective voltage utilization, which is particularly beneficial
in applications like renewable energy systems and motor drives, where efficiency is critical
for maximizing energy conversion.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Flexibility and Scalability:

 APOD SPWM is well-suited for multilevel inverters, where a higher number of voltage levels
can be easily accommodated by adding more carrier signals with appropriate phase shifts.
 This scalability makes APOD SPWM a good choice for high-power applications where both
efficiency and harmonic performance are paramount.

4.6 APOD’s Role in CHB Inverters

When applied to CHB inverters, APOD modulation offers the following advantages:

1. Harmonic Mitigation: By strategically arranging the carrier waves, APOD effectively reduces
low-frequency harmonics from the inverter output. This is critical for improving power quality,
especially in industrial motor drives and other high-power applications where harmonic
distortion can affect system performance and reliability.
2. Modularity: APOD can be easily implemented in the modular structure of CHB inverters,
where multiple H-bridge modules work together to synthesize the output voltage. The ability
to adjust phase opposition in each module allows for more efficient harmonic cancellation,
particularly in systems with a large number of output levels.
3. Reduced dv/dt Stress: APOD also helps in minimizing the dv/dt stress on the semiconductor
switches, which reduces the electromagnetic interference (EMI) and switching losses. This is
particularly important for high-voltage applications, where EMI can be a significant challenge.
4. Scalability and Flexibility: The ability to scale the number of output voltage levels easily with
the addition of more H-bridge modules in the CHB inverter allows APOD to adapt to various
power requirements. This makes it suitable for both low- and high-voltage applications, with
improved efficiency and reduced switching losses.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Chapter-05

Harmonics

5.1 Introduction:

5.1.1 Harmonics in Inverters

In electrical power systems, particularly in multilevel inverters, harmonics are unwanted

frequency components of the output waveform that are multiples of the fundamental frequency.
They arise due to the discrete nature of the switching events in the inverter and the inherent
nonlinearity of pulse width modulation (PWM) techniques.

In an ideal system, the output of the inverter would be a pure sinusoidal waveform. However,
due to the switching behaviour of the inverter, the waveform approximates a sinusoidal shape
but includes additional frequencies that cause distortion. The presence of these harmonics can
lead to several issues such as:

 Increased heat losses in motors and transformers,

 Electromagnetic interference (EMI),
 Reduced efficiency in power conversion,
 Voltage stress on components like capacitors and switches.

In Alternative Phase Opposition Disposition (APOD) Sinusoidal Pulse Width Modulation

(SPWM), the harmonic content of the output waveform is an essential parameter for evaluating
its performance. APOD SPWM is designed to reduce harmonic distortion compared to
conventional SPWM techniques by using phase-shifted carriers. This section explores the
mathematical analysis of harmonic content in the APOD SPWM technique and quantifies the
effect of these harmonics using the Total Harmonic Distortion (THD) measure.

5.2 Total Harmonic Distortion (THD) in Multilevel Inverters

5.2.1 Definition of THD

Total Harmonic Distortion (THD) is a measure of the distortion in a waveform caused by the
presence of harmonics. It is defined as the ratio of the sum of the powers of all the harmonic
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

components to the power of the fundamental component of the waveform. Mathematically,

THD is expressed as:

∑ 𝑉
THD =
𝑉

Where:

 V1V_1V1 is the amplitude of the fundamental frequency (the first harmonic),

 VnV_nVn is the amplitude of the nnn-th harmonic component,
 The summation extends over all harmonic components from the second harmonic (n=2n =
2n=2) to the ∞\infty∞-th harmonic.

The THD provides an overall measure of how much harmonic content is present in a signal
compared to the fundamental component. A lower THD indicates a higher-quality output
waveform that is closer to a pure sinusoidal shape.

In the case of multilevel inverters, where multiple voltage levels are used, the waveform can
approximate a sinusoidal shape more closely than traditional two-level inverters, reducing the
THD. However, even in multilevel systems, the modulation technique used (such as APOD
SPWM) can still affect the amount of harmonic distortion present in the output.

5.2.2 Harmonic Generation in Inverters

The harmonics in an inverter’s output waveform are generated due to the switching events that
occur when the inverter switches between different voltage levels. These switching transitions
are not smooth, leading to the generation of frequency components that are integer multiples
of the fundamental frequency.

In an inverter with a modulation technique like SPWM, the higher the modulation frequency
(i.e., the carrier frequency), the finer the voltage steps, and thus the closer the output waveform
is to a pure sinusoidal signal. However, a high carrier frequency also leads to higher switching
losses and can be limited by hardware constraints.

Multilevel inverters, on the other hand, have more voltage levels available, allowing them to
approximate a sinusoidal waveform more closely. By using advanced modulation techniques
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

like APOD SPWM, the inverter can further reduce the low-order harmonics that contribute
most to the THD.

5.3 Harmonics in APOD SPWM

The APOD SPWM technique is a variant of sinusoidal pulse width modulation (SPWM) in
which multiple carrier signals are phase-shifted to achieve better harmonic performance.
APOD SPWM achieves this by creating alternating phase opposition between adjacent
carrier signals. As a result, the switching transitions occur at different times for each carrier,
reducing the concentration of harmonic energy in lower-order frequencies and spreading it
across a broader range.

To Analyze the effect of APOD SPWM on harmonics, it is important to understand how the
phase-shifted carriers interact with the modulating signal and contribute to the overall harmonic
spectrum. The carrier phase shifts alter the timing of the switching events, which affects the
frequency components of the output waveform.

5.3.1 Harmonic Content in APOD SPWM:

The harmonic content of an APOD-modulated signal can be understood by examining the

Fourier series expansion of the output waveform. The output voltage Vout(t) for an APOD-
modulated inverter can be expressed as a Fourier series:

𝑉 (𝑡) = 𝑉 ⋅ sin(2𝜋𝑓 𝑡) + 𝑉 ⋅ sin(2𝜋𝑛𝑓 𝑡 + 𝜃 )

Where:

 V1 is the amplitude of the fundamental frequency component,

 Vn is the amplitude of the n-th harmonic,
 θn\theta_nθn is the phase angle of the n-th harmonic,
 fm is the frequency of the modulating signal (which determines the fundamental frequency).

The harmonics generated in an APOD-modulated multilevel inverter are a result of the

switching transitions between the different voltage levels. The phase-shifting of the carriers
helps distribute the harmonic energy over a wider frequency range, reducing the amplitude of
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

low-order harmonics (which are the most detrimental) and shifting the harmonic content to
higher-order frequencies.

5.3.2 Harmonics and Carrier Configuration:

In APOD SPWM, the number of carrier signals used (i.e., the number of inverter voltage levels)
plays a crucial role in determining the harmonic spectrum of the output. Increasing the number
of levels effectively increases the number of carrier signals and thus reduces the magnitude of
each harmonic component.

The phase shift applied to each carrier determines the timing of the switching events and affects
the frequency components of the output. When carriers are phase-shifted in opposition, the
resulting switching transitions spread the harmonic components across a wider range of
frequencies, thus reducing the concentration of low-order harmonics. The degree of harmonic
suppression depends on the number of carriers, the number of inverter levels, and the
modulation scheme used.

5.4 Mathematical Derivation of THD in APOD SPWM

To quantify the harmonic content in the APOD SPWM, we first need to calculate the individual
harmonic components and then derive the Total Harmonic Distortion (THD).

5.4.1 Fourier Series for APOD SPWM Output:

The output voltage Vout(t) of an APOD-modulated inverter is a sum of sinusoidal components

with different frequencies. As mentioned, we can represent it as:

𝑉 (𝑡) = 𝑉 ⋅ sin(2𝜋𝑓 𝑡) + 𝑉 ⋅ sin(2𝜋𝑛𝑓 𝑡 + 𝜃 )

Where:

 V1 is the amplitude of the fundamental frequency,

 Vn is the amplitude of the n-th harmonic,
 fm is the frequency of the modulating signal,
 θn is the phase shift of the n-th harmonic.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

5.4.2 Harmonic Amplitudes in APOD:

In the APOD method, the phase opposition between adjacent carriers reduces the magnitude of
lower-order harmonics (such as the 5th, 7th, etc.). The amplitude of each harmonic Vn depends
on the carrier frequency, the number of levels, and the specific characteristics of the phase
shifts.

The amplitude Vn of the n-th harmonic for the APOD-modulated inverter can be derived from
the Fourier series analysis of the output waveform. In general, the lower-order harmonics
(such as the 3rd, 5th, and 7th harmonics) are reduced due to the alternating phase shifts of
the carriers, which helps suppress them. The amplitude of the n-th harmonic is a function of
the number of levels in the inverter, the modulation index, and the carrier frequency.

5.4.3 Calculation of THD:Once the amplitudes of the harmonic components are known,
we can calculate the Total Harmonic Distortion (THD) as:

∑ 𝑉
THD =
𝑉

Where:

 V1 is the amplitude of the fundamental component,

 Vn is the amplitude of the n-th harmonic component,
 N is the highest harmonic to consider (usually limited to a finite number of harmonics based
on system specifications).

5.4.4 Impact of Carrier Configuration on THD:The carrier configuration (i.e., the

number of carriers and their phase shifts) in APOD SPWM directly affects the THD. As the
number of carriers increases, the output waveform becomes closer to a pure sinusoid, resulting
in a lower THD. Conversely, with fewer carriers (or fewer voltage levels in the inverter), the
harmonic distortion increases.

5.5 Harmonic mitigation property

Harmonic mitigation property of the proposed MCPWM technique is elaborated using a

set of switching angles (θj ) of the MCPWM pulse-train [24], i.e., θj ∈ (0, 2π), j = 0, 1, …, n;
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

where θj ≤ θj+1. Considering the proposed modulation strategy presented in Fig. 3, a five-level
staircase phase voltage waveform is obtained under variable switching angles as depicted in
Fig. 4. Here, θj must enumerate a set of (n + 1) equations as expressed in (3) and (4) to suppress
up to nth number of odd harmonics where, n = 5, 7, 11, …, k. Since the objective of this work
is to mitigate the non triplen order harmonics from the inverter output voltage, the value of n
is extended up to 11 for simplicity in the calculation.

Fig. 5.1. Proposed MCPWM generated five-level staircase voltage waveform.

The theoretical MI (m) of the voltage waveform (see Fig. 4) is presented in terms of Fourier
expansion series [27], as

4
𝑚= [sin𝜃 − sin𝜃 + sin𝜃 − ⋯ + (−1) sin𝜃 ]
𝑛𝜋

To mitigate the odd number of harmonics (3) can be reorganized as

4
0= [sin(5𝜃 ) − sin(5𝜃 ) + sin(5𝜃 ) − ⋯ + (−1) sin(5𝜃 )]
5𝜋

4
0= [sin(7𝜃 ) − sin(7𝜃 ) + sin(7𝜃 ) − ⋯ + (−1) sin(7𝜃 )]
7𝜋

4
0= [sin(11𝜃 ) − sin(11𝜃 ) + sin(11𝜃 ) − ⋯ + (−1) sin(11𝜃 )]
11𝜋

4
0= [sin(𝑘𝜃 ) − sin(𝑘𝜃 ) + sin(𝑘𝜃 ) − ⋯ + (−1) sin(𝑘𝜃 )]
𝑘𝜋

where, 0 < θ0 < ··· < θj < θj+1 < ··· < θn < 2π.

5.6 Harmonic Mitigation Algorithm

 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Fig. 5.2 Harmonic mitigation algorithm of the proposed MCPWM technique.

Fig. 5.1 presents the harmonic mitigation algorithm based on (3) and (4), which curtails
the harmonic percentage of the improved MCPWM strategy. Here, Mj symbolizes the
analytical Fourier series expanded value of MI. The ratio of the difference between theoretical
(m) and analytical (Mj) value of MI to the theoretical MI defines the harmonic error percentage
(ej ). With initial conditions, the proposed algorithm may allow some harmonic contents, but
the acceptable error percentage (ej ) is to be maintained at a permissible level which is below
the maximum percentage of a relative voltage level (Xj ) defined in the grid code [28]. Table
II lists the maximum voltage amplitudes of the odd non triplen order harmonics [25], [28],
which are used as the reference of this work. The set of (n + 1) equations determines the value
of j; and j belongs to the set (1, 5, 7, 11, 13, 17, 19, 23, 25, 29, 31, 35, 37, 41, 43, 47, 49) as the
grid code usually limit the value of j to 49 [25], [28]. Now, the problem is defined as an
optimization process that searches for a specific set of switching angles (θj ) over the
continuous interval (0, 2π) [27]. The analytical MI (Mj) is expressed in terms of Fourier
expansion series as
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

𝑀 = [sin𝜃 − sin𝜃 + sin𝜃 − ⋯ + (−1) sin𝜃 ].

The harmonic error percentage is presented as

𝑚−∣ 𝑀 ∣
𝑒 = × 100 ≤ 𝑋
𝑚

1 4
𝑒 = [sin(5𝜃 )sin(5𝜃 ) + sin(5𝜃 ) − ⋯ + (−1) sin(5𝜃 )] ≤ 𝑋
∣ 𝑀 ∣ 5𝜋

1 4
𝑒 = [sin(7𝜃 )sin(7𝜃 ) + sin(7𝜃 ) − ⋯ + (−1) sin(7𝜃 )] ≤ 𝑋
∣ 𝑀 ∣ 7𝜋

1 4
𝑒 = [sin(49𝜃 )sin(49𝜃 ) + sin(49𝜃 ) − ⋯ + (−1) sin(49𝜃 )] ≤ 𝑋
∣ 𝑀 ∣ 49𝜋

TABLE II

NONTRIPLEN ODD HARMONICS AMPLITUDE STANDARD [25], [28]

Harmonic Maximum
order allowable level
5 6
7 5
11 3.5
13 3
17 2

In order to have a negligible error, the objective of this algorithm is to find a solution close to
the theoretical one. Switching harmonic function (SHF) computes the switching angles (θ0,
θ1,..., θn) based on the pre-calculated online harmonic error (ej ) and total harmonic distortion
(THD) for a fixed value of j

𝑆𝐻𝐹(𝜃 , 𝜃 , … , 𝜃 ) = ∑ ∣ 𝑒 ∣ +∑𝑇𝐻𝐷 , 𝑗 = 1,2, … ,49

SHE-PWM [19], [20] and SHM-PWM [25] techniques provide worthy approaches in
reducing some of the selected harmonics but suffer from the issue related to the uncontrolled
noneliminated harmonics. Fast-converging optimization technique [19] is used to mitigate
these uncontrolled harmonics by varying the MI [28]; but, at the cost of sluggish voltage
response of the inverter. These noneliminated harmonics lead to the use of a tuned filter, which,
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

in turn, increases the weight, volume, and overall budget of the system. On the contrary to the
SHE-PWM technique, the number of switching angles can be increased with the proposed
algorithm to suppress a higher amount of harmonic contents. Moreover, the proposed algorithm
decreases the calculation burden in terms of iteration. When the conventional MCPWM [22]
needs to be computed for each value of m under a specific switching angle, the SHF of the
proposed algorithm is computed only once to cover the same value of m under the total range
of switching angles. This prominent feature helps to decrease the required memory capacity
hugely in a microcontroller for implementing the improved MCPWM technique since a look
up table is not required any more.

5.7 Harmonic Spectral Characteristics

The proposed MCPWM triggered CHB-MLI phase voltage presents a staircase voltage
waveform trend (see Fig. 4), where the initial switching angles (i.e., θ1 and θ2) control the time
duration of the low and high voltage levels, respectively. The analytical Fourier expanded series
of the phase voltages are expressed as a function of the switching angles in (9)–(11) [24]. Here,
Aj and ∅j represent the phase voltage amplitude and phase angle of the jth harmonic order,
respectively

⎧ 𝑉 (𝑡) = ∣ 𝐴 ∣ cos 𝑗𝜔𝑡 + 𝜙

⎪
⎪
⎪
2𝜋
𝑉 (𝑡) = ∣ 𝐴 ∣ cos[𝑗 𝜔𝑡 − +𝜙 ]
⎨ 3
⎪
⎪ 4𝜋
⎪ 𝑉 (𝑡) = ∣ 𝐴 ∣ cos[𝑗 𝜔𝑡 − +𝜙 ]
3
⎩

2𝑉
𝐴 = [cos(𝑗𝛽 ) + cos(𝑗𝛽 )]
𝑗𝜋

𝜋
− , 𝐴 >0
𝜙 = 𝜋2
, 𝐴 ≤0
2

Using (9)–(11), the Fourier expanded series of the line voltages are also obtained in the time
domain as
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

⎧𝑉 (𝑡) = ∣ 𝑉 ∣ cos(𝑗𝜔𝑡 + 𝜙 )
⎪
⎪
⎪
𝑉 (𝑡) = ∣ 𝑉 ∣ cos(𝑗𝜔𝑡 + 𝜙 )
⎨
⎪
⎪
⎪ 𝑉 (𝑡) = ∣ 𝑉 ∣ cos(𝑗𝜔𝑡 + 𝜙 )
⎩

2𝜋
𝑉 =∣ 𝐴 ∣ 2 − 2cos 𝑗
3

2𝜋
⎧ sin 𝜙 − sin 𝜙 − 𝑗
𝜙 = 3
⎪
⎪ 2𝜋
cos 𝜙 − cos 𝜙 − 𝑗
⎪ 3
⎪ 2𝜋 4𝜋
⎪ sin 𝜙 − 𝑗 − sin 𝜙 − 𝑗
𝜙 = 3 3
⎨ 2𝜋 4𝜋
cos 𝜙 − 𝑗 − cos 𝜙 − 𝑗
⎪ 3 3
⎪ 4𝜋
⎪ sin 𝜙 − 𝑗 − sin 𝜙
⎪ 𝜙 = 3
⎪ 4𝜋
cos 𝜙 − 𝑗 − cos 𝜙
⎩ 3

Equation (13) depicts that the line voltage module (Vj ) is composed of the phase voltage
amplitude (Aj ) multiplied with a term that is equal to zero when j = 3, 6, 9, …, 48; whereas
the phase angles (∅ab, ∅bc, ∅ca) of the line voltages are defined in (14). Now, the amplitude
of the fundamental (V1), fifth (V5), seventh (V7), and eleventh-order harmonics (V11) are
simply determined by (13) and formulated as

34𝑉𝑑𝑐
⎧ 𝑉1 = √ ⋅ [cos(𝜃1 ) + cos(𝜃2 ) ]
⎪ 𝜋
⎪ √34𝑉𝑑𝑐
⎪ 𝑉5 = ⋅ [cos(5𝜃1 ) + cos(5𝜃2 )]
5𝜋
⎨ √34𝑉𝑑𝑐
⎪ 𝑉7 = 7𝜋 ⋅ [cos(7𝜃1 ) + cos(7𝜃2 )]
⎪
⎪ √34𝑉𝑑𝑐
( ) ( )
⎩𝑉11 = 11𝜋 ⋅ [cos 11𝜃1 + cos 11𝜃2 ]

Fig. 6 displays the harmonic spectral characteristics of the phase voltage amplitude (%) at
fundamental, fifth-, seventh-, and eleventh-order harmonics under a wide range of switching
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

angles. The magnitude of the fifth-, seventh-, and eleventh-order harmonic of the proposed
MCPWM technique [see Fig. 6(b)– (d)] is limited between 0-4.5%, 0-4%, 0-3%, respectively;
whereas that of the fundamental [see Fig. 6(a)] ranges between 0% and 9%.

The eleventh-order harmonic spectrum spreads over a lower percentage of voltage

amplitude than the fifth- and seventh-order harmonics, which is complying with the theoretical
standard (see Table II). It clearly indicates the improvement of MCPWM in terms of harmonics
amplitude and also, it takes the benefit of defining a specific range of switching angles at the
lowest harmonic content. Besides, it can be observed that with the incremental changes in
switching angles, the lower-order harmonics have only a minor deviation in amplitude; which
holds a good parity between theoretical analysis and the simulation study.

(a)

(b)
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

(c)

(d)

Fig. 5.3. Voltage amplitude deviation for the variation of switching angles at m = 0.8: (a)
fundamental, (b) fifth harmonic, (c) seventh harmonic, and (d) eleventh harmonic.

5.7.1 Impact on Harmonics

The impact of dynamic carrier frequency modulation on harmonic mitigation can be analyzed
by looking at the Fourier transform of the output waveform. As the carrier frequency varies
with time, the higher-order harmonics are distributed over a wider frequency spectrum. This
results in a reduction in the amplitude of lower-order harmonics, leading to a reduction in
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

THD. The switching frequency modulation can be optimized to achieve the best harmonic
performance while avoiding excessive switching losses.

5.8 Proposed System:

The proposed technique effectively reduces harmonic content in the AC output voltage while
ensuring continuous output current with a reduced peak magnitude. A harmonic mitigation
algorithm is introduced, which adjusts the modulation index and switching frequency of the
semiconductor switches dynamically, based on the switching angles of the MCPWM pulse.

The main focus of this research is to mitigate the fifth, seventh, and eleventh-order
harmonics from the inverter's output voltage, by identifying a new range of switching angles
that result in the lowest possible amplitude for these specific harmonics. Additionally , the
paper presents an innovative approach to estimate the switching angles of the MCPWM pulse
train in real-time operation, without the need for solving complex nonlinear equations. This
technique offers advantages such as low-frequency harmonic mitigation, reduced processing
time, and minimal hardware requirements (using a medium-sized FPGA), providing an
effective balance between design complexity and performance.

Fig 5.4 21-Level Inverter

21-level inverter is a type of multilevel inverter used to convert DC power into AC with a
high-quality output waveform. Unlike traditional inverters that produce a two-level output
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

(typically +V and -V), a 21-level inverter generates an output voltage with 21 discrete steps,
which closely approximates a pure sine wave. This significantly reduces harmonic distortion,
improves power quality, and minimizes the need for bulky filters. One of the most common
topologies used to achieve 21 levels is the Cascaded H-Bridge (CHB) inverter, where multiple
H-bridge cells are connected in series, each contributing a portion of the output voltage. These
inverters are widely used in medium- and high-power applications such as solar energy
systems, industrial motor drives, and grid-connected inverters. While they offer advantages
like improved efficiency, lower electromagnetic interference, and reduced switching losses,
they also come with challenges such as increased complexity, higher component count, and
more sophisticated control requirements.

Fig.5.5 Input sequence of the APOD Method.

The "Repeating Sequence" blocks (Sequence7 to Sequence12) likely generate periodic

waveforms or reference signals, while the "Relational Operator" blocks (e.g., Operator15 with
"==" or Operator7 with "<=") compare "In1" against these sequences. The outputs (3, 2, 1, -1,
-2, -3) could represent the number of matches or the degree of phase alignment, with positive
values indicating in-phase conditions and negative values suggesting opposition or thresholds
exceeded. This setup could be used to detect phase relationships or trigger actions in
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

applications like audio cancellation or motor control, aligning with your past interest in those
areas

Fig 5.6 Main MATlab Circuit.

This diagram appears to be a Simulink model for a three-phase power system simulation, likely
focused on power electronics or electrical engineering. Here's a brief explanation:

 Discrete Power gui: Sets the simulation as discrete with a sample time of 50 µs,
managing the power system computations.

 Subsystems (Subsystem1, Subsystem2, Subsystem3): These likely contain control

logic or signal processing blocks (e.g., PWM generation or commutation commands)
connected via "Comm" inputs.

 Three-Phase V-I Measurement: Measures voltage and current across three phases (A,
B, C) of the system.

 Three-Phase Series RLC Load: Represents a load with resistance (R), inductance (L),
and capacitance (C) connected in series, simulating a realistic electrical load.

 Scopes (Scope1 to Scope7): Display various outputs, such as phase voltages, currents,
or control signals, for analysis.
Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

 Connections: The model integrates control inputs, power flow, and measurement
outputs, suggesting a study of load behaviour or inverter performance in a three-phase
system.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

CHAPTER - 6

SOFTWARE

6.1 MATLAB:

6.1.1 MATLAB:

MATLAB is a high-performance language for technical computing. It integrates

computation, visualization, and programming in an easy-to-use environment where
problems and solutions are expressed in familiar mathematical notation. Typical uses
include:

 Math and computation

 Algorithm development
 Data analysis, exploration, and visualization
 Scientific and engineering graphics
Application development, including graphical user interface building

MATLAB is an interactive system whose basic data element is an array that does
not require dimensioning. This allows you to solve many technical computing problems,
especially those with matrix and vector formulations, in a fraction of the time it would
take to write a program in a scalar noninteractive language such as C or FORTRAN.

The name MATLAB stands for matrix laboratory. MATLAB was originally
written to provide easy access to matrix software developed by the LINPACK and
EISPACK projects. Today, MATLAB uses software developed by the LAPACK and
ARPACK projects, which together represent the state-of-the-art in software for matrix
computation.

MATLAB has evolved over a period of years with input from many users. In
university environments, it is the standard instructional tool for introductory and
advanced courses in mathematics, engineering, and science. In industry, MATLAB is the
tool of choice for high-productivity research, development, and analysis.

MATLAB features a family of application-specific solutions called toolboxes.

Very important to most users of MATLAB, toolboxes allow you to learn and apply
specialized technology. Toolboxes are comprehensive collections of MATLAB functions
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

(M-files) that extend the MATLAB environment to solve particular classes of problems.
Areas in which toolboxes are available include signal processing, control systems, neural
networks, fuzzy logic, wavelets, simulation, and many others.

6.1.2 The MATLAB System:

The MATLAB system consists of five main parts:

6.1.2.1 Development Environment:

This is the set of tools and facilities that help you use MATLAB functions and
files. Many of these tools are graphical user interfaces. It includes the MATLAB desktop
and Command Window, a command history, and browsers for viewing help, the
workspace, files, and the search path.

6.1.2.2 The MATLAB Mathematical Function Library:

This is a vast collection of computational algorithms ranging from elementary

functions like sum, sine, cosine, and complex arithmetic, to more sophisticated functions
like matrix inverse, matrix eigenvalues, Bessel functions, and fast Fourier transforms.

6.1.2.3 The MATLAB Language:

This is a high-level matrix/array language with control flow statements,

functions, data structures, input/output, and object-oriented programming features. It
allows both "programming in the small" to rapidly create quick and dirty throw-away
programs, and "programming in the large" to create complete large and complex
application programs.

6.1.2.4 Handle Graphics:

This is the MATLAB graphics system. It includes high-level commands for two-
dimensional and three-dimensional data visualization, image processing, animation, and
presentation graphics. It also includes low-level commands that allow you to fully
customize the appearance of graphics as well as to build complete graphical user
interfaces on your MATLAB applications.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

6.1.2.5 The MATLAB Application Program Interface (API) :

This is a library that allows you to write C and FORTRAN programs that interact
with MATLAB. It include facilities for calling routines from MATLAB (dynamic
linking), calling MATLAB as a computational engine, and for reading and writing MAT-
files.

6.1.3 DEVELOPMENT ENVIRONMENT:

6.1.3.1 Introduction:

This chapter provides a brief introduction to starting and quitting MATLAB, and
the tools and functions that help you to work with MATLAB variables and files. For more
information about the topics covered here, see the corresponding topics under
Development Environment in the MATLAB documentation, which is available online as
well as in print.

6.1.3.2 Starting and Quitting MATLAB:

6.1.3.2.1 Starting MATLAB:

On a Microsoft Windows platform, to start MATLAB, double-click the MATLAB

shortcut icon on your Windows desktop. On a UNIX platform, to start MATLAB, type
matlab at the operating system prompt.

After starting MATLAB, the MATLAB desktop opens - see MATLAB Desktop.

You can change the directory in which MATLAB starts, define startup options including
running a script upon startup, and reduce startup time in some situations.

6.1.3.2.2 Quitting MATLAB :

To end your MATLAB session, select Exit MATLAB from the File menu in the
desktop, or type quit in the Command Window. To execute specified functions each time
MATLAB quits, such as saving the workspace, you can create and run a finish.m script.

6.1.3.3 MATLAB Desktop :

When you start MATLAB, the MATLAB desktop appears, containing tools (graphical
user interfaces) for managing files, variables, and applications associated with MATLAB.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

The first time MATLAB starts, the desktop appears as shown in the following
illustration, although your Launch Pad may contain different entries.

You can change the way your desktop looks by opening, closing, moving, and
resizing the tools in it. You can also move tools outside of the desktop or return them
back inside the desktop (docking). All the desktop tools provide common features such
as context menus and keyboard shortcuts.

You can specify certain characteristics for the desktop tools by selecting
Preferences from the File menu. For example, you can specify the font characteristics for
Command Window text. For more information, click the Help button in the Preferences
dialog box.

6.1.3.4 Desktop Tools:

This section provides an introduction to MATLAB's desktop tools. You can also
use MATLAB functions to perform most of the features found in the desktop tools. The
tools are:

6.1.3.5 Command Window:

Use the Command Window to enter variables and run functions and M-files.

6.1.3.6 Command History:

Lines you enter in the Command Window are logged in the Command History
window. In the Command History, you can view previously used functions, and copy and
execute selected lines. To save the input and output from a MATLAB session to a file,
use the diary function.

6.1.3.7 Running External Programs:

You can run external programs from the MATLAB Command Window. The
exclamation point character! is a shell escape and indicates that the rest of the input line
is a command to the operating system. This is useful for invoking utilities or running
other programs without quitting MATLAB. On Linux, for example,!emacsmagik.m
invokes an editor called emacs for a file named magik.m. When you quit the external
program, the operating system returns control to MATLAB.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

6.1.3.8 Launch Pad:

MATLAB's Launch Pad provides easy access to tools, demos, and

documentation.

6.1.3.9 Help Browser:

Use the Help browser to search and view documentation for all your Math Works
products. The Help browser is a Web browser integrated into the MATLAB desktop that
displays HTML documents.

To open the Help browser, click the help button in the toolbar, or type help
browser in the Command Window. The Help browser consists of two panes, the Help
Navigator, which you use to find information, and the display pane, where you view the
information.

6.1.3.10 Help Navigator:

Use to Help Navigator to find information. It includes:

 Product filter - Set the filter to show documentation only for the products you
specify.
 Contents tab - View the titles and tables of contents of documentation for your
products.
 Index tab - Find specific index entries (selected keywords) in the MathWorks
documentation for your products.
 Search tab - Look for a specific phrase in the documentation. To get help for
a specific function, set the Search type to Function Name.
 Favourites tab - View a list of documents you previously designated as favorites.
6.1.3.11 Display Panel:

After finding documentation using the Help Navigator, view it in the display
pane. While viewing the documentation, you can:

 Browse to other pages - Use the arrows at the tops and bottoms of the pages,
or use the back and forward buttons in the toolbar.
 Bookmark pages - Click the Add to Favorites button in the toolbar.
 Print pages - Click the print button in the toolbar.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

 Find a term in the page - Type a term in the Find in page field in the toolbar and
click Go.
Other features available in the display pane are: copying information, evaluating a
selection, and viewing Web pages.

6.1.3.12 Current Directory Browser :

MATLAB file operations use the current directory and the search path as
reference points. Any file you want to run must either be in the current directory or on
the search path.

6.1.3.13 Search Path :

To determine how to execute functions you call, MATLAB uses a search path to
find M-files and other MATLAB-related files, which are organized in directories on your
file system. Any file you want to run in MATLAB must reside in the current directory or
in a directory that is on the search path. By default, the files supplied with MATLAB and
MathWorks toolboxes are included in the search path.

6.1.3.14 Workspace Browser :

The MATLAB workspace consists of the set of variables (named arrays) built up
during a MATLAB session and stored in memory. You add variables to the workspace by
using functions, running M-files, and loading saved workspaces.

To view the workspace and information about each variable, use the Workspace
browser, or use the functions who and whos.

To delete variables from the workspace, select the variable and select Delete from
the Edit menu. Alternatively, use the clear function.

6.1.3.15 Array Editor :

Double-click on a variable in the Workspace browser to see it in the Array Editor.

Use the Array Editor to view and edit a visual representation of one- or two-dimensional
numeric arrays, strings, and cell arrays of strings that are in the workspace.This exactly
matches the numbers in the engraving. Once you have entered the matrix, it is
automatically remembered in the MATLAB workspace. You can refer to it simply as A.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

6.1.3.16 Expressions:

Like most other programming languages, MATLAB provides mathematical

expressions, but unlike most programming languages, these expressions involve entire
matrices. The building blocks of expressions are:

6.1.3.17 Variables:

MATLAB does not require any type declarations or dimension statements. When
MATLAB encounters a new variable name, it automatically creates the variable and
allocates the appropriate amount of storage. If the variable already exists, MATLAB
changes its contents and, if necessary, allocates new storage. For example, number
students = 25

Creates a 1-by-1 matrix named num_students and stores the value 25 in its single
element.Variable names consist of a letter, followed by any number of letters, digits, or
underscores. MATLAB uses only the first 31 characters of a variable name. MATLAB is
case sensitive; it distinguishes between uppercase and lowercase letters. A and a are not
the same variable. To view the matrix assigned to any variable, simply enter the variable
name.

6.1.3.18 Functions:

MATLAB provides a large number of standard elementary mathematical

functions, including abs, sqrt, exp, and sin. Taking the square root or logarithm of a
negative number is not an error; the appropriate complex result is produced
automatically. MATLAB also provides many more advanced mathematical functions,
including Bessel and gamma functions. Most of these functions accept complex
arguments. For a list of the elementary mathematical functions, type

For a list of more advanced mathematical and matrix functions, Some of the functions,
like sqrt and sin, are built-in. They are part of the MATLAB core so they are very
efficient, but the computational details are not readily accessible. Other functions, like
gamma and sinh, are implemented in M-files. You can see the code and even modify it if
you want. Several special functions provide values of useful constants.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

6.1.4 GUI:

A graphical user interface (GUI) is a user interface built with graphical objects, such as buttons,
text fields, sliders, and menus. In general, these objects already have meanings to most
computer users. For example, when you move a slider, value changes; when you press an OK
button, your settings are applied and the dialog box is dismissed. Of course, to leverage this
built-in familiarity, you must be consistent in how you use the various GUI-building
components.

Applications that provide GUIs are generally easier to learn and use since the person using the
application does not need to know what commands are available or how they work. The action
that results from a particular user action can be made clear by the design of the interface.

The sections that follow describe how to create GUIs with MATLAB. This includes laying out
the components, programming them to do specific things in response to user actions, and saving
and launching the GUI; in other words, the mechanics of creating GUIs. This documentation
does not attempt to cover the "art" of good user interface design, which is an entire field unto
itself. Topics covered in this section include:

6.1.4.1 Creating GUIs with GUIDE:

MATLAB implements GUIs as figure windows containing various styles of GUI control
objects. You must program each object to perform the intended action when activated by the
user of the GUI. In addition, you must be able to save and launch your GUI. All of these tasks
are simplified by GUIDE, MATLAB's graphical user interface development environment.

6.1.4.2 GUI Development Environment:

The process of implementing a GUI involves two basic tasks:

 Laying out the GUI components

 Programming the GUI components
GUIDE primarily is a set of layout tools. However, GUIDE also generates an M-file
that contains code to handle the initialization and launching of the GUI. This M-file provides
a framework for the implementation of the call backs - the functions that execute when users
activate components in the GUI.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

6.2 Simulink:

Simulink is a visual programming interface designed to make modelling systems

intuitive. It offers a way to solve equations numerically using a graphical user interface, rather
than requiring code.

Models contain blocks, signals and annotation on a background:

 Blocks are mathematical functions , they can have varying numbers of inputs and
outputs.
 Signals are lines connecting blocks, transferring values between them. Signals are
different data types, for example numbers, vectors or matrices. Signals can be
labelled.

 Annotations of text or images can be added to the model, and while not used in the
calculations they can make it easier for others to understand design decisions in the
model.
6.2.1 The Simulink Toolbar:Above the main canvas of a Simulink model, is the toolbar.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

6.2.2 Working with Blocks :8.2.2.1 Adding Blocks to Model:

There are two ways to add blocks to a model: the Library Browser or the Quick Search:

 Library Browser Shows all blocks available in Simulink, sorted by folders such as
‘Math Operations’ or ‘Signal Routing’. There is a search bar on the top left. Drag
blocks from the library straight onto your model canvas.
 Quick Search Directly search for blocks by single clicking on the background of
your model and typing in a search term. Select a block from the search results to
quickly add it to your model.
6.2.2.2 Automatic Block Input Box :

When adding a block to a model for the first time, the most common parameter will
often pop up automatically for a value to be specified.

6.2.2.3 Positioning Blocks :

 Blocks can be moved by simply clicking and dragging.

 Connect blocks by clicking output of one block and dragging it to an input of
another block.
 Once a signal connects two blocks, it can be clicked and dragged to be repositioned.
 To create a branch from an existing signal, hold ctrl while clicking and dragging.
 Blocks can be rotated/flipped for better positioning: Right click block, select “Rotate
& Flip”.
6.2.2.4 Overview of Libraries :
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

6.2.2.5 Block Settings :Each block has its own settings in Block Parameters and Block
Properties.

6.2.2.5.1 Block Parameters :

Double click on a block to open Block Parameters, where you change the settings for
that specific block.

6.2.2.5.2 Block Properties :

Right click and select “Properties…” to open

the Block roperties. This contains settings to do with
how the block works as part of the larger model. You
can change what information is displayed about the block in the
Block Annotation tab. For properties to be displayed under a block
in your model, move properties from the left to the right by using
the double arrow (>>).

You can also add your own text around the various %< Properties> %<BlockType> x0
= %<InitialCondition> m The example above shows how to display the block type and initial
condition to under an Integration Block.

6.2.3 Simulink Models & MATLAB Variables :

Simulink blocks can contain MATLAB variables. These variables need to be defined
in the MATLAB workspace before you run the Simulink model, otherwise an error will state
there is an undefined function or variable. Below c and zeta, in the gain block, are defined in
the MATLAB workspace. It is good practice to design a MATLAB script that sets up all the
parameters needed in your model. It is easier to change a variable in a script than to open many
block parameter menus in Simulink. It allows you to set up loops to run a simulation for many
values of c.

6.2.3.1 Model Annotation :

 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

6.2.3.1.1 Text and Image Annotation :

You can double click anywhere on the background of

your model and type a comment. Pressing Enter will

select the “Create Annotation” option of the quick

menu.

You can also use the shortcuts on the left to bring up the annotation tool. There are many
formatting options. You can insert

6.2.3.2 Text and images :

6.2.3.2.1 Greek letters:

Text typesetting: Right click text box, select Properties… and tick Enable Text Commands.

6.2.3.2.2 Signal Labelling :

The lines connected the blocks are called signals. By double-clicking directly on a signal you
can label it. This makes it easier to recall what the signals are, gives useful legend labels on
scopes and can be used when importing data into MATLAB.

 Display Menu – Useful for Debugging Errors

The Display Menu allows you to easily toggle
on and off information about your signals.

 Display > Signals & Ports > Port Data Types

Shows you the data type on each signal e.g. double or logical

 Display > Signals & Ports > Signal Dimensions

Shows you the dimensions of each signal e.g. [3 4] vector Useful if you have a
dimension mismatch error.

 Display > Sample Time > All

 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Colours each block to show the different sample times, this is particularly useful
when you obtain a sample time mismatch error.

 Display > Signals & Ports > Wide Non-scalar Lines

Gives different thicknesses to each signal that is actually a combination of
signals. Useful if you have a dimension mismatch error. This visualises Mux and Bus
signals.

6.2.3.2.3 Format Menu – Block Annotation :

By right-clicking on any block, you can select the Format menu to:

 Show/Hide Block Name

 Add foreground and background colours
 Add shadows to blocks

6.2.4 The Solver :

Most of the time, you can just use the default

settings to run your model. However you will sometimes
find that you will want the model to use smaller steps, or
fixed width steps. This is all configurable on the Solver page
of the Configuration Parameters. From the menu bar on
your model select Simulation ► Model Configuration
Parameters Or simply use the shortcut on the toolbar Once
opened, select Solver. There are many configurable settings.

 Start/Stop time: It is suggested that you leave the start time as zero. The stop time is
same as in the toolbar at the top of your model.
There are two types of solver:

 A variable step solver (the default): This will automatically adjust the step size as the
 model runs. If you are using variable step generally keep the default solver (ode45).
 Set the Max step size to a small fixed value to improve the smoothness of any plots.
 A fixed step solver will be necessary for models with discrete components. If it also
 has no continuous components, change the solver to Discrete (no continuous states)
 and set the step size to a known value. The fixed solvers are numbered in order of
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

 simplicity, ode1 being the simplest.

 Zero-crossing options: Under “Additional Parameters” you will find the Zero-
crossing options.
6.2.5 Sources Library:

Source blocks provide different signals for your model.

The simplest source is simply a Constant.

A block that outputs a constant value.

The Signal Builder allows custom signals to be built

using a graphical user interface.

For more typical periodic functions, see the table below with key blocks from this library:

6.2.6 Sinks Library:

The blocks in this library are mostly used for viewing data from the model.

Scope :

 Scope plots inputs against time.

 It has an extensive toolbar.
 The magnifying glass icon allows you to zoom in and
 out in the 𝑥 and 𝑦 direction simultaneously and
 individually.
 The hand allows you to pan or drag the plot around.
 The scaling icons allow you to automatically scale axes individually or simultaneously in
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

 the 𝑥 and 𝑦 directions.

The Cog icon opens a Configuration Menu. This allows you to set the:

 number of input ports layout of the plots ranges of the axes

legend enable data logging.

The Logging Tab contains a tick box to ‘Log data to workspace’. If this is enabled then
whenever the simulation is run, a variable is automatically populated in the MATLAB
workspace.

You can name the variable and set the datatype.

6.2.7 Data Logging without Scope: To Workspace Block :

Data can also be sent to the MATLAB workspace using a To Workspace

block. Any input to the block is sent to the MATLAB workspace after the model
has been run. The variable name by default is ‘simout’ but can be changed along with data
type.

Other Blocks in the Sinks Library :

6.2.8 Math Operations Library :

The blocks in this library relate to common mathematical functions.

6.2.8.1 Add, Subtract and Sum Blocks :

 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

The Add, Subtract and Sum blocks are all essentially the same. By changing the Icon shape
and List of signs in the block parameter you can convert one into the other.

6.2.8.2 Product and Divide Blocks :

The Product and Divide blocks are also interchangeable. You can use a list of asterisks and
forward slashes in the number of inputs block parameter to define operations Needed.

6.2.8.3 Gain Block :

The Gain block can be used to multiply a signal by a constant value. You must
configure the Block Parameters to perform matrix or element-wise (array)
multiplication.

6.2.9 Array and Matrix Multiplication :

Array multiplication with column vector 𝐾 = [ 1 2 ] and Matrix multiplication where 𝐾 = [ 5 7

6 8 ] .Both examples have Gain block configured to do Matrix(u*K) multiplication. For a Gain
block to contain a matrix or vector, simply use MATLAB notation. For example [ 5 7 6 8 ] is
entered as [5, 6; 7, 8] – commas separate row elements and semi colons separate columns.

6.2.10 Mathematical Functions :

There are lots of blocks for specific mathematical functions:

The Abs block finds the magnitude or absolute value of a

signal, the Unary Minus block negates a signal and the

Bias block adds a constant to a signal. The Sign block outputs +/- 1 depending on the sign of
the input.

There are also blocks with multiple functions to choose from:

The Math Function block can perform many different functions: square,

square root, log, reciprocal etc. A block parameter allows you to select which
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

particular function you want. The Trigonometric Function block operates in a similar manner
but for cos, sin, tan-1 etc.

6.3 MATLAB & Simulink Working Together:

While Simulink is useful for modelling and visualising processes such as feedback loops,
detailed data analysis and generation of good quality figures is still best completed within
MATLAB. You can run Simulink models and export the results to MATLAB or run Simulink
models from MATLAB.

6.3.1 Exporting Simulink Data to MATLAB:

There are multiple ways to get data from a Simulink to MATAB:

6.3.1.1 Scope Block: You can enabling data logging from a Scope
block within the Configuration Menu Logging tab.

6.3.1.2 To Workspace block:

Once this block is used in your model, each time you run your
model two variables are created in the MATLAB workspace:

 tout – column vector of time steps

 simout – variable storing simulation data
Use a Mux if you need more than one output.

The simulation data can be of type timeseries, array or structure, as set in ‘Save Format’
in Block Parameters. Accessing your data in MATLAB depends on the variable type you set.

6.3.2 Running Simulations from MATLAB :

You can also run your Simulink models using commands from MATLAB. The most basic way
is to use the sim command with two outputs and one input (the model file name as a string):

where t is a column vector of time steps and y is a corresponding matrix with columns of signal
data. The sim command can also be used with other inputs that allow the control of simulation
run time for example, but only one output must be assigned. The extra inputs are known as
‘name-valued pairs’ as a condition is specified and then the value set.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

CHAPTER-07

SIMULATION RESULTS

7.1 Voltage Waveforms:

Fig 7. R-Phase Voltage Waveform

Fig 7.1 Y-Phase Voltage Waveform

Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Fig 7.2 B-Phase Voltage Waveform

Fig 7.3 Three Phase Voltage Waveform

 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

7.2 Current Waveforms:

Fig 7.4 R-Phase Current Waveform

Fig 7.5 Y-Phase Current Waveform

Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Fig 7.6 B-Phase Current Waveform

Fig 7.7 Three-Phase Current Waveforms

 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Chapter-08

Conclusion

Cascaded H-Bridge (CHB) inverters, due to their multi-level topology, offer significant
advantages in high-power and high-voltage applications by reducing voltage stress on
switching components and improving system efficiency. However, they can introduce
challenges such as low-frequency harmonic distortion and discontinuous high-peak current,
which can negatively impact the performance of industrial motor drive systems. These issues
can result in torque ripple, reduced motor efficiency, and increased wear and tear on the motor,
ultimately affecting system reliability and operational costs.

The integration of Alternative Phase Opposition Disposition (APOD) Sinusoidal Pulse

Width Modulation (SPWM) serves as an effective solution to these challenges. By applying
phase opposition between the carrier signals, APOD SPWM helps to distribute the harmonic
content across higher frequencies and reduce the amplitude of low-frequency harmonics, which
are primarily responsible for torque ripple and current discontinuities. This modulation
technique significantly improves the output voltage waveform, leading to a smoother current
profile, reduced torque ripple, and enhanced motor performance.

Moreover, the application of APOD SPWM in Cascaded H-Bridge inverters not only
mitigates harmonic distortion but also optimizes the overall system efficiency, making it a
highly beneficial approach for motor drive systems. This approach ensures more stable
operation, extended motor life, and higher energy efficiency, thereby increasing the overall
reliability of industrial applications.

In conclusion, while CHB inverters in their basic form present challenges in motor drive
systems, the adoption of advanced modulation techniques such as APOD SPWM can
significantly enhance their performance, offering a robust solution for harmonic mitigation and
improved power quality. As industry demands for high-performance motor drives and energy-
efficient solutions continue to rise, the combination of CHB inverters and APOD SPWM will
likely become an increasingly popular choice for achieving optimal motor control and efficient
system operation.
 Improved Mul carrier PWM Technique for Harmonic Reduc on by using APOD method for
cascaded H-bridge DC/AC converters.

Chapter - 09
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