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Sessions

The document outlines a series of sessions focused on transistor analysis and simulation, including steps for small signal analysis, power sweep, and load pull techniques. It details the procedures for importing transistor files, adjusting circuit parameters, and verifying stability and performance metrics. Additionally, it emphasizes the importance of impedance matching and the effects of various configurations on amplifier performance.

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Neha Parmar
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0% found this document useful (0 votes)
6 views6 pages

Sessions

The document outlines a series of sessions focused on transistor analysis and simulation, including steps for small signal analysis, power sweep, and load pull techniques. It details the procedures for importing transistor files, adjusting circuit parameters, and verifying stability and performance metrics. Additionally, it emphasizes the importance of impedance matching and the effects of various configurations on amplifier performance.

Uploaded by

Neha Parmar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Session 1

Change frequency range from Project Options


Change unit in Project Options
First, we will check whether we have .S2p file.
If yes, then import from data files. Otherwise, import PDK and
select the relevant transistor file.
Import CGHV401000F transistor file in circuit schematic
Measurement Device>> IV Curve
Connect Gate to Step and Drain to Sweep
Source to gnd connection
Add graph
Non linear>> Current >> IV Curve >> Data source name: IV Curve
and Use for all x axis. Plot all traces

Change values of Vsweep and Vstep


Vsweep(VDS) see the values in datasheet: Absoulte maximum
Change values given in Electrical characterstics and verify the
typical VGS quiescent value is coming -2.7 or -2.6 V.

Now we will proceed for small signal analysis.


1. Add transistor file from library
2. Add Bias tee at input and output side
3. Add port 1 and 2 at input and output side.
4. Add DCVS to the DC point in bias tee.
5. RF & DC will be connected to input & Output of Transistor.
6. Change values of Input voltage of Transistor to -2.6 V and
Output voltage of transistor to 50 V. (As mentioned in electrical
characteristics.
7. Add graph >> Add measurements >> Linear>> S11 in dB and S21 in
dB.
8. Once check the units of Frequency and Power to be GHz and W.
9. S21 decreases with the frequency because at high frequencies,
the gain will reduce due to increase in parasitic effects.
10. The gain at 2.0 GHz should match with 17.5 dB as given in
datasheet. It will come when all the matching are done.

Session 2
System Diagrams: system level simulation and Budget level
simulation
Add circuit schematics
change units and frequency range from project options
1. IMport MLIN, MLEF (Closed form) and MTEE for junctions
*******MLEFX is EM based. It has already EM
simulation done.
MTEE has some three W values. Which are dependent on the
connecting MLIN. So if we change the value of Width of one MLIN
it will not automatically change the MTEE W value. So there is
another element, MTEE$. We will use this element of intelligent
value updation.

2. Add substrate and ports using element or right click on MLIN


and add model block.
3. Add graphs to see S21 and S11
4. Find W and L for certain frequency using TXLINE
5. Right click on Synthesis, click on W and L. Put values for Er,
Zo re and Zo im. It will automatically change values of W and L
after synthesis.

6. S11 drop is exactly not at 5 GHz, So use tuning or


optimization features to get proper results.
7. Use tuning feature and tune length parameter to get desired
results.
8. We can define the unit and frequency range for local files.
Right click on circuit schematic file>> options and change the
values.
9. We will use optimization tool to get a good bandwidth.
10. Add optimization goal from graphs or by right click on
particular measurement S11 or S21.
11. Simulate >> OPtimization>> Select Vars and put range. Start
Optimization
10. FOR EM SIMULATION
Scripts>> EM >> Create Stackup
For EM Simulation we need to have a Microstrip structure. MLIN>>
Help>> It will show closed form MLIN, it means only the equations
were solved and there is structure created.

Double click on Stackup>> Material definition, Add copper


material for gnd. In the dielectric layer, we can see the
substrate layer and air.
AXIEM simulator is used, So the side boundary will not matter. If
Analyst simulation is going to be used then side boundary will
matter.
Define the EM layer mapping.

Select the elements for EM simulation and click on properties.


Enable EM extract in Model options.
Xsize and YSize in EM extract: 1/5 to 1/10 of width of the Width
of microstrip line.
View the layout, remove red lines using Snap together.
Click on EM extract, add extraction. A new document will be
created in EM Extract Doc. Open that document. Now we can see the
ports assignment.

Free trace can be used to see the other results after changes.
The layout is fully connected then only the S11 and S21 will have
the proper results.

Session 3
1. In the datasheet the VDS voltage is given as 50 V and Class A
amplifier swings till 100 V. So VDS has to be applied with 100 V
for the class A amplifier.
2. The First step is to verify the Current by applying VDS and
VGS to the transistor.
3. Plot Transfer characteristics for VDS = 50 V and VGS will be
in x-axis.
4. Making sub circuit>> using in circuits of BIASTEE (Ideal
Biasing)
5. Use s2p file. To verify the S parameters results. Import S2p
file from data files.
6. Plot S parameters results again in the graph plot of biastee.
The results will be equal.
7. Now we will use power sweep for observing the transistor
behaviour for other high powers. The Normal linear S parameters
are calculated for the lower power (generally 0 dBm).
8. Therefore whenever Port_PS1 (power sweeping at port) is used,
Non linear S parameter to be used for visualizing the other
transistor behaviour at higher power (other than 0 dBm).
** As power increases the gain decreases. The power level at
which the gain reduces by 1dBm, that power is called as 1dB
compression point.
9. Check stability by using either B1, K. Mostly Mu1 is good to
use.
10. for stability check whether Mu1 > 1. In some cases Mu1 can be
greater than 1 but still be unstable. This thing we will verify
by Non linear stability>> Loop gain
11. We want to make the amplifier stable for large frequency
range.
12. First the transistor has to be stabilized then we will match
the transistor
13. The source of transistor connected to ground using a via. Via
has also an inductor. So via diameter decides this factor.
14. From tuning we found that decreasing inductor value,
stability is increased and increasing resistor stability is
increased.
15. Adding inductor and capacitor parallel to resistor at input
side. If the transistor resonate at 1.1 GHz, then reactance will
cancel. Then current will by pass the resistor.
Session 4
1. In the datasheet the VDS voltage is given as 50 V and Class A
amplifier swings till 100 V. So VDS has to be applied with 100 V
for the class A amplifier.
2. The First step is to verify the Current by applying VDS and
VGS to the transistor.
3. Plot Transfer characteristics for VDS = 50 V and VGS will be
in the x-axis.
4. Making sub circuit>> using in circuits of BIASTEE (Ideal
Biasing)
5. Use s2p file. To verify the S parameters results. Import S2p
file from data files.
6. Plot S parameters results again in the graph plot of bias tee.
The results will be equal.
7. Now we will use power sweep for observing the transistor
behavior for other high powers. The Normal linear S parameters
are calculated for the lower power (generally 0 dBm).
8. Therefore whenever Port_PS1 (power sweeping at port) is used,
Non-linear S parameter to be used for visualizing the other
transistor behavior at higher power (other than 0 dBm).
** As power increases the gain decreases. The power level at
which the gain reduces by 1dBm, that power is called as 1dB
compression point.
9. Check stability by using either B1, K. Mostly Mu1 is good to
use.
10. for stability check whether Mu1 > 1. In some cases Mu1 can be
greater than 1 but still be unstable. This thing we will verify
by Non-linear stability>> Loop gain
11. We want to make the amplifier stable for a large frequency
range.
12. First the transistor has to be stabilized then we will match
the transistor
13. The source of the transistor is connected to the ground using
a via. Via has also an inductor. So via diameter decides this
factor.
14. From tuning we found that with decreasing inductor value,
stability is increased and increasing resistor stability is
increased.
15. Adding inductor and capacitor parallel to a resistor at the
input side. If the transistor resonates at 1.1 GHz, then
reactance will cancel. Then the current will bypass the resistor.

***** LOAD PULL ******


Learning load and source pull
1. Scripts>>Load pull>> create load pull template
2. Read all the things present in the template
3. Scripts>>Load Pull>>select Load pull >> Generally, in an
amplifier the optimum impedance is left side of the smith chart
4. Number of harmonics = 1
5. Simulate. After simulation one file is going to be created in
the data file (LP_Data).
6. Graph>>Smith Chart>>G_LPC and G_LPCMMAX... select file
LP_Data... Data for contour: P_Load, Power sweep: plot all
traces.
7. Note that in license configuration, load pull is selected.
8. Select one frequency point and plot traces of power.
9. Mark the power value = 1
10. Change the marker notation by clicking on measurement result
block>> options>> markers>> reflection coefficient or real/
imaginary impedances or angle and degree impedances.
11. The output got in LPCM and LPCMMAX gives the optimum power
(19dBm) at the r, x. Change impedance to reflection coefficient.

Finding load and source side reflection coefficient For


transistor specification
12. load and source pull analysis, is the same process of finding
the reflection coefficient of the source side and load side.
13. See the datasheet of transistor and find the typical
performance, gain 15.8 dBi at 1.1 GHz, saturated power 30 and
drain efficiency 74.
14. After making stable system using inductor and
capacitor.dB(S21)=19.47 dB. This is small signal gain. Large
signal gain is 3-4 dB less. As per datasheet 30 W is the
saturated power. 30W = 44.7 dB. So input power will be 44.7-
16.47.
28.23 dB. Lets take 29 dB.
15. Neglect the gamma ranges while doimg load pull. Change the
input of the transistor from the stable inductor, capacitor and
resistor values. Change input and output voltage of transistor.
Generate source and load pull to find mag and ang of reflection
coefficient.
16. Check the obtained value of LCPmAX for PLoad and PSrc_del in
impedance. Source and Load Impedances for Application Circuit CGHV40030-AMP .
17. Change the value of reflection coefficient at input and
output side.
18. Check Nonlinear>>Power>> PT values. Compare with load pull
and without load pull
The total power is increased by 3 dB. Before source and load pull
impedance, it predicted power of 45 dBm at output but after
adding impedance, PT is going 46 dBm.
Large signal gain is the total power PT.
19. Change the circuit for Ideal PA design. Use Biastee, change
impedance of port 1 and port 2.
We will see Pgain, Pcom, Power Efficiency.
20. In later process, we will add matching network to match this
impedance to 50 ohms.
21. Small signal gain is 19.47 and after adding impedance from
source pull and load pull impedance. The large signal gain Pgain
is 17 dB.

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