Department of Electrical & Electronic Engineering

Bangladesh University of Engineering & Technology

EEE458 VLSI II Laboratory

Lab 5:
Design of a Two Stage CMOS Operational Amplifier and study of its dc and ac
characteristics using Cadence Virtuoso

Objectives:

 To design an un-buffered two stage CMOS Operational Amplifier with an n-channel input
pair
 To study the large signal dc characteristics of the Op-Amp
 To study the small signal characteristics of the Op-Amp

Lab 5-1. To write the specification of a two stage CMOS Op-Amp and to fix the
transistor sizes and bias currents from the level 2 model parameters of the NMOS
and PMOS transistors.

The design procedures of the Two-stage CMOS Op-Amp are described in great details in the book :
CMOS Analog Circuit Design, Second Edition by Philips E. Allen and Douglas R. Holberg,
OXFORD University Press. You are required to study section 6.3 Design procedure for the Two-
stage CMOS Op-Amps (Page 269-280) carefully and design the op-amp using typical NMOS and
typical PMOS transistors of the Analog library provided by Cadence.

Specification of the Op-Amp :

The specification of the of the Op-Amp is given below

Av> 5000 V/V VDD : 1.8 V VSS : -1.8 V

GB : 5 MHz CL: 10 pF SR > 10 V/µs
Vout range :  2V ICMR : -1 to 2 V Pdiss  2 mW

In this lab we will use tsmc 180nm pdk obtained under a Non-disclosure agreement signed between
BUET and TSMC. You must sign the student portion of the NDA and must not copy it or use it for
any purpose other than this lab and your project.
Create a new library named opamp and attach tsmc 180 nm process from the following library.
/home/cad/euromixed/33v/mixed33v/tsmc18
All NMOS are nmos3v and all PMOS are pmos3v used in the design.

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For the pre-lab use the typical NMOS and typical PMOS model sown below:

simulator lang=spice
* VTI-derived Level=2 nominal model
.model nmos4 nmos level=2 vto = 0.775 gamma=0.4 tox = 400e-10 nsub = 8e+15 xj = 0.15U ld =
0.20U u0 = 650 ucrit = 0.62e+5 uexp = 0.125 vmax = 5.1e+4 neff = 4.0 delta = 1.4 rsh = 36 cgso =
1.95e-10 cgdo = 1.95e-10 cj = 195U cjsw = 500P mj = 0.76 mjsw = 0.30 pb = 0.8

.model pmos4 pmos level=2 vto = -0.75 gamma=0.57 tox = 400e-10 nsub = 6e+15 xj = 0.05U ld =
0.20U u0 = 255 ucrit = 0.86e+5 uexp = 0.29 vmax = 3.0e+4 neff = 2.65 delta = 1.0 rsh = 101 cgso =
1.90e-10 cgdo = 1.90e-10 cj = 250U cjsw = 350P mj = 0.535 mjsw = 0.34 pb = 0.8

PRE_LAB : From the model parameters and with reference to Figure 6.3-2 of the Book CMOS
Analog Circuit Design by Philips E Allen, and Douglas R. Holberg design the various
components of the Op-Amp and fill up the table below. Please fill up the form before coming
to the Lab for this experiment. You will not be allowed to proceed further without completing
the PRE-LAB.

Parameters Equation/Criteria used to fix Design value

value
Compensation capacitor Cc
Steering current I5
Current Mirror Transistor size
(W/L)3 and (W/L)4
gm1
Input Pair Transistor size
(W/L)1 and (W/L)2
VDS5
Current source transistor size
(W/L)5, (W/L)8
gm6
Output stage load transistor size
(W/L)6
Output stage drive transistor
size (W/L)7

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 Vdd

1.8 V
W=7.5u W=7.5u W=67u
L=1u L=1u L=1u

30uA 3p
10p
W=3u W=3u
L=1u L=1u
1.8 V
W=4.5u W=4.5u W=14u
L=1u L=1u L=1u

Vss

Fig. Schematic of the two stage Op-Amp

Design of the Two Stage CMOS Operational Amplifier

The following figure show the Schematic diagram of the two stage Op amp. Please note that the
transistor dimension of your circuit may be different from that shown in the figure below.

1. Simulate the transfer characteristics of the Op-Amp.

Find the transfer characteristics of the Op-amp and determine the output offset voltage of the
amplifier. For this purpose set the voltage of the V+ terminal as a variable and then make a
coarse sweep of this variable form -1.8 Volts to +1.8 Volts and run a dc analysis to find the
values of Vin where the output makes the transition from VDD to VSS. Once the transition
range is found, Vin is swept over values that only include the transition region. Use the
following voltage specification for the V+ and the V- terminal.

V+ DC voltage : inp, AC magniture : 1 V

V- DC voltage: 0 , AC magintude: 0 V

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 From the transfer characteristics curve determine the output off-set voltage as well as the input
off-set voltage. You will find that the offset voltage is about 1.47 Voltage. Now adjust the
output PMOS transistor width to obtain almost zero offset.

Fig. Transfer characteristics of the Op-Amp

2. Frequency response of the Op-AMP

For this purpose we will perform the ac analysis in spectre. In the ac sweep use frequency as
a sweep variable, and vary the frequency from 10 kHz to 1 GHz. Set sweep type as automatic.
Now a plot of output voltage magnitude in V versus frequency in Hz will be plotted out.
However, we want to plot the output voltage in dB. For this purpose in the graph window
execute Tools → Calculator. The Virtuoso Visualization and Analysis Calculator window
will appear as follows. In the calculator window execute Options → Algebric. Now double
click the dB20 function and it will appear in the evaluation window.

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 Now Click the vf variable to select the ac voltage expression. The cursor will automatically
move to the virtuoso schematic window. Now select the voltage Vout in the schematic
window and it will be automatically loaded to the expression. You need to close the bracket
of the expression manually. Now the expression is ready to be plotted. In the calculator
window execute Tools → plot. The output voltage Vout in dB versus frequency curve will
be plotted.

Fig. Frequency response of Output Voltage

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 From the graph determine the location of the dominant pole and the gain band width (GB) of
the amplifier. Also determine the phase margin and the gain margin of the amplifier from the
calculator. You can find the gainBWProd, PhaseMargin and the GainMargin in the special
function of the calculator.

3. simulation of Common Mode Rejection Ratio

The objective of this simulation is to get an output that is equal to CMRR or can be
related to CMRR. The following figure shows a method that can accomplish this objective.
Two identical voltage sources designated as Vcm are placed in series with both op amp inputs
where the op amp is connected in the unity gain configuration. To accomplish this first create
a symbol of the Op-Amp and then connect it as shown below. For this circuit it can be shown
V 1
that out 
Vcm CMRR
The amplifier CMRR is measured by observing how the voltage offset changes as the input
ommon-mode voltage at the amplifier’s input stage changes. Similarly you can measure the
PSRR by changing the power supply voltages and how the voltage offset changes.

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 Fig. Set-up for the simulation of the CMRR

The equivalent circuit of the op-amp is as shown below from where we can derive CMRR.

The frequency response of CMRR is given in figure below.

Fig. Frequency response of (CMRR)

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4. Simulation of PSRR+ and PSRR-
Similarly the circuit model shown below is used to measure power supply rejection ratio (PSRR).
Here we obtain PSRR+ (VDD/Vout) as Vdd/Vout and PSRR- (VSS/Vout) as Vss/Vout.

To simulate PSRR we could use the xf analysis in spectre. With the xf analysis, you'd specify the
frequency sweep and the output of the circuit. Then after simulation, you could use the direct plot
form and find the transfer function from Vdd to the output for PSRR+ and Vss to the output for
PSRR- from your single simulation run.
The circuit diagram of the test cell is shown below. The output Vout is shorted to V+ with a 0.1 ohm
resistor in series to avoid SPICE connection problem.

The PSRR+ is shown below

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Similarly PSRR- is shown below:

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5 Creating Schematic Driven Layout using Virtuoso XL (VXL)
1. Open the schematic of the opamp cell you have generated in previous lab using virtuoso
schematic editor. Here delete all the power sources such as vdd and vss etc. Now replace the
3pF capacitor from analog library with mimcap_2p0_sin and load capacitor with
mimcap_2p0_sin.
2. Next, you need to invoke Layout XL from the schematic editor. Execute Launch Layout
XL A schematic window dialog will pop up and ask you to define connectivity reference.
3. Now go back to the Virtuoso Layout Editor to create layout view for this schematic. At the
left most side of the bottom of the layout editor you will see Generate from source. Click this
icon. The following pop-up window will appear:

4. The initial pin and transistor placement in layout will look like this:

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After option  Display  Display level is changed to 32 you will see as below.

After rearranging the transistor we can come out with a convenient layout like below:

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Now complete the wiring and perform DRC and LVS.

6 Parasitic Extraction.

Now perform Parasitic extraction from the layout and run SPECTR SPICE with the parasitic
included in the net list. For this purpose you need to execute QRC  Setup Quantus QRC

Report :
1. Provide the circuit diagram and performance curves of the circuits
2. Compare in a table the design specifications with the simulated specifications.
3. Discuss about the discrepancy between the design specifications and the simulated
specifications.
4. Simulate the design at fast fast and slow slow corner and compare the specification again.

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