MICROPROCESSORS AND

MICROCONTROLLERS (BECE204L)
DR. VIVEK RAJPOOT
ASSISTANT PROFESSOR SG-1
SCHOOL OF ELECTRONICS ENGINEERING (SENSE)
VELLORE INSTITUTE OF TECHNOLOGY, VELLORE
Generalized Block Diagram ✓ controls the computer
and performs all
ALU performs arithmetic and Communication through calculations.
logical operations on the data I/O Port/Bus
received from an input device ✓ ability to perform
or memory various operations
quickly

Register array consists of

registers identified by
letters like B, C, D, E, H, L,
and accumulator.

Control unit controls the

instructions and flow of
data within the computer
stores programs and data
required by the processor
8085 Microprocessor: A brief study
8 bit NMOS MICROPROCESSOR USED IN MANY MOBILES, WASHING MACHINES ETC.

Pin Diagram

Architecture
MODULE 2: MICROPROCESSOR ARCHITECTURE AND INTERFACING:INTELx86
16 bit Microprocessor:8086
▪ Enhanced version of Intel 8085 microprocessor. It 8085 8086
was designed by Intel in 1978.
8 bit data bus, 16 bit address line 16 bit data bus, 20 bit address line

▪ 16-bit, N-channel, HMOS microprocessor. Where the 5 Flags and 64 KB memory capacity 9 Flags and 1 MB memory capacity
HMOS is used for "High-speed Metal Oxide
Semiconductor“
Does not support memory Supports memory segmentation,
▪ Built on a single semiconductor chip and packaged in segmentation, maximum or maximum or minimum mode &
a 40-pin IC package. The type of package is DIP (Dual minimum mode & pipelining pipelining
Inline Package) Accumulator based General Purpose Registers based

▪ Uses 20 address lines and 16 data- lines. It can

directly address up to 2^20 = 1 Mbyte of memory One Processor used An additional external processor can
also be employed.

▪ Consists of a powerful instruction set, which provides Low Cost High Cost
operation like division and multiplication very quickly.

▪ Designed to operate in two modes, i.e., Minimum

and Maximum mode
 Architecture of 8086
➢ Receives opcode of an instruction from Independent Functional Units with parallel operation
the queue, decodes it and then executes it
➢ While Execution, unit decodes or executes
an instruction, then the BIU fetches
instruction codes from the memory and
stores them in the queue

Data Registers

Pointer Registers
Segment
Index Registers Registers

Instruction Pointer

6 bit instruction queue

➢ Handles transfer of data and addresses

➢ Fetches instruction codes, stores fetched instruction
codes in first-in-first-out register set called a queue
➢ Relocates addresses of operands
➢ Reads/Writes data from/to memory and I/O devices
Makes the processor faster
Bus Interface Unit
▪ Instruction Queue: When EU executes instructions, the BIU gets 6-bytes of the next instruction and stores them in the
instruction queue and this process is known as instruction pre fetch. This process increases the speed of the processor.
▪ Segment Registers: A segment register contains the addresses of instructions and data in memory which are used by the
processor to access memory locations. It points to the starting address of a memory segment currently being used.
▪ Instruction Pointer (IP): It acts as a program counter. It indicates to the address of the next instruction to be executed

16 bit register. Holds instruction codes of a program and base address of memory segment
16 bit register. Data, variables and constants given in the program and logical address of memory segment are held
❑ 16 bit register. Holds addresses and data of subroutines. Holds the contents of registers and memory locations
given in PUSH instruction and offset address of memory segment
16 bit register. Holds the destination addresses of some data of certain string instructions and starting address of memory
segment

Generation of 20 bit physical address from IP

Execution Unit
▪ General Purpose Registers: There are four 16-bit general purpose registers: AX (Accumulator Register), BX (Base Register), CX (Counter)
and DX.
➢ Accumulator is involved in most of the I/O and string operations and in operations such as Div,Mult,Shift,Rotate etc.
➢ Base Register can be used as memory pointer in data segment
➢ Counter Register is default counter in loop instructions,string manipulations and used in shift/rotate instructions
➢ Data Register is used in Div,Mult instructions to hold higher word of 32 bit operand and result respectively. Also remainder in Div.

▪ Index Register:Stack Pointer (SP),Base Pointer (BP),Source Index (SI),Destination Index (DI).Hold offset or logical address within a
segment.16 bit

▪ ALU: It handles all arithmetic and logical operations. Such as addition, subtraction, multiplication, division, AND, OR, NOT operations

▪ Flag Register: 16 bit register which exactly behaves like a flip-flop, means it changes states according to the result stored in the
accumulator. It has 9 flags and they are divided into 2 groups i.e. conditional and control flags
8086 Pin Diagram ✓ BHE/S7 (Output): Bus High Enable/Status.
During T1, it is low. It enables the data onto the
most significant half of data bus, D8-D15. 8-bit
➢ AD0-AD15:Low order address device connected to upper half of the data bus
bus. They are multiplexed with use BHE signal. It is multiplexed with status
data. When used to transmit signal S7. S7 signal is available during T3 and T4.
memory address, the symbol A ✓ RD (Read): For read operation. It is an output
is used instead of AD signal. It is active when LOW.
✓ Ready (Input): The addressed memory or I/O
sends acknowledgment through this pin. When
➢ A16-A19 (Output): High
HIGH, it denotes that the peripheral is ready to
order address lines. These
transfer data.
are multiplexed with status
✓ RESET (Input): System reset. The signal is active
signals
HIGH.
➢ A16/S3, A17/S4: A16 and A17 ✓ CLK (input): Clock 5, 8 or 10 MHz
are multiplexed with segment
identifier signals S3 and S4. ❑ INTR: Interrupt Request.
❑ NMI (Input): Non-maskable interrupt request.
➢ A18/S5: A18 is multiplexed with ❑ TEST (Input): Wait for test control. When LOW the
interrupt status S5. microprocessor continues execution otherwise
waits.
➢ A19/S6: A19 is multiplexed with ❑ VCC: Power supply +5V dc.
status signal S6 ❑ GND: Ground

Minimum Mode: One 8086 CPU is to be used

Maximum Mode: Multiprocessor system
Addressing Modes in 8086
▪ The way for which an operand is specified for an instruction in the accumulator, in a general purpose register or in memory location, is called
addressing mode/Data Addressing Mode

▪ 8086 microprocessors have 8 addressing modes. Of these, two addressing modes have been provided for instructions which operate on register
or immediate data
▪ Register Addressing: Operand is placed in one of the 16-bit or 8-bit general purpose registers (Source). Ex. MOV AX, CX, ADD CX, DX
▪ Immediate Addressing: Operand is specified in the instruction itself. Ex. MOV AL, 35H

▪ 6 addressing modes specify the location of an operand which is placed in a memory

▪ Direct Addressing: Effective address (Operand's offset) of the memory location is written directly in the instruction.. Ex. ADD AL, [0301]
▪ Register Indirect Addressing: Operand's offset is placed in any one of the registers BX, BP, SI or DI as specified in the instruction.
Ex. MOV AX, [BX]
▪ Based Addressing: Operand's offset is the sum of an 8-bit or 16-bit displacement and the contents of the base register BX or BP. BX is used
as base register for data segment, and the BP is used as a base register for stack segment. Ex. MOV AL, [BX+05]; (8-bit)
Effective address (Offset) = [BX + 8-bit or 16-bit displacement].
▪ Indexed Addressing: Offset of an operand is the sum of the content of an index register SI or DI and an 8-bit or 16-bit displacement. Ex.
MOV AX, [SI + 1528H]; (16-bit displacement).
▪ Based Indexed Addressing: The offset of operand is the sum of the content of a base register BX or BP and an index register SI or DI. Ex.
ADD AX, [BX + SI]
▪ Based Indexed with Displacement: Operand's offset is given by adding the base register contents

Effective Address (Offset) = [BX or BP] + [SI or DI] + 8-bit or 16-bit displacement
Ex. MOV AX, [BX + SI + 05]; 8-bit displacement
Address Addressing Modes in 8086

▪ These indicates the branch address in CALL and JUMP Instructions. Used for Control Transfer Instructions

Addressing Mode

Intersegment
Intrasegment

Direct Indirect
Direct Indirect
Memory Segmentation in 8086
▪ Process in which the main memory of the computer is logically divided into different segments and each segment has its own base
address
▪ To enhance the speed of execution of the computer system, so that the processor is able to fetch and execute the data from the
memory easily and fast.
▪ BIU contains four 16 bit special purpose registers called as Segment Registers
▪ Code segment register (CS): Used for addressing memory location in the code segment of the memory, where the executable
program is stored.
▪ Data segment register (DS): Points to the data segment of the memory where the data is stored.
▪ Extra Segment Register (ES): Also refers to a segment in the memory which is another data segment in the memory.
▪ Stack Segment Register (SS): Used for addressing stack segment of the memory. The stack segment is that segment of memory
which is used to store stack data.
▪ To enhance the speed of execution of the computer system, so that the processor is able to fetch and execute the data from the
memory easily and fast.
▪ BIU sends 20bit address, so as to access one of the 1MB memory locations
▪ Four segment registers actually contain the upper 16 bits of the starting addresses of the four memory segments of 64 KB each with
which the 8086 is working at that instant of time. May be up to 64 kilobytes long
▪ 8086 does not work the whole 1MB memory at any given time. However, it works only with four 64KB segments within the whole
1MB memory.
▪ Starting address will always be changing. It will not be fixed.
Memory Segmentation in 8086
Types of Segmentation
➢ Overlapping Segment – A segment starts at a particular address and its maximum size can go up to 64kilobytes. But if another
segment starts along with this 64kilobytes location of the first segment, then the two are said to be Overlapping Segment.
➢ Non-Overlapped Segment – A segment starts at a particular address and its maximum size can go up to 64kilobytes. But if another
segment starts before this 64kilobytes location of the first segment, then the two segments are said to be Non-Overlapped Segment

Rules of Segmentation
➢ The starting address of a segment should be such that it can be evenly divided by 16.
➢ Minimum size of a segment can be 16 bytes and the maximum can be 64 kB

Advantages of Segmentation
➢ It provides a powerful memory management mechanism.
➢ Data related or stack related operations can be performed in different segments.
➢ Code related operation can be done in separate code segments.
➢ It allows to processes to easily share data.
➢ It allows to extend the address ability of the processor, i.e. segmentation allows the use of 16 bit registers to give
an addressing capability of 1 Megabytes. Without segmentation, it would require 20 bit registers.
➢ It is possible to enhance the memory size of code data or stack segments beyond 64 KB by allotting more than
one segment for each area
8086 Instruction Format
The opcode/addressing mode byte(s) may be followed by :
❑ No additional byte
❑ Two byte EA (For direct addressing only).
❑ One or two byte displacement
❑ One or two byte immediate operand
❑ One or two byte displacement followed by a one or two byt
immediate operand
❑ Two byte displacement and a two byte segment address (for direc
intersegment addressing only)

8086 Instruction Format vary from 1 to 6 bytes in length

8086 Instruction Format
Most of the opcodes in 8086 has a special 1-bit indicates
▪ W-bit : Some instructions of 8086 can operate on byte or a word. The W-bit in the opcode of such instruction specify
whether instruction is a byte instruction (W = 0) or a word instruction (W = 1).
▪ D-bit : The D-bit in the opcode of the instruction indicates that the register specified within the instruction is a source
register (D = 0) or destination register (D =1).
▪ S-bit : An 8-bit 2’s complement number can be extended to a 16-bit 2’s complement number by making all of the bits in
the higher-order byte equal the most significant bit in the low order byte. This is known as sign extension. The S-bit along
with the W-bit indicate operations mentioned below
▪ V-bit : V-bit decides the number of shifts for rotate and shift instructions. If V = 0, then count = 1; if V = 1, the count is in
CL register. For example, if V = 1 and CL = 2 then shift or rotate instruction shifts or rotates 2-bits
▪ Z-bit : It is used for string primitives such as REP for comparison with ZF Flag
Maximum and Minimum Mode Configuration
▪ In minimum mode,8086 is the only
processor in the system which provides all ▪ HOLD
the control signals which are needed for This is a control signal sent by the connected external peripheral device to acquire
memory operations and I/O interfacing. the microprocessor buses. If an external device like the input and output devices are
▪ Here the circuit is simple but it does not connected to the 8086 microprocessor and they require the control over the buses,
then a HOLD signal is sent by that device at this pin.
support multiprocessing. ▪ HLDA
▪ The other components which are After the control of buses is transferred to the external peripheral device, then an
transceivers, latches, 8284 clock generator, acknowledgment signal is sent for the same through this pin.
74138 decoder, memory and i/o devices are ▪ WR'
also present in the system. This signal is used for writing purpose. It is an active low signal.
▪ The address bus of 8086 is 20 bits long. By ▪ M / IO'
This pin tells whether the operation is performed in the memory or through the IO
this we can access 220 byte memory i.e. 1MB devices. If this pin is 1, then the operations are performed in memory, else in the IO
. Out of 20 bits, 16 bits A0 to A15(or 16 lines) devices.
are multiplexed with a data bus. By ▪ DT / R'
multiplexing, it means they will act as This signal tells whether the data is transferred or received. The microprocessor
address lines during the first T state of the transfers the data when the pin is at 1, and at 0, it receives data.
machine cycle and in the rest, they act as ▪ DEN'
DEN stands for Data Enable. This pin is used to activate a chip in case of multiple
data lines. A16 to A19 are multiplexed S3 to chips. It is an active low signal.
S6 and BHE’ is multiplexed with S7. ▪ ALE
This pin is used to Latch address from multiplexed bus to temporary storage in the
8086 microprocessor. If this pin is set to high, then the AD0 to AD15 pins will carry
The pin 33 decides whether the processor
address, else they will carry data in them.
will work in minimum mode or maximum ▪ INTA
mode. If the pin is set, then the minimum INTA stands for interrupt acknowledgment. If an interrupt request is received at
mode is followed, else the processor INTR, then the acknowledgment for it is sent through this pin
works in maximum mode.
 ▪ Control signals provided by 8086
for memory operations and i/o
interfacing are used to
identifying whether the bus is ❑ 8282 (8 bits) latch :
carrying a valid address or not , The latches are buffered D FF. They are used to
in which direction data is separate the valid address from the multiplexed
needed to be transferred over Address/data bus by using the control signal ALE,
the bus, when there is valid which is connected to strobe(STB) of 8282. The
write data on the data bus and ALE is active high signal. Here three such latches
when to put read data on the are required because the address is 20 bits.
system bus ❑ 8286 (8 bits) transceivers :
They are bidirectional buffers and also known as
❑ 8284 clock generator is used to provide data amplifiers. They are used to separate the
the clock. valid data from multiplexed add/data bus. Two
❑ Control signals for all operations are such transceivers are needed because the data
generated by decoding M/IO’, RD’, WR’. bus is 16 bits long. 8286 is connected to DT/R’ and
They are decoded by 74138 3:8 DEN’ signals. They are enabled through the DEN
decoder signal .The direction of data on the data bus is
controlled by the DT/R’ signal. DT/R’ is connected
Minimum Mode Circuit to T and DEN’ is connected to OE’.
 Timing Diagram Minimum Mode
▪ All processors bus cycle is of at least 4 T-
states(T1,T2,T3,T4) .The address is given by
processor in the T1 state. It is available on
the bus for one T-state.
▪ In T2, the bus is tristated for changing the
direction of the bus( in the case of a data
read cycle.)
▪ The data transfer takes place between
T3 and T4.
▪ If the addressed device is slower, then the
wait state is inserted between T3 and T4.

Opcode fetch or read timing diagram Write memory cycle

▪ At T1 state ALE =1 ,this indicates that a valid address is latched on the
▪ At T1 state ALE =1 ,this indicates that a valid address is latched
address bus and also M / IO’= 1, which indicates the memory
on the address bus and also M / IO’= 1, which indicates the
operation is in progress.
memory operation is in progress.
▪ In T2, the address is removed from the local bus and is sent to the
▪ In T2, the processor sends the data to be written to the
addressed device. Then the bus is tristated.
addressed location.
▪ When RD’ = 0 , the valid data is present on the data bus.
▪ The data is buffered on the bus until the middle of T4 state.
▪ During T2 DEN’ =0, which enables transceivers and DT/R’ = 0 ,which
▪ The WR’=0 becomes at the beginning of T2.
indicates that the data is received.
▪ The BHE’ and A0 signals are used to select the byte or bytes of
▪ During T3, data is put on the data bus and the processor reads it.
memory or I/O word.
▪ The output device makes the READY line high. This means the output
▪ During T2 DEN’ =0, which enables, transceivers and DT/R’ = 1
device has performed the data transfer process. When the processor
,which indicates that the data is transferred by the processor to
makes the read signal to 1, then the output device will again tristate
the addressed device
its bus drivers
 Maximum Mode
▪ (RQ' / GT 0) and (RQ’ / GT 1)
These two pins are used for bus request and
grant purpose. Through these pins, a
connection is established between the
external peripheral devices and the 8086
microprocessor. Among these two pins, the
pin- (RT / GT 0) has higher priority over (RT /
GT 1).
▪ LOCK'
This pin is used to lock the internal buses of
the microprocessor. When the control of
buses is handed over to an external
peripheral device, then the microprocessor is
locked through this pin. It is an active low
signal.
▪ QS0 and QS1
QS stands for Queue status, and as the name
suggests, these two pins are used to tell the
status of the queue
▪ S2, S1 and S0
Here, the S in each of these pins stands for
Status. These three pins: S2, S1, and S0
together tell about the CPU cycle. The
different of the values of these pins taken When the pin 33 of the 8086 microprocessor is in the reset
together tell about which CPU cycle is state, i.e. 0, then the microprocessor functions in the
currently running Maximum Mode.
▪ We can connect more processors Control signals for all operations are
to 8086 (8087/8089). generated by decoding S’2, S’1 and
▪ 8086 max mode is basically for S’0 using 8288 bus controller
implementation of allocation of
global resources and passing bus
control to other coprocessor(i.e.
second processor in the system),
because two processors can not
access system bus at same
instant.
▪ All processors execute their own
program.
▪ The resources which are
common to all processors are
known as global resources.
▪ The resources which are ▪ Bus request is done using RQ’ / GT’ lines
allocated to a particular interfaced with 8086. RQ0/GT0 has more
processor are known as local or priority than RQ1/GT1.
private resources ▪ INTA’ is given by 8288, in response to an
interrupt on INTR line of 8086.
▪ Clock is provided by 8284 clock generator.
▪ In max mode, the advanced write signals
▪ 8288 bus controller- Address form the address bus is latched into
get enabled one T-state in advance as
8282 8-bit latch. Three such latches are required because address
compared to normal write signals. This
bus is 20 bit. The ALE(Address latch enable) is connected to
gives slower devices more time to get
STB(Strobe) of the latch. The ALE for latch is given by 8288 bus
ready to accept the data, therefore it
controller.
reduces the number of cycles
▪ The data bus is operated through 8286 8-bit transceiver. Two such
transceivers are required, because data bus is 16-bit. The ADV: It supports multiprocessing, Therefore it helps to increase the
transceivers are enabled the DEN signal, while the direction of efficiency.
data is controlled by the DT/R signal. DEN is connected to OE’ and DISADV: More complex circuit than min mode
DT/ R’ is connected to T. Both DEN and DT/ R’ are given by 8288
bus controller
Programmable Peripheral Interface
▪ To communicate with the outside world microcomputers use peripherals (I/O
devices). Commonly used peripherals are: A/D converter, D/A converter, CRT,
printers, Hard disks, floppy disks, magnetic tapes etc.

▪ Peripherals are connected to the microcomputer through electronic circuits

known as interfacing circuits.

▪ A programmable peripheral interface is a multiport device. The ports may be

programmed in a variety of ways as required by the programmer. The device is
very useful for interfacing peripheral devices.

Intel 8255

▪ It has two versions, namely the Intel 8255A and Intel 8255A-5. General
descriptions for both are same but there exists some differences in electrical
characteristics
▪ It has three 8-bit ports, namely Port A, Port B and Port C.
▪ Port C has been further divided into two 4-bit ports, port C upper and Port C
lower. Thus a total of 4-ports are available, two 8-bit ports and two 4-bit ports.
▪ Each port can be programmed either as an input port or an output port.

8255 Architecture
Operating Modes of 8255
▪ Mode 0 - Simple Input/output: The 8255 has two 8-bit ports (Port A and Port B) and two 4-bit ports (Port Cupper and Port Clower). In Mode 0
operation, a port can be operated as a simple input or output port. Each of the 4 ports of 8255 can be programmed to be either an input
or output port.
▪ Mode 1-Strobed Input/output: Mode 1 is strobed input/output mode of operation. The Port A and Port B both are designed to operate in
this mode of operation. When Port A and Port B are programmed in Mode 1, six pins of Port C are used for their control.
▪ Mode 2 -Bidirectional Port: Mode 2 is strobed bidirectional mode of operation. In this mode Port A can be programmed to operate as a
bidirectional port. The mode 2 operation is only for Port A. When Port A is programmed in Mode 2, the port B can be used either Mode 1
or Mode 0 Operates on a single 5 Vd.c. supply Control Signals
▪ CS (Chip Select): It is a chip select signal. The LOW status of this
signal enables communication between the CPU and 8255.
PA0 - PA7 :8 ▪ RD (READ): When RD goes LOW the 8255 sends out data or status
Pins of port A information to the CPU on the data bus. In other words it allows the
PB0 - PB7 :8 CPU to read data from the input port of 8255.
pins of port B ▪ WR (Write): When WR goes LOW the CPU writes data or control
word into 8255. The CPU writes data into the output port of 8255
PC0 - PC3 :4
and the control word into the control word register.
pins of port ▪ RESET: RESET is an active high signal. It clears the control register
Clower PC4 - and sets all ports in the input mode.
PC7 :4 pins of ▪ A0 and A1: The selection of input port and control word register is
Port Cupper done using A0 and A1 in conjunction with RD and WR. A0 and A1
are normally connected to the least significant bits of the address
bus
8255 Pin Diagram
1st Unit

2nd Unit
Programmable Timer Controller
Used in real time application for timing and counting function such as BCD/binary counting, generation of accurate time delay,
generation of square wave of desired frequency, rate generation, hardware/software triggered strobe signal, one shot signal of
desired width etc

Intel 8253 and 8254:Both are pin to pin compatible and operate in six modes
▪ Mode 0: Interrupt on terminal count
▪ Mode 1: Programmable one-shot
▪ Mode 2: Rate generator
▪ Mode 3: Square wave generator
▪ Mode 4: Software triggered mode
▪ Mode 5: Hardware triggered mode
Note: The 8254 is compatible to 8086, 8088, 8085 and most other
microprocessors

24-pin IC and operates at 5 Vd.c.. It contains

three independent 16-bit counters. The
programmer can program 8253 to operate in
any one of the 6 operating modes. It operates
under software control.

8254 Architecture
8254 Pin Diagram
❑ RD (Read): When this pin is LOW the CPU reads data.
❑ ¯WR: (Write): When this is low, the CPU outputs data in the form of
mode information or loading of counters.
❑ A0, A1: These pins are connected to the address bus. These are used to
select one of three counters. These are also used to address the control
word registers for mode selection.
❑ CS: Chip Select.
❑ D0 - D7: Bidirectional data bus.
❑ CLK0, CLK1 and CLK2 are clock for Counter 0, Counter 1 and Counter 2
respectively.
❑ GATE0, GATE1 and GATE2 are gate terminals of Counter 0, Counter 1 and
Counter 2 respectively.
❑ OUT0, OUT1 and OUT2 are output terminals of Counter 0, Counter 1 and
Counter 2 respectively.
❑ The 8254 contains a data buffer, read/write logic and control word
register as described below:
❑ Data Bus Buffer: This buffer is within 8254. It is a 3-state, bidirectional, 8-
bit buffer. It is used to interface 8254 to the system data bus through D0 -
D7 lines.
❑ Read/Write logic: The 8254 contains a read/write logic which accepts
input from the system bus and then generates control signals for the
operation
❑ Counter Word Register: When the pins A0, A1 are 11, the control word register is
selected.
8254 Operational Modes
❑ The bits D7 and D6 of the control word are to select one of the 3 counters. D5 and D4 are for loading/reading the count. D3,
D2 and D1 are for the selection of operating mode of the selected counter.
❑ These are six modes of operation for each counter of 8254. The six modes of operation are: MODE 0, MODE 1, MODE 2,
MODE 3, MODE 4 and MODE 5. The bit D0 is for the selection of binary or BCD counting.

MODE 0 : Interrupt on Terminal Count

▪ Used for the generation of accurate time delay under software control.
▪ One of the counters of 8253 is initialized and loaded with suitable count for the desired time delay.
▪ When counting is finished the counter interrupts the CPU. On interruption the microprocessor performs the required task
which is to be performed after the desired time delay.
▪ For MODE 0 operation GATE is kept high. While counting is going on the counter output OUT remains LOW. When the
terminal count is reached i.e. count reaches 0, the output becomes HIGH until the count is reloaded or new count is loaded.
▪ When the count is reloaded or OUT becomes LOW and the counter starts its counting operation again.

MODE 1 : Programmable One-Shot

▪ In MODE 1 the counter acts as a retriggerable and programmable one-shot.

▪ The LOW to HIGH transition of the signal applied to GATE acts as a trigger signal.
▪ In this mode of operation OUT becomes initially HIGH after the mode is set. After mode set operation the counter is loaded
by a count value of N. The counter decrements count, and the output (OUT) goes LOW for N clock cycles for every LOW to
HIGH transition of the GATE input.
MODE 2 : RATE Generator

▪ In MODE 2 the counter acts as a simple divide by N counter.

▪ When this mode is set the output of the counter becomes initially HIGH.
▪ After mode set operation the counter is loaded by a count of value N.
▪ For MODE 2 operation GATE is kept HIGH.
▪ In this mode the output remains HIGH for (N-1) clock pulses and then goes LOW for one clock pulse.
MODE 3 : Square Wave Generation

▪ In MODE 3 the counter acts as a square wave generator. After mode set operation the counter is loaded by a count of value N.
▪ For MODE 3 operation GATE is kept HIGH.
▪ For even values of N the output remains HIGH for N/2 clock pulses abd then goes LOW for next N/2 clock pulses
MODE 5 : Hardware Triggered Strobe
MODE 4 : Software Triggered Strobe
▪ In this mode of operation GATE input acts as a trigger.
▪ In MODE 4 operation the output of the counter becomes initially
▪ After the mode is set, the output becomes initially HIGH.
HIGH after the mode is set.
▪ A count value of N is loaded into the counter.
▪ GATE is kept HIGH for this mode of operation. The counter begins
▪ Following a LOW to HIGH transition of the GATE input the
counting immediately after the count is loaded into the count
counter starts decrementing the count.
register.
▪ The counting begins at the first negative edge of the clock
▪ When the counter reaches terminal count (i.e. counter content = 0)
after the rising edge of the GATE input.
the output goes LOW for one clock period, then it returns to HIGH.
▪ On terminal count the output goes LOW for one clock
▪ The output signal may be used as strobe.
period, and then it goes HIGH again.
▪ This mode of operation is referred to as a software triggered
▪ As the LOW to HIGH transition of the GATE input causes
strobe because the generation of the strobe signal is triggered by
triggering, this mode is referred to as hardware triggered
loading the count into the count register.
strobe.
Memory Interfacing
To interface the memory with 8086, we need the system bus and the control signals for memory read and write operations

Four common types of

memory:
❖ Read only memory (ROM)
❖ Flash memory (EEPROM)
❖ Static Random access
memory (SARAM)
❖ Dynamic Random access
memory (DRAM).

▪ When we are executing any instruction, the address of memory

location or an I/O device is sent out by the microprocessor. The Address connections: All memory devices have address inputs that
corresponding memory chip or I/O device is selected by a select a memory location within the memory device. Address
decoding circuit. inputs are labeled (A0 –An)
▪ Memory requires some signals to read from and write to Data connections: All memory devices have a set of data outputs
registers and microprocessor transmits some signals for reading or
or writing data input/outputs. Today many of them have bi-directional common
▪ Interfacing process includes matching the memory requirements I/O pins.
with the microprocessor signals. Selection connections: Each memory device has an input that
▪ Therefore, the interfacing circuit should be designed in such a selects or enables the memory device. This kind of input is most
way that it matches the memory signal requirements with the often called a chip select (CS)
microprocessor's signals. Control connections: The control input most often found on the
▪ 8 bit data line, 16 bit address line , control signals are connected ROM is the output enable (OE) or gate (G) this allows data to flow
to corresponding lines of memory IC. out of the output data pins of the ROM.
Minimum Mode Memory Interfacing
Address bus & Data bus are multiplexed on same lines
(AD0 to AD15).
During first clock cycle, it serves as a memory/ IO address
bus.
For second and third clock cycles it acts as data bus and
carries data.
Demultiplexing refers to separating Address & Data
signals for read/write operations.

Block Diagram
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