S-25A080A/160A/320A, S-25A080B/160B/320B

FOR AUTOMOTIVE 125°C OPERATION

www.ablic.com
www.ablicinc.com
SPI SERIAL E2PROM
© ABLIC Inc., 2008-2014 Rev.4.2_02
2
This IC is a SPI serial E PROM which operates under the high temperature, at high speed, with the wide range operation for
automotive components. This IC has the capacity of 8 K-bit, 16 K-bit, 32 K-bit and the organization of 1024 words  8-bit,
2048 words  8-bit, 4096 words  8-bit. Page write and Sequential read are available.

Caution Before using the product in automobile control unit or medical equipment, contact to ABLIC Inc. is
indispensable.

 Features  Packages

 Operating voltage range  8-Pin SOP (JEDEC)

Read: 2.5 V ~ 5.5 V
Write: 2.5 V ~ 5.5 V 5
 Operation frequency: 6.5 MHz max.
8
 Write time 4
S-25A080A/160A/320A: 4.0 ms max.
S-25A080B/160B/320B: 5.0 ms max. 1
 SPI mode (0, 0) and (1, 1)
 Page write: 32 bytes / page (5.0  6.0  t1.75 mm)
 Sequential read
 Write protect: Software, Hardware
Protect area: 25%, 50%, 100%
 Monitoring of a write memory state by the status register  8-Pin TSSOP
 Function to prevent malfunction by monitoring clock pulse
 Write protect function during the low power supply voltage 5
8
 CMOS schmitt input ( CS , SCK, SI, WP , HOLD )
 Endurance*1 4
S-25A080A/160A/320A: 106 cycle / word*2 (Ta = 25C) 1
5  105 cycle / word*2 (Ta = 125C)
S-25A080B/160B/320B: 106 cycle / word*2 (Ta = 25C) (3.0  6.4  t1.1 mm)
3  105 cycle / word*2 (Ta = 125C)
 Data retention: 100 years (Ta = 25C)
50 years (Ta = 125C)
 Memory capacity  TMSOP-8
S-25A080A, S-25A080B: 8 K-bit
S-25A160A, S-25A160B: 16 K-bit 5
8
S-25A320A, S-25A320B: 32 K-bit
4
 Initial delivery state: FFh, SRWD = 0, BP1 = 0, BP0 = 0
1
 Burn-in specification: Wafer level burn-in
 Operation temperature range: Ta = 40°C to 125°C
 Lead-free (Sn 100%), halogen-free*3 (2.9  4.0  t0.8 mm)
 AEC-Q100 qualified*4

*1. Refer to " Endurance" for details.

*2. For each address (Word: 8-bit)
*3. Refer to " Product Name Structure" for details.
*4. Contact our sales office for details.

Remark Refer to "3. Product name list" in " Product Name Structure" for details of package and product.

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FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A080A/160A/320A, S-25A080B/160B/320B Rev.4.2_02

 Block Diagram

Step-up Circuit
Voltage Detector

Page Latch
Input Control Circuit

CS
Clock Counter Memory
SCK
Mode

X Decoder
Cell
SI Decoder Array
HOLD Data Register
WP Status
Memory Cell Array

Y Decoder
Address Register Status Register

Output
SO Control
Circuit Read Circuit

VCC
GND

Figure 1

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 FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.4.2_02 S-25A080A/160A/320A, S-25A080B/160B/320B

 AEC-Q100 Qualified

This IC supports AEC-Q100 for operation temperature grade 1.

Contact our sales office for details of AEC-Q100 reliability specification.

 Product Name Structure

1. Product name
1. 1 S-25A080A/160A
S-25AxxxA 0A  xxxx U D

Fixed

Environmental code
U: Lead-free (Sn 100%), halogen-free

Package name (abbreviation) and IC packing specification*1

J8T2: 8-Pin SOP (JEDEC), Tape
T8T2: 8-Pin TSSOP, Tape

Fixed

Product name
S-25A080A: 8 K-bit
S-25A160A: 16 K-bit

1. 2 S-25A320A
S-25A320A 0A  J8T2 U D

Fixed

Environmental code
U: Lead-free (Sn 100%), halogen-free

Package name (abbreviation) and IC packing specification*1

J8T2: 8-Pin SOP (JEDEC), Tape

Fixed

Product name
S-25A320A: 32 K-bit

1. 3 S-25A080B/160B/320B
S-25AxxxB 0A  xxxx U 3

Fixed

Environmental code
U: Lead-free (Sn 100%), halogen-free

Package name (abbreviation) and IC packing specification*1

J8T2: 8-Pin SOP (JEDEC), Tape
T8T2: 8-Pin TSSOP, Tape
K8T2: TMSOP-8, Tape

Fixed

Product name
S-25A080B: 8 K-bit
S-25A160B: 16 K-bit
S-25A320B: 32 K-bit
*1. Refer to the tape drawing.

Remark This IC is wafer level burn-in specification.

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FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A080A/160A/320A, S-25A080B/160B/320B Rev.4.2_02

2. Packages
Table 2 Package Drawing Codes
Package Name Dimension Tape Reel
8-Pin SOP (JEDEC) FJ008-A-P-SD FJ008-D-C-SD FJ008-D-R-S2
8-Pin TSSOP FT008-A-P-SD FT008-E-C-SD FT008-E-R-S2
TMSOP-8 FM008-A-P-SD FM008-A-C-SD FM008-A-R-SD

3. Product name list

Table 3
Product Name Capacity Package Quantity
S-25A080A0A-J8T2UD 8 K bit 8-Pin SOP (JEDEC) 2000 pcs / reel
S-25A080A0A-T8T2UD 8 K bit 8-Pin TSSOP 3000 pcs / reel
S-25A160A0A-J8T2UD 16 K bit 8-Pin SOP (JEDEC) 2000 pcs / reel
S-25A160A0A-T8T2UD 16 K bit 8-Pin TSSOP 3000 pcs / reel
S-25A320A0A-J8T2UD 32 K bit 8-Pin SOP (JEDEC) 2000 pcs / reel

S-25A080B0A-J8T2U3 8 K bit 8-Pin SOP (JEDEC) 4000 pcs / reel

S-25A080B0A-T8T2U3 8 K bit 8-Pin TSSOP 4000 pcs / reel
S-25A080B0A-K8T2U3 8 K bit TMSOP-8 4000 pcs / reel
S-25A160B0A-J8T2U3 16 K bit 8-Pin SOP (JEDEC) 4000 pcs / reel
S-25A160B0A-T8T2U3 16 K bit 8-Pin TSSOP 4000 pcs / reel
S-25A160B0A-K8T2U3 16 K bit TMSOP-8 4000 pcs / reel

S-25A320B0A-J8T2U3 32 K bit 8-Pin SOP (JEDEC) 4000 pcs / reel

S-25A320B0A-T8T2U3 32 K bit 8-Pin TSSOP 4000 pcs / reel
S-25A320B0A-K8T2U3 32 K bit TMSOP-8 4000 pcs / reel
Remark 1. Please contact our sales office for products with product name structure other than those
specified above.
2. This IC is wafer level burn-in specification.

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 FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.4.2_02 S-25A080A/160A/320A, S-25A080B/160B/320B

 Pin Configurations

1. 8-Pin SOP (JEDEC)

Top view Table 3
Pin No. Symbol Description
1 8 *1
1 CS Chip select input
2 7 2 SO Serial data output
*1
3 6 3 WP Write protect input
4 GND Ground
4 5
5 SI*1 Serial data input
6 SCK*1 Serial clock input
Figure 2
7 HOLD *1 Hold input
8 VCC Power supply

2. 8-Pin TSSOP
Top view Table 4
Pin No. Symbol Description
1 8 *1
2 7 1 CS Chip select input
3 6 2 SO Serial data output
4 5 *1
3 WP Write protect input
4 GND Ground
Figure 3
5 SI*1 Serial data input
6 SCK*1 Serial clock input
7 HOLD *1 Hold input
8 VCC Power supply

3. TMSOP-8
Top view Table 5
Pin No. Symbol Description
1 8 *1
2 7 1 CS Chip select input
3 6 2 SO Serial data output
4 5
3 WP *1 Write protect input

Figure 4 4 GND Ground

5 SI*1 Serial data input
6 SCK*1 Serial clock input
7 HOLD *1 Hold input
8 VCC Power supply

*1. Do not use it in "High-Z".

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FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A080A/160A/320A, S-25A080B/160B/320B Rev.4.2_02

 Absolute Maximum Ratings

Table 6
Absolute Maximum Rating
Item Symbol Unit
S-25A080A/160A/320A S-25A080B/160B/320B
Power supply voltage VCC 0.3 to 7.0 0.3 to 6.5 V
Input voltage VIN 0.3 to 7.0 0.3 to 6.5 V
Output voltage VOUT 0.3 to VCC  0.3 V
Operation ambient temperature Topr 40 to 125 °C
Storage temperature Tstg 65 to 150 °C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.

 Recommended Operating Conditions

Table 7
Ta = 40C to 125C
Item Symbol Condition Unit
Min. Max.
Read 2.5 5.5 V
Power supply voltage VCC
Write 2.5 5.5 V
High level input voltage VIH VCC = 2.5 V to 5.5 V 0.7  VCC VCC  1.0 V
Low level input voltage VIL VCC = 2.5 V to 5.5 V 0.3 0.3  VCC V

 Pin Capacitance
Table 8
(Ta = 25°C, f = 1.0 MHz, VCC = 5.0 V)
Item Symbol Condition Min. Max. Unit
Input capacitance CIN VIN = 0 V ( CS , SCK, SI, WP , HOLD ) － 8 pF
Output capacitance COUT VOUT = 0 V (SO) － 10 pF

 Endurance

1. S-25A080A/160A/320A
Table 9
Item Symbol Operation Ambient Temperature Min. Max. Unit
6 *1
Ta = 40°C to 85°C 10 － cycle / word
*1
Endurance NW Ta = 40°C to 105°C 8  105 － cycle / word
*1
Ta = 40°C to 125°C 5  105 － cycle / word
*1. For each address (Word: 8-bit)

2. S-25A080B/160B/320B
Table 10
Item Symbol Operation Ambient Temperature Min. Max. Unit
6 *1
Ta = 25°C 10 － cycle / word
*1
Ta = 40°C to 85°C 7  105 － cycle / word
Endurance NW *1
Ta = 40°C to 105°C 5  105 － cycle / word
*1
Ta = 40°C to 125°C 3  105 － cycle / word
*1. For each address (Word: 8-bit)

 Data Retention
Table 11
Item Symbol Operation Ambient Temperature Min. Max. Unit
Ta = 25°C 100 － year
Data retention －
Ta = 40°C to 125°C 50 － year

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 FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.4.2_02 S-25A080A/160A/320A, S-25A080B/160B/320B

 DC Electrical Characteristics

1. S-25A080A/160A/320A

Table 12
Ta = 40°C to 125°C
VCC = 2.5 V to 3.0 V VCC = 3.0 V to 4.5 V VCC = 4.5 V to 5.5 V
Item Symbol Condition Unit
fSCK = 3.5 MHz fSCK = 5.0 MHz fSCK = 6.5 MHz
Min. Max. Min. Max. Min. Max.
Current consumption No load at
ICC1 － 1.5 － 2.0 － 2.5 mA
(read) SO pin

Table 13
Ta = 40°C to 125°C
VCC = 2.5 V to 3.0 V VCC = 3.0 V to 4.5 V VCC = 4.5 V to 5.5 V
Item Symbol Condition Unit
fSCK = 3.5 MHz fSCK = 5.0 MHz fSCK = 6.5 MHz
Min. Max. Min. Max. Min. Max.
Current consumption No load at
ICC2 － 2.0 － 2.5 － 3.0 mA
(write) SO pin

Table 14
Ta = 40°C to 125°C
Item Symbol Condition VCC = 2.5 V to 4.5 V VCC = 4.5 V to 5.5 V Unit
Min. Max. Min. Max.

CS = VCC,
Standby current SO = Open
ISB － 8.0 － 10.0 A
consumption Other inputs are
VCC or GND
Input leakage current ILI VIN = GND to VCC － 2.0 － 2.0 A
Output leakage current ILO VOUT = GND to VCC － 2.0 － 2.0 A
Low level VOL1 IOL = 2.0 mA － － － 0.4 V
output voltage VOL2 IOL = 1.5 mA － 0.4 － 0.4 V
High level VOH1 IOH = 2.0 mA － － 0.8  VCC － V
output voltage VOH2 IOH = 0.4 mA 0.8  VCC － 0.8  VCC － V

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FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A080A/160A/320A, S-25A080B/160B/320B Rev.4.2_02

2. S-25A080B/160B/320B
Table 15
Ta = 40°C to 125°C
VCC = 2.5 V to 4.5 V VCC = 4.5 V to 5.5 V
Item Symbol Condition Unit
fSCK = 6.5 MHz fSCK = 6.5 MHz
Min. Max. Min. Max.
Current consumption
ICC1 No load at SO pin － 2.0 － 2.5 mA
(read)

Table 16
Ta = 40°C to 125°C
VCC = 2.5 V to 5.5 V
Item Symbol Condition Unit
fSCK = 6.5 MHz
Min. Max.
Current consumption
ICC2 No load at SO pin － 4.0 mA
(write)

Table 17
Ta = 40°C to 125°C
Item Symbol Condition VCC = 2.5 V to 4.5 V VCC = 4.5 V to 5.5 V Unit
Min. Max. Min. Max.

CS = VCC,
Standby current SO = Open
ISB － 8.0 － 10.0 A
consumption Other inputs are
VCC or GND
Input leakage current ILI VIN = GND to VCC － 2.0 － 2.0 A
Output leakage current ILO VOUT = GND to VCC － 2.0 － 2.0 A
Low level VOL1 IOL = 2.0 mA － － － 0.4 V
output voltage VOL2 IOL = 1.5 mA － 0.4 － 0.4 V
High level VOH1 IOH = 2.0 mA － － 0.8  VCC － V
output voltage VOH2 IOH = 0.4 mA 0.8  VCC － 0.8  VCC － V

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 FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.4.2_02 S-25A080A/160A/320A, S-25A080B/160B/320B

 AC Electrical Characteristics

1. S-25A080A/160A/320A

Table 18 Measurement Conditions

Input pulse voltage 0.2  VCC to 0.8  VCC
Output reference voltage 0.5  VCC
Output load 100 pF

Table 19
Ta = 40°C to 125°C
Item Symbol VCC = 2.5 V to 5.5 V VCC = 3.0 V to 5.5 V VCC = 4.5 V to 5.5 V Unit
Min. Max. Min. Max. Min. Max.
SCK clock frequency fSCK － 3.5 － 5.0 － 6.5 MHz
CS setup time during CS falling tCSS.CL 90 － 90 － 65 － ns
CS setup time during CS rising tCSS.CH 90 － 90 － 65 － ns
CS deselect time tCDS 160 － 140 － 110 － ns
CS hold time during CS falling tCSH.CL 90 － 90 － 65 － ns
CS hold time during CS rising tCSH.CH 90 － 90 － 65 － ns
SCK clock time "H"*1 tHIGH 125 － 95 － 65 － ns
SCK clock time "L"*1 tLOW 125 － 95 － 65 － ns
Rising time of SCK clock*2 tRSK － 1 － 1 － 1 s
Falling time of SCK clock*2 tFSK － 1 － 1 － 1 s
SI data input setup time tDS 20 － 20 － 20 － ns
SI data input hold time tDH 30 － 30 － 30 － ns
SCK "L" hold time during HOLD rising tSKH.HH 70 － 70 － 45 － ns
SCK "L" hold time during HOLD falling tSKH.HL 40 － 40 － 30 － ns
SCK "L" setup time during HOLD falling tSKS.HL 0 － 0 － 0 － ns
SCK "L" setup time during HOLD rising tSKS.HH 0 － 0 － 0 － ns
Disable time of SO output*2 tOZ － 100 － 100 － 75 ns
Delay time of SO output tOD － 120 － 90 － 60 ns
Hold time of SO output tOH 0 － 0 － 0 － ns
Rising time of SO output*2 tRO － 80 － 80 － 50 ns
Falling time of SO output*2 tFO － 80 － 80 － 50 ns
Disable time of SO output during HOLD falling*2 tOZ.HL － 100 － 100 － 75 ns
Delay time of SO output during HOLD rising*2 tOD.HH － 80 － 80 － 60 ns
WP setup time tWS1 0 － 0 － 0 － ns
WP hold time tWH1 0 － 0 － 0 － ns
WP release / setup time tWS2 0 － 0 － 0 － ns
WP release / hold time tWH2 150 － 150 － 100 － ns
*1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK s. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.)  tHIGH (min.) by
minimizing the SCK clock cycle time.
*2. These are values of sample and not 100% tested.

Table 20
Ta = 40°C to 125°C
Item Symbol VCC = 2.5 V to 5.5 V Unit
Min. Max.
Write time tPR － 4.0 ms

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FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A080A/160A/320A, S-25A080B/160B/320B Rev.4.2_02

2. S-25A080B/160B/320B

Table 21 Measurement Conditions

Input pulse voltage 0.2  VCC to 0.8  VCC
Output reference voltage 0.5  VCC
Output load 100 pF

Table 22
Ta = 40°C to 125°C
Item Symbol VCC = 2.5 V to 5.5 V Unit
Min. Max.
SCK clock frequency fSCK － 6.5 MHz
CS setup time during CS falling tCSS.CL 65 － ns
CS setup time during CS rising tCSS.CH 65 － ns
CS deselect time tCDS 65 － ns
CS hold time during CS falling tCSH.CL 65 － ns
CS hold time during CS rising tCSH.CH 65 － ns
SCK clock time "H" *1 tHIGH 65 － ns
SCK clock time "L"*1 tLOW 65 － ns
Rising time of SCK clock*2 tRSK － 1 s
Falling time of SCK clock*2 tFSK － 1 s
SI data input setup time tDS 15 － ns
SI data input hold time tDH 20 － ns
SCK "L" hold time during HOLD rising tSKH.HH 45 － ns
SCK "L" hold time during HOLD falling tSKH.HL 30 － ns
SCK "L" setup time during HOLD falling tSKS.HL 0 － ns
SCK "L" setup time during HOLD rising tSKS.HH 0 － ns
*2
Disable time of SO output tOZ － 75 ns
Delay time of SO output tOD － 50 ns
Hold time of SO output tOH 0 － ns
*2
Rising time of SO output tRO － 30 ns
Falling time of SO output*2 tFO － 30 ns
Disable time of SO output during HOLD falling*2 tOZ.HL － 75 ns
*2
Delay time of SO output during HOLD rising tOD.HH － 50 ns
WP setup time tWS1 0 － ns
WP hold time tWH1 0 － ns
WP release / setup time tWS2 0 － ns
WP release / hold time tWH2 20 － ns
*1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK s. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.)  tHIGH (min.) by
minimizing the SCK clock cycle time.
*2. These are values of sample and not 100% tested.

Table 23
Ta = 40°C to 125°C
Item Symbol VCC = 2.5 V to 5.5 V Unit
Min. Max.
Write time tPR － 5.0 ms

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 FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.4.2_02 S-25A080A/160A/320A, S-25A080B/160B/320B

tCDS

CS
tCSH.CL tCSS.CH
tCSS.CL tCSH.CH

SCK

tDS
tDH tRSK tFSK

SI MSB IN LSB IN

High-Z
SO

Figure 5 Serial Input Timing

CS

tSKS.HL
tSKH.HL tSKH.HH

SCK

tSKS.HH

SI

tOZ.HL tOD.HH

SO

HOLD

Figure 6 Hold Timing

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FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A080A/160A/320A, S-25A080B/160B/320B Rev.4.2_02

CS tSCK

tOZ
tHIGH

SCK

tLOW
ADDR

SI LSB IN

tOD
tOD tOH tOH

SO LSB OUT

tRO
tFO

Figure 7 Serial Output Timing

tWS1 tWH1

CS

WP

Figure 8 Valid Timing in Write Protect

tWS2 tWH2

CS

WP

Figure 9 Invalid Timing in Write Protect

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 FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.4.2_02 S-25A080A/160A/320A, S-25A080B/160B/320B

 Pin Functions

1. CS (chip select input) pin

This is an input pin to set a chip in the select status. In the "H" input level, this IC is in the non-select status and its
output is "High-Z". This IC is in standby as long as it is not in write inside. This IC goes in active by setting the chip
select to "L". Input any instruction code after power-on and a falling of chip select.

2. SI (serial data input) pin

This pin is to input serial data. This pin receives an instruction code, an address and write data. This pin latches
data at rising edge of serial clock.

3. SO (serial data output) pin

This pin is to output serial data. The data output changes at falling edge of serial clock.

4. SCK (serial clock input) pin

This is a clock input pin to set the timing of serial data. An instruction code, an address and write data are
received at a rising edge of clock. Data is output during falling edge of clock.

5. WP (write protect input) pin

Write protect is purposed to protect the area size against the write instruction (BP1, BP0 in the status register).
Fix this pin "H" or "L" not to set it in the floating state.
Refer to " Protect Operation" for details.

6. HOLD (hold input) pin

This pin is used to pause serial communications without setting this IC in the non-select status.
In the hold status, the serial output goes in "High-Z", the serial input and the serial clock go in "Don't care". During
the hold operation, be sure to set this IC in active by setting the chip select ( CS pin) to "L".
Refer to " Hold Operation" for details.

 Initial Delivery State

Initial delivery state of all addresses is "FFh".

Moreover, initial delivery state of the status register nonvolatile memory is as follows.

 SRWD = 0
 BP1 = 0
 BP0 = 0

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FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A080A/160A/320A, S-25A080B/160B/320B Rev.4.2_02

 Instruction Set

Table 24 is the list of instruction for This IC. The instruction is able to be input by changing the CS pin "H" to "L".
Input the instruction in the MSB first. Each instruction code is organized with 1-byte as shown below. If This IC
receives any invalid instruction code, this IC goes in the non-select status.

Table 24 Instruction Set

Instruction Code Address Data
Instruction Operation SCK Input Clock SCK Input Clock SCK Input Clock SCK Input Clock
1 to 8 9 to 16 17 to 24 25 to 32
WREN Write enable 0000 0110 － － －
WRDI Write disable 0000 0100 － － －
Read the status
RDSR 0000 0101 b7 to b0 output*1 － －
register
Write in the status
WRSR 0000 0001 b7 to b0 input － －
register
READ Read memory data 0000 0011 A15 to A8*2 A7 to A0 D7 to D0 output*3
WRITE Write memory data 0000 0010 A15 to A8*2 A7 to A0 D7 to D0 input
*1. Sequential data reading is possible.
*2. In the S-25A080A and the S-25A080B, the higher addresses A15 to A10 = Don't care.
In the S-25A160A and the S-25A160B, the higher addresses A15 to A11 = Don't care.
In the S-25A320A and the S-25A320B, the higher addresses A15 to A12 = Don't care.
*3. After outputting data in the specified address, data in the following address is output.

 Operation

1. Status register
The status register's organization is below. The status register can write and read by a specific instruction.

b7 b6 b5 b4 b3 b2 b1 b0

SRWD 0 0 0 BP1 BP0 WEL WIP

Status Register Write Disable

Block Protect
Write Enable Latch
Write In Progress

Figure 10 Organization of Status Register

The status / control bits of the status register are as follows.

1. 1 SRWD (b7) : Status Register Write Disable

Bit SRWD operates in conjunction with the write protect signal ( WP ). With a combination of bit SRWD and
signal WP (SRWD = "1", WP = "L"), this IC goes in Hardware Protect status. In this case, the bits
composed of the nonvolatile memory in the status register (SRWD, BP1, BP0) go in read only, so that the
WRSR instruction is not be performed.

14
 FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.4.2_02 S-25A080A/160A/320A, S-25A080B/160B/320B

1. 2 BP1, BP0 (b3, b2) : Block Protect

Bit BP1 and BP0 are composed of the nonvolatile memory. The area size of Software Protect against WRITE
instruction is defined by them. Rewriting these bits is possible by the WRSR instruction. To protect the
memory area against the WRITE instruction, set either or both of bit BP1 and BP0 to "1". Rewriting bit BP1
and BP0 is possible unless they are in Hardware Protect mode. Refer to " Protect Operation" for details of
Block Protect.

1. 3 WEL (b1) : Write Enable Latch

Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit
WEL is "1", this is the status that Write Enable Latch is set. If bit WEL is "0", Write Enable Latch is in reset, so
that this IC does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;

 The power supply voltage is dropping

 At power-on
 After performing WRDI
 After the completion of write operation by the WRSR instruction
 After the completion of write operation by the WRITE instruction

1. 4 WIP (b0) : Write In Progress

Bit WIP is read only and shows whether the internal memory is in the write operation or not by the WRITE or
WRSR instruction. Bit WIP is "1" during the write operation but "0" during any other status. Figure 11 shows
the usage example.

CS
WRITE or WRSR instruction
RDSR instruction RDSR instruction RDSR instruction

D2 D1 D0 RDSR RDSR RDSR

SI

S S S
R BB R BB R BB
W PP W PP W PP
D 1 0 D 1 0 D 1 0

SO 000
000 11 000 11 00

WEL, WIP WEL, WIP WEL, WIP

tPR

Figure 11 Usage Example of WEL, WIP Bits during Write

2. Write enable (WREN)

Before writing data (WRITE and WRSR), be sure to set bit Write Enable Latch (WEL). This instruction is to set bit
WEL. Its operation is below.
After selecting this IC by the chip select ( CS ), input the instruction code from serial data input (SI). To set bit
WEL, set this IC in the non-select status by CS at the 8th clock of the serial clock (SCK). To cancel the WREN
instruction, input the clock different from a specified value (n = 8 clock) while CS is in "L".

15
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A080A/160A/320A, S-25A080B/160B/320B Rev.4.2_02

CS

WP High / Low

SCK 1 2 3 4 5 6 7 8

Instruction

SI

High-Z
SO

Figure 12 WREN Operation

3. Write disable (WRDI)

The WRDI instruction is one of ways to reset bit Write Enable Latch (WEL). After selecting this IC by the chip
select ( CS ), input the instruction code from serial data input (SI).
To reset bit WEL, set this IC in the non-select status by CS at the 8th clock of the serial clock.
To cancel the WRDI instruction, input the clock different from a specified value (n = 8 clock) while CS is in "L".
Bit WEL is reset after the operations shown below.

 The power supply voltage is dropping

 At power-on
 After performing WRDI
 After the completion of write operation by the WRSR instruction
 After the completion of write operation by the WRITE instruction

CS

WP High / Low

SCK 1 2 3 4 5 6 7 8

Instruction

SI

High-Z
SO

Figure 13 WRDI Operation

16
 FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.4.2_02 S-25A080A/160A/320A, S-25A080B/160B/320B

4. Read the status register (RDSR)

Reading data in the status register is possible by the RDSR instruction. During the write operation, it is possible to
confirm the progress by checking bit WIP.
Set the chip select ( CS ) "L" first. After that, input the instruction code from serial data input (SI). The status of bit
in the status register is output from serial data output (SO). Sequential read is available for the status register. To
stop the read cycle, set CS to "H".
It is possible to read the status register always. The bits in it are valid and can be read by RDSR even in the write
cycle.
The 2 bits WEL and WIP are updated during the write cycle. The updated nonvolatile bits SRWD, BP1 and BP0
can be acquired by performing a new RDSR instruction after verifying the completion of the write cycle.

CS

WP High / Low

SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Instruction

SI

Outputs Data in the Status Register

High-Z
SO b7 b6 b5 b4 b3 b2 b1 b0 b7

Figure 14 RDSR Operation

5. Write in the status register (WRSR)

The values of status register (SRWD, BP1, BP0) can be rewritten by inputting the WRSR instruction. But b6, b5,
b4, b1, b0 of status register cannot be rewritten. b6 to 4 are always data "0" when reading the status register.
Before inputting the WRSR instruction, set bit WEL by the WREN instruction. The operation of WRSR is shown
below.
Set the chip select ( CS ) "L" first. After that, input the instruction code and data from serial data input (SI). To start
WRSR write (tPR), set the chip select ( CS ) to "H" after inputting data or before inputting a rising of the next serial
clock. It is possible to confirm the operation status by reading the value of bit WIP during WRSR write. Bit WIP is
"1" during write, "0" during any other status. Bit WEL is reset when write is completed.
With the WRSR instruction, the values of BP1 and BP0; which determine the area size the users can handle as
the read only memory; can be changed. Besides bit SRWD can be set or reset by the WRSR instruction
depending on the status of write protect ( WP ). With a combination of bit SRWD and write protect ( WP ), this IC
can be set in Hardware Protect mode (HPM). In this case, the WRSR instruction is not be performed (Refer to "
Protect Operation").
Bit SRWD and BP1, BP0 keep the value which is the one prior to the WRSR instruction during the WRSR
instruction. The newly updated value is changed when the WRSR instruction has completed.
To cancel the WRSR instruction, input the clock different from a specified value (n = 16 clock) while CS is in "L".

17
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A080A/160A/320A, S-25A080B/160B/320B Rev.4.2_02

CS

WP High / Low

SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Instruction
Inputs Data in the Status Register

SI b7 b6 b5 b4 b3 b2 b1 b0

High-Z
SO

Figure 15 WRSR Operation

6. Read memory data (READ)

The READ operation is shown below. Input the instruction code and the address from serial data input (SI) after
inputting "L" to the chip select ( CS ). The input address is loaded to the internal address counter, and data in the
address is output from the serial data output (SO).
Next, by inputting the serial clock (SCK) keeping the chip select ( CS ) in "L", the address is automatically
incremented so that data in the following address is sequentially output. The address counter rolls over to the first
address by increment in the last address.
To finish the read cycle, set CS to "H". It is possible to raise the chip select always during the cycle. During write,
the READ instruction code is not be accepted or operated.

CS

WP High / Low

SCK 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 32

Instruction 16-bit Address

SI A15 A14 A13 A3 A2 A1 A0

Outputs
Outputs the First Byte the Second
High-Z
SO D7 D6 D5 D4 D3 D2 D1 D0 D7

Remark In the S-25A080A and the S-25A080B, the higher addresses A15 to A10 = Don't care.
In the S-25A160A and the S-25A160B, the higher addresses A15 to A11 = Don't care.
In the S-25A320A and the S-25A320B, the higher addresses A15 to A12 = Don't care.

Figure 16 READ Operation

18
 FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.4.2_02 S-25A080A/160A/320A, S-25A080B/160B/320B

7. Write memory data (WRITE)

Figure 17 shows the timing chart when inputting 1-byte data. Input the instruction code, the address and data
from serial data input (SI) after inputting "L" to the chip select ( CS ). To start WRITE (tPR), set the chip select
( CS ) to "H" after inputting data or before inputting a rising of the next serial clock. Bit WIP and WEL are reset to
"0" when write has completed.
This IC can Page write of 32 bytes. Its function to transmit data is as same as Byte write basically, but it operates
Page write by receiving sequential 8-bit write data as much data as page size has. Input the instruction code, the
address and data from serial data input (SI) after inputting “L” in CS , as the WRITE operation (page) shown in
Figure 18. Input the next data while keeping CS in “L”. After that, repeat inputting data of 8-bit sequentially. At
the end, by setting CS to “H”, the WRITE operation starts (tPR).
5 of the lower bits in the address are automatically incremented every time when receiving write data of 8-bit.
Thus, even if write data exceeds 32 bytes, the higher bits in the address do not change. And 5 of lower bits in the
address roll over so that write data which is previously input is overwritten.

These are cases when the WRITE instruction is not accepted or operated.

 Bit WEL is not set to "1" (not set to "1" beforehand immediately before the WRITE instruction)
 During WRITE operation
 The address to be written is in the protect area by BP1 and BP0

To cancel the WRITE instruction, input the clock different from a specified value (n = 24  m  8 clock) while CS
is in "L".

CS

WP High / Low

SCK 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 32

Instruction 16-bit Address Data Byte 1

SI A15 A14 A13 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

High-Z
SO

Remark In the S-25A080A and the S-25A080B, the higher addresses A15 to A10 = Don't care.
In the S-25A160A and the S-25A160B, the higher addresses A15 to A11 = Don't care.
In the S-25A320A and the S-25A320B, the higher addresses A15 to A12 = Don't care.

Figure 17 WRITE Operation (1 Byte)

19
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A080A/160A/320A, S-25A080B/160B/320B Rev.4.2_02

CS

WP High / Low

1 2 3 4 5 6 7 8 9 10 11 22 23 24 25 26 27 28 29 30 31 32

SCK

Instruction 16-bit Address (n) Data Byte (n) Data Byte (n + x)

SI A15 A14 A13 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0

High-Z
SO

Remark In the S-25A080A and the S-25A080B, the higher addresses A15 to A10 = Don't care.
In the S-25A160A and the S-25A160B, the higher addresses A15 to A11 = Don't care.
In the S-25A320A and the S-25A320B, the higher addresses A15 to A12 = Don't care.

Figure 18 WRITE Operation (Page)

 Protect Operation

Table 25 shows the block settings of write protect. Table 26 shows the protect operation for this IC. As long as bit
SRWD, the Status Register Write Disable bit, in the status register is reset to "0" (it is in reset before the shipment),
the value of status register can be changed.

These are two statues when bit SRWD is set to "1".

 Write in the status register is possible; write protect ( WP ) is in "H".

 Write in the status register is impossible; write protect ( WP ) is in "L". Therefore the write protect area which is
set by protect bit (BP1, BP0) in the status register cannot be changed.

These operations are to set Hardware Protect (HPM).

 After setting bit SRWD, set write protect ( WP ) to "L".

 Set bit SRWD completed setting write protect ( WP ) to "L".

The timing during the cycle write to the status register is showed in "Figure 8 Valid Timing in Write Protect" and
"Figure 9 Invalid Timing in Write Protect".

By inputting "H" to write protect ( WP ), Hardware Protect (HPM) is released. If the write protect ( WP ) is "H",
Hardware Protect (HPM) does not function, Software Protect (SPM) which is set by the protect bits in the status
register (BP1, BP0) only works.

20
 FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.4.2_02 S-25A080A/160A/320A, S-25A080B/160B/320B

Table 25 Block Settings of Write Protect

Status Register Address of Write Protect Block
Area of Write Protect S-25A080A, S-25A160A, S-25A320A,
BP1 BP0
S-25A080B S-25A160B S-25A320B
0 0 0% None None None
0 1 25% 300h to 3FFh 600h to 7FFh C00h to FFFh
1 0 50% 200h to 3FFh 400h to 7FFh 800h to FFFh
1 1 100% 000h to 3FFh 000h to 7FFh 000h to FFFh

Table 26 Protect Operation

Mode WP Pin Bit SRWD Bit WEL Write Protect Block General Block Status Register
1 X 0 Write disable Write disable Write disable
Software Protect 1 X 1 Write disable Write enable Write enable
(SPM) X 0 0 Write disable Write disable Write disable
X 0 1 Write disable Write enable Write enable
Hardware Protect 0 1 0 Write disable Write disable Write disable
(HPM) 0 1 1 Write disable Write enable Write disable
Remark X = Don't care

 Hold Operation
The hold operation is used to pause serial communications without setting this IC in the non-select status. In the hold
status, the serial data output goes in "High-Z", and both of the serial data input and the serial clock go in "Don't care".
Be sure to set the chip select ( CS ) to "L" to set this IC in the select status during the hold status.
Generally, during the hold status, this IC holds the select status. But if setting this IC in the non-select status, the
users can finish the operation even in progress. Figure 19 shows the hold operation.

These are two statuses when the serial clock (SCK) is set to "L".

 If setting hold ( HOLD ) to "L", hold ( HOLD ) is switched at the same time the hold status starts.
 If setting hold ( HOLD ) to "H", hold ( HOLD ) is switched at the same time the hold status ends.

These are two statuses when the serial clock (SCK) is set to "H".

 If setting hold ( HOLD ) to "L", the hold status starts when the serial clock goes in "L" after hold ( HOLD ) is switched.
 If setting hold ( HOLD ) to "H", the hold status ends when the serial clock goes in "L" after hold ( HOLD ) is switched.

Hold status Hold status

SCK

HOLD

Figure 19 Hold Operation

21
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A080A/160A/320A, S-25A080B/160B/320B Rev.4.2_02

 Write Protect Function during the Low Power Supply Voltage

This IC has a built-in detection circuit which operates with the low power supply voltage. This IC cancels the write
operation (WRITE, WRSR) when the power supply voltage drops and power-on, at the same time, goes in the write
protect status (WRDI) automatically to reset bit WEL.
To operate write, after the power supply voltage dropped once but rose to the voltage level which allows write again,
be sure to set the Write Enable Latch bit (WEL) before operating write (WRITE, WRSR).
In the write operation, data in the address written during the low power supply voltage is not assured.
In the S-25A080A/160A/320A, the detection voltage is 1.20 V typ., the release voltage is 1.35 V typ., and its
hysteresis is approx. 0.15 V (Refer to Figure 20).
In the S-25A080B/160B/320B, the detection and the release voltages are 1.20 V typ. (Refer to Figure 21).

Hysteresis
Power supply voltage approx. 0.15 V

Detection voltage (−VDET) Release voltage (+VDET)

1.20 V typ. 1.35 V typ.

Cancel the write instruction

Set in write protect (WRDI) automatically

Figure 20 Operation during the Low Power Supply Voltage (S-25A080A/160A/320A)

Power supply voltage

Detection voltage (−VDET) Release voltage (+VDET)

1.20 V typ. 1.20 V typ.

Cancel the write instruction

Set in write protect (WRDI) automatically

Figure 21 Operation during the Low Power Supply Voltage (S-25A080B/160B/320B)

 Input Pin and Output Pin

1. Connection of input pin

All input pins in this IC have the CMOS structure. Do not set these pins in "High-Z" during operation when you
design. Especially, set the CS input pin in the non-select status "H" during power-on/off and standby. The error
write does not occur as long as the CS pin is in the non-select status "H". Set the CS pin to VCC via a resistor
(the pull-up resistor of 10 k to 100 k).
If the CS pin and the SCK pin change from "L" to "H" simultaneously, data may be input from the SI pin.
To prevent the error for sure, it is recommended to pull down the SCK pin to GND. In addition, it is recommended
to pull up the SI pin, the WP pin and the HOLD pin to VCC, or pull down these pins to GND, respectively.
Connecting the WP pin and the HOLD pin to VCC directly is also possible when these pins are not in use.

2. Equivalent circuit of input pin and output pin

Figure 22 and Figure 23 show the equivalent circuits of input pins in this IC. A pull-up and pull-down elements
are not included in each input pin, pay attention not to set it in the floating state when you design.
Figure 24 shows the equivalent circuit of the output pin. This pin has the tri-state output of "H" / "L" / "High-Z".

22
 FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
Rev.4.2_02 S-25A080A/160A/320A, S-25A080B/160B/320B

2. 1 Input pin
CS, SCK

Figure 22 CS , SCK Pin

SI, WP, HOLD

Figure 23 SI, WP , HOLD Pin

2. 2 Output pin
VCC

SO

Figure 24 SO Pin

 Precautions

 Absolute maximum ratings: Do not operate these ICs in excess of the absolute maximum ratings (as listed on the
data sheet). Exceeding the supply voltage rating can cause latch-up. Perform operations after confirming the
detailed operation condition in the data sheet.

 Operations with moisture on this IC's pins may occur malfunction by short-circuit between pins. Especially, in
occasions like picking this IC up from low temperature tank during the evaluation. Be sure that not remain frost on
this IC's pins to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.

 Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.

 ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of
the products including this IC upon patents owned by a third party.

23
 5.02±0.2

8 5

1 4
0.20±0.05

1.27 0.4±0.05

No. FJ008-A-P-SD-2.2

TITLE SOP8J-D-PKG Dimensions

No. FJ008-A-P-SD-2.2
ANGLE
UNIT mm

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ø1.55±0.05 0.3±0.05

ø2.0±0.05 8.0±0.1 2.1±0.1

6.7±0.1

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Enlarged drawing in the central part 13.5±0.5

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TITLE TSSOP8-E-PKG Dimensions

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(4.4)

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 Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
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4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
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