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OPA180, OPA2180, OPA4180

SBOS584E – NOVEMBER 2011 – REVISED JUNE 2018

OPAx180 0.1-μV/°C Drift, Low-Noise, Rail-to-Rail Output, 36-V,

Zero-Drift Operational Amplifiers
1 Features 3 Description
•
1 Low Offset Voltage: 75 μV (Maximum) The OPA180, OPA2180 and OPA4180 operational
amplifiers (op amps) use TI's proprietary zero-drift
• Zero-Drift: 0.1 μV/°C techniques to simultaneously provide low offset
• Low Noise: 10 nV/√Hz voltage (75 μV), and near zero-drift over time and
• Very Low 1/f Noise temperature. These miniature, high-precision, low-
• Excellent DC Precision: quiescent-current op amps offer high input
impedance and rail-to-rail output swing within 18 mV
– PSRR: 126 dB of the rails. The input common-mode range includes
– CMRR: 114 dB the negative rail. Single- or dual-supplies ranging
– Open-Loop Gain (AOL): 120 dB from 4 V to 36 V (±2 V to ±18 V) can be used.
• Quiescent Current: 525 μA (Maximum) The dual-channel version is offered in VSSOP-8
• Wide Supply Range: ±2 V to ±18 V packages and SOIC-8 packages. The quad-channel
version is offered in SOIC-14 and TSSOP-14
• Rail-to-Rail Output: packages. The single and quad package offerings
Input Includes Negative Rail (OPA180 and OPA4180) are specified from –40°C to
• Low Bias Current: 250 pA (Typical) +125°C, and the dual package (OPA2180) is
• RFI Filtered Inputs specified from –40°C to +105°C.
• MicroSIZE Packages Device Information(1)
DEVICE NAME PACKAGE BODY SIZE (NOM)
2 Applications
SOT-23 (5) 1.60 mm × 2.90 mm
• Bridge Amplifiers OPA180 VSSOP, MSOP (8) 3.00 mm × 3.00 mm
• Strain Gauges SOIC (8) 4.90 mm × 3.91 mm
• Test Equipment VSSOP, MSOP (8) 3.00 mm × 3.00 mm
OPA2180
• Transducer Applications SOIC (8) 4.90 mm × 3.91 mm
• Temperature Measurement TSSOP (14) 5.00 mm × 4.40 mm
OPA4180
• Electronic Scales SOIC (14) 8.65 mm × 3.91 mm

• Medical Instrumentation (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Resister Thermal Detectors
• Precision Active Filters space
space
space

Low Noise
(Peak-to-Peak Noise = 250 nV)
50 nV/div

Time (1 s/div)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.1 Overview ................................................................. 17
2 Applications ........................................................... 1 8.2 Functional Block Diagram ....................................... 17
3 Description ............................................................. 1 8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 20
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 4 9 Application and Implementation ........................ 21
9.1 Application Information............................................ 21
6 Pin Configuration and Functions ......................... 5
9.2 Typical Applications ................................................ 21
7 Specifications......................................................... 8
10 Power Supply Recommendations ..................... 25
7.1 Absolute Maximum Ratings ...................................... 8
7.2 ESD Ratings ............................................................ 8 11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
7.3 Recommended Operating Conditions....................... 8
11.2 Layout Example .................................................... 26
7.4 Thermal Information: OPA180 .................................. 9
7.5 Thermal Information: OPA2180 ................................ 9 12 Device and Documentation Support ................. 27
7.6 Thermal Information: OPA4180 ................................ 9 12.1 Related Links ........................................................ 27
7.7 Electrical Characteristics: VS = ±2 V to ±18 V (VS = 12.2 Trademarks ........................................................... 27
4 V to 36 V).............................................................. 10 12.3 Electrostatic Discharge Caution ............................ 27
7.8 Typical Characteristics: Table of Graphs ................ 12 12.4 Glossary ................................................................ 27
7.9 Typical Characteristics ............................................ 13 13 Mechanical, Packaging, and Orderable
8 Detailed Description ............................................ 17 Information ........................................................... 27

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (May 2014) to Revision E Page

• Changed OPA180 and OPA4180 operating temperature from "–40°C to +105°C" to "–40°C to +125°C" in
Description section ................................................................................................................................................................. 1
• Added storage temperature parameter as the last row in the Absolute Maximum Ratings table ......................................... 8
• Changed maximum operating temperature value from 105°C to 125°C in Absolute Maximum Ratings table ..................... 8
• Changed maximum operating temperature value from 105°C to 125°C in Recommended Operating Conditions table ...... 8
• Changed input offset voltage drift temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................. 10
• Changed power supply rejection ratio temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................. 10
• Changed OPA180 input bias current temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................. 10
• Added minimum OPA2180 input bias current value of 18 nA in Electrical Characteristics table ........................................ 10
• Added minimum OPA180 input bias current value of 18 nA in Electrical Characteristics table........................................... 10
• Changed OPA180 input offset current temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................. 10
• Added minimum OPA2180 input offset current value of 6 nA in Electrical Characteristics table ....................................... 10
• Added minimum OPA180 input offset current value of 6 nA in Electrical Characteristics table ......................................... 10
• Changed common-mode rejection ratio temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................. 10
• Changed open-loop voltage gain temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in Electrical
Characteristics table ............................................................................................................................................................. 10
• Changed voltage output swing from rail temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................. 11
• Changed quiescent current temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in Electrical
Characteristics table ............................................................................................................................................................. 11
• Changed operating temperature from "–40°C to +105°C" to " –40°C to +125°C" in Feature Description section .............. 18
• Updated Figure 34................................................................................................................................................................ 24

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Revision History (continued)

• Changed operating temperature from "–40°C to +105°C" to " –40°C to +125°C" in Power Supply Recommendations
section .................................................................................................................................................................................. 25

Changes from Revision C (December 2012) to Revision D Page

• Changed format to meet latest data sheet standards; added Device Functional Modes, Application and
Implementation, and Power Supply Recommendations sections, and moved existing sections ........................................... 1
• Added OPA180 to document.................................................................................................................................................. 1
• Added Device Information table ............................................................................................................................................ 1
• Deleted Package Information table ........................................................................................................................................ 5
• OPA180 pinout drawings ....................................................................................................................................................... 5
• Added Pin Functions table ..................................................................................................................................................... 5
• Added Pin Functions table ..................................................................................................................................................... 6
• Added Pin Functions table ..................................................................................................................................................... 7
• Added Recommended Operating Conditions table ................................................................................................................ 8
• Added Thermal Information: OPA180 table............................................................................................................................ 9
• Changed Offset Voltage, Long-term stability parameter typical specification in Electrical Characteristics table................. 10
• Changed last sentence of EMI Rejection section................................................................................................................. 18

Changes from Revision B (December 2011) to Revision C Page

• Changed product status from Mixed Status to Production Data ............................................................................................ 1

• Changed OPA4180 status to Production Data....................................................................................................................... 1
• Added package marking to OPA2180 VSSOP-8 row in Package Information table.............................................................. 5
• Deleted ordering number and transport media columns from Package Information table..................................................... 5
• Changed Input Bias Current section in Electrical Characteristics (VS = +4 V to +36 V) table ............................................. 10

Changes from Revision A (November 2011) to Revision B Page

• Changed footnote 1 of Electrical Characteristics table......................................................................................................... 10

• Updated Figure 7 ................................................................................................................................................................. 13

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5 Device Comparison Table

Table 1. Zero-Drift Amplifier Portfolio

OFFSET VOLTAGE OFFSET VOLTAGE DRIFT BANDWIDTH
VERSION PRODUCT (µV) (µV/°C) (MHz)
OPA188(4 V to 36 V) 25 0.085 2
OPA180 (4 V to 36 V) 75 0.35 2
Single OPA333 (5 V) 10 0.05 0.35
OPA378 (5 V) 50 0.25 0.9
OPA735 (12 V) 5 0.05 1.6
OPA2188 (4 V to 36 V) 25 0.085 2
OPA2180 (4 V to 36 V) 75 0.35 2
Dual OPA2333 (5 V) 10 0.05 0.35
OPA2378 (5 V) 50 0.25 0.9
OPA2735 (12 V) 5 0.05 1.6
OPA4188 (4 V to 36 V) 25 0.085 2
Quad OPA4180 (4 V to 36 V) 75 0.35 2
OPA4330 (5 V) 50 0.25 0.35

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6 Pin Configuration and Functions

OPA180 DBV Package

5-Pin SOT-23
(Top View)

OUT 1 5 V+

V- 2

+IN 3 4 -IN

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
–IN 4 I Inverting input
+IN 3 I Noninverting input
OUT 1 O Output
V– 2 — Negative supply or ground (for single-supply operation)
V+ 5 — Positive supply or ground (for single-supply operation)

OPA180 D, DGK Packages

8-Pin SO, MSOP
Top View

NC(1) 1 8 NC(1)

-IN 2 7 V+

+IN 3 6 OUT

V- 4 5 NC(1)

(1) NC- no internal connection

Pin Functions: OPA180

PIN
DESCRIPTION
NAME NO.
–IN 2 Inverting input
+IN 3 Noninverting input
NC 1, 5, 8 No connection
OUT 6 Output
V– 4 Negative power supply
V+ 7 Positive power supply

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OPA2180 D, DGK Packages

8-Pin SOIC, VSSOP
Top View

OUT A 1 8 V+
A
-IN A 2 7 OUT B

+IN A 3 B 6 -IN B

V- 4 5 +IN B

Pin Functions: OPA2180

PIN
DESCRIPTION
NAME NO.
–IN A 2 Inverting input, channel A
+IN A 3 Noninverting input, channel A
–IN B 6 Inverting input, channel B
+IN B 5 Noninverting input, channel B
OUT A 1 Output, channel A
OUT B 7 Output, channel B
V– 4 Negative power supply
V+ 8 Positive power supply

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OPA4180 D, PW Packages
14-Pin SOIC, TSSOP
(Top View)

OUT A 1 14 OUT D

-IN A 2 A D 13 -IN D

+IN A 3 12 +IN D

V+ 4 11 V-

+IN B 5 10 +IN C
B C
-IN B 6 9 -IN C

OUT B 7 8 OUT C

Pin Functions: OPA4180

PIN
DESCRIPTION
NAME NO.
–IN A 2 Inverting input, channel A
+IN A 3 Noninverting input, channel A
–IN B 6 Inverting input, channel B
+IN B 5 Noninverting input, channel B
–IN C 9 Inverting input, channel C
+IN C 10 Noninverting input, channel C
–IN D 13 Inverting input, channel D
+IN D 12 Noninverting input, channel D
OUT A 1 Output, channel A
OUT B 7 Output, channel B
OUT C 8 Output, channel C
OUT D 14 Output, channel D
V– 11 Negative supply or ground (for single-supply operation)
V+ 4 Positive supply or ground (for single-supply operation)

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
±20, ±40
Supply voltage V
(single-supply)
Voltage (V–) – 0.5 (V+) + 0.5 V
Signal input terminals
Current ±10 mA
Output short-circuit (2) Continuous
Operating temperature –55 125 °C
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.

7.2 ESD Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
–1.5 1.5
pins (1)
V(ESD) Electrostatic discharge kV
Charged device model (CDM), per JEDEC specification
–1 1
JESD22-C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted), RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS /
2, (unless otherwise noted)
MIN NOM MAX UNIT
Single-supply 4.5 36 V
Supply voltage [(V+) – (V–)]
Bipolar-supply ±2.25 ±18 V
Operating temperature –40 125 °C

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7.4 Thermal Information: OPA180

OPA180
THERMAL METRIC (1) D (SOIC) DBV (SOT-23) DGK (MSOP) UNIT
8 PINS 5 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 115.8 158.8 180.4 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 60.1 60.7 67.9 °C/W
RθJB Junction-to-board thermal resistance 56.4 44.8 102.1 °C/W
ψJT Junction-to-top characterization parameter 12.8 1.6 10.4 °C/W
ψJB Junction-to-board characterization parameter 55.9 4.2 100.3 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.5 Thermal Information: OPA2180

OPA2180
THERMAL METRIC (1) D (SOIC) DGK (MSOP) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 111 159.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 54.9 37.4 °C/W
RθJB Junction-to-board thermal resistance 51.7 48.5 °C/W
ψJT Junction-to-top characterization parameter 9.3 1.2 °C/W
ψJB Junction-to-board characterization parameter 51.1 77.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.6 Thermal Information: OPA4180

OPA4180
THERMAL METRIC (1) D (SOIC) PW (TSSOP) UNIT
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 93.2 106.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 51.8 24.4 °C/W
RθJB Junction-to-board thermal resistance 49.4 59.3 °C/W
ψJT Junction-to-top characterization parameter 13.5 0.6 °C/W
ψJB Junction-to-board characterization parameter 42.2 54.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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7.7 Electrical Characteristics: VS = ±2 V to ±18 V (VS = 4 V to 36 V)

at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS / 2, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VIO Input offset voltage 15 75 μV
dVIO/dT Input offset voltage drift TA = –40°C to +125°C 0.1 0.35 μV/°C
VS = 4 V to 36 V,
0.1 0.5 μV/V
VCM = VS / 2
PSRR Power supply rejection ratio
TA = –40°C to +125°C,
0.5 μV/V
VS = 4 V to 36 V, VCM = VS / 2
Long-term stability 4 (1) μV
Channel separation, DC 1 μV/V
INPUT BIAS CURRENT
OPA2180 ±0.25 ±1 nA
OPA2180: TA = –40°C to +105°C 18 ±5 nA
IIB Input bias current
OPA180, OPA4180 ±0.25 ±1.7 nA
OPA180, OPA4180: TA = –40°C to +125°C 18 ±6 nA
OPA2180 ±0.5 ±2 nA
OPA2180: TA = –40°C to +105°C 6 ±2.5 nA
IIO Input offset current
OPA180, OPA4180 ±3.4 nA
OPA180, OPA4180: TA = –40°C to +125°C 6 ±3 nA
NOISE
Input voltage noise ƒ = 0.1 Hz to 10 Hz 0.25 μVPP
en Input voltage noise density ƒ = 1 kHz 10 nV/√Hz
in Input current noise density ƒ = 1 kHz 10 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range V– (V+) – 1.5 V
(V–) < VCM < (V+) – 1.5 V 104 114 dB
CMRR Common-mode rejection ratio TA = –40°C to +125°C,
100 104 dB
(V–) + 0.5 V < VCM < (V+) – 1.5 V
INPUT IMPEDANCE
zid Differential 100 || 6 MΩ || pF
zic Common-mode 6 || 9.5 1012 Ω || pF
OPEN-LOOP GAIN
(V–) + 500 mV < VO < (V+) – 500 mV
110 120 dB
RL = 10 kΩ
AOL Open-loop voltage gain TA = –40°C to +125°C
(V–) + 500 mV < VO < (V+) – 500 mV, 104 114 dB
RL = 10 kΩ
FREQUENCY RESPONSE
GBW Gain bandwidth product 2 MHz
SR Slew rate G=1 0.8 V/μs
0.1% VS = ±18 V, G = 1, 10-V step 22 μs
ts Settling time
0.01% VS = ±18 V, G = 1, 10-V step 30 μs
tor Overload recovery time VIN × G = VS 1 μs
THD+N Total harmonic distortion + noise ƒ = 1 kHz, G = 1, VOUT = 1 VRMS 0.0001%

(1) 1000-hour life test at 125°C demonstrated randomly distributed variation in the range of measurement limits, or approximately 4 μV.

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Electrical Characteristics: VS = ±2 V to ±18 V (VS = 4 V to 36 V) (continued)

at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS / 2, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNIT
OUTPUT
No load 8 18 mV
RL = 10 kΩ 250 300 mV
Voltage output swing from rail
TA = –40°C to +125°C
325 360 mV
RL = 10 kΩ
IOS Short-circuit current ±18 mA
ro Output resistance (open loop) ƒ = 2 MHz, IO = 0 mA 120 Ω
CLOAD Capacitive load drive 1 nF
POWER SUPPLY
VS Operating voltage range ±2 (or 4) ±18 (or 36) V
450 525 μA
IQ Quiescent current (per amplifier) TA = –40°C to +125°C
600 μA
IO = 0 mA
TEMPERATURE
Specified range –40 105 °C
Operating range –40 105 °C

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7.8 Typical Characteristics: Table of Graphs

Table 2. Characteristic Performance Measurements
DESCRIPTION FIGURE
IB and IOS vs Common-Mode Voltage Figure 1
Input Bias Current vs Temperature Figure 2
Output Voltage Swing vs Output Current (Maximum Supply) Figure 3
CMRR vs Temperature Figure 4
0.1-Hz to 10-Hz Noise Figure 5
Input Voltage Noise Spectral Density vs Frequency Figure 6
Open-Loop Gain and Phase vs Frequency Figure 7
Open-Loop Gain vs Temperature Figure 8
Open-Loop Output Impedance vs Frequency Figure 9
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 10, Figure 11
No Phase Reversal Figure 12
Positive Overload Recovery Figure 13
Negative Overload Recovery Figure 14
Small-Signal Step Response (100 mV) Figure 15, Figure 16
Large-Signal Step Response Figure 17, Figure 18
Large-Signal Settling Time (10-V Positive Step) Figure 19
Large-Signal Settling Time (10-V Negative Step) Figure 20
Short-Circuit Current vs Temperature Figure 21
Maximum Output Voltage vs Frequency Figure 22
Channel Separation vs Frequency Figure 23
EMIRR IN+ vs Frequency Figure 24

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7.9 Typical Characteristics

VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.

500 4000
+IIB IIB+
400 IIB-
-IIB 3000
IIO

Input Bias Current (pA)

300 IIO
2000
IIB and IIO (pA)

200

100 1000

0
0
-100
-1000
-200

-300 -2000
-20 -15 -10 -5 0 5 10 15 20 -55 -35 -15 5 25 45 65 85 105 125
VCM (V) Temperature (°C)

Figure 1. IIB and IIO vs Common-Mode Voltage Figure 2. Input Bias Current vs Temperature
20 40

Common-Mode Rejection Ratio (mV/V)

19 -40°C (V-) < VCM < (V+) - 1.5 V
18 85°C 35 (V-) + 0.5 V < VCM < (V+) - 1.5 V
17 125°C
30
Output Voltage (V)

16
15 25
14
20
-14
-15 15
-16
-17 10
-18
5
-19
-20 0
0 2 4 6 8 10 12 14 16 18 20 22 24 -55 -35 -15 5 25 45 65 85 105 125
Output Current (mA) Temperature (°C)
VSUPPLY = ±2 V

Figure 3. Output Voltage Swing vs Output Current Figure 4. CMRR vs Temperature

(Maximum Supply)
100
Voltage Noise Density (nV/ÖHz)
50 nV/div

10

1
Time (1 s/div) 0.1 1 10 100 1k 10k 100k
Peak-to-Peak Noise = 250 nV Frequency (Hz)

Figure 5. 0.1-Hz to 10-Hz Noise Figure 6. Input Voltage Noise Spectral Density vs Frequency

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Typical Characteristics (continued)

VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
140 180 3
Gain VSUPPLY = 4 V, RL = 10 kW
120 Phase
2.5 VSUPPLY = 36 V, RL = 10 kW
100 135

80 2
Gain (dB)

Phase (°)

AOL (mV/V)
60 90
1.5
40

20 45 1
0
0.5
−20 0
10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz) G007 0
-55 -35 -15 5 25 45 65 85 105 125
Temperature (°C)

Figure 7. Open-Loop Gain and Phase vs Frequency Figure 8. Open-Loop Gain vs Temperature
10k 40
ROUT = 0 W
35
ROUT = 25 W
1k
30 ROUT = 50 W
Overshoot (%)

100 25
ZO (W)

20
10 15
18 V
G=1
ROUT
10 Device

1 -18 V
RL CL

1m 0
1 10 100 1k 10k 100k 1M 10M 0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz) Capacitive Load (pF)
RL = 10 kΩ

Figure 9. Open-Loop Output Impedance vs Frequency Figure 10. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
40
ROUT = 0 W 18 V

35
ROUT = 25 W Device

30 ROUT = 50 W
-18 V
Overshoot (%)

37 VPP
25 Sine Wave
5 V/div

(±18.5 V)

20

15
RI = 10 kW RF = 10 kW G = -1
10 18 V
ROUT VI
Device
5 CL
VO
-18 V

0
0 100 200 300 400 500 600 700 800 900 1000 Time (100 ms/div)
Capacitive Load (pF)
RL = 10 kΩ

Figure 11. Small-Signal Overshoot vs Capacitive Load Figure 12. No Phase Reversal
(100-mV Output Step)

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Typical Characteristics (continued)

VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.

VO VI

20 kW
20 kW
2 kW 18 V

2 kW 18 V
5 V/div

5 V/div
Device VO
VI Device VO
-18 V VI
-18 V
G = -10 G = -10

VO
VI

Time (5 ms/div) Time (5 ms/div)

Figure 13. Positive Overload Recovery Figure 14. Negative Overload Recovery
20 mV/div

20 mV/div
RI = 2 kW RF = 2 kW
+18 V
G=1
18 V

Device
Device

-18 V RL CL CL
-18 V
G = -1

Time (1 ms/div) Time (20 ms/div)

RL = 10 kΩ CL = 10 pF RL = 10 kΩ CL = 10 pF

Figure 15. Small-Signal Step Response Figure 16. Small-Signal Step Response (100 mV)
(100 mV)
5 V/div

5 V/div

Time (50 ms/div) Time (50 ms/div)

G=1 RL = 10 kΩ CL = 10 pF G = –1 RL = 10 kΩ CL = 10 pF

Figure 17. Large-Signal Step Response Figure 18. Large-Signal Step Response

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Typical Characteristics (continued)

VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
10 10
8 8
6 6
D from Final Value (mV)

D from Final Value (mV)

4 4
12-Bit Settling 12-Bit Settling
2 2
0 0
-2 -2
(±1/2 LSB = ±0.024%) (±1/2 LSB = ±0.024%)
-4 -4
-6 -6
-8 -8
-10 -10
0 10 20 30 40 50 60 0 10 20 30 40 50 60
Time (ms) Time (ms)
G = –1 G = –1

Figure 19. Large-Signal Settling Time (10-V Positive Step) Figure 20. Large-Signal Settling Time (10-V Negative Step)
30 15
VS = ±15 V
20 12.5
Output Voltage (VPP)
10 10 Maximum output voltage without
slew-rate induced distortion.
ISC (mA)

ISC, Source
0 ISC, Sink 7.5
VS = ±5 V
-10 5

-20 2.5 VS = ±2.25 V

-30 0
-55 -35 -15 5 25 45 65 85 105 125 1k 10k 100k 1M 10M
Temperature (°C) Frequency (Hz)

Figure 21. Short-Circuit Current vs Temperature Figure 22. Maximum Output Voltage vs Frequency
-60 160
Channel A to B
-70 Channel B to A 140
Channel Separation (dB)

-80 120
EMIRR IN+ (dB)

-90
100
-100
80
-110
60
-120
40
-130

-140 20

-150 0
1 10 100 1k 10k 100k 1M 10M 100M 10M 100M 1G 10G
Frequency (Hz) Frequency (Hz)

Figure 23. Channel Separation vs Frequency Figure 24. EMIRR IN+ vs Frequency

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8 Detailed Description

8.1 Overview
The OPAx180 family of operational amplifiers combine precision offset and drift with excellent overall
performance, making them designed for many precision applications. The precision offset drift of only 0.1 µV/°C
provides stability over the entire temperature range. In addition, the devices offer excellent overall performance
with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or
high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF
capacitors are adequate.

8.2 Functional Block Diagram

V+

C2

Notch
CHOP1 GM1 CHOP2 Filter GM2 GM3

+IN OUT

-IN

C1

GM_FF

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V-

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8.3 Feature Description

8.3.1 Operating Characteristics
The OPAx180 family of amplifiers is specified for operation from 4 V to 36 V (±2 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in the Typical Characteristics.

8.3.2 EMI Rejection

The OPAx180 family uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely populated boards with a mix of analog
signal chain and digital components. EMI immunity can improve with circuit design techniques; the OPAx180
family benefits from these design improvements. Texas Instruments has developed the ability to accurately
measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from
10 MHz to 6 GHz. Figure 25 shows the results of this testing on the OPAx180 family . For more detailed
information, see the EMI Rejection Ratio of Operational Amplifiers application report, available for download from
www.ti.com.
160

140

120
EMIRR IN+ (dB)

100

80

60

40

20

0
10M 100M 1G 10G
Frequency (Hz)

Figure 25. OPAx180 EMIRR Testing

8.3.3 Phase-Reversal Protection

The OPAx180 family has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The input of the OPAx180 prevents phase reversal with excessive common-mode
voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 26.

18 V

Device

-18 V
37 VPP
Sine Wave
5 V/div

(±18.5 V)

VI
VO

Time (100 ms/div)

Figure 26. No Phase Reversal

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Feature Description (continued)

8.3.4 Capacitive Load and Stability
The dynamic characteristics of the OPAx180 are optimized for a range of common operating conditions. The
combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and
can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output.
The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series
with the output. Figure 27 and Figure 28 illustrate graphs of small-signal overshoot versus capacitive load for
several values of ROUT. See the Feedback Plots Define Op Amp AC Performance, application report, available
for download from the TI website, for details of analysis techniques and application circuits.

40 40
ROUT = 0 W ROUT = 0 W
35 35
ROUT = 25 W ROUT = 25 W
30 ROUT = 50 W 30 ROUT = 50 W
Overshoot (%)

Overshoot (%)
25 25

20 20

15 G=1 15
18 V
ROUT
RI = 10 kW RF = 10 kW G = -1
10 Device 10 18 V
ROUT
RL CL
-18 V Device
5 5 CL

-18 V

0 0
0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF) Capacitive Load (pF)
100-mV output 100-mV output
RL = 10 kΩ RL = 10 kΩ
step step

Figure 27. Small-Signal Overshoot Versus Capacitive Load Figure 28. Small-Signal Overshoot Versus Capacitive Load

8.3.5 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA as stated in the Absolute Maximum Ratings table. Figure 29 shows how a series input resistor may be
added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier
input and the value must be kept to a minimum in noise-sensitive applications.

V+

IOVERLOAD
10 mA max
VOUT
VIN
Device
5 kW

Figure 29. Input Current Protection

An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-
current pulse as the pulse discharges through a semiconductor device. The ESD protection circuits are designed
to provide a current path around the operational amplifier core to protect the core from damage. The energy
absorbed by the protection circuitry is then dissipated as heat.

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Feature Description (continued)

When the operational amplifier connects into a circuit, the ESD protection components are intended to remain
inactive and not become involved in the application circuit operation. However, circumstances may arise when an
applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk that
some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow
occurs through ESD cells and rarely involves the absorption device.
If there is an uncertainty about the ability of the supply to absorb this current, external zener diodes may be
added to the supply pins. The zener voltage must be selected so the diode does not turn on during normal
operation.
However, the zener voltage must be low enough so that the zener diode conducts if the supply pin begins to rise
above the safe operating supply voltage level.

8.4 Device Functional Modes

The OPAx180, OPA2180 , and OPA4180 devices are powered on when the supply is connected. These devices
can operate as a single-supply operational amplifier or dual-supply amplifier depending on the application. In
single-supply operation with V– at ground (0 V), V+ can be any value between 4 V and 36 V. In dual-supply
operation, the supply voltage difference between V– and V+ is from 4 V to 36 V. Typical examples of dual-supply
configuration are ±5 V, ±10 V, ±15 V, and ±18 V. However, the supplies must not be symmetrical. Less common
examples are V– at –3 V and V+ at 9 V, or V– at –16 V and V+ at 5 V. Any combination where the difference
between V– and V+ is at least 4 V and no greater than 36 V is within the normal operating capabilities of these
devices.

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9 Application and Implementation

9.1 Application Information
The OPAx180 family offers excellent DC precision and AC performance. These devices operate up to 36-V
supply rails and offer rail-to-rail output, ultra-low offset voltage, offset voltage drift and 2-MHz bandwidth. These
features make the OPAx180 a robust, high-performance amplifier for high-voltage industrial applications.

9.2 Typical Applications

These application examples highlight a few of the circuits where the OPAx180 family can be used.

9.2.1 Bipolar ±10-V Analog Output from a Unipolar Voltage Output DAC
This design is used for conditioning a unipolar digital-to-analog converter (DAC) into an accurate bipolar signal
source using the OPAx180 family and three resistors. The circuit is designed with reactive load stability in mind,
and is compensated to drive nearly any conventional capacitive load associated with long cable lengths.
RG1 RFB

CCOMP
VREF

RG2
VOUT

DAC8560 +
RISO
CLOAD
Device

Copyright © 2017, Texas Instruments Incorporated

Figure 30. Circuit Schematic

9.2.1.1 Design Requirements

The design requirements are as follows:
• DAC supply voltage: +5-V dc
• Amplifier supply voltage: ±15-V dc
• Input: 3-wire, 24-bit SPI
• Output: ±10-V dc

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Typical Applications (continued)

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Component Selection

DAC: For convenience, devices with an external reference option or devices with accessible internal references
are desirable in this application because the reference creates an offset. The DAC selection in this design must
primarily be based on DC error contributions typically described by offset error, gain error, and integral
nonlinearity error. Occasionally, additional specifications are provided that summarize end-point errors of the
DAC typically called zero-code and full-scale errors. For AC applications, slew rate and settling time may require
additional consideration.
Amplifier: Amplifier input offset voltage (VIO) is a key consideration for this design. VIO of an operational amplifier
is a typical data sheet specification, but in-circuit performance is also affected by drift over temperature, the
common-mode rejection ratio (CMRR), and power-supply rejection ratio (PSRR); thus consideration should be
given to these parameters as well. For ac operation, additional considerations should be made concerning slew
rate and settling time. Input bias current (IIB) can also be a factor, but typically the resistor network is
implemented with sufficiently small resistor values that the effects of input bias current are negligible.
Passive: Resistor matching for the op-amp resistor network is critical for the success of this design; components
with tight tolerances must be selected. For this design, 0.1% resistor values are implemented, but this constraint
may be adjusted based on application-specific design goals. Resistor matching contributes to offset error and
gain error in this design; see Bipolar ±10V Analog Output from a Unipolar Voltage Output DAC for further details.
The tolerance of the RISOand CCOMP stability components is not critical, and 1% components are acceptable.

9.2.1.3 Application Curves

Figure 31. Full-Scale Output Waveform

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Typical Applications (continued)

Figure 32. DC Transfer Characteristic

For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIPD125, Bipolar ±10V Analog Output from a Unipolar Voltage Output DAC

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9.2.2 Discrete INA + Attenuation

The OPAx180 family can be used as a high-voltage, high-impedance front-end for a precision, discrete
instrumentation amplifier with attenuation. The INA159 in Figure 33 provides the attenuation that allows this
circuit to simply interface with 3.3-V or 5-V analog-to-digital converters (ADCs).
15 V

U2
½
OPA2180 VOUTP

3.3 V
VDIFF/2 R5
-15 V 1 kW
Ref 1
Ref 2
RG R7 U1 VOUT
+ 500 W 1 kW INA159
VCM
10 Sense

-VDIFF/2 -15 V

U5
½
OPA2180 VOUTN

15 V

Figure 33. Discrete INA + Attenuation for ADC With a 3.3-V Supply

9.2.3 RTD Amplifier

The OPAx180 is excellent for use in analog linearization of resistance temperature detectors (RTDs). The circuit
below (Figure 34) combines the precision of the OPAx180 amplifier and the precision reference of the REF5050
to linearize a Pt100 RTD.
15 V

(5 V) Out In
REF5050
1 µF
R2
49.1 k
1 µF
R1
4.99 k R3
60.4 k

± ½
VOUT 0°C = 0 V
OPA2180
+ 200°C = 5 V

RTD
Pt100 R5
105.8 k

R4
1k

Copyright © 2017, Texas Instruments Incorporated

(1) R5 provides positive-varying excitation to linearize output.

Figure 34. RTD Amplifier with Linearization

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10 Power Supply Recommendations

The OPAx180 family is specified for operation from 4 V to 36 V (±2 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in Layout

CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see Layout .

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11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically
separate digital and analog grounds, paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep the input traces separate, it is much better to cross the sensitive
trace perpendicular as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 35, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.

11.2 Layout Example

Place components close
Run the input traces to device and to each VS+
as far away from other to reduce parasitic
the supply lines errors
as possible RF

NC NC
Use a low-ESR,
RG
ceramic bypass
GND ±IN V+ capacitor

VIN +IN OUTPUT

V± NC GND

VS± GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor

Figure 35. Operational Amplifier Board Layout for Noninverting Configuration

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12 Device and Documentation Support

12.1 Related Links

Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.

Table 3. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
OPA180 Click here Click here Click here Click here Click here
OPA2180 Click here Click here Click here Click here Click here
OPA4180 Click here Click here Click here Click here Click here

12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

OPA180ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 OPA180
& no Sb/Br)
OPA180IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 SHJ
& no Sb/Br)
OPA180IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 SHJ
& no Sb/Br)
OPA180IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 SHK
& no Sb/Br)
OPA180IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 SHK
& no Sb/Br)
OPA180IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 OPA180
& no Sb/Br)
OPA2180ID ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 2180
& no Sb/Br)
OPA2180IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 105 2180
& no Sb/Br)
OPA2180IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 105 2180
& no Sb/Br)
OPA2180IDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 2180
& no Sb/Br)
OPA4180ID ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 OPA4180
& no Sb/Br)
OPA4180IDR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 OPA4180
& no Sb/Br)
OPA4180IPW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 OPA4180
& no Sb/Br)
OPA4180IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 OPA4180
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 11-Oct-2016

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA180IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
OPA180IDBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
OPA180IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA180IDGKT VSSOP DGK 8 250 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA180IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2180IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2180IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA4180IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
OPA4180IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA180IDBVR SOT-23 DBV 5 3000 223.0 270.0 35.0
OPA180IDBVT SOT-23 DBV 5 250 223.0 270.0 35.0
OPA180IDGKR VSSOP DGK 8 2500 346.0 346.0 29.0
OPA180IDGKT VSSOP DGK 8 250 223.0 270.0 35.0
OPA180IDR SOIC D 8 2500 367.0 367.0 35.0
OPA2180IDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
OPA2180IDR SOIC D 8 2500 367.0 367.0 35.0
OPA4180IDR SOIC D 14 2500 367.0 367.0 38.0
OPA4180IPWR TSSOP PW 14 2000 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/E 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/E 09/2019

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/E 09/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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